diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd index 9985eb19c958972147fd60cfb547f6560d7d6e81..a7b2234a79a41c7fb71c5250e2a999c8d3cbb43e 100644 --- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd +++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd @@ -211,35 +211,35 @@ BEGIN -- Read stream enable bits, default '1' after power up FOR I IN 0 TO c_nof_streams-1 LOOP - proc_mem_mm_bus_rd(I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); + proc_mem_mm_bus_rd(2*I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); proc_mem_mm_bus_rd_latency(1, mm_clk); ASSERT reg_bsn_align_cipo.rddata(0) = '1' REPORT "Wrong stream disable for output " & int_to_str(I) SEVERITY ERROR; END LOOP; -- Write stream enable bits for stream_en_arr FOR I IN 0 TO c_nof_streams-1 LOOP - proc_mem_mm_bus_wr(I, 0, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); + proc_mem_mm_bus_wr(2*I, 0, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); END LOOP; proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency); proc_common_wait_some_cycles(dp_clk, c_cross_clock_domain_latency); -- Read stream enable bits, should now be '0' FOR I IN 0 TO c_nof_streams-1 LOOP - proc_mem_mm_bus_rd(I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); + proc_mem_mm_bus_rd(2*I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); proc_mem_mm_bus_rd_latency(1, mm_clk); ASSERT reg_bsn_align_cipo.rddata(0) = '0' REPORT "Wrong BSN align stream enable for output " & int_to_str(I) SEVERITY ERROR; END LOOP; -- Write stream enable bits for stream_en_arr FOR I IN 0 TO c_nof_streams-1 LOOP - proc_mem_mm_bus_wr(I, 1, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); + proc_mem_mm_bus_wr(2*I, 1, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); END LOOP; proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency); proc_common_wait_some_cycles(dp_clk, c_cross_clock_domain_latency); -- Read stream enable bits, should now be '1' FOR I IN 0 TO c_nof_streams-1 LOOP - proc_mem_mm_bus_rd(I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); + proc_mem_mm_bus_rd(2*I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); proc_mem_mm_bus_rd_latency(1, mm_clk); ASSERT reg_bsn_align_cipo.rddata(0) = '1' REPORT "Wrong BSN align stream enable for output " & int_to_str(I) SEVERITY ERROR; END LOOP;