From 1fcaa2e32c2d71665ed77038bf790b343697fa03 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Wed, 8 Apr 2015 15:30:14 +0000
Subject: [PATCH] Added array types
---
libraries/technology/ddr/tech_ddr_pkg.vhd | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/libraries/technology/ddr/tech_ddr_pkg.vhd b/libraries/technology/ddr/tech_ddr_pkg.vhd
index 68bf8412d6..75060c7780 100644
--- a/libraries/technology/ddr/tech_ddr_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_pkg.vhd
@@ -131,6 +131,14 @@ PACKAGE tech_ddr_pkg IS
odt : STD_LOGIC_VECTOR(c_tech_ddr4_max.odt_w-1 DOWNTO 0); -- on-die termination control signal
END RECORD;
+ TYPE t_tech_ddr3_phy_in_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr3_phy_in;
+ TYPE t_tech_ddr3_phy_io_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr3_phy_io;
+ TYPE t_tech_ddr3_phy_ou_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr3_phy_ou;
+
+ TYPE t_tech_ddr4_phy_in_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr4_phy_in;
+ TYPE t_tech_ddr4_phy_io_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr4_phy_io;
+ TYPE t_tech_ddr4_phy_ou_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr4_phy_ou;
+
TYPE t_tech_ddr3_phy_terminationcontrol IS RECORD -- DDR3 Termination control
seriesterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr3_max.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY (internal signal in FPGA)
parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr3_max.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY (internal signal in FPGA)
--
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