diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
index c1f0a74c2641dac6656dd31e02848772ebc82276..84cf3e5107796f2bee35dcb0323cebd68a8d60f6 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
@@ -38,11 +38,11 @@ USE dp_lib.tb_dp_pkg.ALL;
ENTITY tb_dp_block_gen IS
GENERIC (
- g_use_src_in : BOOLEAN := TRUE;
+ g_use_src_in : BOOLEAN := FALSE;
g_nof_data_per_block : NATURAL := 11;
- g_nof_blk_per_sync : NATURAL := 8;
+ g_nof_blk_per_sync : NATURAL := 1;
g_enable : t_dp_flow_control_enum := e_active; -- always e_active or e_pulse block generator enable
- g_out_ready : t_dp_flow_control_enum := e_random; -- always e_active, e_random or e_pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
g_nof_repeat : NATURAL := 100
);
END tb_dp_block_gen;
@@ -54,25 +54,36 @@ ARCHITECTURE tb OF tb_dp_block_gen IS
CONSTANT c_pulse_active : NATURAL := 1;
CONSTANT c_pulse_period : NATURAL := 7;
+ CONSTANT c_bsn_init : NATURAL := 3;
+
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC := '1';
+ SIGNAL sl1 : STD_LOGIC := '1';
SIGNAL random : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
SIGNAL pulse : STD_LOGIC;
SIGNAL pulse_en : STD_LOGIC := '1';
SIGNAL enable : STD_LOGIC;
+ SIGNAL ready : STD_LOGIC;
SIGNAL ref_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL out_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL out_sosi : t_dp_sosi;
SIGNAL prev_out_sosi : t_dp_sosi;
SIGNAL prev_out_ready : STD_LOGIC_VECTOR(0 TO c_rl);
- SIGNAL out_gap : STD_LOGIC;
+ SIGNAL out_gap : STD_LOGIC := '0';
+ SIGNAL hold_sop : STD_LOGIC := '0';
+ SIGNAL exp_size : NATURAL := g_nof_data_per_block;
+ SIGNAL cnt_size : NATURAL := 0;
SIGNAL verify_en : STD_LOGIC := '0';
SIGNAL verify_bsn_en : STD_LOGIC := '0';
+ SIGNAL verify_done : STD_LOGIC := '0';
+ SIGNAL verify_valid : STD_LOGIC := '0';
+ SIGNAL verify_sop : STD_LOGIC := '0';
+ SIGNAL verify_eop : STD_LOGIC := '0';
BEGIN
@@ -87,9 +98,9 @@ BEGIN
-- STREAM CONTROL
------------------------------------------------------------------------------
- out_siso.ready <= '1' WHEN g_out_ready=e_active ELSE
- random(random'HIGH) WHEN g_out_ready=e_random ELSE
- pulse WHEN g_out_ready=e_pulse;
+ ready <= '1' WHEN g_out_ready=e_active ELSE
+ random(random'HIGH) WHEN g_out_ready=e_random ELSE
+ pulse WHEN g_out_ready=e_pulse;
------------------------------------------------------------------------------
@@ -115,15 +126,21 @@ BEGIN
-- End of stimuli
proc_common_wait_some_cycles(clk, 100);
+ proc_common_gen_pulse(clk, verify_done);
+ proc_common_wait_some_cycles(clk, 10);
tb_end <= '1';
WAIT;
END PROCESS;
- ref_sosi.valid <= '0' WHEN g_nof_blk_per_sync=0 ELSE out_siso.ready;
+ -- input data
ref_sosi.data <= INCR_UVEC(ref_sosi.data, 1) WHEN out_siso.ready='1' AND rising_edge(clk);
ref_sosi.re <= INCR_UVEC(ref_sosi.re, 2) WHEN out_siso.ready='1' AND rising_edge(clk);
ref_sosi.im <= INCR_UVEC(ref_sosi.im, 3) WHEN out_siso.ready='1' AND rising_edge(clk);
+ -- flow control via input valid or via output ready
+ ref_sosi.valid <= '0' WHEN g_use_src_in=TRUE ELSE ready;
+ out_siso.ready <= '1' WHEN g_use_src_in=FALSE ELSE ready;
+
------------------------------------------------------------------------------
-- VERIFICATION
------------------------------------------------------------------------------
@@ -141,11 +158,25 @@ BEGIN
END LOOP;
END PROCESS;
+ -- Verify that the stimuli have been applied at all
+ verify_valid <= '1' WHEN out_sosi.valid='1' AND rising_edge(clk);
+ verify_sop <= '1' WHEN out_sosi.sop='1' AND rising_edge(clk);
+ verify_eop <= '1' WHEN out_sosi.eop='1' AND rising_edge(clk);
+ proc_dp_verify_value("out_sosi.valid", clk, verify_done, sl1, verify_valid);
+ proc_dp_verify_value("out_sosi.sop", clk, verify_done, sl1, verify_sop);
+ proc_dp_verify_value("out_sosi.eop", clk, verify_done, sl1, verify_eop);
+
-- Verify some general streaming interface properties
proc_dp_verify_valid(c_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_sosi.valid); -- Verify that the out_sosi valid fits with the ready latency
proc_dp_verify_gap_invalid(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, out_gap); -- Verify that the out_sosi valid is low between blocks
proc_dp_verify_data("BSN", clk, verify_bsn_en, out_sosi.sop, out_sosi.bsn, prev_out_sosi.bsn);
-
+
+ -- Verify intervals
+ proc_dp_verify_sync(g_nof_blk_per_sync, c_bsn_init, clk, verify_en, out_sosi.sync, out_sosi.sop, out_sosi.bsn);
+
+ proc_dp_verify_sop_and_eop(c_rl, clk, out_siso.ready, out_sosi.valid, out_sosi.sop, out_sosi.eop, hold_sop);
+
+ proc_dp_verify_block_size(exp_size, clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, cnt_size);
------------------------------------------------------------------------------
-- DUT : dp_block_gen
@@ -158,7 +189,8 @@ BEGIN
g_nof_blk_per_sync => g_nof_blk_per_sync,
g_empty => 1,
g_channel => 2,
- g_error => 3
+ g_error => 3,
+ g_bsn => c_bsn_init
)
PORT MAP (
rst => rst,