diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold index 77fe32282999f98d955ee7d3314b3bb96d38d831..ae1a70b3986901025ae0c3a48f5b42bde0470b4b 100644 --- a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold +++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold @@ -14,7 +14,7 @@ number_of_columns = 11 # # col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 # ------------------------ ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- - ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO - - - + ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0] PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] - - - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] - - - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] - @@ -32,10 +32,10 @@ number_of_columns = 11 PIO_WDI 1 1 REG wdi_override 0x0000a000 1 WO uint32 b[31:0] - REG_FPGA_TEMP_SENS 1 1 REG temp 0x0000c000 1 RO uint32 b[31:0] - REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0000c000 6 RO uint32 b[31:0] - - RAM_SCRAP 1 1 RAM data 0x0000e000 512 RW - - - + RAM_SCRAP 1 1 RAM data 0x0000e000 512 RW uint32 b[31:0] - AVS_ETH_0_TSE 1 1 REG status 0x00010000 1024 RO uint32 b[31:0] - AVS_ETH_0_REG 1 1 REG status 0x00010000 12 RO uint32 b[31:0] - - AVS_ETH_0_RAM 1 1 RAM data 0x00010400 1024 RW - - - + AVS_ETH_0_RAM 1 1 RAM data 0x00010400 1024 RW uint32 b[31:0] - PIO_PPS 1 1 REG capture_cnt 0x00012000 1 RO uint32 b[29:0] - - - - - stable 0x00012000 1 RO uint32 b[30:30] - - - - - toggle 0x00012000 1 RO uint32 b[31:31] - @@ -50,10 +50,10 @@ number_of_columns = 11 - - - - busy 0x00014005 1 RO uint32 b[0:0] - - - - - unprotect 0x00014006 1 WO uint32 b[31:0] - REG_DPMM_CTRL 1 1 REG rd_usedw 0x00016000 1 RO uint32 b[31:0] - - REG_DPMM_DATA 1 1 FIFO data 0x00016400 1 RO - - - + REG_DPMM_DATA 1 1 FIFO data 0x00016400 1 RO uint32 b[31:0] - REG_MMDP_CTRL 1 1 REG wr_usedw 0x00018000 1 RO uint32 b[31:0] - - - - - wr_availw 0x00018001 1 RO uint32 b[31:0] - - REG_MMDP_DATA 1 1 FIFO data 0x00018400 1 WO - - - + REG_MMDP_DATA 1 1 FIFO data 0x00018400 1 WO uint32 b[31:0] - REG_REMU 1 1 REG reconfigure 0x0001a000 1 WO uint32 b[31:0] - - - - - param 0x0001a001 1 WO uint32 b[2:0] - - - - - read_param 0x0001a002 1 WO uint32 b[0:0] - @@ -115,19 +115,20 @@ number_of_columns = 11 - - - - phase 0x00028001 1 RW uint32 b[15:0] - - - - - freq 0x00028002 1 RW uint32 b[30:0] - - - - - ampl 0x00028003 1 RW uint32 b[16:0] - - RAM_DIAG_WG 1 12 RAM data 0x0002c000 1024 RW - - - + RAM_DIAG_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] - REG_ADUH_MON 1 12 REG mean_sum_lo 0x00030000 1 RO uint32 b[31:0] - - - - - mean_sum_hi 0x00030001 1 RO uint32 b[31:0] - - - - - power_sum_lo 0x00030002 1 RO uint32 b[31:0] - - - - - power_sum_hi 0x00030003 1 RO uint32 b[31:0] - REG_DIAG_DATA_BUF_BSN 1 12 REG sync_cnt 0x00032000 1 RO uint32 b[31:0] - - - - - word_cnt 0x00032001 1 RO uint32 b[31:0] - - RAM_DIAG_DATA_BUF_BSN 1 12 RAM data 0x00034000 1024 RW - - - + RAM_DIAG_DATA_BUF_BSN 1 12 RAM data 0x00034000 1024 RW uint32 b[15:0] - REG_SI 1 1 REG enable 0x00038000 1 RW uint32 b[0:0] - - RAM_FIL_COEFS 1 16 RAM data 0x0003c000 1024 RW - - - - RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW - - - + RAM_FIL_COEFS 1 16 RAM data 0x0003c000 1024 RW uint32 b[15:0] - + RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - REG_DP_SELECTOR 1 1 REG input_select 0x00042000 1 RW uint32 b[0:0] - - RAM_ST_SST 1 6 RAM data 0x00044000 2048 RW - - - + RAM_ST_SST 1 6 RAM data 0x00044000 2048 RW uint64 b[31:0] b[31:0] + - - - - - 0x00042001 - - - b[21:0] b[53:32] REG_STAT_ENABLE 1 1 REG enable 0x00048000 1 RW uint32 b[0:0] - REG_STAT_HDR_INFO 1 1 REG bsn 0x0004a000 1 RW uint64 b[31:0] b[31:0] - - - - - 0x0004a001 - - - b[31:0] b[63:32] @@ -190,8 +191,8 @@ number_of_columns = 11 - - - - n_rn 0x0004c00b 1 RW uint32 b[7:0] - - - - - block_period 0x0004c00c 1 RO uint32 b[15:0] - - - - - beamlet_scale 0x0004c00d 1 RW uint32 b[15:0] - - RAM_SS_SS_WIDE 2 6 RAM data 0x0004e000 976 RW - - - - RAM_BF_WEIGHTS 2 12 RAM data 0x00054000 976 RW - - - + RAM_SS_SS_WIDE 2 6 RAM data 0x0004e000 976 RW uint32 b[9:0] - + RAM_BF_WEIGHTS 2 12 RAM data 0x00054000 976 RW cint16_ir b[31:0] - REG_BF_SCALE 2 1 REG scale 0x0005c000 1 RW uint32 b[15:0] - - - - - unused 0x0005c001 1 RW uint32 b[31:0] - REG_HDR_DAT 2 1 REG bsn 0x0005e000 1 RW uint64 b[31:0] b[31:0] @@ -238,7 +239,8 @@ number_of_columns = 11 - - - - eth_destination_mac 0x0005e021 1 RW uint64 b[31:0] b[31:0] - - - - - 0x0005e022 - - - b[15:0] b[47:32] REG_DP_XONOFF 2 1 REG enable_stream 0x00060000 1 RW uint32 b[0:0] - - RAM_ST_BST 2 1 RAM data 0x00062000 1952 RW - - - + RAM_ST_BST 2 1 RAM data 0x00062000 1952 RW uint64 b[31:0] b[31:0] + - - - - - 0x00060001 - - - b[21:0] b[53:32] REG_STAT_ENABLE_BST 1 1 REG enable 0x00064000 1 RW uint32 b[0:0] - REG_STAT_HDR_INFO_BST 1 1 REG bsn 0x00066000 1 RW uint64 b[31:0] b[31:0] - - - - - 0x00066001 - - - b[31:0] b[63:32]