diff --git a/applications/arts/designs/arts_unb1_sc1_bg_1GbE/tb/vhdl/tb_arts_unb1_sc1_bg_1GbE.vhd b/applications/arts/designs/arts_unb1_sc1_bg_1GbE/tb/vhdl/tb_arts_unb1_sc1_bg_1GbE.vhd
index cce786c2dec07b1a83b03f8f11d3156113934796..192f9300a0402ecef193b2ac01d5e7609df97039 100644
--- a/applications/arts/designs/arts_unb1_sc1_bg_1GbE/tb/vhdl/tb_arts_unb1_sc1_bg_1GbE.vhd
+++ b/applications/arts/designs/arts_unb1_sc1_bg_1GbE/tb/vhdl/tb_arts_unb1_sc1_bg_1GbE.vhd
@@ -36,46 +36,48 @@ END tb_arts_unb1_sc1_bg_1GbE;
ARCHITECTURE tb OF tb_arts_unb1_sc1_bg_1GbE IS
- CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_sim : BOOLEAN := TRUE;
- CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
- CONSTANT c_node_nr : NATURAL := 7; -- Back node 3
- CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 7; -- Back node 3
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
- CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
- CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0);
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0);
- CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
- CONSTANT c_clk_period : TIME := 5 ns;
- CONSTANT c_pps_period : NATURAL := 1000;
+ CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
+ CONSTANT c_clk_period : TIME := 5 ns;
+ CONSTANT c_pps_period : NATURAL := 1000;
-- DUT
- SIGNAL clk : STD_LOGIC := '0';
- SIGNAL pps : STD_LOGIC := '0';
- SIGNAL pps_rst : STD_LOGIC := '0';
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
- SIGNAL WDI : STD_LOGIC;
- SIGNAL INTA : STD_LOGIC;
- SIGNAL INTB : STD_LOGIC;
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
- SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_clk : STD_LOGIC := '0';
- SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version;
- SIGNAL ID : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id;
- SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version;
+ SIGNAL ID : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id;
+ SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-- Ethernet stats
- SIGNAL eth_statistics_serial_in : STD_LOGIC;
- SIGNAL eth_statistics_pkt_cnt : NATURAL;
- SIGNAL eth_statistics_pkt_len : NATURAL;
+ CONSTANT c_eth_check_nof_packets : NATURAL := 10;
+ CONSTANT c_eth_packet_size : NATURAL := 1221; --(24 subbands*50 timesamples=) 1200 (2pols*16b=) 32b words + 21 header words
+
+ SIGNAL eth_statistics_serial_in : STD_LOGIC;
+ SIGNAL tb_end : STD_LOGIC;
BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
+ clk <= NOT clk OR tb_end AFTER c_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk OR tb_end AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
------------------------------------------------------------------------------
-- External PPS
@@ -106,12 +108,15 @@ BEGIN
-- Verify proper DUT output using Ethernet packet statistics
------------------------------------------------------------------------------
u_eth_statistics : ENTITY eth_lib.eth_statistics
+ GENERIC MAP (
+ g_runtime_nof_packets => c_eth_check_nof_packets,
+ g_runtime_timeout => 1000000 ns,
+ g_check_nof_valid => TRUE,
+ g_check_nof_valid_ref => c_eth_check_nof_packets*c_eth_packet_size
+ )
PORT MAP (
- eth_clk => eth_clk,
eth_serial_in => eth_statistics_serial_in,
-
- pkt_cnt => eth_statistics_pkt_cnt,
- pkt_len => eth_statistics_pkt_len
+ tb_end => tb_end
);
END tb;