diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg
index 69ff415e9630d8b6a2d69d16751657d5f1c7775f..f37420dc518785494f820ed0ff46347f2f3f05e8 100644
--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = ip_stratixiv_tse_sgmii_lvds
hdl_library_clause_name = ip_stratixiv_tse_sgmii_lvds_lib
-hdl_lib_uses = technology
+hdl_lib_uses = common
build_sim_dir = $HDL_BUILD_DIR
build_synth_dir =
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd
index 4a8642d22031d454678cd3b23ed32572de9ecfa4..3e52d14989e89dadf910eae568973e362eeabddf 100644
--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd
@@ -30,10 +30,10 @@
-- > as 10
-- > run 50 us
-LIBRARY IEEE, technology_lib;
+LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
-USE technology_lib.technology_pkg.ALL;
+USE common_lib.common_pkg.ALL;
ENTITY tb_ip_stratixiv_tse_sgmii_lvds IS
@@ -258,15 +258,15 @@ ARCHITECTURE tb OF tb_ip_stratixiv_tse_sgmii_lvds IS
-- DST MAC
dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w));
dp_src_out.data <= (OTHERS=>'0');
- dp_src_out.data(15 DOWNTO 0) <= tech_hton(dst_mac_addr(15 DOWNTO 0)); -- send to itself
+ dp_src_out.data(15 DOWNTO 0) <= hton(dst_mac_addr(15 DOWNTO 0)); -- send to itself
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '1', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
- dp_src_out.data <= tech_hton(dst_mac_addr(47 DOWNTO 16));
+ dp_src_out.data <= hton(dst_mac_addr(47 DOWNTO 16));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
-- SRC MAC
- dp_src_out.data <= tech_hton(src_mac_addr(31 DOWNTO 0));
+ dp_src_out.data <= hton(src_mac_addr(31 DOWNTO 0));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
-- SRC MAC & ETHERTYPE
- dp_src_out.data <= tech_hton(src_mac_addr(47 DOWNTO 32)) & tech_hton(c_eth_ethertype);
+ dp_src_out.data <= hton(src_mac_addr(47 DOWNTO 32)) & hton(c_eth_ethertype);
-- DATA
FOR I IN 0 TO c_nof_data_beats-1 LOOP
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
@@ -344,16 +344,16 @@ ARCHITECTURE tb OF tb_ip_stratixiv_tse_sgmii_lvds IS
-- Verify DST MAC
proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
ASSERT dp_snk_in.data(31 DOWNTO 16) = X"0000" REPORT "RX: Alignment half word not zero" SEVERITY ERROR;
- ASSERT dp_snk_in.data(15 DOWNTO 0) = tech_hton(dst_mac_addr(15 DOWNTO 0)) REPORT "RX: Wrong dst_mac_addr(15 DOWNTO 0)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(dst_mac_addr(15 DOWNTO 0)) REPORT "RX: Wrong dst_mac_addr(15 DOWNTO 0)" SEVERITY ERROR;
proc_valid(dp_clk, dp_snk_in.valid);
- ASSERT dp_snk_in.data(31 DOWNTO 0) = tech_hton(dst_mac_addr(47 DOWNTO 16)) REPORT "RX: Wrong dst_mac_addr(47 DOWNTO 16)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(dst_mac_addr(47 DOWNTO 16)) REPORT "RX: Wrong dst_mac_addr(47 DOWNTO 16)" SEVERITY ERROR;
-- Verify SRC MAC
proc_valid(dp_clk, dp_snk_in.valid);
- ASSERT dp_snk_in.data(31 DOWNTO 0) = tech_hton(src_mac_addr(31 DOWNTO 0)) REPORT "RX: Wrong src_mac_addr(31 DOWNTO 0)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(src_mac_addr(31 DOWNTO 0)) REPORT "RX: Wrong src_mac_addr(31 DOWNTO 0)" SEVERITY ERROR;
-- Verify SRC MAC & ETHERTYPE
proc_valid(dp_clk, dp_snk_in.valid);
- ASSERT dp_snk_in.data(31 DOWNTO 16) = tech_hton(src_mac_addr(47 DOWNTO 32)) REPORT "RX: Wrong src_mac_addr(47 DOWNTO 32)" SEVERITY ERROR;
- ASSERT dp_snk_in.data(15 DOWNTO 0) = tech_hton(c_eth_ethertype) REPORT "RX: Wrong ethertype" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(31 DOWNTO 16) = hton(src_mac_addr(47 DOWNTO 32)) REPORT "RX: Wrong src_mac_addr(47 DOWNTO 32)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(c_eth_ethertype) REPORT "RX: Wrong ethertype" SEVERITY ERROR;
-- Verify DATA
v_first := TRUE;
proc_valid(dp_clk, dp_snk_in.valid);
diff --git a/libraries/technology/technology_pkg.vhd b/libraries/technology/technology_pkg.vhd
index 53d62326c5e9d8cf3801fd4caea59be663e63d54..7f7aed5f48147eda72816f745aba5bb31481866d 100644
--- a/libraries/technology/technology_pkg.vhd
+++ b/libraries/technology/technology_pkg.vhd
@@ -19,6 +19,20 @@
--
-------------------------------------------------------------------------------
+-- Purpose: Define the list of FPGA technology identifiers
+-- Description:
+-- The technology dependent IP is organised per FPGA device type. Each FPGA
+-- type that is supported has a c_tech_<device_name> identifier constant.
+-- Remark:
+-- . The package also contains some low level functions that often are copied
+-- from common_pkg.vhd. They need to be redefined in this technology_pkg.vhd
+-- because the common_lib also use technology dependent IP like RAM, FIFO,
+-- DDIO. Therefore common_lib can not be used in the IP wrappers for those
+-- IP blocks, because common_lib is compiled later.
+-- . For technology wrappers that are not used by components in common_lib the
+-- common_pkg.vhd can be used. Similar technology wrappers that are not used
+-- by components in dp_lib can use the dp_stream_pkg.
+
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.MATH_REAL.ALL;
@@ -35,15 +49,14 @@ PACKAGE technology_pkg IS
CONSTANT c_tech_nof_technologies : INTEGER := 6;
-- Functions
- FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING;
+ FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING;
+ FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : INTEGER) RETURN INTEGER;
FUNCTION tech_true_log2(n : NATURAL) RETURN NATURAL; -- tech_true_log2(n) = log2(n)
FUNCTION tech_ceil_log2(n : NATURAL) RETURN NATURAL; -- tech_ceil_log2(n) = log2(n), but force tech_ceil_log2(1) = 1
FUNCTION tech_ceil_div(n, d : NATURAL) RETURN NATURAL; -- tech_ceil_div = n/d + (n MOD d)/=0
-
- FUNCTION tech_hton(a :IN STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- convert endianity from host to network byte order or vice versa
-
+
FUNCTION tech_nat_to_mbps_str( n : IN NATURAL ) RETURN STRING;
END technology_pkg;
@@ -54,6 +67,11 @@ PACKAGE BODY technology_pkg IS
BEGIN
IF sel=TRUE THEN RETURN a; ELSE RETURN b; END IF;
END;
+
+ FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : INTEGER) RETURN INTEGER IS
+ BEGIN
+ IF sel=TRUE THEN RETURN a; ELSE RETURN b; END IF;
+ END;
FUNCTION tech_true_log2(n : NATURAL) RETURN NATURAL IS
-- Purpose: For calculating extra vector width of existing vector
@@ -90,21 +108,7 @@ PACKAGE BODY technology_pkg IS
FUNCTION tech_ceil_div(n, d : NATURAL) RETURN NATURAL IS
BEGIN
- RETURN n/d + sel_a_b(n MOD d = 0, 0, 1);
- END;
-
- FUNCTION tech_hton(a :IN STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
- CONSTANT c_sz : NATURAL := a'LENGTH/c_byte_w;
- VARIABLE vA : STD_LOGIC_VECTOR(a'LENGTH-1 DOWNTO 0) := a; -- map a to range [h:0]
- BEGIN
- CASE c_sz IS
- WHEN 1 => NULL;
- WHEN 2 => vA := a(7 DOWNTO 0) & a(15 DOWNTO 8);
- WHEN 4 => vA := a(7 DOWNTO 0) & a(15 DOWNTO 8) & a(23 DOWNTO 16) & a(31 DOWNTO 24);
- WHEN OTHERS =>
- REPORT "tech_hton only supports size of 1, 2 or 4 bytes" SEVERITY FAILURE;
- END CASE;
- RETURN vA;
+ RETURN n/d + tech_sel_a_b(n MOD d = 0, 0, 1);
END;
FUNCTION tech_nat_to_mbps_str( n : IN NATURAL ) RETURN STRING IS -- Converts a selection of naturals to Mbps strings, used for edited MegaWizard file in ip_stratixiv_hssi_*_generic.vhd