From 1e2a23f24733df57d4ac53f18e75612fe7c6f46d Mon Sep 17 00:00:00 2001
From: Jonathan Hargreaves <hargreaves@astron.nl>
Date: Fri, 16 Oct 2015 14:22:47 +0000
Subject: [PATCH] Commented modelsim_compile_ip_files because there is no
 simulation model for the FPGA voltage sensor IP.

---
 libraries/technology/ip_arria10/voltage_sense/hdllib.cfg | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
index 5b0fcb4501..1c0b337feb 100644
--- a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
@@ -5,8 +5,9 @@ hdl_lib_uses_sim =
 
 hdl_lib_technology = ip_arria10
 
-modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
+# There is no simulation model for the FPGA voltage sensor IP
+#modelsim_compile_ip_files =
+#    $RADIOHDL/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
 
 synth_files =
     
-- 
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