diff --git a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
index 5b0fcb4501deb1da7f2999d2b2f8e9e45cec3839..1c0b337feb7bedd1c9eac6c898e1d344d8115af5 100644
--- a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
@@ -5,8 +5,9 @@ hdl_lib_uses_sim =
 
 hdl_lib_technology = ip_arria10
 
-modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
+# There is no simulation model for the FPGA voltage sensor IP
+#modelsim_compile_ip_files =
+#    $RADIOHDL/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
 
 synth_files =