From 1e1a147cb226bd5e972344b33158419c436524a2 Mon Sep 17 00:00:00 2001 From: Erik Kooistra <kooistra@astron.nl> Date: Mon, 17 Nov 2014 16:47:37 +0000 Subject: [PATCH] Added description of tools/quartus/run_altera_simlib_comp for compiling the Altera libraries for simulation with Modelsim. --- tools/hdltool_readme.txt | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/tools/hdltool_readme.txt b/tools/hdltool_readme.txt index 2b6af0f619..7d4a243c6f 100644 --- a/tools/hdltool_readme.txt +++ b/tools/hdltool_readme.txt @@ -28,7 +28,8 @@ Contents: c) Simulation 7) Synthesis in Quartus - a) Creating the Quartus project files + a) Compiling the Altera libraries for simulation with Modelsim + b) Creating the Quartus project files 8) Design revisions @@ -427,7 +428,16 @@ entire eth library gets verified in one simulation. 7) Synthesis in Quartus -a) Creating the Quartus project files +a) Compiling the Altera libraries for simulation with Modelsim + +The Altera verilog and vhdl libraries for the required FPGA device families can be compile using: + + > tools/quartus/run_altera_simlib_comp <tool target> <compilation output directory> <FPGA device family> + +This script must be used and not the tools/Launch simulation library compiler in the Quartus GUI, because +the libraries have to be compiled with the 'vlib -type directory' option to be able to use 'mk all'. + +b) Creating the Quartus project files The quartus_config.py creates the Quartus qpf, qsf and or qip files for a design library. -- GitLab