diff --git a/tools/hdltool_readme.txt b/tools/hdltool_readme.txt
index 2b6af0f6192ff1eed0536b98bc9502bb54d306bd..7d4a243c6fdc730444fdc2b067adda66c5e68cd7 100644
--- a/tools/hdltool_readme.txt
+++ b/tools/hdltool_readme.txt
@@ -28,7 +28,8 @@ Contents:
   c) Simulation
   
 7) Synthesis in Quartus
-  a) Creating the Quartus project files
+  a) Compiling the Altera libraries for simulation with Modelsim
+  b) Creating the Quartus project files
 
 8) Design revisions
   
@@ -427,7 +428,16 @@ entire eth library gets verified in one simulation.
 
 7) Synthesis in Quartus
 
-a) Creating the Quartus project files
+a) Compiling the Altera libraries for simulation with Modelsim
+
+The Altera verilog and vhdl libraries for the required FPGA device families can be compile using:
+
+ > tools/quartus/run_altera_simlib_comp <tool target> <compilation output directory> <FPGA device family>
+
+This script must be used and not the tools/Launch simulation library compiler in the Quartus GUI, because
+the libraries have to be compiled with the 'vlib -type directory' option to be able to use 'mk all'.
+
+b) Creating the Quartus project files
 
 The quartus_config.py creates the Quartus qpf, qsf and or qip files for a design library.