diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
index 58b475f24bdb53728f064bad47966fcf0b89806a..879c30d8f8b6727020208e38f6fe5331c94809d8 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
@@ -330,12 +330,11 @@ BEGIN
u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
GENERIC MAP (
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
)
PORT MAP (
green_led_arr => qsfp_green_led_arr,
red_led_arr => qsfp_red_led_arr,
-
QSFP_LED => QSFP_LED
);
diff --git a/boards/uniboard2/designs/unb2_test/hdllib.cfg b/boards/uniboard2/designs/unb2_test/hdllib.cfg
index 8c70cfcd1934e45a338704718a092c00e18622cb..86dae878650fcc30515769e711843719de1f1429 100644
--- a/boards/uniboard2/designs/unb2_test/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/hdllib.cfg
@@ -1,6 +1,5 @@
hdl_lib_name = unb2_test
hdl_library_clause_name = unb2_test_lib
-#hdl_lib_uses = common mm unb2_board
hdl_lib_uses = common technology mm unb2_board dp eth tech_tse tr_10GbE diagnostics diag
hdl_lib_technology = ip_arria10
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index e6615152b45705fd8c2b32c900f2fc4d88e58326..e54990ce65e8e72f025e511d7a6f1e6db7cbfb0c 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -131,8 +131,8 @@ ENTITY ctrl_unb2_board IS
this_chip_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_chip_w-1 DOWNTO 0); -- [1:0], so range 0-3 for PN
this_bck_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_uniboard_w-1 DOWNTO 0); -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
- app_led_red : IN STD_LOGIC := '0';
- app_led_green : IN STD_LOGIC := '1';
+ app_led_red : IN STD_LOGIC := '0';
+ app_led_green : IN STD_LOGIC := '1';
-- PIOs
pout_wdi : IN STD_LOGIC; -- Toggled by unb_osy; can be overriden by reg_wdi.
@@ -227,10 +227,11 @@ ARCHITECTURE str OF ctrl_unb2_board IS
SIGNAL i_mm_rst : STD_LOGIC;
SIGNAL i_mm_clk : STD_LOGIC;
SIGNAL i_mm_locked : STD_LOGIC;
- SIGNAL i_epcs_clk : STD_LOGIC;
- SIGNAL i_clk125 : STD_LOGIC;
- SIGNAL i_clk100 : STD_LOGIC;
- SIGNAL i_clk50 : STD_LOGIC;
+ SIGNAL i_epcs_clk : STD_LOGIC := '1';
+ SIGNAL i_clk125 : STD_LOGIC := '1';
+ SIGNAL i_clk100 : STD_LOGIC := '1';
+ SIGNAL i_clk50 : STD_LOGIC := '1';
+ SIGNAL i_dp_clk : STD_LOGIC := '1';
SIGNAL mm_wdi : STD_LOGIC;
SIGNAL eth1g_st_clk : STD_LOGIC;
@@ -288,27 +289,39 @@ BEGIN
TESTIO <= (OTHERS=>'Z'); -- Leave unused INOUT tri-state
-- Clock and reset
- i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
- ext_clk200 <= CLK; -- use the external 200 MHz CLK as ext_clk
- ext_pps <= PPS; -- use more special name for PPS pin signal to ease searching for it in editor
+ i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
+ ext_clk200 <= CLK; -- use the external 200 MHz CLK as ext_clk
+ ext_pps <= PPS; -- use more special name for PPS pin signal to ease searching for it in editor
dp_dis <= i_mm_rst; -- could use software control for this instead
- gen_pll: IF g_dp_clk_use_pll = TRUE GENERATE
- u_unb2_board_clk200_pll : ENTITY work.unb2_board_clk200_pll
- GENERIC MAP (
- g_technology => g_technology,
- g_clk200_phase_shift => g_dp_clk_phase
- )
- PORT MAP (
- arst => dp_dis,
- clk200 => ext_clk200,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => dp_rst
- );
+
+
+ gen_pll_dp_clk: IF g_dp_clk_use_pll = TRUE GENERATE
+ gen_pll_dp_clk_sim: IF g_sim = TRUE GENERATE
+ dp_clk <= i_dp_clk;
+ dp_rst <= '1', '0' AFTER 10 ns;
+ i_dp_clk <= NOT i_dp_clk AFTER 2.5 ns; -- 200MHz , 5ns/2
+ END GENERATE;
+
+ gen_pll_dp_clk_pll: IF g_sim = FALSE GENERATE
+ u_unb2_board_clk200_pll : ENTITY work.unb2_board_clk200_pll
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ PORT MAP (
+ arst => dp_dis,
+ clk200 => ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => dp_rst
+ );
+ END GENERATE;
END GENERATE;
- no_pll: IF g_dp_clk_use_pll = FALSE GENERATE
+
+
+ no_pll_dp_clk: IF g_dp_clk_use_pll = FALSE GENERATE
dp_rst <= node_ctrl_dp_rst_out;
node_ctrl_dp_clk_in <= dp_clk_in;
END GENERATE;
@@ -329,20 +342,29 @@ BEGIN
- u_unb2_board_clk125_pll : ENTITY work.unb2_board_clk125_pll
- GENERIC MAP (
- g_technology => g_technology
- )
- PORT MAP (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c0_clk20 => i_epcs_clk,
- c1_clk50 => i_clk50,
- c2_clk100 => i_clk100,
- c3_clk125 => i_clk125,
- pll_locked => i_mm_locked
- );
+ gen_pll_mm_clk_sim: IF g_sim = TRUE GENERATE
+ i_mm_locked <= '0', '1' AFTER 70 ns;
+ i_epcs_clk <= NOT i_epcs_clk AFTER 25 ns; -- 20 MHz, 50ns/2
+ i_clk50 <= NOT i_clk50 AFTER 10 ns; -- 50 MHz, 20ns/2
+ i_clk100 <= NOT i_clk100 AFTER 5 ns; -- 100 MHz, 10ns/2
+ i_clk125 <= NOT i_clk125 AFTER 4 ns; -- 125 MHz, 8ns/2
+ END GENERATE;
+ gen_pll_mm_clk_pll: IF g_sim = FALSE GENERATE
+ u_unb2_board_clk125_pll : ENTITY work.unb2_board_clk125_pll
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => i_epcs_clk,
+ c1_clk50 => i_clk50,
+ c2_clk100 => i_clk100,
+ c3_clk125 => i_clk125,
+ pll_locked => i_mm_locked
+ );
+ END GENERATE;
i_tse_clk <= i_xo_ethclk;
@@ -469,6 +491,7 @@ BEGIN
-- Every design instantiates an mms_remu instance + MM status & control ports.
-- So there is full control over the memory mapped registers to set start address of the flash
-- and reconfigure from that address.
+ --gen_mms_remu: IF g_sim = FALSE GENERATE
u_mms_remu: ENTITY remu_lib.mms_remu
GENERIC MAP (
g_technology => g_technology
@@ -482,10 +505,12 @@ BEGIN
remu_mosi => reg_remu_mosi,
remu_miso => reg_remu_miso
);
+ --END GENERATE;
-----------------------------------------------------------------------------
-- EPCS
-----------------------------------------------------------------------------
+ --gen_mms_epcs: IF g_sim = FALSE GENERATE
u_mms_epcs: ENTITY epcs_lib.mms_epcs
GENERIC MAP (
g_technology => g_technology
@@ -511,6 +536,7 @@ BEGIN
mmdp_data_mosi => reg_mmdp_data_mosi,
mmdp_data_miso => reg_mmdp_data_miso
);
+ --END GENERATE;
------------------------------------------------------------------------------
-- PPS input
@@ -592,6 +618,8 @@ BEGIN
eth1g_st_rst <= i_mm_rst;
END GENERATE;
+
+ gen_mac: IF g_sim = FALSE GENERATE
u_mac : ENTITY eth_lib.eth
GENERIC MAP (
g_technology => g_technology,
@@ -628,5 +656,6 @@ BEGIN
-- LED interface
tse_led => eth1g_led
);
+ END GENERATE;
END str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
index 37d5c14ced31b82bce63111c5ca8972d585ee9ac..8142ed4527a9840b4b19c806788f9fb1da0b1737 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
@@ -25,37 +25,44 @@ USE work.unb2_board_pkg.ALL;
ENTITY unb2_board_back_io IS
+ GENERIC (
+ g_nof_back_bus : NATURAL := c_unb2_board_tr_back.nof_bus
+ );
PORT (
- serial_tx_arr : IN STD_LOGIC_VECTOR(c_unb2_board_tr_back_hw_nof_lines-1 DOWNTO 0);
- serial_rx_arr : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_back_hw_nof_lines-1 DOWNTO 0);
+ serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_back_bus * c_unb2_board_tr_back.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_back_bus * c_unb2_board_tr_back.bus_w-1 DOWNTO 0);
-- back transceivers
- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
- BCK_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
+ BCK_RX : IN t_unb2_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+ BCK_TX : OUT t_unb2_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0);
- BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
- BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
- BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0)
+ BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 DOWNTO 0);
+ BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 DOWNTO 0);
+ BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 DOWNTO 0)
);
END unb2_board_back_io;
ARCHITECTURE str OF unb2_board_back_io IS
-- help signals so we can iterate through buses
- SIGNAL si_tx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_back_hw_nof_lines-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL si_rx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_back_hw_nof_lines-1 DOWNTO 0);
+ SIGNAL si_tx_2arr : t_unb2_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0);
+ SIGNAL si_rx_2arr : t_unb2_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0);
BEGIN
- connect_back : FOR i IN 0 TO c_unb2_board_tr_back_hw_nof_lines-1 GENERATE
- BCK_TX(i) <= si_tx_arr(i);
- si_rx_arr(i) <= BCK_RX(i);
+ gen_buses : FOR i IN 0 TO g_nof_back_bus-1 GENERATE
+ BCK_TX(i) <= si_tx_2arr(i);
+ si_rx_2arr(i) <= BCK_RX(i);
END GENERATE;
- wire_signals : FOR i IN 0 TO c_unb2_board_tr_back_hw_nof_lines-1 GENERATE
- si_tx_arr(i) <= serial_tx_arr(i);
- serial_rx_arr(i) <= si_rx_arr(i);
+ gen_wire_bus : FOR i IN 0 TO g_nof_back_bus-1 GENERATE
+ gen_wire_signals : FOR j IN 0 TO c_unb2_board_tr_back.bus_w-1 GENERATE
+
+ si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2_board_tr_back.bus_w + j);
+ serial_rx_arr(i*c_unb2_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
+
+ END GENERATE;
END GENERATE;
END;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
index a20c7dff0c20264cf75cd47b395321ba95c95968..f79e563dbf3d53363895cd1fc616a02fd9f4db09 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
@@ -26,17 +26,17 @@ USE work.unb2_board_pkg.ALL;
ENTITY unb2_board_front_io IS
GENERIC (
- g_nof_qsfp : NATURAL := c_unb2_board_tr_qsfp.nof_bus
+ g_nof_qsfp_bus : NATURAL := c_unb2_board_tr_qsfp.nof_bus
);
PORT (
- serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_qsfp * c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_qsfp * c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_qsfp_bus * c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_qsfp_bus * c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
- green_led_arr : IN STD_LOGIC_VECTOR(g_nof_qsfp-1 DOWNTO 0) := (OTHERS=>'0');
- red_led_arr : IN STD_LOGIC_VECTOR(g_nof_qsfp-1 DOWNTO 0) := (OTHERS=>'0');
+ green_led_arr : IN STD_LOGIC_VECTOR(g_nof_qsfp_bus-1 DOWNTO 0) := (OTHERS=>'0');
+ red_led_arr : IN STD_LOGIC_VECTOR(g_nof_qsfp_bus-1 DOWNTO 0) := (OTHERS=>'0');
- QSFP_RX : IN t_unb2_board_qsfp_bus_2arr(g_nof_qsfp-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
- QSFP_TX : OUT t_unb2_board_qsfp_bus_2arr(g_nof_qsfp-1 DOWNTO 0);
+ QSFP_RX : IN t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+ QSFP_TX : OUT t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0);
QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
@@ -49,24 +49,24 @@ END unb2_board_front_io;
ARCHITECTURE str OF unb2_board_front_io IS
-- help signals so we can iterate through buses
- SIGNAL si_tx_2arr : t_unb2_board_qsfp_bus_2arr(g_nof_qsfp-1 DOWNTO 0);
- SIGNAL si_rx_2arr : t_unb2_board_qsfp_bus_2arr(g_nof_qsfp-1 DOWNTO 0);
+ SIGNAL si_tx_2arr : t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0);
+ SIGNAL si_rx_2arr : t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0);
BEGIN
- gen_leds : FOR i IN 0 TO g_nof_qsfp-1 GENERATE
+ gen_leds : FOR i IN 0 TO g_nof_qsfp_bus-1 GENERATE
QSFP_LED(i*2) <= green_led_arr(i);
QSFP_LED(i*2+1) <= red_led_arr(i);
END GENERATE;
- gen_buses : FOR i IN 0 TO g_nof_qsfp-1 GENERATE
+ gen_buses : FOR i IN 0 TO g_nof_qsfp_bus-1 GENERATE
QSFP_TX(i) <= si_tx_2arr(i);
si_rx_2arr(i) <= QSFP_RX(i);
END GENERATE;
- gen_wire_bus : FOR i IN 0 TO g_nof_qsfp-1 GENERATE
+ gen_wire_bus : FOR i IN 0 TO g_nof_qsfp_bus-1 GENERATE
gen_wire_signals : FOR j IN 0 TO c_unb2_board_tr_qsfp.bus_w-1 GENERATE
si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2_board_tr_qsfp.bus_w + j);
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
index 107618feaadd8e1c9cc126a1d31bd598448d3980..2c924997a546d3de8092e6107b80f868482b3617 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
@@ -26,33 +26,32 @@ USE work.unb2_board_pkg.ALL;
ENTITY unb2_board_ring_io IS
GENERIC (
- g_nof_ring_io : NATURAL := c_unb2_board_tr_ring.nof_bus
+ g_nof_ring_bus : NATURAL := c_unb2_board_tr_ring.nof_bus
);
PORT (
- serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_ring_io * c_unb2_board_tr_ring.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_ring_io * c_unb2_board_tr_ring.bus_w-1 DOWNTO 0);
+ serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_ring_bus * c_unb2_board_tr_ring.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_ring_bus * c_unb2_board_tr_ring.bus_w-1 DOWNTO 0);
- -- ring transceivers
- RING_RX : IN t_unb2_board_ring_bus_2arr(g_nof_ring_io-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
- RING_TX : OUT t_unb2_board_ring_bus_2arr(g_nof_ring_io-1 DOWNTO 0)
+ RING_RX : IN t_unb2_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+ RING_TX : OUT t_unb2_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0)
);
END unb2_board_ring_io;
ARCHITECTURE str OF unb2_board_ring_io IS
-- help signals so we can iterate through buses
- SIGNAL si_tx_2arr : t_unb2_board_ring_bus_2arr(g_nof_ring_io-1 DOWNTO 0);
- SIGNAL si_rx_2arr : t_unb2_board_ring_bus_2arr(g_nof_ring_io-1 DOWNTO 0);
+ SIGNAL si_tx_2arr : t_unb2_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0);
+ SIGNAL si_rx_2arr : t_unb2_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0);
BEGIN
- gen_buses : FOR i IN 0 TO g_nof_ring_io-1 GENERATE
+ gen_buses : FOR i IN 0 TO g_nof_ring_bus-1 GENERATE
RING_TX(i) <= si_tx_2arr(i);
si_rx_2arr(i) <= RING_RX(i);
END GENERATE;
- gen_wire_bus : FOR i IN 0 TO g_nof_ring_io-1 GENERATE
+ gen_wire_bus : FOR i IN 0 TO g_nof_ring_bus-1 GENERATE
gen_wire_signals : FOR j IN 0 TO c_unb2_board_tr_ring.bus_w-1 GENERATE
si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2_board_tr_ring.bus_w + j);