From 1de186dd98e0b5cd3fd98cd863f69eb46348f724 Mon Sep 17 00:00:00 2001
From: Jonathan Hargreaves <hargreaves@astron.nl>
Date: Fri, 6 Feb 2015 10:58:15 +0000
Subject: [PATCH] pinning design final
---
.../designs/unb2_pinning/src/ip/ddr4.qsys | 6 +++---
.../unb2_pinning/src/ip/system_pll.qsys | 4 ++--
.../unb2_pinning/src/vhdl/unb2_pinning.vhd | 18 +++++++++---------
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/ddr4.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/ddr4.qsys
index ca062c9154..fa2b8ddf6f 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/ddr4.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/ddr4.qsys
@@ -28,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U4F45I3SG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
@@ -659,7 +659,7 @@
<parameter name="PHY_DDR4_DEFAULT_IO" value="true" />
<parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
<parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
- <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="900.0" />
+ <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="1000.0" />
<parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
<parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_DDR4_STARTING_VREFIN" value="70.0" />
@@ -751,7 +751,7 @@
<parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
<parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
<parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
- <parameter name="SYS_INFO_DEVICE" value="10AX115U4F45I3SG" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115U4F45I3SGES" />
<parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
<parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="3" />
<parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_ddr4_inst</parameter>
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/system_pll.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/system_pll.qsys
index 8f76e9b367..82ccfce8d7 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/system_pll.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/system_pll.qsys
@@ -118,7 +118,7 @@
<parameter name="gui_actual_output_clock_frequency15" value="0.0" />
<parameter name="gui_actual_output_clock_frequency16" value="0.0" />
<parameter name="gui_actual_output_clock_frequency17" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency2" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency2" value="120.0" />
<parameter name="gui_actual_output_clock_frequency3" value="0.0" />
<parameter name="gui_actual_output_clock_frequency4" value="0.0" />
<parameter name="gui_actual_output_clock_frequency5" value="0.0" />
@@ -282,7 +282,7 @@
<parameter name="gui_number_of_clocks" value="3" />
<parameter name="gui_operation_mode" value="direct" />
<parameter name="gui_output_clock_frequency0" value="100.0" />
- <parameter name="gui_output_clock_frequency1" value="300.0" />
+ <parameter name="gui_output_clock_frequency1" value="250.0" />
<parameter name="gui_output_clock_frequency10" value="100.0" />
<parameter name="gui_output_clock_frequency11" value="100.0" />
<parameter name="gui_output_clock_frequency12" value="100.0" />
diff --git a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
index 052ffc1fac..7c2f5251bd 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
+++ b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
@@ -374,8 +374,8 @@ architecture str of unb2_pinning is
constant cs_sync : std_logic := '1';
-- general reset and clock signals
- signal reset_n : std_logic := '0';
- signal reset_p : std_logic := '0';
+ signal reset_n : std_logic;
+ signal reset_p : std_logic;
signal pout_wdi : std_logic := '0';
signal sys_clk : std_logic := '0';
signal sys_locked : std_logic := '0';
@@ -856,13 +856,13 @@ begin
u_system_pll : system_pll
port map(
--- refclk => ETH_CLK,
- refclk => CLK,
+ refclk => ETH_CLK,
+-- refclk => CLK,
rst => reset_p,
locked => sys_locked,
outclk_0 => mm_clk, -- 100MHz
outclk_1 => sys_clk, -- 300MHz
- outclk_2 => clk_125 -- 125MHz for 1ge
+ outclk_2 => clk_125 -- 125MHz for 1ge
);
-- ****** i2c interfaces ******
@@ -921,10 +921,10 @@ begin
avs_i2c_master_11_i2c_scl_export => mb_scl,
eth_tse_0_serial_connection_rxp_0 => ETH_SGIN(0),
eth_tse_0_serial_connection_txp_0 => ETH_SGOUT(0),
--- eth_tse_0_pcs_ref_clk_clock_connection_clk => clk_125,
- eth_tse_0_pcs_ref_clk_clock_connection_clk => ETH_CLK,
--- eth_tse_1_pcs_ref_clk_clock_connection_clk => clk_125,
- eth_tse_1_pcs_ref_clk_clock_connection_clk => ETH_CLK,
+ eth_tse_0_pcs_ref_clk_clock_connection_clk => clk_125,
+ --eth_tse_0_pcs_ref_clk_clock_connection_clk => ETH_CLK,
+ eth_tse_1_pcs_ref_clk_clock_connection_clk => clk_125,
+ --eth_tse_1_pcs_ref_clk_clock_connection_clk => ETH_CLK,
eth_tse_1_serial_connection_rxp_0 => ETH_SGIN(1),
eth_tse_1_serial_connection_txp_0 => ETH_SGOUT(1),
pio_0_external_connection_export => ver_id_pmbusalert
--
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