diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
index 2cf4f8646acc02dbac3df1388fee73b6cb1cfb11..576605ce6fadab9c6cc2701cbd4cc2611e2ec37a 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
@@ -62,6 +62,7 @@ ENTITY mmm_unb2_minimal IS
     reg_ppsh_miso            : IN  t_mem_miso; 
                              
     -- eth1g
+    eth1g_mm_rst             : OUT STD_LOGIC;
     eth1g_tse_mosi           : OUT t_mem_mosi;  
     eth1g_tse_miso           : IN  t_mem_miso;  
     eth1g_reg_mosi           : OUT t_mem_mosi;  
@@ -69,6 +70,7 @@ ENTITY mmm_unb2_minimal IS
     eth1g_reg_interrupt      : IN  STD_LOGIC; 
     eth1g_ram_mosi           : OUT t_mem_mosi;  
     eth1g_ram_miso           : IN  t_mem_miso;
+
     -- EPCS read
     reg_dpmm_data_mosi       : OUT t_mem_mosi;
     reg_dpmm_data_miso       : IN  t_mem_miso;
@@ -164,7 +166,7 @@ BEGIN
       -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
       pio_wdi_external_connection_export        => pout_wdi,
 
-      avs_eth_0_reset_export                    => OPEN,
+      avs_eth_0_reset_export                    => eth1g_mm_rst,
       avs_eth_0_clk_export                      => OPEN,
       avs_eth_0_tse_address_export              => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
       avs_eth_0_tse_write_export                => eth1g_tse_mosi.wr,
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
index fe44cfe325ceebe16430ab2aef8347953c35dee5..c80cd566a973448b323f66163e680443b43e5bb5 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
@@ -107,6 +107,7 @@ ARCHITECTURE str OF unb2_minimal IS
   SIGNAL reg_unb_sens_miso          : t_mem_miso;
 
   -- eth1g
+  SIGNAL eth1g_mm_rst               : STD_LOGIC;
   SIGNAL eth1g_tse_mosi             : t_mem_mosi;  -- ETH TSE MAC registers
   SIGNAL eth1g_tse_miso             : t_mem_miso;
   SIGNAL eth1g_reg_mosi             : t_mem_mosi;  -- ETH control and status registers
@@ -217,6 +218,7 @@ BEGIN
     reg_ppsh_miso            => reg_ppsh_miso,
     
     -- eth1g
+    eth1g_mm_rst             => eth1g_mm_rst,
     eth1g_tse_mosi           => eth1g_tse_mosi,
     eth1g_tse_miso           => eth1g_tse_miso,
     eth1g_reg_mosi           => eth1g_reg_mosi,
@@ -280,6 +282,7 @@ BEGIN
     reg_ppsh_miso            => reg_ppsh_miso, 
   
     -- eth1g
+    eth1g_mm_rst             => eth1g_mm_rst,
     eth1g_tse_mosi           => eth1g_tse_mosi,
     eth1g_tse_miso           => eth1g_tse_miso,
     eth1g_reg_mosi           => eth1g_reg_mosi,