diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
index d91b50b60553e8fcb6630b1763cd2e314a833f78..70256dad57cccbec5d8635333ac67a2ce2363ed0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
@@ -9,9 +9,11 @@ hdl_lib_technology = ip_arria10_e1sg
test_bench_files =
tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+ tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
regression_test_vhdl =
tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+ tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
[modelsim_project_file]
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a3a44d2dc0893d3abfd2d7b6f3c4b426ca1fb190
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
@@ -0,0 +1,256 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_sdp_station_xsub_one capturing BST UDP offload packets.
+--
+-- Description:
+-- MM control actions:
+--
+-- 1) Enable BSN source and enable BST offload
+--
+-- 2) Verify ethernet statistics using eth_statistics, it checks the number of
+-- received packets and the total number of valid data. The content of the packets is not verified.
+--
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- > run -a
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib, eth_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload IS
+END tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+
+ CONSTANT c_nof_block_per_sync : NATURAL := 16; -- long enough to stream out udp data
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
+ CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+
+ -- MM
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+ CONSTANT c_mm_file_reg_stat_enable_xst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_XST";
+ CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER_XSUB";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL eth_done : STD_LOGIC := '0';
+
+ -- . 1GbE output
+ CONSTANT c_eth_check_nof_packets : NATURAL := 1; -- received packets in 1 sync period
+ CONSTANT c_eth_header_size : NATURAL := 19; -- words
+ CONSTANT c_eth_crc_size : NATURAL := 1; -- word
+ CONSTANT c_eth_packet_size : NATURAL := c_eth_header_size + c_eth_crc_size + (c_sdp_W_statistic / c_word_w) * c_sdp_S_pn * c_sdp_S_pn * c_nof_complex; -- 20 + 2 * 12 * 12 * 2 = 596
+ CONSTANT c_eth_check_nof_valid : NATURAL := c_eth_check_nof_packets * c_eth_packet_size;
+ CONSTANT c_eth_runtime_timeout : TIME := 2 * c_nof_clk_per_sync * c_ext_clk_period; -- eth statistics should be done at the second sync interval
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ -- back transceivers
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
+
+ -- jesd204b syncronization signals
+ SIGNAL jesd204b_sysref : STD_LOGIC;
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
+ jesd204b_sysref <= pps;
+ ext_pps <= pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_lofar_unb2b_sdp_station_xsub_one : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2b_sdp_station_xsub_one",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
+
+ ------------------------------------------------------------------------------
+ -- MM slave accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ ----------------------------------------------------------------------------
+ -- Enable BSN
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk); -- Enable BSN immediately
+
+ ----------------------------------------------------------------------------
+ -- Enable xsub
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, 1, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+
+ ----------------------------------------------------------------------------
+ -- Offload enable
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_stat_enable_xst, 0, 1, tb_clk);
+
+ -- wait for udp offload is done
+ proc_common_wait_until_high(ext_clk, eth_done);
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+ WAIT;
+ END PROCESS;
+
+ -------------------------------------------------------------------------
+ -- Verify proper DUT 1GbE offload output using Ethernet packet statistics
+ -------------------------------------------------------------------------
+ u_eth_statistics : ENTITY eth_lib.eth_statistics
+ GENERIC MAP (
+ g_runtime_nof_packets => c_eth_check_nof_packets,
+ g_runtime_timeout => c_eth_runtime_timeout,
+ g_check_nof_valid => TRUE,
+ g_check_nof_valid_ref => c_eth_check_nof_valid
+ )
+ PORT MAP (
+ eth_serial_in => eth_txp(0),
+ tb_end => eth_done
+ );
+
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index d79ab32df21746a83d0753413e441f987c16aec1..9f8ecfbddf90215cb723d7c0cb500d708250ddba 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -362,6 +362,18 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
-- Statistics header info
SIGNAL reg_stat_hdr_dat_sst_mosi : t_mem_mosi;
SIGNAL reg_stat_hdr_dat_sst_miso : t_mem_miso;
+
+ ----------------------------------------------
+ -- XST
+ ----------------------------------------------
+ -- Statistics Enable
+ SIGNAL reg_stat_enable_xst_mosi : t_mem_mosi;
+ SIGNAL reg_stat_enable_xst_miso : t_mem_miso;
+
+ -- Statistics header info
+ SIGNAL reg_stat_hdr_dat_xst_mosi : t_mem_mosi;
+ SIGNAL reg_stat_hdr_dat_xst_miso : t_mem_miso;
+
----------------------------------------------
-- BST
----------------------------------------------
@@ -404,8 +416,6 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL bf_udp_siso_arr : t_dp_siso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
SIGNAL bf_10GbE_hdr_fields_out_arr : t_slv_1024_arr(c_sdp_N_beamsets-1 DOWNTO 0);
- SIGNAL out_crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
-
-- 10GbE
SIGNAL tr_ref_clk_312 : STD_LOGIC;
SIGNAL tr_ref_clk_156 : STD_LOGIC;
@@ -695,6 +705,10 @@ BEGIN
reg_stat_enable_sst_miso => reg_stat_enable_sst_miso,
reg_stat_hdr_dat_sst_mosi => reg_stat_hdr_dat_sst_mosi,
reg_stat_hdr_dat_sst_miso => reg_stat_hdr_dat_sst_miso,
+ reg_stat_enable_xst_mosi => reg_stat_enable_xst_mosi,
+ reg_stat_enable_xst_miso => reg_stat_enable_xst_miso,
+ reg_stat_hdr_dat_xst_mosi => reg_stat_hdr_dat_xst_mosi,
+ reg_stat_hdr_dat_xst_miso => reg_stat_hdr_dat_xst_miso,
reg_stat_enable_bst_mosi => reg_stat_enable_bst_mosi,
reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
@@ -862,7 +876,10 @@ BEGIN
dp_rst => dp_rst,
in_sosi_arr => fsub_sosi_arr,
-
+
+ xst_udp_sosi => udp_tx_sosi_arr(1),
+ xst_udp_siso => udp_tx_siso_arr(1),
+
mm_rst => mm_rst,
mm_clk => mm_clk,
@@ -875,8 +892,16 @@ BEGIN
ram_st_xsq_mosi => ram_st_xsq_mosi,
ram_st_xsq_miso => ram_st_xsq_miso,
- out_crosslets_info => out_crosslets_info
-
+ reg_stat_enable_mosi => reg_stat_enable_xst_mosi,
+ reg_stat_enable_miso => reg_stat_enable_xst_miso,
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_xst_mosi,
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_xst_miso,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => xst_udp_src_port
);
END GENERATE;
@@ -893,17 +918,17 @@ BEGIN
g_scope_selected_beamlet => g_scope_selected_subband
)
PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- in_sosi_arr => fsub_sosi_arr,
- bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
- bf_udp_siso => bf_udp_siso_arr(beamset_id),
- bst_udp_sosi => udp_tx_sosi_arr(1+ beamset_id),
- bst_udp_siso => udp_tx_siso_arr(1+ beamset_id),
+ in_sosi_arr => fsub_sosi_arr,
+ bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
+ bf_udp_siso => bf_udp_siso_arr(beamset_id),
+ bst_udp_sosi => udp_tx_sosi_arr(2+ beamset_id),
+ bst_udp_siso => udp_tx_siso_arr(2+ beamset_id),
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
@@ -920,19 +945,18 @@ BEGIN
reg_stat_enable_mosi => reg_stat_enable_bst_mosi_arr(beamset_id),
reg_stat_enable_miso => reg_stat_enable_bst_miso_arr(beamset_id),
reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_mosi_arr(beamset_id),
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_miso_arr(beamset_id),
- sdp_info => sdp_info,
- gn_id => gn_id,
-
- eth_src_mac => cep_eth_src_mac,
- ip_src_addr => cep_ip_src_addr,
- udp_src_port => cep_udp_src_port,
-
- stat_eth_src_mac => stat_eth_src_mac,
- stat_ip_src_addr => stat_ip_src_addr,
- stat_udp_src_port => bst_udp_src_port,
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_miso_arr(beamset_id),
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => cep_eth_src_mac,
+ ip_src_addr => cep_ip_src_addr,
+ udp_src_port => cep_udp_src_port,
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => bst_udp_src_port,
- hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
+ hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
);
END GENERATE;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index 7e1bbd362023e50017798aeb2dc505e072bf2977..01eded088e51e68dc9d9440f268f0ca389260c00 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -190,6 +190,14 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
reg_stat_hdr_dat_sst_mosi : OUT t_mem_mosi;
reg_stat_hdr_dat_sst_miso : IN t_mem_miso;
+ -- Crosslet Statistics offload
+ reg_stat_enable_xst_mosi : OUT t_mem_mosi;
+ reg_stat_enable_xst_miso : IN t_mem_miso;
+
+ -- Crosslet Statistics header info
+ reg_stat_hdr_dat_xst_mosi : OUT t_mem_mosi;
+ reg_stat_hdr_dat_xst_miso : IN t_mem_miso;
+
-- Beamlet Statistics offload
reg_stat_enable_bst_mosi : OUT t_mem_mosi;
reg_stat_enable_bst_miso : IN t_mem_miso;
@@ -344,6 +352,12 @@ BEGIN
u_mm_file_reg_stat_hdr_info_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_sst_mosi, reg_stat_hdr_dat_sst_miso);
+
+ u_mm_file_reg_stat_enable_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_xst_mosi, reg_stat_enable_xst_miso );
+
+ u_mm_file_reg_stat_hdr_info_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_xst_mosi, reg_stat_hdr_dat_xst_miso);
u_mm_file_reg_stat_enable_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_mosi, reg_stat_enable_bst_miso );
@@ -731,6 +745,22 @@ BEGIN
reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_mosi.rd,
reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_xst_clk_export => OPEN,
+ reg_stat_enable_xst_reset_export => OPEN,
+ reg_stat_enable_xst_address_export => reg_stat_enable_xst_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+ reg_stat_enable_xst_write_export => reg_stat_enable_xst_mosi.wr,
+ reg_stat_enable_xst_writedata_export => reg_stat_enable_xst_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_xst_read_export => reg_stat_enable_xst_mosi.rd,
+ reg_stat_enable_xst_readdata_export => reg_stat_enable_xst_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_stat_hdr_dat_xst_clk_export => OPEN,
+ reg_stat_hdr_dat_xst_reset_export => OPEN,
+ reg_stat_hdr_dat_xst_address_export => reg_stat_hdr_dat_xst_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_xst_write_export => reg_stat_hdr_dat_xst_mosi.wr,
+ reg_stat_hdr_dat_xst_writedata_export => reg_stat_hdr_dat_xst_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_xst_read_export => reg_stat_hdr_dat_xst_mosi.rd,
+ reg_stat_hdr_dat_xst_readdata_export => reg_stat_hdr_dat_xst_miso.rddata(c_word_w-1 DOWNTO 0),
+
reg_stat_enable_bst_clk_export => OPEN,
reg_stat_enable_bst_reset_export => OPEN,
reg_stat_enable_bst_address_export => reg_stat_enable_bst_mosi.address(c_sdp_reg_stat_enable_bst_addr_w-1 DOWNTO 0),
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index dfdc3433e9f2452a9452cb3a8c66e1189076159c..461075358e25bed8e93cef89b6783e17d3a64ca5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -301,6 +301,20 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_xst_clk_export : out std_logic; -- export
+ reg_stat_enable_xst_read_export : out std_logic; -- export
+ reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_xst_reset_export : out std_logic; -- export
+ reg_stat_enable_xst_write_export : out std_logic; -- export
+ reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
reg_stat_enable_bst_clk_export : out std_logic; -- export
reg_stat_enable_bst_read_export : out std_logic; -- export
diff --git a/applications/lofar2/libraries/sdp/hdllib.cfg b/applications/lofar2/libraries/sdp/hdllib.cfg
index 7068a9f4104a54a404540a09e830491c0ded6074..c4922d48959a7f833f7a037362781c0d9727b380 100644
--- a/applications/lofar2/libraries/sdp/hdllib.cfg
+++ b/applications/lofar2/libraries/sdp/hdllib.cfg
@@ -23,11 +23,13 @@ synth_files =
test_bench_files =
tb/vhdl/tb_sdp_info.vhd
tb/vhdl/tb_sdp_statistics_offload.vhd
+ tb/vhdl/tb_tb_sdp_statistics_offload.vhd
tb/vhdl/tb_sdp_crosslets_subband_select.vhd
regression_test_vhdl =
tb/vhdl/tb_sdp_info.vhd
tb/vhdl/tb_sdp_statistics_offload.vhd
+ tb/vhdl/tb_tb_sdp_statistics_offload.vhd
tb/vhdl/tb_sdp_crosslets_subband_select.vhd
[modelsim_project_file]
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index 47b5fe4db662beeb34011a709bb341c35c57a558..191577e824056e530783ed46a88fcb65a9133d2b 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -40,16 +40,16 @@ USE work.sdp_pkg.ALL;
ENTITY node_sdp_correlator IS
GENERIC (
g_sim : BOOLEAN := FALSE;
- g_P_sq : NATURAL := c_sdp_P_sq
- --g_offload_time : NATURAL := c_sdp_offload_time
+ g_P_sq : NATURAL := c_sdp_P_sq;
+ g_offload_time : NATURAL := c_sdp_offload_time
);
PORT (
dp_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
in_sosi_arr : IN t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
- --xst_udp_sosi : OUT t_dp_sosi;
- --xst_udp_siso : IN t_dp_siso;
+ xst_udp_sosi : OUT t_dp_sosi;
+ xst_udp_siso : IN t_dp_siso;
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
@@ -62,15 +62,16 @@ ENTITY node_sdp_correlator IS
reg_bsn_scheduler_xsub_miso : OUT t_mem_miso;
ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_st_xsq_miso : OUT t_mem_miso;
-
- --sdp_info : IN t_sdp_info;
- --gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
- --stat_eth_src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
- --stat_ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
- --stat_udp_src_port : IN STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0)
-
- out_crosslets_info : OUT STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0)
-
+ reg_stat_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_enable_miso : OUT t_mem_miso;
+ reg_stat_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_hdr_dat_miso : OUT t_mem_miso;
+
+ sdp_info : IN t_sdp_info;
+ gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
+ stat_eth_src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ stat_ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ stat_udp_src_port : IN STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0)
);
END node_sdp_correlator;
@@ -79,16 +80,16 @@ ARCHITECTURE str OF node_sdp_correlator IS
CONSTANT c_nof_blk_per_sync_max : NATURAL := c_sdp_xst_nof_blk_per_sync_max;
CONSTANT c_nof_blk_per_sync_min : NATURAL := c_sdp_xst_nof_blk_per_sync_min;
--- CONSTANT c_nof_masters : POSITIVE := 2;
+ CONSTANT c_nof_masters : POSITIVE := 2;
- -- crosslet statistics offload
--- SIGNAL ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
--- SIGNAL ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
-
--- SIGNAL master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
--- SIGNAL master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
--- SIGNAL master_mosi_arr : t_mem_mosi_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
--- SIGNAL master_miso_arr : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
+-- crosslet statistics offload
+ SIGNAL ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL master_mosi_arr : t_mem_mosi_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
+ SIGNAL master_miso_arr : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
SIGNAL quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL xin_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
@@ -97,6 +98,7 @@ ARCHITECTURE str OF node_sdp_correlator IS
SIGNAL crosslets_mosi_arr : t_mem_mosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL crosslets_miso_arr : t_mem_miso_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
BEGIN
---------------------------------------------------------------
-- Requantize 18b to 16b
@@ -168,7 +170,7 @@ BEGIN
reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
- out_crosslets_info => out_crosslets_info
+ out_crosslets_info => crosslets_info
);
---------------------------------------------------------------
@@ -234,69 +236,70 @@ BEGIN
mm_mosi_arr => crosslets_mosi_arr,
mm_miso_arr => crosslets_miso_arr,
- ram_st_xsq_mosi => ram_st_xsq_mosi, --master_mem_mux_mosi,
- ram_st_xsq_miso => ram_st_xsq_miso --master_mem_mux_miso
+ ram_st_xsq_mosi => master_mem_mux_mosi,
+ ram_st_xsq_miso => master_mem_mux_miso
);
--- ---------------------------------------------------------------
--- -- MM master multiplexer
--- ---------------------------------------------------------------
--- -- Connect 2 mm_masters to the common_mem_mux output
--- master_mosi_arr(0) <= ram_st_bst_mosi; -- MM access via QSYS MM bus
--- ram_st_bst_miso <= master_miso_arr(0);
--- master_mosi_arr(1) <= ram_st_offload_mosi; -- MM access by SST offload
--- ram_st_offload_miso <= master_miso_arr(1);
---
--- u_mem_master_mux : ENTITY mm_lib.mm_master_mux
--- GENERIC MAP (
--- g_nof_masters => c_nof_masters,
--- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
--- )
--- PORT MAP (
--- mm_clk => mm_clk,
---
--- master_mosi_arr => master_mosi_arr,
--- master_miso_arr => master_miso_arr,
--- mux_mosi => master_mem_mux_mosi,
--- mux_miso => master_mem_mux_miso
--- );
---
--- ---------------------------------------------------------------
--- -- XST UDP offload
--- ---------------------------------------------------------------
--- u_sdp_bst_udp_offload: ENTITY work.sdp_statistics_offload
--- GENERIC MAP (
--- g_statistics_type => "XST",
--- g_offload_time => g_offload_time,
--- g_beamset_id => g_beamset_id
--- )
--- PORT MAP (
--- mm_clk => mm_clk,
--- mm_rst => mm_rst,
---
--- dp_clk => dp_clk,
--- dp_rst => dp_rst,
---
--- master_mosi => ram_st_offload_mosi,
--- master_miso => ram_st_offload_miso,
---
--- reg_enable_mosi => reg_stat_enable_mosi,
--- reg_enable_miso => reg_stat_enable_miso,
---
--- reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
--- reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
---
--- sdp_info => sdp_info,
--- gn_index => TO_UINT(gn_id),
---
--- in_sosi => bf_sum_sosi,
--- out_sosi => bst_udp_sosi,
--- out_siso => bst_udp_siso,
---
--- eth_src_mac => stat_eth_src_mac,
--- udp_src_port => stat_udp_src_port,
--- ip_src_addr => stat_ip_src_addr
--- );
+ ---------------------------------------------------------------
+ -- MM master multiplexer
+ ---------------------------------------------------------------
+ -- Connect 2 mm_masters to the common_mem_mux output
+ master_mosi_arr(0) <= ram_st_xsq_mosi; -- MM access via QSYS MM bus
+ ram_st_xsq_miso <= master_miso_arr(0);
+ master_mosi_arr(1) <= ram_st_offload_mosi; -- MM access by UDP offload
+ ram_st_offload_miso <= master_miso_arr(1);
+
+ u_mem_master_mux : ENTITY mm_lib.mm_master_mux
+ GENERIC MAP (
+ g_nof_masters => c_nof_masters,
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ )
+ PORT MAP (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => master_mosi_arr,
+ master_miso_arr => master_miso_arr,
+ mux_mosi => master_mem_mux_mosi,
+ mux_miso => master_mem_mux_miso
+ );
+
+ ---------------------------------------------------------------
+ -- XST UDP offload
+ ---------------------------------------------------------------
+ u_sdp_xst_udp_offload: ENTITY work.sdp_statistics_offload
+ GENERIC MAP (
+ g_statistics_type => "XST",
+ g_offload_time => g_offload_time,
+ g_P_sq => g_P_sq
+ )
+ PORT MAP (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ master_mosi => ram_st_offload_mosi,
+ master_miso => ram_st_offload_miso,
+
+ reg_enable_mosi => reg_stat_enable_mosi,
+ reg_enable_miso => reg_stat_enable_miso,
+
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
+
+ sdp_info => sdp_info,
+ gn_index => TO_UINT(gn_id),
+
+ in_sosi => crosslets_sosi_arr(0),
+ out_sosi => xst_udp_sosi,
+ out_siso => xst_udp_siso,
+
+ eth_src_mac => stat_eth_src_mac,
+ udp_src_port => stat_udp_src_port,
+ ip_src_addr => stat_ip_src_addr,
+ crosslets_info => crosslets_info
+ );
END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index a30bf342f7766974952a2bc51bdb9824b95d587d..1ecebdc0cb4714579b70843a8b0a4df13be7749b 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -299,7 +299,7 @@ BEGIN
u_mem_master_mux : ENTITY mm_lib.mm_master_mux
GENERIC MAP (
g_nof_masters => c_nof_masters,
- g_rd_latency_min => 1 -- TODO, make constant and check if value is right
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
)
PORT MAP (
mm_clk => mm_clk,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index 7752b969126231d28336e4ee30ca848437197f9c..287331749627f658af4d5ffdb785c249e7f54fb2 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
--
--- Author: P. Donker
+-- Author: P. Donker, R van der Walle
-- Purpose:
-- . SDP statistics offload
@@ -45,7 +45,8 @@ ENTITY sdp_statistics_offload IS
GENERIC (
g_statistics_type : STRING := "SST";
g_offload_time : NATURAL := c_sdp_offload_time;
- g_beamset_id : NATURAL := 0
+ g_beamset_id : NATURAL := 0;
+ g_P_sq : NATURAL := c_sdp_P_sq
);
PORT (
-- Clocks and reset
@@ -79,6 +80,7 @@ ENTITY sdp_statistics_offload IS
ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
sdp_info : IN t_sdp_info;
subband_calibrated_flag : IN STD_LOGIC := '0';
+ crosslets_info : IN STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
gn_index : IN NATURAL
);
@@ -89,20 +91,20 @@ ARCHITECTURE str OF sdp_statistics_offload IS
CONSTANT c_nof_streams : NATURAL := 1;
- CONSTANT c_data_size : NATURAL := 2;
- CONSTANT c_nof_data_per_step : NATURAL := 2;
+ CONSTANT c_data_size : NATURAL := 2;
+ CONSTANT c_nof_data_per_step : NATURAL := 2;
CONSTANT c_step_size : NATURAL := sel_a_b(g_statistics_type="BST", c_data_size,
sel_a_b(g_statistics_type="XST", c_data_size,
c_data_size * c_nof_data_per_step)); -- SST
CONSTANT c_nof_data : NATURAL := sel_a_b(g_statistics_type="BST", c_sdp_N_pol * c_sdp_S_sub_bf,
- sel_a_b(g_statistics_type="XST", (c_sdp_S_pn * c_sdp_S_pn * c_nof_complex),
+ sel_a_b(g_statistics_type="XST", c_sdp_S_pn * c_sdp_S_pn * c_nof_complex,
c_sdp_N_sub)); -- SST
CONSTANT c_block_size : NATURAL := c_nof_data * c_step_size;
CONSTANT c_nof_packets : NATURAL := sel_a_b(g_statistics_type="BST", 1,
- sel_a_b(g_statistics_type="XST", c_sdp_S_pn,
+ sel_a_b(g_statistics_type="XST", g_P_sq,
c_sdp_S_pn)); -- SST
CONSTANT c_marker : NATURAL := sel_a_b(g_statistics_type="BST", c_sdp_marker_bst,
@@ -147,12 +149,13 @@ ARCHITECTURE str OF sdp_statistics_offload IS
SIGNAL dp_header_info : STD_LOGIC_VECTOR(1023 DOWNTO 0):= (OTHERS => '0');
SIGNAL bsn_at_sync : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL selected_crosslet : STD_LOGIC_VECTOR(c_sdp_crosslets_index_w-1 DOWNTO 0);
--SIGNAL sdp_data_id : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
bsn_at_sync <= RESIZE_UVEC(in_sosi.bsn, 64) WHEN rising_edge(dp_clk) AND in_sosi.sync = '1';
-
+ selected_crosslet <= crosslets_info(c_sdp_crosslets_index_w-1 DOWNTO 0);
-------------------------------------------------------------------------------
-- Assemble offload header info
@@ -217,7 +220,7 @@ BEGIN
ELSIF g_statistics_type = "BST" THEN
v.data_id := x"0000" & TO_UVEC(c_beamlet_id, 16);
ELSIF g_statistics_type = "XST" THEN
- v.data_id := x"00" & TO_UVEC(0, 8) & TO_UVEC(0, 8) & TO_UVEC(0, 8); -- TODO: fill in right values for XST.
+ v.data_id := x"0" & "000" & RESIZE_UVEC(selected_crosslet, 9) & TO_UVEC(r.block_count * c_sdp_S_pn, 8) & TO_UVEC(r.block_count * c_sdp_S_pn, 8); -- RW TODO: define for P_sq > 1
ELSE
v.data_id := x"00000000";
END IF;
@@ -227,10 +230,10 @@ BEGIN
-- Use trigger to start first packet
v.start_pulse := '1';
v.start_address := 0;
- v.block_count := 1;
+ v.block_count := 0;
ELSIF done = '1' THEN
-- Use done to start next packets
- IF r.block_count < c_nof_packets THEN
+ IF r.block_count < c_nof_packets-1 THEN
IF r.block_count MOD c_nof_data_per_step = 0 THEN
v.start_address := r.block_count / c_nof_data_per_step * c_block_size; -- jump to first packet in next block
ELSE
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
index ad26814881b3aa41ff5e9114e3f3128ca294f5d8..42f947700310ff1af936a0e5aa16a945c31765b9 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
@@ -49,8 +49,9 @@ USE work.sdp_pkg.ALL;
ENTITY tb_sdp_statistics_offload IS
GENERIC (
g_statistics_type : STRING := "SST";
- g_nof_signal_inputs_per_pn : NATURAL := 12;
- g_offload_time : NATURAL := 500
+ g_offload_time : NATURAL := 500;
+ g_beamset_id : NATURAL := 0;
+ g_P_sq : NATURAL := c_sdp_P_sq
);
END tb_sdp_statistics_offload;
@@ -73,18 +74,29 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS
CONSTANT c_hdr_dat_mm_addr_udp_src_port : NATURAL := 15;
-- Define SST RAM structure.
- CONSTANT c_nof_data : NATURAL := 512;
CONSTANT c_data_size : NATURAL := 2;
- CONSTANT c_step_size : NATURAL := 4;
-
- -- Define SST RAM size for g_nof_signal_inputs_per_pn.
- CONSTANT c_ram_size : NATURAL := c_nof_data * c_data_size * g_nof_signal_inputs_per_pn;
+ CONSTANT c_nof_data_per_step : NATURAL := 2;
+ CONSTANT c_step_size : NATURAL := sel_a_b(g_statistics_type="BST", c_data_size,
+ sel_a_b(g_statistics_type="XST", c_data_size,
+ c_data_size * c_nof_data_per_step)); -- SST
+
+ CONSTANT c_nof_data : NATURAL := sel_a_b(g_statistics_type="BST", c_sdp_N_pol * c_sdp_S_sub_bf,
+ sel_a_b(g_statistics_type="XST", c_sdp_S_pn * c_sdp_S_pn * c_nof_complex,
+ c_sdp_N_sub)); -- SST
+
+ CONSTANT c_nof_packets : NATURAL := sel_a_b(g_statistics_type="BST", 1,
+ sel_a_b(g_statistics_type="XST", g_P_sq,
+ c_sdp_S_pn)); -- SST
+
+
+ -- Define SST RAM size for c_nof_packets.
+ CONSTANT c_ram_size : NATURAL := c_nof_data * c_data_size * c_nof_packets;
CONSTANT c_ram_w : NATURAL := ceil_log2(c_ram_size);
--CONSTANT c_ram_buf : t_c_mem := (c_mem_ram_rd_latency, c_ram_w, 32, 2**c_ram_w, 'X');
CONSTANT c_ram_buf : t_c_mem := (1, c_ram_w, 32, 2**c_ram_w, 'X');
-- Define block timing.
- CONSTANT c_nof_block_per_sync : NATURAL := 20; -- Sufficient to fit more than g_nof_signal_inputs_per_pn offload packets per sync interval.
+ CONSTANT c_nof_block_per_sync : NATURAL := 80; -- Sufficient to fit more than c_nof_packets offload packets per sync interval.
CONSTANT c_nof_clk_per_block : NATURAL := c_nof_data * c_data_size;
-- Based on g_statistics_type: 'S'=0x53="SST", 'B'=0x42="BST", 'X'=0x58="XST".
@@ -96,10 +108,12 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS
sel_a_b(g_statistics_type="XST", c_sdp_S_pn,
1)); -- SST
- CONSTANT c_nof_statistics_per_packet : NATURAL := sel_a_b(g_statistics_type="BST", c_sdp_S_sub_bf,
+ CONSTANT c_nof_statistics_per_packet : NATURAL := sel_a_b(g_statistics_type="BST", c_sdp_N_pol * c_sdp_S_sub_bf,
sel_a_b(g_statistics_type="XST", (c_sdp_S_pn * c_sdp_S_pn * c_nof_complex),
c_sdp_N_sub)); -- SST
+ CONSTANT c_beamlet_id : NATURAL := g_beamset_id * c_sdp_S_sub_bf;
+
CONSTANT c_nof_valid_per_block : NATURAL := c_nof_data * c_data_size;
CONSTANT c_nof_sync : NATURAL := 5;
CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync * c_nof_clk_per_block;
@@ -241,7 +255,7 @@ BEGIN
IF test_offload_sosi.eop = '1' THEN
-- bsn is not fully received (bit 0-15 is missing) because 32 bit allignment not working in dp_offload_rx.vhd.
-- Check fixed settings.
- ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "eth_dst_mac") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "eth_dst_mac")) = x"00074306C700"
+ ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "eth_dst_mac") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "eth_dst_mac")) = x"001B217176B9"
REPORT "wrong eth_dst_mac" SEVERITY ERROR;
ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "eth_type") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "eth_type")) = x"0800"
REPORT "wrong eth_type" SEVERITY ERROR;
@@ -251,7 +265,7 @@ BEGIN
REPORT "wrong ip_header_length" SEVERITY ERROR;
ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "ip_services") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "ip_services")) = TO_UVEC(0, 8)
REPORT "wrong ip_services" SEVERITY ERROR;
- ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "ip_total_length") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "ip_total_length")) = TO_UVEC(7868, 16)
+ ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "ip_total_length") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "ip_total_length")) = TO_UVEC(4156, 16)
REPORT "wrong ip_total_length" SEVERITY ERROR;
ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "ip_identification") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "ip_identification")) = TO_UVEC(0, 16)
REPORT "wrong ip_identification" SEVERITY ERROR;
@@ -263,11 +277,11 @@ BEGIN
REPORT "wrong ip_time_to_live" SEVERITY ERROR;
ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "ip_protocol") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "ip_protocol")) = TO_UVEC(17, 8)
REPORT "wrong ip_protocol" SEVERITY ERROR;
- ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "ip_dst_addr") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "ip_dst_addr")) = x"C0A80001"
+ ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "ip_dst_addr") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "ip_dst_addr")) = x"0A6300FE"
REPORT "wrong ip_dst_addr" SEVERITY ERROR;
- ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "udp_dst_port") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "udp_dst_port")) = TO_UVEC(0, 16)
+ ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "udp_dst_port") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "udp_dst_port")) = TO_UVEC(5001, 16)
REPORT "wrong udp_dst_port" SEVERITY ERROR;
- ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "udp_total_length") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "udp_total_length")) = TO_UVEC(7848, 16)
+ ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "udp_total_length") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "udp_total_length")) = TO_UVEC(4136, 16)
REPORT "wrong udp_total_length" SEVERITY ERROR;
ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_version_id") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_version_id")) = TO_UVEC(5, 8)
REPORT "wrong sdp_version_id" SEVERITY ERROR;
@@ -309,8 +323,14 @@ BEGIN
REPORT "wrong sdp_block_period" SEVERITY ERROR;
-- Check variable header info.
- ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_data_id") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_data_id")) = TO_UVEC(rx_block_cnt + c_sdp_S_pn * gn_index, 32)
- REPORT "wrong block count number, received data_id not same as counted blocks" SEVERITY ERROR;
+ IF g_statistics_type = "SST" THEN
+ ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_data_id") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_data_id")) = TO_UVEC(rx_block_cnt + c_sdp_S_pn * gn_index, 32)
+ REPORT "wront SST sdp_data_id" SEVERITY ERROR;
+ ELSIF g_statistics_type = "BST" THEN
+ ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_data_id") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_data_id")) = TO_UVEC(c_beamlet_id, 32)
+ REPORT "wront BST sdp_data_id" SEVERITY ERROR;
+ --ELSIF g_statistics_type = "XST" THEN --TODO: RW define check
+ END IF;
END IF;
END PROCESS;
@@ -346,7 +366,7 @@ BEGIN
IF init_ram_done = '1' THEN
IF in_sosi.sync = '1' AND rx_block_cnt > 0 THEN
- ASSERT rx_block_cnt = g_nof_signal_inputs_per_pn - 1 REPORT "wrong number of blocks between 2 sync" SEVERITY ERROR;
+ ASSERT rx_block_cnt = c_nof_packets-1 REPORT "wrong number of blocks between 2 sync" SEVERITY ERROR;
END IF;
-- rx_prev_bsn > 0 is needed for the first time, when there is no previous BSN.
@@ -365,7 +385,7 @@ BEGIN
IF test_offload_sosi.sop = '1' THEN
rx_valid_clk_cnt <= 1;
ELSIF test_offload_sosi.eop = '1' THEN
- ASSERT rx_valid_clk_cnt = c_nof_valid_per_block REPORT "wrong number of clock counts while valid" SEVERITY ERROR;
+ ASSERT rx_valid_clk_cnt+1 = c_nof_valid_per_block REPORT "wrong number of clock counts while valid" SEVERITY ERROR;
ELSE
rx_valid_clk_cnt <= rx_valid_clk_cnt + 1;
END IF;
@@ -409,8 +429,8 @@ BEGIN
adr_a => ram_wr_addr,
-- DP read only port clock domain.
- rst_b => dp_rst,
- clk_b => dp_clk,
+ rst_b => mm_rst,
+ clk_b => mm_clk,
adr_b => master_mosi.address(c_ram_buf.adr_w-1 DOWNTO 0),
rd_en_b => master_mosi.rd,
rd_dat_b => master_miso.rddata(c_ram_buf.dat_w-1 DOWNTO 0),
@@ -448,9 +468,10 @@ BEGIN
-- SDP info
u_dut: ENTITY work.sdp_statistics_offload
GENERIC MAP (
- g_statistics_type => "SST",
+ g_statistics_type => g_statistics_type,
g_offload_time => g_offload_time,
- g_beamset_id => 0
+ g_beamset_id => g_beamset_id,
+ g_P_sq => g_P_sq
)
PORT MAP (
mm_clk => mm_clk,
@@ -480,4 +501,4 @@ BEGIN
ip_src_addr => c_ip_src_addr
);
-END tb;
\ No newline at end of file
+END tb;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e0506591d517a9df01f03904a3c1bec1c98a1c28
--- /dev/null
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
@@ -0,0 +1,51 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Verify multiple variations of tb_sdp_statistics_offload
+-- Description:
+-- Usage:
+-- > as 3
+-- > run -all
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY tb_tb_sdp_statistics_offload IS
+END tb_tb_sdp_statistics_offload;
+
+ARCHITECTURE tb OF tb_tb_sdp_statistics_offload IS
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+
+-- g_statistics_type : STRING := "SST";
+-- g_offload_time : NATURAL := 500;
+-- g_beamset_id : NATURAL := 0;
+-- g_P_sq : NATURAL := c_sdp_P_sq
+
+ u_sst : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("SST");
+ u_bst_0 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("BST");
+ u_bst_1 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("BST", 500, 1);
+ u_xst_1 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("XST", 500, 0, 1);
+ u_xst_P_sq : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("XST");
+
+END tb;
diff --git a/libraries/dsp/st/src/vhdl/st_xsq.vhd b/libraries/dsp/st/src/vhdl/st_xsq.vhd
index 997e13c1b253434c103dca1bc505447b0bfa37ab..4378a4c7507b12ec38b0467b1f2ac923b9c2f998 100644
--- a/libraries/dsp/st/src/vhdl/st_xsq.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xsq.vhd
@@ -185,9 +185,11 @@ BEGIN
u_mem_mux_select : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => c_nof_complex,
- g_mult_addr_w => c_nof_word_w
+ g_mult_addr_w => c_nof_word_w,
+ g_rd_latency => 1
)
port map (
+ clk => mm_clk,
mosi => remapped_ram_st_xsq_mosi,
miso => ram_st_xsq_miso,
mosi_arr => ram_st_xsq_mosi_arr,