diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
index a7851a6999cb1cf5c0c0e87010b927f1d14bd63d..de07a231519203c124b736afa91ff909626338e1 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
@@ -164,8 +164,8 @@ ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
--------------------------------------------------------------------------------------------------
-- Temporarily ss instance
- SIGNAL dp_offload_in_sosi_arr : t_dp_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0);
- SIGNAL dp_offload_out_siso_arr : t_dp_siso_arr(g_bf.nof_bf_units-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL udp_offload_snk_in_arr : t_dp_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0);
+ SIGNAL udp_offload_snk_out_arr : t_dp_siso_arr(g_bf.nof_bf_units-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-- SIGNAL ss_in_sosi : t_dp_sosi;
-- SIGNAL ss_in_siso : t_dp_siso := c_dp_siso_rdy;
-- SIGNAL ss_out_sosi : t_dp_sosi;
@@ -464,7 +464,7 @@ BEGIN
);
gen_no_transpose : IF c_use_transpose = FALSE GENERATE
- dp_offload_in_sosi_arr <= beamlets_qua_sosi_arr;
+ udp_offload_snk_in_arr <= beamlets_qua_sosi_arr;
END GENERATE;
gen_transpose : IF c_use_transpose = TRUE GENERATE
@@ -522,9 +522,9 @@ BEGIN
-- gen_merge_out : PROCESS(ss_out_sosi)
-- BEGIN
-- FOR i IN 0 TO g_bf.nof_bf_units-1 LOOP
--- dp_offload_in_sosi_arr(i) <= ss_out_sosi;
--- dp_offload_in_sosi_arr(i).re <= RESIZE_DP_DSP_DATA(ss_out_sosi.data((2*i+1)*8-1 DOWNTO 2*i*8));
--- dp_offload_in_sosi_arr(i).im <= RESIZE_DP_DSP_DATA(ss_out_sosi.data((2*i+2)*8-1 DOWNTO (2*i+1)*8));
+-- udp_offload_snk_in_arr(i) <= ss_out_sosi;
+-- udp_offload_snk_in_arr(i).re <= RESIZE_DP_DSP_DATA(ss_out_sosi.data((2*i+1)*8-1 DOWNTO 2*i*8));
+-- udp_offload_snk_in_arr(i).im <= RESIZE_DP_DSP_DATA(ss_out_sosi.data((2*i+2)*8-1 DOWNTO (2*i+1)*8));
-- END LOOP;
-- END PROCESS;
@@ -554,8 +554,8 @@ BEGIN
snk_in_arr => beamlets_qua_sosi_arr,
-- ST source
- src_in_arr => dp_offload_out_siso_arr,
- src_out_arr => dp_offload_in_sosi_arr,
+ src_in_arr => udp_offload_snk_out_arr,
+ src_out_arr => udp_offload_snk_in_arr,
ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
@@ -762,7 +762,7 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
- snk_in_arr => dp_offload_in_sosi_arr, -- 8b beamlets
+ snk_in_arr => udp_offload_snk_in_arr, -- 8b beamlets
src_out_arr => dp_offload_tx_src_out_arr,
src_in_arr => dp_offload_tx_src_in_arr,
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd
index e210c9d00c7c70faba5fcc1c43a2985f9bc697c2..22c3976e15c4a8ed19bd2568df0173aedc7ef26d 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd
@@ -95,23 +95,45 @@ ARCHITECTURE wrap OF apertif_unb1_fn_beamformer_udp_offload IS
SIGNAL id_backplane : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
SIGNAL id_chip : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+ SIGNAL dp_fifo_sc_snk_in : t_dp_sosi;
SIGNAL dp_offload_tx_snk_in_arr : t_dp_sosi_arr(c_nof_offload_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_snk_out_arr : t_dp_siso_arr(c_nof_offload_streams-1 DOWNTO 0);
BEGIN
---------------------------------------------------------------------------------------
-- 4 BF unit outputs: 2*8b complex; concatenate these into one 64b word.
---------------------------------------------------------------------------------------
- gen_bf_out_concat: FOR i IN 0 TO c_nof_offload_streams-1 GENERATE
- p_connect : PROCESS(snk_in_arr(i))
- BEGIN
- dp_offload_tx_snk_in_arr(i) <= snk_in_arr(0); -- Control
- dp_offload_tx_snk_in_arr(i).data(c_data_w-1 DOWNTO 0) <= snk_in_arr(3).im(c_bf_out_compl_dat_w-1 DOWNTO 0) & snk_in_arr(3).re(c_bf_out_compl_dat_w-1 DOWNTO 0) &
- snk_in_arr(2).im(c_bf_out_compl_dat_w-1 DOWNTO 0) & snk_in_arr(2).re(c_bf_out_compl_dat_w-1 DOWNTO 0) &
- snk_in_arr(1).im(c_bf_out_compl_dat_w-1 DOWNTO 0) & snk_in_arr(1).re(c_bf_out_compl_dat_w-1 DOWNTO 0) &
- snk_in_arr(0).im(c_bf_out_compl_dat_w-1 DOWNTO 0) & snk_in_arr(0).re(c_bf_out_compl_dat_w-1 DOWNTO 0);
- END PROCESS;
- END GENERATE;
+ p_connect : PROCESS(snk_in_arr)
+ BEGIN
+ dp_fifo_sc_snk_in <= snk_in_arr(0); -- Control
+ dp_fifo_sc_snk_in.data(c_data_w-1 DOWNTO 0) <= snk_in_arr(3).im(c_bf_out_compl_dat_w-1 DOWNTO 0) & snk_in_arr(3).re(c_bf_out_compl_dat_w-1 DOWNTO 0) &
+ snk_in_arr(2).im(c_bf_out_compl_dat_w-1 DOWNTO 0) & snk_in_arr(2).re(c_bf_out_compl_dat_w-1 DOWNTO 0) &
+ snk_in_arr(1).im(c_bf_out_compl_dat_w-1 DOWNTO 0) & snk_in_arr(1).re(c_bf_out_compl_dat_w-1 DOWNTO 0) &
+ snk_in_arr(0).im(c_bf_out_compl_dat_w-1 DOWNTO 0) & snk_in_arr(0).re(c_bf_out_compl_dat_w-1 DOWNTO 0);
+ END PROCESS;
+
+ ---------------------------------------------------------------------------------------
+ -- FIFO to provide a flow controllable buffer while dp_offload_tx inserts headers
+ ---------------------------------------------------------------------------------------
+ u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
+ GENERIC MAP (
+ g_data_w => c_data_w,
+ g_bsn_w => 64,
+ g_use_sync => TRUE,
+ g_use_bsn => TRUE,
+ g_fifo_size => 128
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => OPEN,
+ snk_in => dp_fifo_sc_snk_in,
+
+ src_in => dp_offload_tx_snk_out_arr(0),
+ src_out => dp_offload_tx_snk_in_arr(0)
+ );
---------------------------------------------------------------------------------------
-- dp_offload_tx
@@ -142,7 +164,7 @@ BEGIN
reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
snk_in_arr => dp_offload_tx_snk_in_arr,
- snk_out_arr => OPEN,
+ snk_out_arr => dp_offload_tx_snk_out_arr,
src_out_arr => src_out_arr,
src_in_arr => src_in_arr,