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rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_sens.ip
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
similarity index 100%
rename from boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
similarity index 100%
rename from boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
similarity index 100%
rename from boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/qsys_unb2c_test.qsys b/boards/uniboard2c/designs/unb2c_test/quartus/qsys_unb2c_test.qsys
similarity index 100%
rename from boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/qsys_unb2c_test.qsys
rename to boards/uniboard2c/designs/unb2c_test/quartus/qsys_unb2c_test.qsys
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/README.txt b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/README.txt
deleted file mode 100644
index 5f5ce33c8c1c44386da742ce658af37d6a619c5b..0000000000000000000000000000000000000000
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/README.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-
-
-Simulation
-----------
--> Read ../../doc/README first until step 3
-Modelsim instructions:
-
- # in Modelsim do:
- lp unb2c_test_10GbE
- mk all
- # now double click on testbench file
- as 10
- run 500us
-
-
- # while the simulation runs... in another terminal/bash session do:
- cd unb2c_test/tb/python
-
- # To read out the design_name, ppsh and sensors; do:
- python tc_unb2c_test.py --sim --unb 0 --fn 3 --seq INFO,PPSH,SENSORS
- # (sensor results only show up after 1000us of simulation runtime)
-
- # To test the 10GbE offload; do:
- python tc_unb2c_test.py --sim --unb 0 --fn 3 --seq BGDB -s 10GBE -r 0
-
-
- # to end simulation in Modelsim do:
- quit -sim
-
-
-
-Testing on hardware
--------------------
--> Read ../../doc/README first until step 5
-
-# (assume that the Uniboard is --unb 1)
-
-# To read out the design_name, ppsh and sensors; do:
-
-python tc_unb2_test.py --unb 1 --fn 0:3 --seq REGMAP,INFO,PPSH,SENSORS -v5
-
-# To test the 10GbE offload:
-
-python tc_unb2_test.py --unb 1 --fn 0:3 --seq REGMAP,BGDB -v5 -s 10GBE -r 0:15 -v 3 --rep -1
-
-
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
index 32aebe63e38cd50482e9288388e449e928335a23..e392b2f828bbfc81b5d3c309fca6631ceccfcc7c 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
@@ -39,6 +39,7 @@ synth_top_level_entity =
quartus_copy_files =
quartus .
+ ../../quartus .
../../src/hex hex
quartus_qsf_files =
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..3650cb799d7997997f727fcf574060350d047778
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
@@ -0,0 +1,112 @@
+hdl_lib_name = unb2c_test_minimal
+hdl_library_clause_name = unb2c_test_minimal_lib
+hdl_lib_uses_synth = common mm technology unb2c_board unb2c_test
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+hdl_lib_include_ip =
+
+synth_files =
+ unb2c_test_minimal.vhd
+
+test_bench_files =
+ tb_unb2c_test_minimal.vhd
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus .
+ ../../quartus .
+ ../../src/hex hex
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+
+quartus_sdc_pre_files =
+ quartus/unb2c_test_minimal.sdc
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+
+quartus_sdc_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+
+quartus_tcl_files =
+ quartus/unb2c_test_minimal_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/qsys_unb2c_test/qsys_unb2c_test.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+
+
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal.sdc b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..fbcc86fb1bb44ec25f621483883c32ce0ba743e3
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal.sdc
@@ -0,0 +1 @@
+#set_false_path -from [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}] -to [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ae417258f888c910d593c6ab6e5117615ebbd36f
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal_pins.tcl
@@ -0,0 +1,22 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/tb_unb2c_test_minimal.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/tb_unb2c_test_minimal.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fd8d3bd83e1ac09a154993de19b8add792cda7c5
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/tb_unb2c_test_minimal.vhd
@@ -0,0 +1,38 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, unb2c_test_lib;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_unb2c_test_minimal IS
+END tb_unb2c_test_minimal;
+
+
+ARCHITECTURE tb OF tb_unb2c_test_minimal IS
+BEGIN
+ u_tb_unb2c_test : ENTITY unb2c_test_lib.tb_unb2c_test
+ GENERIC MAP (
+ g_design_name => "unb2c_test_minimal"
+ );
+END tb;
+
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cc65f82fea2df7b00038e5c99b673634974d4f08
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
@@ -0,0 +1,117 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+
+ENTITY unb2c_test_minimal IS
+ GENERIC (
+ g_design_name : STRING := "unb2c_test_minimal";
+ g_design_note : STRING := "minimal: none";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+
+ -- pmbus
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC;
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2c_test_minimal;
+
+
+ARCHITECTURE str OF unb2c_test_minimal IS
+
+BEGIN
+ u_revision : ENTITY unb2c_test_lib.unb2c_test
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ QSFP_LED => QSFP_LED
+ );
+END str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index a90418cfe5d42e459bc27b38ff6f4cedf56a1a37..3bf00207945900a27b7781251cb157f13dce13bf 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -175,8 +175,6 @@ ENTITY mmm_unb2c_test IS
reg_diag_rx_seq_10GbE_miso : IN t_mem_miso;
-- 10GbE
- reg_10gbase_r_24_mosi : OUT t_mem_mosi;
- reg_10gbase_r_24_miso : IN t_mem_miso;
reg_tr_10GbE_qsfp_ring_mosi : OUT t_mem_mosi;
reg_tr_10GbE_qsfp_ring_miso : IN t_mem_miso;
reg_tr_10GbE_back0_mosi : OUT t_mem_mosi;
@@ -388,9 +386,6 @@ BEGIN
u_mm_file_reg_eth1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
PORT MAP(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
- u_mm_file_reg_10gbase_r_24 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_10GBASE_R_24")
- PORT MAP(mm_rst, mm_clk, reg_10gbase_r_24_mosi, reg_10gbase_r_24_miso);
-
u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
u_mm_file_reg_tr_10GbE_back0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
@@ -478,25 +473,25 @@ BEGIN
avs_eth_0_ram_readdata_export => eth1g_eth0_ram_miso.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_irq_export => eth1g_eth0_reg_interrupt,
- avs_eth_1_reset_export => eth1g_eth1_mm_rst,
- avs_eth_1_clk_export => OPEN,
- avs_eth_1_tse_address_export => eth1g_eth1_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
- avs_eth_1_tse_write_export => eth1g_eth1_tse_mosi.wr,
- avs_eth_1_tse_read_export => eth1g_eth1_tse_mosi.rd,
- avs_eth_1_tse_writedata_export => eth1g_eth1_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_1_tse_readdata_export => eth1g_eth1_tse_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_1_tse_waitrequest_export => eth1g_eth1_tse_miso.waitrequest,
- avs_eth_1_reg_address_export => eth1g_eth1_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
- avs_eth_1_reg_write_export => eth1g_eth1_reg_mosi.wr,
- avs_eth_1_reg_read_export => eth1g_eth1_reg_mosi.rd,
- avs_eth_1_reg_writedata_export => eth1g_eth1_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_1_reg_readdata_export => eth1g_eth1_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_1_ram_address_export => eth1g_eth1_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
- avs_eth_1_ram_write_export => eth1g_eth1_ram_mosi.wr,
- avs_eth_1_ram_read_export => eth1g_eth1_ram_mosi.rd,
- avs_eth_1_ram_writedata_export => eth1g_eth1_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_1_ram_readdata_export => eth1g_eth1_ram_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_1_irq_export => eth1g_eth1_reg_interrupt,
+ avs2_eth_coe_1_reset_export => eth1g_eth1_mm_rst,
+ avs2_eth_coe_1_clk_export => OPEN,
+ avs2_eth_coe_1_tse_address_export => eth1g_eth1_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs2_eth_coe_1_tse_write_export => eth1g_eth1_tse_mosi.wr,
+ avs2_eth_coe_1_tse_read_export => eth1g_eth1_tse_mosi.rd,
+ avs2_eth_coe_1_tse_writedata_export => eth1g_eth1_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs2_eth_coe_1_tse_readdata_export => eth1g_eth1_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs2_eth_coe_1_tse_waitrequest_export => eth1g_eth1_tse_miso.waitrequest,
+ avs2_eth_coe_1_reg_address_export => eth1g_eth1_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs2_eth_coe_1_reg_write_export => eth1g_eth1_reg_mosi.wr,
+ avs2_eth_coe_1_reg_read_export => eth1g_eth1_reg_mosi.rd,
+ avs2_eth_coe_1_reg_writedata_export => eth1g_eth1_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs2_eth_coe_1_reg_readdata_export => eth1g_eth1_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs2_eth_coe_1_ram_address_export => eth1g_eth1_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs2_eth_coe_1_ram_write_export => eth1g_eth1_ram_mosi.wr,
+ avs2_eth_coe_1_ram_read_export => eth1g_eth1_ram_mosi.rd,
+ avs2_eth_coe_1_ram_writedata_export => eth1g_eth1_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs2_eth_coe_1_ram_readdata_export => eth1g_eth1_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs2_eth_coe_1_irq_export => eth1g_eth1_reg_interrupt,
reg_unb_sens_reset_export => OPEN,
reg_unb_sens_clk_export => OPEN,
@@ -610,15 +605,6 @@ BEGIN
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_10gbase_r_24_reset_export => OPEN,
- reg_10gbase_r_24_clk_export => OPEN,
- reg_10gbase_r_24_address_export => reg_10gbase_r_24_mosi.address(14 DOWNTO 0),
- reg_10gbase_r_24_write_export => reg_10gbase_r_24_mosi.wr,
- reg_10gbase_r_24_writedata_export => reg_10gbase_r_24_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_10gbase_r_24_read_export => reg_10gbase_r_24_mosi.rd,
- reg_10gbase_r_24_readdata_export => reg_10gbase_r_24_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_10gbase_r_24_waitrequest_export => reg_10gbase_r_24_miso.waitrequest,
-
reg_tr_10gbe_qsfp_ring_reset_export => OPEN,
reg_tr_10gbe_qsfp_ring_clk_export => OPEN,
reg_tr_10gbe_qsfp_ring_address_export => reg_tr_10GbE_qsfp_ring_mosi.address(c_reg_tr_10GbE_qsfp_ring_multi_adr_w-1 DOWNTO 0),
@@ -670,34 +656,6 @@ BEGIN
reg_eth10g_back1_read_export => reg_eth10g_back1_mosi.rd,
reg_eth10g_back1_readdata_export => reg_eth10g_back1_miso.rddata(c_word_w-1 DOWNTO 0),
--- -- the_reg_dp_offload_tx_1GbE
--- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
--- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
--- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_tx_1GbE_hdr_dat
--- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_rx_1GbE_hdr_dat
--- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-
reg_bsn_monitor_1gbe_reset_export => OPEN,
reg_bsn_monitor_1gbe_clk_export => OPEN,
reg_bsn_monitor_1gbe_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w-1 DOWNTO 0),
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index b194971094051ed4aa5e7ffd761e589ee4dd316b..29ed873843d5516585d0ccaac4b9478ae445ea59 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -69,7 +69,6 @@ ENTITY unb2c_test IS
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC := '0';
- ETH_CLK1 : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
@@ -136,7 +135,7 @@ ARCHITECTURE str OF unb2c_test IS
-- Firmware version x.y
CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 1);
- CONSTANT c_mm_clk_freq : NATURAL := c_unb2c_board_mm_clk_freq_125M;
+ CONSTANT c_mm_clk_freq : NATURAL := c_unb2c_board_mm_clk_freq_100M;
@@ -733,8 +732,8 @@ BEGIN
-- 10GbE
- reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+ --reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ --reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
@@ -870,8 +869,8 @@ BEGIN
-- Clocks and reset
mm_rst => mm_rst, -- use reset from QSYS
mm_clk => mm_clk, -- use mm_clk direct
--- eth_clk => xo_ethclk, -- 125 MHz clock
- eth_clk => ETH_CLK1, -- try direct connection to the pin
+ eth_clk => xo_ethclk, -- 125 MHz clock
+ --eth_clk => ETH_CLK1, -- try direct connection to the pin
st_rst => dp_rst,
st_clk => dp_clk,
@@ -975,8 +974,8 @@ BEGIN
reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
- reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+ --reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ --reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
dp_rst => dp_rst,
dp_clk => dp_clk,
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index b9babf90561858780ff58ac4ba126ec6ed51fed0..20ebbd4b30c5f27958f2180e66ca886255905718 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -247,8 +247,8 @@ ENTITY ctrl_unb2c_board IS
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC; -- 125 MHz
- ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0) := (OTHERS=>'0');
- ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0)
+ ETH_SGIN : IN STD_LOGIC; -- _VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0) := (OTHERS=>'0');
+ ETH_SGOUT : OUT STD_LOGIC -- _VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0)
);
END ctrl_unb2c_board;
@@ -813,8 +813,8 @@ BEGIN
ram_sla_out => eth1g_ram_miso,
-- PHY interface
- eth_txp => ETH_SGOUT(0),
- eth_rxp => ETH_SGIN(0),
+ eth_txp => ETH_SGOUT,
+ eth_rxp => ETH_SGIN,
-- LED interface
tse_led => eth1g_led
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd
index b088417ccff51d9f1a44da59ff564fe2abf92727..7182c37f372b05a0531310fa37e76a9932a6f817 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd
@@ -44,7 +44,7 @@ ARCHITECTURE str OF ip_arria10_e2sg_ddio_in IS
component ip_arria10_e2sg_ddio_in_1 is
port (
datain : in std_logic_vector(0 downto 0) := (others => '0'); -- pad_in.export
- inclock : in std_logic := '0'; -- ck.export
+ ck : in std_logic := '0'; -- ck.export
aclr : in std_logic := '0'; -- aclr.export
dataout_h : out std_logic_vector(0 downto 0); -- dataout_h.fragment
dataout_l : out std_logic_vector(0 downto 0) -- dataout_l.fragment
@@ -58,7 +58,7 @@ BEGIN
u_ip_arria10_e2sg_ddio_in_1 : ip_arria10_e2sg_ddio_in_1
PORT MAP (
datain => in_dat(I DOWNTO I),
- inclock => in_clk,
+ ck => in_clk,
aclr => rst,
dataout_h => out_dat_hi(I DOWNTO I),
dataout_l => out_dat_lo(I DOWNTO I)