diff --git a/libraries/io/eth/tb/vhdl/tb_eth.vhd b/libraries/io/eth/tb/vhdl/tb_eth.vhd
index 800d7afc20d020e09bfb62927889f645234c5c6d..fc7d86206d035ff132083e0c34b26eb16d603d31 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth.vhd
@@ -50,6 +50,7 @@ USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_network_total_header_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE tech_tse_lib.tb_tech_tse_pkg.ALL;
USE WORK.eth_pkg.ALL;
@@ -58,8 +59,9 @@ USE WORK.eth_pkg.ALL;
ENTITY tb_eth IS
-- Test bench control parameters
GENERIC (
- g_technology_dut : NATURAL := c_tech_stratixiv;
- g_technology_lcu : NATURAL := c_tech_stratixiv;
+ g_technology_dut : NATURAL := c_tech_select_default;
+ g_technology_lcu : NATURAL := c_tech_select_default;
+ g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
-- g_data_type = c_tb_tech_tse_data_type_symbols = 0
-- g_data_type = c_tb_tech_tse_data_type_counter = 1
-- g_data_type = c_tb_tech_tse_data_type_arp = 2
@@ -67,6 +69,9 @@ ENTITY tb_eth IS
-- g_data_type = c_tb_tech_tse_data_type_udp = 4
g_data_type : NATURAL := c_tb_tech_tse_data_type_udp
);
+ PORT (
+ tb_end : OUT STD_LOGIC
+ );
END tb_eth;
@@ -197,7 +202,6 @@ ARCHITECTURE tb OF tb_eth IS
CONSTANT c_dut_control_tx_en : NATURAL := 2**c_eth_mm_reg_control_bi.tx_en;
-- Clocks and reset
- SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL eth_clk : STD_LOGIC := '0'; -- tse reference clock
SIGNAL sys_clk : STD_LOGIC := '0'; -- system clock
SIGNAL st_clk : STD_LOGIC; -- stream clock
@@ -251,6 +255,7 @@ ARCHITECTURE tb OF tb_eth IS
SIGNAL lcu_led : t_tech_tse_led;
-- Verification
+ SIGNAL tx_end : STD_LOGIC := '0';
SIGNAL tx_pkt_cnt : NATURAL := 0;
SIGNAL rx_pkt_cnt : NATURAL := 0;
@@ -258,8 +263,8 @@ BEGIN
-- run 50 us
- eth_clk <= NOT eth_clk OR tb_end AFTER eth_clk_period/2; -- TSE reference clock
- sys_clk <= NOT sys_clk OR tb_end AFTER sys_clk_period/2; -- System clock
+ eth_clk <= NOT eth_clk AFTER eth_clk_period/2; -- TSE reference clock
+ sys_clk <= NOT sys_clk AFTER sys_clk_period/2; -- System clock
mm_clk <= sys_clk;
st_clk <= sys_clk;
@@ -446,7 +451,7 @@ BEGIN
-- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
FOR I IN 0 TO 1500 * 5 LOOP WAIT UNTIL rising_edge(st_clk); END LOOP;
- tb_end <= '1';
+ tx_end <= '1';
WAIT;
END PROCESS;
@@ -555,7 +560,8 @@ BEGIN
p_tb_end : PROCESS
BEGIN
- WAIT UNTIL tb_end='1';
+ tb_end <= '0';
+ WAIT UNTIL tx_end='1';
-- Verify that all transmitted packets have been received
IF tx_pkt_cnt=0 THEN
@@ -566,9 +572,14 @@ BEGIN
REPORT "Not all transmitted packets were received." SEVERITY ERROR;
END IF;
- -- Do keep wait for 10 us after tb_end. Otherwise without wait for 10 us use severity FAILURE to stop the simulation and avoid the PLL lost lock messages after the tb_end.
+ -- Do keep wait for 10 us after tx_end.
WAIT FOR 10 us;
- ASSERT FALSE REPORT "Simulation tb_eth finished." SEVERITY NOTE;
+ tb_end <= '1';
+ IF g_tb_end=FALSE THEN
+ REPORT "Tb simulation finished." SEVERITY NOTE;
+ ELSE
+ REPORT "Tb simulation finished." SEVERITY FAILURE;
+ END IF;
WAIT;
END PROCESS;
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
index 55cf0109c770c9b2fd38a9652e788a09ef565f67..e612c87c426737f2e5c2b49b00b92d420da2bc81 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
@@ -30,28 +30,46 @@
LIBRARY IEEE, technology_lib, tech_tse_lib;
USE IEEE.std_logic_1164.ALL;
USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
USE tech_tse_lib.tb_tech_tse_pkg.ALL;
ENTITY tb_tb_eth IS
GENERIC (
- g_technology_dut : NATURAL := c_tech_stratixiv
+ g_technology_dut : NATURAL := c_tech_select_default
);
END tb_tb_eth;
ARCHITECTURE tb OF tb_tb_eth IS
- CONSTANT c_technology_lcu : NATURAL := c_tech_stratixiv;
+ CONSTANT c_technology_lcu : NATURAL := c_tech_select_default;
+
+ CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL tb_end_vec : STD_LOGIC_VECTOR(7 DOWNTO 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
BEGIN
- -- Try ETH settings : GENERIC MAP (g_data_type => )
+-- g_technology_dut : NATURAL := c_tech_select_default;
+-- g_technology_lcu : NATURAL := c_tech_select_default;
+-- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+-- -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
+-- -- g_data_type = c_tb_tech_tse_data_type_counter = 1
+-- -- g_data_type = c_tb_tech_tse_data_type_arp = 2
+-- -- g_data_type = c_tb_tech_tse_data_type_ping = 3
+-- -- g_data_type = c_tb_tech_tse_data_type_udp = 4
+-- g_data_type : NATURAL := c_tb_tech_tse_data_type_udp
- u_use_symbols : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, c_tb_tech_tse_data_type_symbols);
- u_use_counter : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, c_tb_tech_tse_data_type_counter);
- u_use_arp : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, c_tb_tech_tse_data_type_arp );
- u_use_ping : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, c_tb_tech_tse_data_type_ping );
- u_use_udp : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, c_tb_tech_tse_data_type_udp );
+ u_use_symbols : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, c_tb_tech_tse_data_type_symbols) PORT MAP (tb_end_vec(0));
+ u_use_counter : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, c_tb_tech_tse_data_type_counter) PORT MAP (tb_end_vec(1));
+ u_use_arp : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, c_tb_tech_tse_data_type_arp ) PORT MAP (tb_end_vec(2));
+ u_use_ping : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, c_tb_tech_tse_data_type_ping ) PORT MAP (tb_end_vec(3));
+ u_use_udp : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(4));
+ p_tb_end : PROCESS
+ BEGIN
+ WAIT UNTIL tb_end_vec=c_tb_end_vec;
+ REPORT "Multi tb simulation finished." SEVERITY FAILURE;
+ WAIT;
+ END PROCESS;
END tb;