diff --git a/libraries/io/eth/src/vhdl/eth_statistics.vhd b/libraries/io/eth/src/vhdl/eth_statistics.vhd
index 3647085944f1d2440dfd991dbc312f3a7b7a0e9f..39c93d010cff133efae51a02c70f8a70cced78a3 100644
--- a/libraries/io/eth/src/vhdl/eth_statistics.vhd
+++ b/libraries/io/eth/src/vhdl/eth_statistics.vhd
@@ -36,6 +36,7 @@ LIBRARY IEEE, common_lib, work, technology_lib, dp_lib, tech_tse_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
@@ -43,7 +44,8 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY eth_statistics IS
PORT (
- serial_in : IN STD_LOGIC;
+ eth_clk : IN STD_LOGIC;
+ eth_serial_in : IN STD_LOGIC;
pkt_cnt : OUT NATURAL;
pkt_len : OUT NATURAL
@@ -53,6 +55,79 @@ END eth_statistics;
ARCHITECTURE str OF eth_statistics IS
+ SIGNAL tech_tse_rx_src_out : t_dp_sosi;
+
BEGIN
+ ------------------------------------------------------------------------------
+ -- Use tech_tse with internal simulation model as Ethernet receiver
+ ------------------------------------------------------------------------------
+ u_tech_tse : ENTITY tech_tse_lib.tech_tse
+ GENERIC MAP(
+ g_sim => TRUE,
+ g_sim_level => 1,
+ g_sim_tx => FALSE,
+ g_sim_rx => TRUE
+ )
+ PORT MAP (
+ mm_rst => '0',
+ mm_clk => '0',
+ cal_rec_clk => '0',
+
+ eth_clk => eth_clk,
+
+ mm_sla_in => c_mem_mosi_rst,
+
+ tx_mac_in => ('0','0','0','0','0'),
+
+ tx_snk_clk => eth_clk,
+ tx_snk_in => c_dp_sosi_rst,
+
+ rx_src_clk => eth_clk,
+ rx_src_in => c_dp_siso_rdy,
+
+ rx_src_out => tech_tse_rx_src_out,
+
+ eth_rxp => eth_serial_in
+ );
+
+ ------------------------------------------------------------------------------
+ -- Use 2 BSN monitors:
+ -- . Monitor A captures the number of SOPs per test interval;
+ -- . Monitor B captures the number of valid words per packet.
+ ------------------------------------------------------------------------------
+-- u_mon : ENTITY work.dp_bsn_monitor
+-- GENERIC MAP (
+-- g_sync_timeout => g_sync_timeout,
+-- g_error_bi => g_error_bi,
+-- g_log_first_bsn => g_log_first_bsn
+-- )
+-- PORT MAP (
+-- rst => dp_rst,
+-- clk => dp_clk,
+--
+-- -- ST interface
+-- in_siso => in_siso_arr(i),
+-- in_sosi => in_sosi_arr(i),
+-- sync_in => sync_in,
+--
+-- -- MM interface
+-- -- . control
+-- mon_evt => mon_evt_arr(i),
+-- mon_sync => OPEN,
+-- mon_sync_timeout => mon_sync_timeout_arr(i),
+-- -- . siso
+-- mon_ready_stable => mon_ready_stable_arr(i),
+-- mon_xon_stable => mon_xon_stable_arr(i),
+-- -- . sosi
+-- mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
+-- mon_nof_sop => mon_nof_sop_arr(i),
+-- mon_nof_err => mon_nof_err_arr(i),
+-- mon_nof_valid => mon_nof_valid_arr(i),
+--
+-- mon_bsn_first => mon_bsn_first_arr(i),
+-- mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt_arr(i)
+-- );
+
+
END str;
diff --git a/libraries/technology/transceiver/sim_transceiver_deserializer.vhd b/libraries/technology/transceiver/sim_transceiver_deserializer.vhd
index 8080af02c149539561c5374f98a851438f2e647e..f1419bac104e735f4dce5d81d876d4b1244d0042 100644
--- a/libraries/technology/transceiver/sim_transceiver_deserializer.vhd
+++ b/libraries/technology/transceiver/sim_transceiver_deserializer.vhd
@@ -20,6 +20,8 @@
--
--------------------------------------------------------------------------------
+-- Author:
+-- . Daniel van der Schuur
-- Purpose:
-- Basic deserializer model for fast transceiver simulation
-- Description:
@@ -44,6 +46,8 @@ ENTITY sim_transceiver_deserializer IS
rx_out_data : OUT STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
rx_out_ctrl : OUT STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);
+ rx_out_sop : OUT STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);
+ rx_out_eop : OUT STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);
rx_serial_in : IN STD_LOGIC
);
@@ -53,9 +57,7 @@ END sim_transceiver_deserializer;
ARCHITECTURE beh OF sim_transceiver_deserializer IS
- CONSTANT c_line_clk_period : TIME := g_tr_clk_period * 8 / 10 / g_data_w;
- CONSTANT c_tr_clk_period_sim : TIME := c_line_clk_period * g_data_w * 10 / 8;
-
+ CONSTANT c_line_clk_period : TIME := g_tr_clk_period * 8 / 10 / g_data_w;
CONSTANT c_nof_bytes_per_data : NATURAL := g_data_w/c_byte_w;
BEGIN
@@ -63,9 +65,14 @@ BEGIN
p_deserialize: PROCESS
VARIABLE v_rx_out_data : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
VARIABLE v_rx_out_ctrl : STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);
+ VARIABLE v_rx_out_sop : STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);
+ VARIABLE v_rx_out_eop : STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);
BEGIN
--rx_out_data <= (OTHERS=>'0');
rx_out_ctrl <= (OTHERS=>'0');
+ rx_out_sop <= (OTHERS=>'0');
+ rx_out_eop <= (OTHERS=>'0');
+
WAIT UNTIL tr_rst='0' ;
-- Align to tr_clk
@@ -84,7 +91,13 @@ BEGIN
END LOOP;
v_rx_out_ctrl(byte) := rx_serial_in; -- Get the 1 control bit from the line for each byte
WAIT FOR c_line_clk_period;
- --Ignore tenth bit -- Get the 1 unused tenth bit = '0' from the line
+ v_rx_out_sop(byte) := '0'; -- Get the SOP/EOP (tenth) bit from the line
+ v_rx_out_eop(byte) := '0';
+ IF rx_serial_in='1' THEN
+ v_rx_out_sop(byte) := '1';
+ ELSIF rx_serial_in = 'U' THEN
+ v_rx_out_eop(byte) := '1';
+ END IF;
IF byte<c_nof_bytes_per_data-1 THEN
WAIT FOR c_line_clk_period; -- exit loop in last half line clock cycle
END IF;
@@ -96,6 +109,8 @@ BEGIN
-- End of this deserialization cycle: the rx data word has been assembled.
rx_out_data <= v_rx_out_data;
rx_out_ctrl <= v_rx_out_ctrl;
+ rx_out_sop <= v_rx_out_sop;
+ rx_out_eop <= v_rx_out_eop;
END LOOP;
END PROCESS;
diff --git a/libraries/technology/transceiver/sim_transceiver_gx.vhd b/libraries/technology/transceiver/sim_transceiver_gx.vhd
index 820b78a6ba6064de4b3798059858766d7406cb68..ed292ea5066da526585efc088d778e2f74907621 100644
--- a/libraries/technology/transceiver/sim_transceiver_gx.vhd
+++ b/libraries/technology/transceiver/sim_transceiver_gx.vhd
@@ -73,7 +73,11 @@ ARCHITECTURE str OF sim_transceiver_gx IS
SIGNAL tx_ready : STD_LOGIC;
SIGNAL tx_in_ctrl : t_ctrl_2arr;
+ SIGNAL tx_in_sop : t_ctrl_2arr;
+ SIGNAL tx_in_eop : t_ctrl_2arr;
SIGNAL rx_out_ctrl : t_ctrl_2arr;
+ SIGNAL rx_out_sop : t_ctrl_2arr;
+ SIGNAL rx_out_eop : t_ctrl_2arr;
BEGIN
@@ -111,6 +115,8 @@ BEGIN
tx_siso_arr(i).xon <= tx_ready;
tx_in_ctrl(i) <= (OTHERS=>tx_sosi_arr(i).valid);
+ tx_in_sop(i) <= (OTHERS=>tx_sosi_arr(i).sop);
+ tx_in_eop(i) <= (OTHERS=>tx_sosi_arr(i).eop);
u_ser: ENTITY work.sim_transceiver_serializer
GENERIC MAP (
@@ -125,6 +131,8 @@ BEGIN
tx_in_data => tx_sosi_arr(i).data(g_data_w-1 DOWNTO 0),
tx_in_ctrl => tx_in_ctrl(i),
+ tx_in_sop => tx_in_sop(i),
+ tx_in_eop => tx_in_eop(i),
tx_serial_out => tx_dataout(i)
);
@@ -144,12 +152,16 @@ BEGIN
rx_out_data => rx_sosi_arr(i).data(g_data_w-1 DOWNTO 0),
rx_out_ctrl => rx_out_ctrl(i),
+ rx_out_sop => rx_out_sop(i),
+ rx_out_eop => rx_out_eop(i),
rx_serial_in => rx_datain(i)
);
END GENERATE;
rx_sosi_arr(i).valid <= andv(rx_out_ctrl(i));
+ rx_sosi_arr(i).sop <= andv(rx_out_sop(i));
+ rx_sosi_arr(i).eop <= andv(rx_out_eop(i));
END GENERATE;
diff --git a/libraries/technology/transceiver/sim_transceiver_serializer.vhd b/libraries/technology/transceiver/sim_transceiver_serializer.vhd
index 4d8598b1ab391811c22c412317c3bf48989620b5..80804911cc5a1e623d7439a398a52079d8adb767 100644
--- a/libraries/technology/transceiver/sim_transceiver_serializer.vhd
+++ b/libraries/technology/transceiver/sim_transceiver_serializer.vhd
@@ -20,6 +20,8 @@
--
--------------------------------------------------------------------------------
+-- Author:
+-- . Daniel van der Schuur
-- Purpose:
-- Basic serializer model for fast transceiver simulation
-- Description:
@@ -83,7 +85,9 @@ ENTITY sim_transceiver_serializer IS
tr_rst : IN STD_LOGIC;
tx_in_data : IN STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
- tx_in_ctrl : IN STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);
+ tx_in_ctrl : IN STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0); -- 1 valid bit per byte
+ tx_in_sop : IN STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0) := (OTHERS=>'0'); -- 1 SOP bit per byte
+ tx_in_eop : IN STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0) := (OTHERS=>'0'); -- 1 EOP bit per byte
tx_serial_out : OUT STD_LOGIC
);
@@ -103,6 +107,8 @@ BEGIN
p_serialize: PROCESS
VARIABLE v_tx_in_data : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
VARIABLE v_tx_in_ctrl : STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);
+ VARIABLE v_tx_in_sop : STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);
+ VARIABLE v_tx_in_eop : STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);
BEGIN
tx_serial_out <= '0';
WAIT UNTIL tr_rst='0';
@@ -111,6 +117,8 @@ BEGIN
WAIT UNTIL rising_edge(tr_clk);
v_tx_in_data := tx_in_data;
v_tx_in_ctrl := tx_in_ctrl;
+ v_tx_in_sop := tx_in_sop;
+ v_tx_in_eop := tx_in_eop;
WHILE tb_end='0' LOOP
-- Data word serialization cycle
@@ -120,9 +128,14 @@ BEGIN
tx_serial_out <= v_tx_in_data(byte*c_byte_w+bit); -- Put the 8 data bits of the data byte on the line
WAIT FOR c_line_clk_period;
END LOOP;
- tx_serial_out <= v_tx_in_ctrl(byte); -- Put the 1 control bit on the line for each byte
+ tx_serial_out <= v_tx_in_ctrl(byte); -- Put the valid bit on the line for each byte
WAIT FOR c_line_clk_period;
- tx_serial_out <= '0'; -- Put the 1 unused tenth bit = '0' on the line
+ tx_serial_out <= '0'; -- Put the SOP/EOP indicator bit on the line. '1'=SOP; 'U'=EOP.
+ IF v_tx_in_sop(byte) = '1' THEN
+ tx_serial_out <= '1';
+ ELSIF v_tx_in_eop(byte)='1' THEN
+ tx_serial_out <= 'U';
+ END IF;
IF byte<c_nof_bytes_per_data-1 THEN
WAIT FOR c_line_clk_period; -- exit loop in last line clock cycle
END IF;
@@ -133,6 +146,9 @@ BEGIN
v_tx_in_data := tx_in_data;
v_tx_in_ctrl := tx_in_ctrl;
+ v_tx_in_sop := tx_in_sop;
+ v_tx_in_eop := tx_in_eop;
+
END LOOP;
END PROCESS;
diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg
index a386155b81b1571939820ef7e4ef31c04f99daf6..2e38ea022f6c2bb162912494a433fe3e061db4aa 100644
--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -4,7 +4,7 @@ hdl_lib_uses_synth = technology common dp
hdl_lib_uses_ip = ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx
ip_arria10_tse_sgmii_lvds ip_arria10_tse_sgmii_gx
ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_gx
-hdl_lib_uses_sim =
+hdl_lib_uses_sim = tech_transceiver
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_lvds_lib
@@ -20,6 +20,7 @@ synth_files =
tech_tse_stratixiv.vhd
tech_tse_arria10.vhd
tech_tse_arria10_e3sge3.vhd
+ sim_tse.vhd
tech_tse.vhd
tb_tech_tse_pkg.vhd
diff --git a/libraries/technology/tse/sim_tse.vhd b/libraries/technology/tse/sim_tse.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9ae20025277303acf57013b3d96e0796e6c639c6
--- /dev/null
+++ b/libraries/technology/tse/sim_tse.vhd
@@ -0,0 +1,196 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2016
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Author:
+-- . Daniel van der Schuur
+-- Purpose:
+-- . Drop-in simulation model for tech_tse.vhd.
+-- Description:
+-- . Basically just a wrapper around sim_tse.
+
+LIBRARY IEEE, common_lib, dp_lib, tech_transceiver_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.tech_tse_pkg.ALL;
+
+ENTITY sim_tse IS
+ GENERIC(
+ g_tx : BOOLEAN;
+ g_rx : BOOLEAN
+ );
+ PORT(
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC; -- unused
+ mm_clk : IN STD_LOGIC; -- unused
+ eth_clk : IN STD_LOGIC; -- 125 MHz
+ tx_snk_clk : IN STD_LOGIC; -- DP
+ rx_src_clk : IN STD_LOGIC; -- DP
+
+ -- Memory Mapped Slave
+ mm_sla_in : IN t_mem_mosi;
+ mm_sla_out : OUT t_mem_miso;
+
+ -- MAC transmit interface
+ -- . ST sink
+ tx_snk_in : IN t_dp_sosi;
+ tx_snk_out : OUT t_dp_siso;
+ -- . MAC specific
+ tx_mac_in : IN t_tech_tse_tx_mac;
+ tx_mac_out : OUT t_tech_tse_tx_mac;
+
+ -- MAC receive interface
+ -- . ST Source
+ rx_src_in : IN t_dp_siso;
+ rx_src_out : OUT t_dp_sosi;
+ -- . MAC specific
+ rx_mac_out : OUT t_tech_tse_rx_mac;
+
+ -- PHY interface
+ eth_txp : OUT STD_LOGIC;
+ eth_rxp : IN STD_LOGIC;
+
+ tse_led : OUT t_tech_tse_led
+ );
+
+END sim_tse;
+
+ARCHITECTURE str OF sim_tse IS
+
+ SIGNAL tr_clk : STD_LOGIC;
+ SIGNAL tr_rst : STD_LOGIC;
+
+ SIGNAL tx_snk_rst : STD_LOGIC;
+ SIGNAL rx_src_rst : STD_LOGIC;
+
+ SIGNAL sim_transceiver_gx_tx_snk_in_arr : t_dp_sosi_arr(0 DOWNTO 0);
+ SIGNAL sim_transceiver_gx_tx_snk_out_arr : t_dp_siso_arr(0 DOWNTO 0);
+
+ SIGNAL sim_transceiver_gx_rx_src_out_arr : t_dp_sosi_arr(0 DOWNTO 0);
+ SIGNAL sim_transceiver_gx_rx_src_in_arr : t_dp_siso_arr(0 DOWNTO 0);
+
+BEGIN
+
+ -------------------------------------------------------------------------------
+ -- TX FIFO
+ -- . tx_snk_clk (dp_clk) -> tr_clk
+ -- . User data width (32b) -> transceiver PCS data width (8b)
+ -------------------------------------------------------------------------------
+ u_common_areset_tx : ENTITY common_lib.common_areset
+ GENERIC MAP(
+ g_rst_level => '1'
+ )
+ PORT MAP(
+ clk => tx_snk_clk,
+ in_rst => '0',
+ out_rst => tx_snk_rst
+ );
+
+ u_dp_fifo_dc_mixed_widths_tx : ENTITY dp_lib.dp_fifo_dc_mixed_widths
+ GENERIC MAP (
+ g_wr_data_w => c_tech_tse_data_w,
+ g_rd_data_w => c_byte_w,
+ g_use_ctrl => TRUE, --SOP, EOP support
+ g_wr_fifo_size => 50,
+ g_rd_fifo_rl => 1
+ )
+ PORT MAP (
+ wr_rst => tx_snk_rst,
+ wr_clk => tx_snk_clk,
+ rd_rst => tr_rst,
+ rd_clk => tr_clk,
+
+ snk_in => tx_snk_in,
+ snk_out => tx_snk_out,
+
+ src_out => sim_transceiver_gx_tx_snk_in_arr(0),
+ src_in => sim_transceiver_gx_tx_snk_out_arr(0)
+ );
+
+ -------------------------------------------------------------------------------
+ -- Transceiver sim model
+ -- . Inside this model, tr_clk = tx_clk = rx_clk. We're using its output
+ -- tx_clk,tx_rst as local tr_clk,tr_rst to prevent delta delay issues.
+ -------------------------------------------------------------------------------
+ u_sim_transceiver_gx : ENTITY tech_transceiver_lib.sim_transceiver_gx
+ GENERIC MAP(
+ g_data_w => c_byte_w,
+ g_nof_gx => 1,
+ g_mbps => 1250,
+ g_rx => g_rx,
+ g_tx => g_tx
+ )
+ PORT MAP (
+ tb_end => '0',
+
+ tr_clk => eth_clk,
+
+ tx_clk(0) => tr_clk,
+ tx_rst(0) => tr_rst,
+
+ tx_sosi_arr => sim_transceiver_gx_tx_snk_in_arr,
+ tx_siso_arr => sim_transceiver_gx_tx_snk_out_arr,
+ tx_dataout(0) => eth_txp,
+
+ rx_datain(0) => eth_rxp,
+ rx_sosi_arr => sim_transceiver_gx_rx_src_out_arr,
+ rx_siso_arr => sim_transceiver_gx_rx_src_in_arr
+ );
+
+ -------------------------------------------------------------------------------
+ -- RX FIFO
+ -- . tr_clk => rx_src_clk (dp_clk)
+ -- . transceiver PCS data width (8b) -> User data width (32b)
+ -------------------------------------------------------------------------------
+ u_common_areset_rx : ENTITY common_lib.common_areset
+ GENERIC MAP(
+ g_rst_level => '1'
+ )
+ PORT MAP(
+ clk => rx_src_clk,
+ in_rst => '0',
+ out_rst => rx_src_rst
+ );
+
+ u_dp_fifo_dc_mixed_widths_rx : ENTITY dp_lib.dp_fifo_dc_mixed_widths
+ GENERIC MAP (
+ g_wr_data_w => c_byte_w,
+ g_rd_data_w => c_tech_tse_data_w,
+ g_use_ctrl => TRUE, --SOP, EOP support
+ g_wr_fifo_size => 50,
+ g_rd_fifo_rl => 1
+ )
+ PORT MAP (
+ wr_rst => tr_rst,
+ wr_clk => tr_clk,
+ rd_rst => rx_src_rst,
+ rd_clk => rx_src_clk,
+
+ snk_in => sim_transceiver_gx_rx_src_out_arr(0),
+ snk_out => sim_transceiver_gx_rx_src_in_arr(0),
+
+ src_out => rx_src_out,
+ src_in => rx_src_in
+ );
+
+end str;
diff --git a/libraries/technology/tse/tech_tse.vhd b/libraries/technology/tse/tech_tse.vhd
index f91fa4c3690d2d3dfce1b2a8bc72bf280c209267..064d5c501403a01e8c2081289af1b2d293a24e95 100644
--- a/libraries/technology/tse/tech_tse.vhd
+++ b/libraries/technology/tse/tech_tse.vhd
@@ -32,7 +32,11 @@ USE work.tech_tse_pkg.ALL;
ENTITY tech_tse IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
- g_ETH_PHY : STRING := "LVDS" -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+ g_ETH_PHY : STRING := "LVDS"; -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model;
+ g_sim_tx : BOOLEAN := TRUE;
+ g_sim_rx : BOOLEAN := TRUE
);
PORT (
-- Clocks and reset
@@ -74,9 +78,12 @@ END tech_tse;
ARCHITECTURE str OF tech_tse IS
+ CONSTANT c_use_technology : BOOLEAN := g_sim = FALSE OR g_sim_level = 0;
+ CONSTANT c_use_sim_model : BOOLEAN := NOT c_use_technology;
+
BEGIN
- gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+ gen_ip_stratixiv : IF c_use_technology=TRUE AND g_technology=c_tech_stratixiv GENERATE
u0 : ENTITY work.tech_tse_stratixiv
GENERIC MAP (g_ETH_PHY)
PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
@@ -90,7 +97,7 @@ BEGIN
tse_led);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF c_use_technology=TRUE AND g_technology=c_tech_arria10 GENERATE
u0 : ENTITY work.tech_tse_arria10
GENERIC MAP (g_ETH_PHY)
PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
@@ -103,7 +110,7 @@ BEGIN
tse_led);
END GENERATE;
- gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ gen_ip_arria10_e3sge3 : IF c_use_technology=TRUE AND g_technology=c_tech_arria10_e3sge3 GENERATE
u0 : ENTITY work.tech_tse_arria10_e3sge3
GENERIC MAP (g_ETH_PHY)
PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
@@ -115,5 +122,18 @@ BEGIN
eth_txp, eth_rxp,
tse_led);
END GENERATE;
+
+ gen_sim_tse : IF c_use_sim_model=TRUE GENERATE
+ u_sim_tse : ENTITY work.sim_tse
+ GENERIC MAP (g_sim_tx, g_sim_rx)
+ PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
+ mm_sla_in, mm_sla_out,
+ tx_snk_in, tx_snk_out,
+ tx_mac_in, tx_mac_out,
+ rx_src_in, rx_src_out,
+ rx_mac_out,
+ eth_txp, eth_rxp,
+ tse_led);
+ END GENERATE;
END ARCHITECTURE;