diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
index 91ef26c0d96f31d1fa81c08e570123b6e8945fbb..ac211ceb77d6fe66c6f641e563556adb4d08f55f 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
@@ -126,65 +126,39 @@ BEGIN
i_tx_rst_arr <= NOT txc_tx_ready_arr;
i_rx_rst_arr <= NOT rxc_rx_ready_arr;
- gen_phy: IF g_sim = FALSE OR g_sim_level = 0 GENERATE
- -- Altera's IP
- u_tech_xaui : ENTITY tech_xaui_lib.tech_xaui
- GENERIC MAP (
- g_technology => g_technology,
- g_nof_xaui => g_nof_xaui
- )
- PORT MAP (
- tr_clk => tr_clk,
-
- cal_rec_clk => cal_rec_clk,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- xaui_mosi => xaui_mosi,
- xaui_miso => xaui_miso,
-
- tx_clk_arr => tx_clk_arr,
- rx_clk_arr_out => rx_clk_arr_out,
- rx_clk_arr_in => rx_clk_arr_in,
-
- txc_tx_ready_arr => txc_tx_ready_arr,
- rxc_rx_ready_arr => rxc_rx_ready_arr,
- txc_rx_channelaligned_arr => txc_rx_channelaligned_arr,
-
- xgmii_tx_dc_arr => xgmii_tx_dc_in_arr,
- xgmii_rx_dc_arr => xgmii_rx_dc_out_arr,
-
- xaui_tx_arr => xaui_tx_arr,
- xaui_rx_arr => xaui_rx_arr
- );
- END GENERATE;
+ u_tech_xaui : ENTITY tech_xaui_lib.tech_xaui
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_xaui => g_nof_xaui
+ )
+ PORT MAP (
+ tr_clk => tr_clk,
+ tr_rst => tr_rst,
- gen_sim: IF g_sim = TRUE AND g_sim_level = 1 GENERATE
- -- Behavioural serdes model (fast)
- u_sim_xaui : ENTITY tech_xaui_lib.sim_xaui
- GENERIC MAP (
- g_nof_xaui => g_nof_xaui
- )
- PORT MAP (
- tr_clk => tr_clk,
- tr_rst => tr_rst,
-
- tx_clk_arr => tx_clk_arr,
- rx_clk_arr_out => rx_clk_arr_out,
- rx_clk_arr_in => rx_clk_arr_in,
+ cal_rec_clk => cal_rec_clk,
- txc_tx_ready_arr => txc_tx_ready_arr,
- rxc_rx_ready_arr => rxc_rx_ready_arr,
- txc_rx_channelaligned_arr => txc_rx_channelaligned_arr,
-
- xgmii_tx_dc_arr => xgmii_tx_dc_in_arr,
- xgmii_rx_dc_arr => xgmii_rx_dc_out_arr,
-
- xaui_tx_arr => xaui_tx_arr,
- xaui_rx_arr => xaui_rx_arr
- );
- END GENERATE;
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ xaui_mosi => xaui_mosi,
+ xaui_miso => xaui_miso,
+
+ tx_clk_arr => tx_clk_arr,
+ rx_clk_arr_out => rx_clk_arr_out,
+ rx_clk_arr_in => rx_clk_arr_in,
+
+ txc_tx_ready_arr => txc_tx_ready_arr,
+ rxc_rx_ready_arr => rxc_rx_ready_arr,
+ txc_rx_channelaligned_arr => txc_rx_channelaligned_arr,
+
+ xgmii_tx_dc_arr => xgmii_tx_dc_in_arr,
+ xgmii_rx_dc_arr => xgmii_rx_dc_out_arr,
+
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr
+ );
-----------------------------------------------------------------------------
-- SOSI-XGMII user interface
diff --git a/libraries/technology/xaui/tech_xaui.vhd b/libraries/technology/xaui/tech_xaui.vhd
index be6fd7cdbe69da5960424c74ae4449b1439ab772..b9101b9c87039107d798b4f5078d0c4cf86039dc 100644
--- a/libraries/technology/xaui/tech_xaui.vhd
+++ b/libraries/technology/xaui/tech_xaui.vhd
@@ -31,11 +31,14 @@ USE common_lib.common_interface_layers_pkg.ALL;
ENTITY tech_xaui IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
g_nof_xaui : NATURAL := 1 -- Up to 3 (hard XAUI only) supported
);
PORT (
-- Transceiver PLL reference clock
tr_clk : IN STD_LOGIC; -- 156.25 MHz
+ tr_rst : IN STD_LOGIC;
-- Calibration & reconfig clock
cal_rec_clk : IN STD_LOGIC;
@@ -65,20 +68,34 @@ ENTITY tech_xaui IS
xaui_rx_arr : IN t_xaui_arr(g_nof_xaui-1 DOWNTO 0)
);
END tech_xaui;
+
ARCHITECTURE str OF tech_xaui IS
+ CONSTANT c_use_technology : BOOLEAN := g_sim = FALSE OR g_sim_level = 0;
+ CONSTANT c_use_sim_model : BOOLEAN := NOT c_use_technology;
+
BEGIN
- gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+ gen_ip_stratixiv : IF c_use_technology=TRUE AND g_technology=c_tech_stratixiv GENERATE
u0 : ENTITY work.tech_xaui_stratixiv
GENERIC MAP (g_nof_xaui)
- PORT MAP (tr_clk, cal_rec_clk, mm_clk, mm_rst, xaui_mosi, xaui_miso,
+ PORT MAP (tr_clk, tr_rst, cal_rec_clk, mm_clk, mm_rst, xaui_mosi, xaui_miso,
tx_clk_arr, rx_clk_arr_out, rx_clk_arr_in, txc_tx_ready_arr, rxc_rx_ready_arr, txc_rx_channelaligned_arr,
xgmii_tx_dc_arr, xgmii_rx_dc_arr,
xaui_tx_arr, xaui_rx_arr);
END GENERATE;
-
+
+
+ gem_sim_xaui : IF c_use_sim_model=TRUE GENERATE
+ u0 : ENTITY work.sim_xaui
+ GENERIC MAP (g_nof_xaui)
+ PORT MAP (tr_clk, tr_rst, cal_rec_clk, mm_clk, mm_rst, xaui_mosi, xaui_miso,
+ tx_clk_arr, rx_clk_arr_out, rx_clk_arr_in, txc_tx_ready_arr, rxc_rx_ready_arr, txc_rx_channelaligned_arr,
+ xgmii_tx_dc_arr, xgmii_rx_dc_arr,
+ xaui_tx_arr, xaui_rx_arr);
+ END GENERATE;
+
END str;
diff --git a/libraries/technology/xaui/tech_xaui_stratixiv.vhd b/libraries/technology/xaui/tech_xaui_stratixiv.vhd
index f4cbe969994ffe5d5ede0e5780e3a8b0fe1ee91c..e520519669f413a8a2a64c2ec51b36fee7b2695f 100644
--- a/libraries/technology/xaui/tech_xaui_stratixiv.vhd
+++ b/libraries/technology/xaui/tech_xaui_stratixiv.vhd
@@ -38,6 +38,7 @@ ENTITY tech_xaui_stratixiv IS
PORT (
-- Transceiver PLL reference clock
tr_clk : IN STD_LOGIC; -- 156.25 MHz
+ tr_rst : IN STD_LOGIC;
-- Calibration & reconfig clock
cal_rec_clk : IN STD_LOGIC;