diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
index cdc4c14fd96e98b0b24e48ec89114455cfcb4528..782748e7d4e2e3d4b6e5ec42794552666401f6cb 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
@@ -24,8 +24,8 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
-USE unb2b_board_lib.unb2_board_peripherals_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE work.qsys_unb2b_heater_pkg.ALL;
@@ -170,23 +170,23 @@ BEGIN
clk_clk => mm_clk,
reset_reset_n => i_reset_n,
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
pio_wdi_external_connection_export => pout_wdi,
avs_eth_0_reset_export => eth1g_mm_rst,
avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
@@ -195,7 +195,7 @@ BEGIN
reg_unb_sens_reset_export => OPEN,
reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
@@ -203,7 +203,7 @@ BEGIN
reg_unb_pmbus_reset_export => OPEN,
reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0),
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0),
reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
@@ -211,7 +211,7 @@ BEGIN
reg_fpga_temp_sens_reset_export => OPEN,
reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
@@ -219,7 +219,7 @@ BEGIN
reg_fpga_voltage_sens_reset_export => OPEN,
reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
@@ -227,7 +227,7 @@ BEGIN
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -235,7 +235,7 @@ BEGIN
pio_system_info_reset_export => OPEN,
pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
pio_system_info_write_export => reg_unb_system_info_mosi.wr,
pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_system_info_read_export => reg_unb_system_info_mosi.rd,
@@ -243,7 +243,7 @@ BEGIN
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
@@ -259,7 +259,7 @@ BEGIN
reg_remu_reset_export => OPEN,
reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
reg_remu_write_export => reg_remu_mosi.wr,
reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_remu_read_export => reg_remu_mosi.rd,
@@ -267,7 +267,7 @@ BEGIN
reg_epcs_reset_export => OPEN,
reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
reg_epcs_write_export => reg_epcs_mosi.wr,
reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_epcs_read_export => reg_epcs_mosi.rd,
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
index 7f85ee6b87a1dbf002ecc1acb9e1b18b61f92abb..f4ab4dd85d9d2d4f11d1f804c3f1a297aa0502f7 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
@@ -26,7 +26,7 @@ USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE util_lib.util_heater_pkg.ALL;
ENTITY unb2b_heater IS
@@ -51,9 +51,9 @@ ENTITY unb2b_heater IS
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
- VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
- TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
SENS_SC : INOUT STD_LOGIC;
@@ -65,10 +65,10 @@ ENTITY unb2b_heater IS
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
- ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
);
END unb2b_heater;
@@ -76,8 +76,8 @@ END unb2b_heater;
ARCHITECTURE str OF unb2b_heater IS
-- Firmware version x.y
- CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 1);
- CONSTANT c_mm_clk_freq : NATURAL := c_unb2_board_mm_clk_freq_50M;
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
+ CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_50M;
-- System
SIGNAL cs_sim : STD_LOGIC;
@@ -156,15 +156,15 @@ ARCHITECTURE str OF unb2b_heater IS
SIGNAL reg_heater_miso : t_mem_miso;
-- QSFP leds
- SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
- SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+ SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+ SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
BEGIN
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
- u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2_board
+ u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
GENERIC MAP (
g_sim => g_sim,
g_technology => g_technology,
@@ -176,8 +176,8 @@ BEGIN
g_fw_version => c_fw_version,
g_mm_clk_freq => c_mm_clk_freq,
g_dp_clk_use_pll=> TRUE,
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
g_tse_clk_buf => FALSE,--TRUE,
g_factory_image => g_factory_image
)
@@ -361,11 +361,11 @@ BEGIN
reg_heater_miso => reg_heater_miso
);
- u_front_led : ENTITY unb2b_board_lib.unb2_board_qsfp_leds
+ u_front_led : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds
GENERIC MAP (
g_sim => g_sim,
g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
)
PORT MAP (
@@ -375,9 +375,9 @@ BEGIN
red_led_arr => qsfp_red_led_arr
);
- u_front_io : ENTITY unb2b_board_lib.unb2_board_front_io
+ u_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io
GENERIC MAP (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
)
PORT MAP (
green_led_arr => qsfp_green_led_arr,
diff --git a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
index 73ece6e76e2bc8e9ccf906b9ec0e46f0b5e7e8bd..a47d705a870a1589c3541ce1037185d92778ea5a 100644
--- a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
@@ -46,7 +46,7 @@ LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
ENTITY tb_unb2b_heater IS
@@ -63,10 +63,10 @@ ARCHITECTURE tb OF tb_unb2b_heater IS
CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
CONSTANT c_node_nr : NATURAL := 3; -- Node 3
- CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb2_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2_board_nof_chip_w);
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb2b_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2b_board_nof_chip_w);
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
- CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 0);
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
CONSTANT c_cable_delay : TIME := 12 ns;
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
@@ -86,9 +86,9 @@ ARCHITECTURE tb OF tb_unb2b_heater IS
SIGNAL eth_txp : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL eth_rxp : STD_LOGIC_VECTOR(1 DOWNTO 0);
- SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0) := c_version;
- SIGNAL ID : STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0) := c_id;
- SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0) := c_version;
+ SIGNAL ID : STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0) := c_id;
+ SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
@@ -97,7 +97,7 @@ ARCHITECTURE tb OF tb_unb2b_heater IS
SIGNAL PMBUS_SD : STD_LOGIC;
SIGNAL PMBUS_ALERT : STD_LOGIC := '0';
- SIGNAL qsfp_led : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+ SIGNAL qsfp_led : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-- Model I2C sensor slaves as on the UniBoard
CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
index bc7abac851ef417315feb804c3ae425820bd7424..3db23c61c4bddb295dcce6bcacb0a95d2ae1a5d4 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
@@ -26,7 +26,7 @@ USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
@@ -52,9 +52,9 @@ ENTITY unb2b_jesd_node0 IS
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
- VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
- TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
SENS_SC : INOUT STD_LOGIC;
@@ -66,10 +66,10 @@ ENTITY unb2b_jesd_node0 IS
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
- ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-- JESD signals
jesd204_rx_serial_data : IN std_logic;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
index 088b8a43361758e264335b41250b1f188a3aff3e..cb0ffaf366e730b5240c16eb0708f9fa03bb48ed 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
@@ -26,7 +26,7 @@ USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
@@ -52,9 +52,9 @@ ENTITY unb2b_jesd_node3 IS
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
- VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
- TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
SENS_SC : INOUT STD_LOGIC;
@@ -66,10 +66,10 @@ ENTITY unb2b_jesd_node3 IS
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
- ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-- JESD signals
jesd204_rx_serial_data : IN std_logic;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
index 4f068ac4abd9aa2fa829ff34ea4a4be4666f80a8..8521bb9e0265a99f97316a9385a7f777c7206c1b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
@@ -24,8 +24,8 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
-USE unb2b_board_lib.unb2_board_peripherals_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE work.qsys_unb2b_jesd_pkg.ALL;
@@ -187,23 +187,23 @@ BEGIN
clk_clk => mm_clk,
reset_reset_n => i_reset_n,
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
pio_wdi_external_connection_export => pout_wdi,
avs_eth_0_reset_export => eth1g_mm_rst,
avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
@@ -212,7 +212,7 @@ BEGIN
reg_unb_sens_reset_export => OPEN,
reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
@@ -220,7 +220,7 @@ BEGIN
reg_unb_pmbus_reset_export => OPEN,
reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0),
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0),
reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
@@ -228,7 +228,7 @@ BEGIN
reg_fpga_temp_sens_reset_export => OPEN,
reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
@@ -236,7 +236,7 @@ BEGIN
reg_fpga_voltage_sens_reset_export => OPEN,
reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
@@ -244,7 +244,7 @@ BEGIN
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -252,7 +252,7 @@ BEGIN
pio_system_info_reset_export => OPEN,
pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
pio_system_info_write_export => reg_unb_system_info_mosi.wr,
pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_system_info_read_export => reg_unb_system_info_mosi.rd,
@@ -260,7 +260,7 @@ BEGIN
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
@@ -276,7 +276,7 @@ BEGIN
reg_remu_reset_export => OPEN,
reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
reg_remu_write_export => reg_remu_mosi.wr,
reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_remu_read_export => reg_remu_mosi.rd,
@@ -284,7 +284,7 @@ BEGIN
reg_epcs_reset_export => OPEN,
reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
reg_epcs_write_export => reg_epcs_mosi.wr,
reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_epcs_read_export => reg_epcs_mosi.rd,
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
index 6ff3fffd7c30bbae5b60df32b0fbebd6340306a9..813424263bcfb4af67ff36614e098620af9a9bfe 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
@@ -26,7 +26,7 @@ USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
@@ -53,9 +53,9 @@ ENTITY unb2b_jesd IS
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
- VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
- TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
SENS_SC : INOUT STD_LOGIC;
@@ -67,10 +67,10 @@ ENTITY unb2b_jesd IS
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
- ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-- JESD signals
jesd204_rx_serial_data : IN std_logic;
@@ -84,8 +84,8 @@ END unb2b_jesd;
ARCHITECTURE str OF unb2b_jesd IS
-- Firmware version x.y
- CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 1);
- CONSTANT c_mm_clk_freq : NATURAL := c_unb2_board_mm_clk_freq_100M;
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
+ CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
signal CLK : STD_LOGIC;
--signal PPS : STD_LOGIC;
@@ -165,8 +165,8 @@ ARCHITECTURE str OF unb2b_jesd IS
SIGNAL reg_remu_miso : t_mem_miso;
-- QSFP leds
- SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
- SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+ SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+ SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
-- JESD signals
@@ -187,7 +187,7 @@ BEGIN
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
- u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2_board
+ u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
GENERIC MAP (
g_sim => g_sim,
g_technology => g_technology,
@@ -198,8 +198,8 @@ BEGIN
g_stamp_svn => g_stamp_svn,
g_fw_version => c_fw_version,
g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
g_factory_image => g_factory_image,
g_protect_addr_range => g_protect_addr_range,
g_dp_clk_use_pll => FALSE
diff --git a/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
index 859aeba6a5062d1066f108f62c6a67388d5b3d8f..fb11681ba351a8052f893a8f7410ebadd19c6f99 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
@@ -46,10 +46,10 @@ LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
-USE i2c_lib.i2c_dev_unb2_pkg.ALL;
-USE i2c_lib.i2c_commander_unb2_pmbus_pkg.ALL;
+USE i2c_lib.i2c_dev_unb2b_pkg.ALL;
+USE i2c_lib.i2c_commander_unb2b_pmbus_pkg.ALL;
ENTITY tb_unb2b_minimal IS
GENERIC (
@@ -65,10 +65,10 @@ ARCHITECTURE tb OF tb_unb2b_minimal IS
CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
CONSTANT c_node_nr : NATURAL := 3; -- Node 3
- CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb2_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2_board_nof_chip_w);
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb2b_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2b_board_nof_chip_w);
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
- CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 0);
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
CONSTANT c_cable_delay : TIME := 12 ns;
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
@@ -88,9 +88,9 @@ ARCHITECTURE tb OF tb_unb2b_minimal IS
SIGNAL eth_txp : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL eth_rxp : STD_LOGIC_VECTOR(1 DOWNTO 0);
- SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0) := c_version;
- SIGNAL ID : STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0) := c_id;
- SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0) := c_version;
+ SIGNAL ID : STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0) := c_id;
+ SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
@@ -99,7 +99,7 @@ ARCHITECTURE tb OF tb_unb2b_minimal IS
SIGNAL PMBUS_SD : STD_LOGIC;
SIGNAL PMBUS_ALERT : STD_LOGIC := '0';
- SIGNAL qsfp_led : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+ SIGNAL qsfp_led : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-- Model I2C sensor slaves as on the UniBoard
CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
@@ -113,7 +113,7 @@ ARCHITECTURE tb OF tb_unb2b_minimal IS
CONSTANT c_uniboard_supply : REAL := 48.0; -- = assume 48.0 V on UniBoard
CONSTANT c_uniboard_adin : REAL := -1.0; -- = NC on UniBoard
- CONSTANT c_pmbus_tcvr0_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := TO_UVEC(I2C_UNB2_PMB_TCVR0_BMR461_ADR, 7);
+ CONSTANT c_pmbus_tcvr0_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := TO_UVEC(I2C_unb2b_PMB_TCVR0_BMR461_ADR, 7);
BEGIN
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
index a0c4d79f3bc65bf86d7ff064947d7632db6f0286..c482ecfc35216fce386e1b046dbe31d06d33f429 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
@@ -24,8 +24,8 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
-USE unb2b_board_lib.unb2_board_peripherals_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE work.qsys_unb2b_minimal_pkg.ALL;
@@ -163,23 +163,23 @@ BEGIN
clk_clk => mm_clk,
reset_reset_n => i_reset_n,
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
pio_wdi_external_connection_export => pout_wdi,
avs_eth_0_reset_export => eth1g_mm_rst,
avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
@@ -188,7 +188,7 @@ BEGIN
reg_unb_sens_reset_export => OPEN,
reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
@@ -196,7 +196,7 @@ BEGIN
reg_unb_pmbus_reset_export => OPEN,
reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0),
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0),
reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
@@ -204,7 +204,7 @@ BEGIN
reg_fpga_temp_sens_reset_export => OPEN,
reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
@@ -212,7 +212,7 @@ BEGIN
reg_fpga_voltage_sens_reset_export => OPEN,
reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
@@ -220,7 +220,7 @@ BEGIN
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -228,7 +228,7 @@ BEGIN
pio_system_info_reset_export => OPEN,
pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
pio_system_info_write_export => reg_unb_system_info_mosi.wr,
pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_system_info_read_export => reg_unb_system_info_mosi.rd,
@@ -236,7 +236,7 @@ BEGIN
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
@@ -252,7 +252,7 @@ BEGIN
reg_remu_reset_export => OPEN,
reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
reg_remu_write_export => reg_remu_mosi.wr,
reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_remu_read_export => reg_remu_mosi.rd,
@@ -260,7 +260,7 @@ BEGIN
reg_epcs_reset_export => OPEN,
reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
reg_epcs_write_export => reg_epcs_mosi.wr,
reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_epcs_read_export => reg_epcs_mosi.rd,
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
index 048e0c48534262f395350bf35cb6abe17b3ca714..d4a92b9ad45754f2f2824b07c2830fea8fda883e 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
@@ -26,7 +26,7 @@ USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
ENTITY unb2b_minimal IS
GENERIC (
@@ -51,9 +51,9 @@ ENTITY unb2b_minimal IS
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
- VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
- TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
SENS_SC : INOUT STD_LOGIC;
@@ -65,10 +65,10 @@ ENTITY unb2b_minimal IS
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
- ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
);
END unb2b_minimal;
@@ -76,8 +76,8 @@ END unb2b_minimal;
ARCHITECTURE str OF unb2b_minimal IS
-- Firmware version x.y
- CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 1);
- CONSTANT c_mm_clk_freq : NATURAL := c_unb2_board_mm_clk_freq_50M;
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
+ CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_50M;
-- System
SIGNAL cs_sim : STD_LOGIC;
@@ -152,15 +152,15 @@ ARCHITECTURE str OF unb2b_minimal IS
SIGNAL reg_remu_miso : t_mem_miso;
-- QSFP leds
- SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
- SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+ SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+ SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
BEGIN
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
- u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2_board
+ u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
GENERIC MAP (
g_sim => g_sim,
g_technology => g_technology,
@@ -171,8 +171,8 @@ BEGIN
g_stamp_svn => g_stamp_svn,
g_fw_version => c_fw_version,
g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
g_factory_image => g_factory_image,
g_protect_addr_range => g_protect_addr_range
)
@@ -352,11 +352,11 @@ BEGIN
reg_remu_miso => reg_remu_miso
);
- u_front_led : ENTITY unb2b_board_lib.unb2_board_qsfp_leds
+ u_front_led : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds
GENERIC MAP (
g_sim => g_sim,
g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
)
PORT MAP (
@@ -366,9 +366,9 @@ BEGIN
red_led_arr => qsfp_red_led_arr
);
- u_front_io : ENTITY unb2b_board_lib.unb2_board_front_io
+ u_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io
GENERIC MAP (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
)
PORT MAP (
green_led_arr => qsfp_green_led_arr,
diff --git a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
index 0f76fc12f302e61638eae4c468454d82bcaaaed0..0276b7b1a58138938f330a5cccb0f0e6ab74f01f 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
@@ -46,7 +46,7 @@ LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE i2c_lib.i2c_dev_unb2_pkg.ALL;
USE i2c_lib.i2c_commander_unb2_pmbus_pkg.ALL;
@@ -65,10 +65,10 @@ ARCHITECTURE tb OF tb_unb2b_minimal IS
CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
CONSTANT c_node_nr : NATURAL := 3; -- Node 3
- CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb2_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2_board_nof_chip_w);
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb2b_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2b_board_nof_chip_w);
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
- CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 0);
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
CONSTANT c_cable_delay : TIME := 12 ns;
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
@@ -88,9 +88,9 @@ ARCHITECTURE tb OF tb_unb2b_minimal IS
SIGNAL eth_txp : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL eth_rxp : STD_LOGIC_VECTOR(1 DOWNTO 0);
- SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0) := c_version;
- SIGNAL ID : STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0) := c_id;
- SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0) := c_version;
+ SIGNAL ID : STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0) := c_id;
+ SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
@@ -99,7 +99,7 @@ ARCHITECTURE tb OF tb_unb2b_minimal IS
SIGNAL PMBUS_SD : STD_LOGIC;
SIGNAL PMBUS_ALERT : STD_LOGIC := '0';
- SIGNAL qsfp_led : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+ SIGNAL qsfp_led : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-- Model I2C sensor slaves as on the UniBoard
CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
index 10ad2ba77416deb919a5148a398fe690fc07117d..f4b19c45cfa7ad6aa684d7564d4463e8714be796 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
@@ -24,7 +24,7 @@ LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_test_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
@@ -48,9 +48,9 @@ ENTITY unb2b_test_10GbE IS
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
- VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
- TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
SENS_SC : INOUT STD_LOGIC;
@@ -58,8 +58,8 @@ ENTITY unb2b_test_10GbE IS
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
- ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
-- Transceiver clocks
SA_CLK : IN STD_LOGIC; -- Clock 10GbE front (qsfp) and ring lines
@@ -67,43 +67,43 @@ ENTITY unb2b_test_10GbE IS
BCK_REF_CLK : IN STD_LOGIC; -- Clock 10GbE back lower 24 lines
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+-- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
+-- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
-- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
-- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
- BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
- BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
- BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
+ BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_back.i2c_w-1 downto 0);
+ BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_back.i2c_w-1 downto 0);
+ BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_back.i2c_w-1 downto 0);
-- ring transceivers
- -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : INOUT STD_LOGIC;
PMBUS_SD : INOUT STD_LOGIC;
PMBUS_ALERT : IN STD_LOGIC;
-- front transceivers
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-
- QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
- QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
-
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+
+ QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.i2c_w-1 downto 0);
+ QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.i2c_w-1 downto 0);
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
);
END unb2b_test_10GbE;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index 2a6b14500f9321740e6c11975b7e0eb25e7026a9..301f25db6d31f29d02654c220272a3cdbbaeeea8 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -28,8 +28,8 @@ USE common_lib.tb_common_mem_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE common_lib.common_network_total_header_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
-USE unb2b_board_lib.unb2_board_peripherals_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE eth_lib.eth_pkg.ALL;
@@ -241,7 +241,7 @@ ARCHITECTURE str OF mmm_unb2b_test IS
CONSTANT c_ram_diag_databuffer_ddr_addr_w : NATURAL := ceil_log2(2 * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
--- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
+-- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2b_board_peripherals_mm_reg_default
-- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
--
-- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
@@ -265,8 +265,8 @@ ARCHITECTURE str OF mmm_unb2b_test IS
CONSTANT c_reg_eth10g_back1_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_back1 * pow2(c_reg_eth10g_adr_w));
-- BSN monitors
- CONSTANT c_reg_rsp_bsn_monitor_1GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_unb2_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
- CONSTANT c_reg_rsp_bsn_monitor_10GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_unb2_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
+ CONSTANT c_reg_rsp_bsn_monitor_1GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_unb2b_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
+ CONSTANT c_reg_rsp_bsn_monitor_10GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_unb2b_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
-- Simulation
CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
@@ -455,23 +455,23 @@ BEGIN
clk_clk => mm_clk,
reset_reset_n => i_reset_n,
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
pio_wdi_external_connection_export => pout_wdi,
avs_eth_0_reset_export => eth1g_eth0_mm_rst,
avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_eth0_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_0_tse_address_export => eth1g_eth0_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
avs_eth_0_tse_write_export => eth1g_eth0_tse_mosi.wr,
avs_eth_0_tse_read_export => eth1g_eth0_tse_mosi.rd,
avs_eth_0_tse_writedata_export => eth1g_eth0_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_0_tse_readdata_export => eth1g_eth0_tse_miso.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_tse_waitrequest_export => eth1g_eth0_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_eth0_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_reg_address_export => eth1g_eth0_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
avs_eth_0_reg_write_export => eth1g_eth0_reg_mosi.wr,
avs_eth_0_reg_read_export => eth1g_eth0_reg_mosi.rd,
avs_eth_0_reg_writedata_export => eth1g_eth0_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_0_reg_readdata_export => eth1g_eth0_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_address_export => eth1g_eth0_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_ram_address_export => eth1g_eth0_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
avs_eth_0_ram_write_export => eth1g_eth0_ram_mosi.wr,
avs_eth_0_ram_read_export => eth1g_eth0_ram_mosi.rd,
avs_eth_0_ram_writedata_export => eth1g_eth0_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
@@ -480,18 +480,18 @@ BEGIN
avs_eth_1_reset_export => eth1g_eth1_mm_rst,
avs_eth_1_clk_export => OPEN,
- avs_eth_1_tse_address_export => eth1g_eth1_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_1_tse_address_export => eth1g_eth1_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
avs_eth_1_tse_write_export => eth1g_eth1_tse_mosi.wr,
avs_eth_1_tse_read_export => eth1g_eth1_tse_mosi.rd,
avs_eth_1_tse_writedata_export => eth1g_eth1_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_1_tse_readdata_export => eth1g_eth1_tse_miso.rddata(c_word_w-1 DOWNTO 0),
avs_eth_1_tse_waitrequest_export => eth1g_eth1_tse_miso.waitrequest,
- avs_eth_1_reg_address_export => eth1g_eth1_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_1_reg_address_export => eth1g_eth1_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
avs_eth_1_reg_write_export => eth1g_eth1_reg_mosi.wr,
avs_eth_1_reg_read_export => eth1g_eth1_reg_mosi.rd,
avs_eth_1_reg_writedata_export => eth1g_eth1_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_1_reg_readdata_export => eth1g_eth1_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_1_ram_address_export => eth1g_eth1_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_1_ram_address_export => eth1g_eth1_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
avs_eth_1_ram_write_export => eth1g_eth1_ram_mosi.wr,
avs_eth_1_ram_read_export => eth1g_eth1_ram_mosi.rd,
avs_eth_1_ram_writedata_export => eth1g_eth1_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
@@ -500,7 +500,7 @@ BEGIN
reg_unb_sens_reset_export => OPEN,
reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
@@ -508,7 +508,7 @@ BEGIN
reg_unb_pmbus_reset_export => OPEN,
reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0),
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0),
reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
@@ -516,7 +516,7 @@ BEGIN
reg_fpga_temp_sens_reset_export => OPEN,
reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
@@ -524,7 +524,7 @@ BEGIN
reg_fpga_voltage_sens_reset_export => OPEN,
reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
@@ -532,7 +532,7 @@ BEGIN
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -540,7 +540,7 @@ BEGIN
pio_system_info_reset_export => OPEN,
pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
pio_system_info_write_export => reg_unb_system_info_mosi.wr,
pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_system_info_read_export => reg_unb_system_info_mosi.rd,
@@ -548,7 +548,7 @@ BEGIN
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
@@ -564,7 +564,7 @@ BEGIN
reg_remu_reset_export => OPEN,
reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
reg_remu_write_export => reg_remu_mosi.wr,
reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_remu_read_export => reg_remu_mosi.rd,
@@ -572,7 +572,7 @@ BEGIN
reg_epcs_reset_export => OPEN,
reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
reg_epcs_write_export => reg_epcs_mosi.wr,
reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_epcs_read_export => reg_epcs_mosi.rd,
@@ -716,7 +716,7 @@ BEGIN
reg_diag_data_buffer_1gbe_reset_export => OPEN,
reg_diag_data_buffer_1gbe_clk_export => OPEN,
- reg_diag_data_buffer_1gbe_address_export => reg_diag_data_buf_1gbe_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_1gbe_address_export => reg_diag_data_buf_1gbe_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
reg_diag_data_buffer_1gbe_write_export => reg_diag_data_buf_1gbe_mosi.wr,
reg_diag_data_buffer_1gbe_writedata_export => reg_diag_data_buf_1gbe_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_data_buffer_1gbe_read_export => reg_diag_data_buf_1gbe_mosi.rd,
@@ -748,7 +748,7 @@ BEGIN
reg_diag_bg_1GbE_reset_export => OPEN,
reg_diag_bg_1GbE_clk_export => OPEN,
- reg_diag_bg_1GbE_address_export => reg_diag_bg_1GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
+ reg_diag_bg_1GbE_address_export => reg_diag_bg_1GbE_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
reg_diag_bg_1GbE_write_export => reg_diag_bg_1GbE_mosi.wr,
reg_diag_bg_1GbE_writedata_export => reg_diag_bg_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_bg_1GbE_read_export => reg_diag_bg_1GbE_mosi.rd,
@@ -756,7 +756,7 @@ BEGIN
reg_diag_bg_10GbE_reset_export => OPEN,
reg_diag_bg_10GbE_clk_export => OPEN,
- reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
+ reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
@@ -778,7 +778,7 @@ BEGIN
ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_io_ddr_adr_w-1 DOWNTO 0),
+ reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_io_ddr_adr_w-1 DOWNTO 0),
reg_io_ddr_MB_I_clk_export => OPEN,
reg_io_ddr_MB_I_read_export => reg_io_ddr_MB_I_mosi.rd,
reg_io_ddr_MB_I_readdata_export => reg_io_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
@@ -786,7 +786,7 @@ BEGIN
reg_io_ddr_MB_I_write_export => reg_io_ddr_MB_I_mosi.wr,
reg_io_ddr_MB_I_writedata_export => reg_io_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_io_ddr_MB_II_address_export => reg_io_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_io_ddr_adr_w-1 DOWNTO 0),
+ reg_io_ddr_MB_II_address_export => reg_io_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_io_ddr_adr_w-1 DOWNTO 0),
reg_io_ddr_MB_II_clk_export => OPEN,
reg_io_ddr_MB_II_read_export => reg_io_ddr_MB_II_mosi.rd,
reg_io_ddr_MB_II_readdata_export => reg_io_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
@@ -796,7 +796,7 @@ BEGIN
reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
@@ -804,7 +804,7 @@ BEGIN
reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
@@ -812,7 +812,7 @@ BEGIN
reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_rx_seq_ddr_MB_I_address_export => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_rx_seq_w-1 downto 0),
+ reg_diag_rx_seq_ddr_MB_I_address_export => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_rx_seq_w-1 downto 0),
reg_diag_rx_seq_ddr_MB_I_write_export => reg_diag_rx_seq_ddr_MB_I_mosi.wr,
reg_diag_rx_seq_ddr_MB_I_writedata_export => reg_diag_rx_seq_ddr_MB_I_mosi.wrdata(c_word_w-1 downto 0),
reg_diag_rx_seq_ddr_MB_I_read_export => reg_diag_rx_seq_ddr_MB_I_mosi.rd,
@@ -820,7 +820,7 @@ BEGIN
reg_diag_rx_seq_ddr_MB_II_reset_export => OPEN,
reg_diag_rx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_rx_seq_ddr_MB_II_address_export => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_rx_seq_w-1 downto 0),
+ reg_diag_rx_seq_ddr_MB_II_address_export => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_rx_seq_w-1 downto 0),
reg_diag_rx_seq_ddr_MB_II_write_export => reg_diag_rx_seq_ddr_MB_II_mosi.wr,
reg_diag_rx_seq_ddr_MB_II_writedata_export => reg_diag_rx_seq_ddr_MB_II_mosi.wrdata(c_word_w-1 downto 0),
reg_diag_rx_seq_ddr_MB_II_read_export => reg_diag_rx_seq_ddr_MB_II_mosi.rd,
@@ -828,7 +828,7 @@ BEGIN
reg_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
reg_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
- reg_diag_data_buffer_ddr_MB_I_address_export => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_ddr_MB_I_address_export => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
reg_diag_data_buffer_ddr_MB_I_write_export => reg_diag_data_buf_ddr_MB_I_mosi.wr,
reg_diag_data_buffer_ddr_MB_I_writedata_export => reg_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_data_buffer_ddr_MB_I_read_export => reg_diag_data_buf_ddr_MB_I_mosi.rd,
@@ -836,7 +836,7 @@ BEGIN
reg_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
reg_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
- reg_diag_data_buffer_ddr_MB_II_address_export => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_ddr_MB_II_address_export => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
reg_diag_data_buffer_ddr_MB_II_write_export => reg_diag_data_buf_ddr_MB_II_mosi.wr,
reg_diag_data_buffer_ddr_MB_II_writedata_export => reg_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_data_buffer_ddr_MB_II_read_export => reg_diag_data_buf_ddr_MB_II_mosi.rd,
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
index cb59ea1537f26b2cd05fcdaeeb971b9f898d76be..55ef53f61ce9ef89b44b095a0192126737c14fc5 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
@@ -29,7 +29,7 @@ USE common_lib.common_interface_layers_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE work.unb2b_test_pkg.ALL;
@@ -58,7 +58,7 @@ ENTITY udp_stream IS
dp_rst : IN STD_LOGIC;
dp_clk : IN STD_LOGIC;
- ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
-- blockgen mm
reg_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG control register (one for all streams)
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
index 4c3eda971ffbb99f72b05c227af080dc2c666baa..7e05761310a47e575255a49c44f258175e9852d2 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
@@ -29,7 +29,7 @@ USE common_lib.common_interface_layers_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE eth_lib.eth_pkg.ALL;
@@ -61,9 +61,9 @@ ENTITY unb2b_test IS
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
- VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
- TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
SENS_SC : INOUT STD_LOGIC;
@@ -71,8 +71,8 @@ ENTITY unb2b_test IS
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
- ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
-- Transceiver clocks
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -84,20 +84,20 @@ ENTITY unb2b_test IS
MB_II_REF_CLK : IN STD_LOGIC := '0'; -- Reference clock for MB_II
-- back transceivers
- --BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0) := (OTHERS=>'0');
- --BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ --BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0) := (OTHERS=>'0');
+ --BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
--BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
--BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
- BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
- BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
- BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
+ BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_back.i2c_w-1 downto 0);
+ BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_back.i2c_w-1 downto 0);
+ BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_back.i2c_w-1 downto 0);
-- ring transceivers
- --RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
- --RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- --RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
- --RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ --RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
+ --RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ --RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
+ --RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : INOUT STD_LOGIC;
@@ -105,21 +105,21 @@ ENTITY unb2b_test IS
PMBUS_ALERT : IN STD_LOGIC := '0';
-- front transceivers
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-
- QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
- QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+
+ QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.i2c_w-1 downto 0);
+ QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.i2c_w-1 downto 0);
QSFP_RST : INOUT STD_LOGIC;
-- SO-DIMM Memory Bank I
@@ -133,7 +133,7 @@ ENTITY unb2b_test IS
MB_II_OU : OUT t_tech_ddr4_phy_ou;
-- Leds
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
);
END unb2b_test;
@@ -141,8 +141,8 @@ END unb2b_test;
ARCHITECTURE str OF unb2b_test IS
-- Firmware version x.y
- CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 1);
- CONSTANT c_mm_clk_freq : NATURAL := c_unb2_board_mm_clk_freq_125M;
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
+ CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_125M;
@@ -157,13 +157,13 @@ ARCHITECTURE str OF unb2b_test IS
CONSTANT c_use_MB_II : BOOLEAN := g_design_name="unb2b_test_ddr_MB_II" OR g_design_name="unb2b_test_ddr_MB_I_II" OR g_design_name="unb2b_test_all";
-- transceivers
- CONSTANT c_nof_qsfp : NATURAL := c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
- CONSTANT c_nof_ring : NATURAL := 0;--8;--12;--c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
- CONSTANT c_nof_back0 : NATURAL := 0;--c_unb2_board_tr_back.bus_w;
- CONSTANT c_nof_back1 : NATURAL := 0;--c_unb2_board_tr_back.bus_w;
+ CONSTANT c_nof_qsfp : NATURAL := c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w;
+ CONSTANT c_nof_ring : NATURAL := 0;--8;--12;--c_unb2b_board_tr_ring.nof_bus * c_unb2b_board_tr_ring.bus_w;
+ CONSTANT c_nof_back0 : NATURAL := 0;--c_unb2b_board_tr_back.bus_w;
+ CONSTANT c_nof_back1 : NATURAL := 0;--c_unb2b_board_tr_back.bus_w;
-- 1GbE
- CONSTANT c_nof_streams_1GbE : NATURAL := sel_a_b(c_use_1GbE,1,0); --sel_a_b(c_use_1GbE,c_unb2_board_nof_eth,0);
+ CONSTANT c_nof_streams_1GbE : NATURAL := sel_a_b(c_use_1GbE,1,0); --sel_a_b(c_use_1GbE,c_unb2b_board_nof_eth,0);
-- 10GbE
CONSTANT c_nof_streams_qsfp : NATURAL := sel_a_b(c_use_10GbE_qsfp,c_nof_qsfp,0);
@@ -173,9 +173,9 @@ ARCHITECTURE str OF unb2b_test IS
CONSTANT c_nof_streams_10GbE : NATURAL := c_nof_streams_qsfp+c_nof_streams_ring+c_nof_streams_back0+c_nof_streams_back1;
- CONSTANT c_nof_qsfp_bus : NATURAL := ceil_div(c_nof_streams_qsfp,c_unb2_board_tr_qsfp.bus_w);
- CONSTANT c_nof_ring_bus : NATURAL := ceil_div(c_nof_streams_ring,c_unb2_board_tr_ring.bus_w);
- CONSTANT c_nof_back_bus : NATURAL := ceil_div(c_nof_streams_back0,c_unb2_board_tr_back.bus_w) + ceil_div(c_nof_streams_back1,c_unb2_board_tr_back.bus_w);
+ CONSTANT c_nof_qsfp_bus : NATURAL := ceil_div(c_nof_streams_qsfp,c_unb2b_board_tr_qsfp.bus_w);
+ CONSTANT c_nof_ring_bus : NATURAL := ceil_div(c_nof_streams_ring,c_unb2b_board_tr_ring.bus_w);
+ CONSTANT c_nof_back_bus : NATURAL := ceil_div(c_nof_streams_back0,c_unb2b_board_tr_back.bus_w) + ceil_div(c_nof_streams_back1,c_unb2b_board_tr_back.bus_w);
CONSTANT c_data_w_32 : NATURAL := c_eth_data_w; -- 1GbE
CONSTANT c_data_w_64 : NATURAL := c_xgmii_data_w; -- 10GbE
@@ -318,12 +318,12 @@ ARCHITECTURE str OF unb2b_test IS
SIGNAL serial_10G_tx_ring_arr : STD_LOGIC_VECTOR(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_ring_arr : STD_LOGIC_VECTOR(c_nof_streams_ring-1 DOWNTO 0);
- SIGNAL i_QSFP_TX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
- SIGNAL i_QSFP_RX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
- -- SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ SIGNAL i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
+ SIGNAL i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_TX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_RX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_TX : t_unb2b_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_RX : t_unb2b_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
SIGNAL serial_10G_tx_back_arr : STD_LOGIC_VECTOR(c_nof_streams_back0+c_nof_streams_back1-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_back_arr : STD_LOGIC_VECTOR(c_nof_streams_back0+c_nof_streams_back1-1 DOWNTO 0);
@@ -434,8 +434,8 @@ ARCHITECTURE str OF unb2b_test IS
SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
-- QSFP leds
- SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
- SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+ SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+ SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
BEGIN
@@ -443,7 +443,7 @@ BEGIN
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
- u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2_board
+ u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
GENERIC MAP (
g_sim => g_sim,
g_technology => g_technology,
@@ -453,9 +453,9 @@ BEGIN
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn,
g_fw_version => c_fw_version,
- g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
+ g_mm_clk_freq => sel_a_b(g_sim,c_unb2b_board_mm_clk_freq_25M,c_unb2b_board_mm_clk_freq_125M),
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
g_udp_offload => c_use_1GbE,
g_udp_offload_nof_streams => c_nof_streams_1GbE,
g_dp_clk_use_pll => TRUE,
@@ -589,11 +589,11 @@ BEGIN
g_technology => g_technology,
g_bg_block_size => c_bg_block_size,
g_hdr_field_arr => c_hdr_field_arr,
- g_nof_streams_1GbE => c_unb2_board_nof_eth,
- g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
- g_nof_streams_ring => 24,--c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
- g_nof_streams_back0 => 24,--c_unb2_board_tr_back.bus_w,
- g_nof_streams_back1 => 24--c_unb2_board_tr_back.bus_w
+ g_nof_streams_1GbE => c_unb2b_board_nof_eth,
+ g_nof_streams_qsfp => c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w,
+ g_nof_streams_ring => 24,--c_unb2b_board_tr_ring.nof_bus * c_unb2b_board_tr_ring.bus_w,
+ g_nof_streams_back0 => 24,--c_unb2b_board_tr_back.bus_w,
+ g_nof_streams_back1 => 24--c_unb2b_board_tr_back.bus_w
)
PORT MAP(
mm_rst => mm_rst,
@@ -893,7 +893,7 @@ BEGIN
);
- u_tr_10GbE_qsfp_and_ring: ENTITY unb2b_board_10gbe_lib.unb2_board_10gbe -- QSFP and Ring lines
+ u_tr_10GbE_qsfp_and_ring: ENTITY unb2b_board_10gbe_lib.unb2b_board_10gbe -- QSFP and Ring lines
GENERIC MAP (
g_sim => g_sim,
g_sim_level => 1,
@@ -947,7 +947,7 @@ BEGIN
- u_front_io : ENTITY unb2b_board_lib.unb2_board_front_io
+ u_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io
GENERIC MAP (
g_nof_qsfp_bus => c_nof_qsfp_bus
)
@@ -978,7 +978,7 @@ BEGIN
-- RING_0_TX <= i_RING_TX(0);
-- RING_1_TX <= i_RING_TX(1);
--
--- u_ring_io : ENTITY unb2b_board_lib.unb2_board_ring_io
+-- u_ring_io : ENTITY unb2b_board_lib.unb2b_board_ring_io
-- GENERIC MAP (
-- g_nof_ring_bus => 2--c_nof_ring_bus
-- )
@@ -990,7 +990,7 @@ BEGIN
-- );
--- u_tr_10GbE_back: ENTITY unb2b_board_10gbe_lib.unb2_board_10gbe -- BACK lines
+-- u_tr_10GbE_back: ENTITY unb2b_board_10gbe_lib.unb2b_board_10gbe -- BACK lines
-- GENERIC MAP (
-- g_sim => g_sim,
-- g_sim_level => 1,
@@ -1032,7 +1032,7 @@ BEGIN
-- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
-- --END GENERATE;
--
--- u_back_io : ENTITY unb2b_board_lib.unb2_board_back_io
+-- u_back_io : ENTITY unb2b_board_lib.unb2b_board_back_io
-- GENERIC MAP (
-- g_nof_back_bus => c_nof_back_bus
-- )
@@ -1053,12 +1053,12 @@ BEGIN
-- );
- u_front_led : ENTITY unb2b_board_lib.unb2_board_qsfp_leds
+ u_front_led : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds
GENERIC MAP (
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_unb2b_board_ext_clk_freq_200M) -- nof clk cycles to get us period
)
PORT MAP (
rst => dp_rst,
@@ -1082,9 +1082,9 @@ BEGIN
END GENERATE;
gen_no_udp_stream_10GbE : IF c_use_10GbE = FALSE GENERATE
- u_front_io : ENTITY unb2b_board_lib.unb2_board_front_io
+ u_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io
GENERIC MAP (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
)
PORT MAP (
green_led_arr => qsfp_green_led_arr,
@@ -1092,11 +1092,11 @@ BEGIN
QSFP_LED => QSFP_LED
);
- u_front_led : ENTITY unb2b_board_lib.unb2_board_qsfp_leds
+ u_front_led : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds
GENERIC MAP (
g_sim => g_sim,
g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
)
PORT MAP (
diff --git a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
index 5ffbd258ad789af8a841120c718f94e7ead46d22..8361faf1d55c54d98896770ac31e1873819a3735 100644
--- a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
@@ -46,7 +46,7 @@ LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, technology_lib, tech_pll_lib
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
-USE unb2b_board_lib.unb2_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE tech_pll_lib.tech_pll_component_pkg.ALL;
@@ -68,10 +68,10 @@ ARCHITECTURE tb OF tb_unb2b_test IS
CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
CONSTANT c_node_nr : NATURAL := 3; -- Node 3
- CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb2_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2_board_nof_chip_w);
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb2b_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2b_board_nof_chip_w);
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
- CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 0);
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
CONSTANT c_cable_delay : TIME := 12 ns;
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
@@ -96,14 +96,14 @@ ARCHITECTURE tb OF tb_unb2b_test IS
SIGNAL eth_txp : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL eth_rxp : STD_LOGIC_VECTOR(1 DOWNTO 0);
- SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0) := c_version;
- SIGNAL ID : STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0) := c_id;
- SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0) := c_version;
+ SIGNAL ID : STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0) := c_id;
+ SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
- SIGNAL qsfp_led : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+ SIGNAL qsfp_led : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-- DDR reference clocks
SIGNAL mb_I_ref_clk : STD_LOGIC := '1'; -- Reference clock for MB_I
@@ -124,17 +124,17 @@ ARCHITECTURE tb OF tb_unb2b_test IS
SIGNAL bck_ref_clk : STD_LOGIC := '1';
-- Serial I/O
- SIGNAL si_lpbk_0 : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
- SIGNAL si_lpbk_1 : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
- SIGNAL si_lpbk_2 : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
- SIGNAL si_lpbk_3 : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
- SIGNAL si_lpbk_4 : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
- SIGNAL si_lpbk_5 : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ SIGNAL si_lpbk_0 : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ SIGNAL si_lpbk_1 : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ SIGNAL si_lpbk_2 : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ SIGNAL si_lpbk_3 : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ SIGNAL si_lpbk_4 : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ SIGNAL si_lpbk_5 : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
- SIGNAL si_lpbk_6 : STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 DOWNTO 0);
- SIGNAL si_lpbk_7 : STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 DOWNTO 0);
+ SIGNAL si_lpbk_6 : STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0);
+ SIGNAL si_lpbk_7 : STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0);
- SIGNAL si_lpbk_8 : STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 DOWNTO 0);
+ SIGNAL si_lpbk_8 : STD_LOGIC_VECTOR(c_unb2b_board_tr_back.bus_w-1 DOWNTO 0);
-- Model I2C sensor slaves as on the UniBoard
diff --git a/boards/uniboard2b/libraries/unb2b_board/hdllib.cfg b/boards/uniboard2b/libraries/unb2b_board/hdllib.cfg
index d6751c34cddc4210f6e4b4199c037b71e5674b8f..f259881a91659e750efe1e23be4c9270134bd9d9 100644
--- a/boards/uniboard2b/libraries/unb2b_board/hdllib.cfg
+++ b/boards/uniboard2b/libraries/unb2b_board/hdllib.cfg
@@ -19,7 +19,6 @@ synth_files =
src/vhdl/unb2b_board_clk200_pll.vhd
src/vhdl/unb2b_board_clk25_pll.vhd
src/vhdl/unb2b_board_clk125_pll.vhd
-# src/vhdl/unb2b_board_clk200mm_pll.vhd
src/vhdl/unb2b_board_wdi_extend.vhd
src/vhdl/unb2b_board_node_ctrl.vhd
src/vhdl/unb2b_board_pmbus_ctrl.vhd
@@ -37,6 +36,7 @@ synth_files =
src/vhdl/unb2b_board_back_io.vhd
src/vhdl/unb2b_board_ring_io.vhd
src/vhdl/unb2b_board_peripherals_pkg.vhd
+# src/vhdl/unb2b_board_clk200mm_pll.vhd
test_bench_files =
tb/vhdl/tb_mms_unb2b_board_sens.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
index 94cfb0fe9a4a33c12a42661e33913d48ff46cb7a..81a1bb301d37a54445806c5f61bf1a1c58a81832 100644
--- a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+++ b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
@@ -292,7 +292,7 @@ set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
# - hover over the ATX PLL block (left side or right side)
# - Right click and click "Copy tooltip"
# - Paste text in here and edit
-#set_location_assignment HSSIPMALCPLL_X0_Y33_N29 -to "unb2_test:u_revision|unb2_board_10gbe:\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:\gen_phy_24:u_ip_arria10_transceiver_pll_10g_0|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst"
+#set_location_assignment HSSIPMALCPLL_X0_Y33_N29 -to "unb2b_test:u_revision|unb2b_board_10gbe:\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:\gen_phy_24:u_ip_arria10_transceiver_pll_10g_0|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst"
@@ -300,11 +300,11 @@ set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
#set_parameter -name dbg_user_identifier 0 -to "\\Generate_XCVR_LANE_INSTANCES:0:xcvr_lane_inst|xcvr_pll_inst|xcvr_atx_pll_a10_0"
#set_parameter -name dbg_user_identifier 1 -to "\\Generate_XCVR_LANE_INSTANCES:1:xcvr_lane_inst|xcvr_pll_inst|xcvr_atx_pll_a10_0"
-set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_0|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_phy_10gbase_r_12:\\gen_phy_12:u_ip_arria10_phy_10gbase_r_12"
-set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_1|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_phy_10gbase_r_12:\\gen_phy_12:u_ip_arria10_phy_10gbase_r_12"
+set_parameter -name dbg_user_identifier 1 -to "unb2b_test:u_revision|unb2b_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_0|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_phy_10gbase_r_12:\\gen_phy_12:u_ip_arria10_phy_10gbase_r_12"
+set_parameter -name dbg_user_identifier 1 -to "unb2b_test:u_revision|unb2b_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_1|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_phy_10gbase_r_12:\\gen_phy_12:u_ip_arria10_phy_10gbase_r_12"
-set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_0|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0"
-set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_1|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0"
+set_parameter -name dbg_user_identifier 1 -to "unb2b_test:u_revision|unb2b_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_0|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0"
+set_parameter -name dbg_user_identifier 1 -to "unb2b_test:u_revision|unb2b_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_1|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0"
# Pass compile stamps as generics (passed to top-level when $UNB_COMPILE_STAMPS is set)
@@ -315,9 +315,9 @@ if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(HDL_GIT_REVISION)] ""]
}
-#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tbi_tx_d"
-#set_instance_assignment -name FAST_INPUT_REGISTER ON -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tbi_rx_d"
-#set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tx_clk"
-#set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_mac:i_tse_mac|rx_clk"
-#set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|rx_clk"
-#set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_mac:i_tse_mac|tx_clk"
+#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "ctrl_unb2b_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tbi_tx_d"
+#set_instance_assignment -name FAST_INPUT_REGISTER ON -to "ctrl_unb2b_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tbi_rx_d"
+#set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to "ctrl_unb2b_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tx_clk"
+#set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to "ctrl_unb2b_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_mac:i_tse_mac|rx_clk"
+#set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to "ctrl_unb2b_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|rx_clk"
+#set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to "ctrl_unb2b_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_mac:i_tse_mac|tx_clk"
diff --git a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
index 2ad15ab8574441ba926493f1639b19be11de81e4..32912a7da33215798e84dce1b722b5fe458e0721 100644
--- a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+++ b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
@@ -21,24 +21,24 @@
###############################################################################
# Constrain the input I/O path
-#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
-#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
+#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
+#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
# Constrain the output I/O path
-#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
-#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
+#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
+#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
# False path the PPS to DDIO:
-#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 3 [get_ports {PPS}]
-#set_false_path -from {PPS} -to {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}; set_false_path -from {PPS} -to {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}
+#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 3 [get_ports {PPS}]
+#set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}; set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}
-#set_false_path -from [get_ports {PPS}] -to [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}]
+#set_false_path -from [get_ports {PPS}] -to [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}]
-#set_input_delay -min -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 2 [get_ports {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
-#set_input_delay -max -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 4 [get_ports {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
+#set_input_delay -min -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 2 [get_ports {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
+#set_input_delay -max -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 4 [get_ports {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
-#set_false_path -from {PPS} -to {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio*}
+#set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio*}
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index 4e76c651b8c47229d1b54c9e9320893d9d23b592..e090188b68e0ca6f3641740f7f6c205fdf70625b 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -22,7 +22,7 @@
-- Purpose: Provide general control infrastructure
-- Usage: In a design <design_name>.vhd that consists of:
-- . mmm_<design_name>.vhd with a Nios2 and the MM bus and the peripherals
--- . ctrl_unb2_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
+-- . ctrl_unb2b_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
LIBRARY IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -30,13 +30,13 @@ USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE work.unb2_board_pkg.ALL;
+USE work.unb2b_board_pkg.ALL;
USE i2c_lib.i2c_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE eth_lib.eth_pkg.ALL;
-ENTITY ctrl_unb2_board IS
+ENTITY ctrl_unb2b_board IS
GENERIC (
----------------------------------------------------------------------------
-- General
@@ -44,20 +44,20 @@ ENTITY ctrl_unb2_board IS
g_technology : NATURAL := c_tech_arria10;
g_sim : BOOLEAN := FALSE;
g_design_name : STRING := "UNUSED";
- g_fw_version : t_unb2_board_fw_version := (0, 0); -- firmware version x.y
+ g_fw_version : t_unb2b_board_fw_version := (0, 0); -- firmware version x.y
g_stamp_date : NATURAL := 0;
g_stamp_time : NATURAL := 0;
g_stamp_svn : NATURAL := 0;
g_design_note : STRING := "UNUSED";
g_base_ip : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy
- g_mm_clk_freq : NATURAL := c_unb2_board_mm_clk_freq_125M;
- g_eth_clk_freq : NATURAL := c_unb2_board_eth_clk_freq_125M;
+ g_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_125M;
+ g_eth_clk_freq : NATURAL := c_unb2b_board_eth_clk_freq_125M;
g_tse_clk_buf : BOOLEAN := FALSE;
----------------------------------------------------------------------------
-- External CLK
----------------------------------------------------------------------------
- g_dp_clk_freq : NATURAL := c_unb2_board_ext_clk_freq_200M;
+ g_dp_clk_freq : NATURAL := c_unb2b_board_ext_clk_freq_200M;
g_dp_clk_use_pll : BOOLEAN := TRUE;
-- PLL phase clk shift with respect to CLK
-- STRING := "0" = 0
@@ -108,7 +108,7 @@ ENTITY ctrl_unb2_board IS
g_app_led_red : BOOLEAN := FALSE; -- when TRUE use external LED control via app_led_red
g_app_led_green : BOOLEAN := FALSE; -- when TRUE use external LED control via app_led_green
- g_aux : t_c_unb2_board_aux := c_unb2_board_aux;
+ g_aux : t_c_unb2b_board_aux := c_unb2b_board_aux;
g_factory_image : BOOLEAN := FALSE;
g_protect_addr_range: BOOLEAN := FALSE;
g_protected_addr_lo : NATURAL := 0; -- Byte address
@@ -140,8 +140,8 @@ ENTITY ctrl_unb2_board IS
mb_I_ref_rst : OUT STD_LOGIC; -- reset in MB_I_REF_CLK domain released after mm_rst
mb_II_ref_rst : OUT STD_LOGIC; -- reset in MB_II_REF_CLK domain released after mm_rst
- this_chip_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_chip_w-1 DOWNTO 0); -- [1:0], so range 0-3 for PN
- this_bck_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_uniboard_w-1 DOWNTO 0); -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
+ this_chip_id : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_chip_w-1 DOWNTO 0); -- [1:0], so range 0-3 for PN
+ this_bck_id : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_uniboard_w-1 DOWNTO 0); -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
app_led_red : IN STD_LOGIC := '0';
app_led_green : IN STD_LOGIC := '1';
@@ -173,7 +173,7 @@ ENTITY ctrl_unb2_board IS
reg_epcs_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_epcs_miso : OUT t_mem_miso;
- -- MM buses to/from mms_unb2_board_system_info
+ -- MM buses to/from mms_unb2b_board_system_info
reg_unb_system_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_unb_system_info_miso : OUT t_mem_miso;
@@ -243,18 +243,18 @@ ENTITY ctrl_unb2_board IS
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC; -- 125 MHz
- ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0) := (OTHERS=>'0');
- ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0)
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0) := (OTHERS=>'0');
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0)
);
-END ctrl_unb2_board;
+END ctrl_unb2b_board;
-ARCHITECTURE str OF ctrl_unb2_board IS
+ARCHITECTURE str OF ctrl_unb2b_board IS
CONSTANT c_rom_version : NATURAL := 1; -- Only increment when something changes to the register map of rom_system_info.
CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg
- CONSTANT c_mm_clk_freq : NATURAL := sel_a_b(g_sim=FALSE,g_mm_clk_freq,c_unb2_board_mm_clk_freq_10M);
+ CONSTANT c_mm_clk_freq : NATURAL := sel_a_b(g_sim=FALSE,g_mm_clk_freq,c_unb2b_board_mm_clk_freq_10M);
-- Clock and reset
@@ -398,7 +398,7 @@ BEGIN
END GENERATE;
gen_pll: IF g_sim=FALSE AND g_dp_clk_use_pll=TRUE GENERATE
- u_unb2_board_clk200_pll : ENTITY work.unb2_board_clk200_pll
+ u_unb2b_board_clk200_pll : ENTITY work.unb2b_board_clk200_pll
GENERIC MAP (
g_technology => g_technology,
g_use_fpll => TRUE,
@@ -430,9 +430,9 @@ BEGIN
-----------------------------------------------------------------------------
i_mm_clk <= mm_sim_clk WHEN g_sim = TRUE ELSE
- clk125 WHEN g_mm_clk_freq = c_unb2_board_mm_clk_freq_125M ELSE
- clk100 WHEN g_mm_clk_freq = c_unb2_board_mm_clk_freq_100M ELSE
- clk50 WHEN g_mm_clk_freq = c_unb2_board_mm_clk_freq_50M ELSE
+ clk125 WHEN g_mm_clk_freq = c_unb2b_board_mm_clk_freq_125M ELSE
+ clk100 WHEN g_mm_clk_freq = c_unb2b_board_mm_clk_freq_100M ELSE
+ clk50 WHEN g_mm_clk_freq = c_unb2b_board_mm_clk_freq_50M ELSE
clk50; -- default
gen_mm_clk_sim: IF g_sim = TRUE GENERATE
@@ -445,7 +445,7 @@ BEGIN
END GENERATE;
gen_mm_clk_hardware: IF g_sim = FALSE GENERATE
- u_unb2_board_clk125_pll : ENTITY work.unb2_board_clk125_pll
+ u_unb2b_board_clk125_pll : ENTITY work.unb2b_board_clk125_pll
GENERIC MAP (
g_use_fpll => TRUE,
g_technology => g_technology
@@ -461,7 +461,7 @@ BEGIN
);
END GENERATE;
- u_unb2_board_node_ctrl : ENTITY work.unb2_board_node_ctrl
+ u_unb2b_board_node_ctrl : ENTITY work.unb2b_board_node_ctrl
GENERIC MAP (
g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
@@ -484,7 +484,7 @@ BEGIN
-----------------------------------------------------------------------------
cs_sim <= is_true(g_sim);
- u_mms_unb2_board_system_info : ENTITY work.mms_unb2_board_system_info
+ u_mms_unb2b_board_system_info : ENTITY work.mms_unb2b_board_system_info
GENERIC MAP (
g_sim => g_sim,
g_technology => g_technology,
@@ -520,11 +520,11 @@ BEGIN
gen_app_led_red: IF g_app_led_red = TRUE GENERATE
-- Let external app control the LED via the app_led_red input
- TESTIO(c_unb2_board_testio_led_red) <= app_led_red;
+ TESTIO(c_unb2b_board_testio_led_red) <= app_led_red;
END GENERATE;
no_app_led_red: IF g_app_led_red = FALSE GENERATE
- TESTIO(c_unb2_board_testio_led_red) <= led_toggle_red;
+ TESTIO(c_unb2b_board_testio_led_red) <= led_toggle_red;
END GENERATE;
@@ -534,16 +534,16 @@ BEGIN
gen_app_led_green: IF g_app_led_green = TRUE GENERATE
-- Let external app control the LED via the app_led_green input
- TESTIO(c_unb2_board_testio_led_green) <= app_led_green;
+ TESTIO(c_unb2b_board_testio_led_green) <= app_led_green;
END GENERATE;
no_app_led_green: IF g_app_led_green = FALSE GENERATE
- TESTIO(c_unb2_board_testio_led_green) <= led_toggle_green;
+ TESTIO(c_unb2b_board_testio_led_green) <= led_toggle_green;
END GENERATE;
------------------------------------------------------------------------------
- -- Toggle red LED when unb2_minimal is running, green LED for other designs.
+ -- Toggle red LED when unb2b_minimal is running, green LED for other designs.
------------------------------------------------------------------------------
led_toggle_red <= sel_a_b(g_factory_image=TRUE, led_toggle, '0');
led_toggle_green <= sel_a_b(g_factory_image=FALSE, led_toggle, '0');
@@ -565,7 +565,7 @@ BEGIN
-- A third option is to override the WDI manually using the output of a dedicated reg_wdi.
WDI <= mm_wdi OR temp_alarm OR wdi_override;
- u_unb2_board_wdi_reg : ENTITY work.unb2_board_wdi_reg
+ u_unb2b_board_wdi_reg : ENTITY work.unb2b_board_wdi_reg
PORT MAP (
mm_rst => i_mm_rst,
mm_clk => i_mm_clk,
@@ -661,7 +661,7 @@ BEGIN
mm_board_sens_start <= mm_pulse_s WHEN g_sim=FALSE ELSE mm_pulse_s; --mm_pulse_ms; ms pulse comes before the end of the I2C frame, this results in an overflow in simulation -- speed up in simulation
- u_mms_unb2_board_sens : ENTITY work.mms_unb2_board_sens
+ u_mms_unb2b_board_sens : ENTITY work.mms_unb2b_board_sens
GENERIC MAP (
g_sim => g_sim,
g_i2c_peripheral => c_i2c_peripheral_sens,
@@ -684,7 +684,7 @@ BEGIN
sda => SENS_SD
);
- u_mms_unb2_board_pmbus : ENTITY work.mms_unb2_board_sens
+ u_mms_unb2b_board_pmbus : ENTITY work.mms_unb2b_board_sens
GENERIC MAP (
g_sim => g_sim,
g_i2c_peripheral => c_i2c_peripheral_pmbus,
@@ -707,7 +707,7 @@ BEGIN
sda => PMBUS_SD
);
- u_mms_unb2_fpga_sens : ENTITY work.mms_unb2_fpga_sens
+ u_mms_unb2b_fpga_sens : ENTITY work.mms_unb2b_fpga_sens
GENERIC MAP (
g_sim => g_sim,
g_technology => g_technology,
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
index 99c8a77fc9f765c6aa1fe3c80cf8b2c7951337a6..777b8d72f82a0365328f3c63904d336cee4fa7e5 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
@@ -19,8 +19,8 @@
--
-------------------------------------------------------------------------------
--- Purpose : MMS for unb2_board_sens
--- Description: See unb2_board_sens.vhd
+-- Purpose : MMS for unb2b_board_sens
+-- Description: See unb2b_board_sens.vhd
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -29,11 +29,11 @@ USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-ENTITY mms_unb2_board_sens IS
+ENTITY mms_unb2b_board_sens IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_i2c_peripheral : NATURAL;
- g_sens_nof_result : NATURAL; -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
+ g_sens_nof_result : NATURAL; -- Should match nof read bytes via I2C in the unb2b_board_sens_ctrl SEQUENCE list
g_clk_freq : NATURAL := 100*10**6; -- clk frequency in Hz
g_temp_high : NATURAL := 85;
g_comma_w : NATURAL := 0
@@ -55,10 +55,10 @@ ENTITY mms_unb2_board_sens IS
-- Temperature alarm output
temp_alarm : OUT STD_LOGIC
);
-END mms_unb2_board_sens;
+END mms_unb2b_board_sens;
-ARCHITECTURE str OF mms_unb2_board_sens IS
+ARCHITECTURE str OF mms_unb2b_board_sens IS
CONSTANT c_temp_high_w : NATURAL := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
@@ -69,7 +69,7 @@ ARCHITECTURE str OF mms_unb2_board_sens IS
BEGIN
- u_unb2_board_sens_reg : ENTITY work.unb2_board_sens_reg
+ u_unb2b_board_sens_reg : ENTITY work.unb2b_board_sens_reg
GENERIC MAP (
g_sens_nof_result => g_sens_nof_result,
g_temp_high => g_temp_high
@@ -91,7 +91,7 @@ BEGIN
temp_high => temp_high
);
- u_unb2_board_sens : ENTITY work.unb2_board_sens
+ u_unb2b_board_sens : ENTITY work.unb2b_board_sens
GENERIC MAP (
g_sim => g_sim,
g_i2c_peripheral => g_i2c_peripheral,
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
index 69c9f0c602854dfa773e96fc6f03a3e1b83d7a2f..70bb6369912db34360db823a7853b0287e6a1dc4 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
@@ -23,21 +23,21 @@ LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE work.unb2_board_pkg.ALL;
+USE work.unb2b_board_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
-ENTITY mms_unb2_board_system_info IS
+ENTITY mms_unb2b_board_system_info IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_technology : NATURAL := c_tech_arria10;
g_design_name : STRING;
- g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version; -- firmware version x.y
+ g_fw_version : t_unb2b_board_fw_version := c_unb2b_board_fw_version; -- firmware version x.y
g_stamp_date : NATURAL := 0;
g_stamp_time : NATURAL := 0;
g_stamp_svn : NATURAL := 0;
g_design_note : STRING := "";
g_rom_version : NATURAL := 1;
- g_aux : t_c_unb2_board_aux := c_unb2_board_aux -- aux contains the hardware version
+ g_aux : t_c_unb2b_board_aux := c_unb2b_board_aux -- aux contains the hardware version
);
PORT (
mm_rst : IN STD_LOGIC;
@@ -53,16 +53,16 @@ ENTITY mms_unb2_board_system_info IS
hw_version : IN STD_LOGIC_VECTOR(g_aux.version_w-1 DOWNTO 0);
id : IN STD_LOGIC_VECTOR(g_aux.id_w-1 DOWNTO 0);
- chip_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_chip_w-1 DOWNTO 0);
- bck_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_uniboard_w-1 DOWNTO 0);
+ chip_id : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_chip_w-1 DOWNTO 0);
+ bck_id : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_uniboard_w-1 DOWNTO 0);
-- Info output still supported for older designs
info : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)
);
-END mms_unb2_board_system_info;
+END mms_unb2b_board_system_info;
-ARCHITECTURE str OF mms_unb2_board_system_info IS
+ARCHITECTURE str OF mms_unb2b_board_system_info IS
-- Provide different prefixes (absolute and relative) for the same path. ModelSim understands $UNB, Quartus does not.
-- Required because the work paths of ModelSim and Quartus are different.
@@ -88,7 +88,7 @@ BEGIN
info <= i_info;
- u_unb2_board_system_info: ENTITY work.unb2_board_system_info
+ u_unb2b_board_system_info: ENTITY work.unb2b_board_system_info
GENERIC MAP (
g_sim => g_sim,
g_fw_version => g_fw_version,
@@ -104,7 +104,7 @@ BEGIN
bck_id => bck_id
);
- u_unb2_board_system_info_reg: ENTITY work.unb2_board_system_info_reg
+ u_unb2b_board_system_info_reg: ENTITY work.unb2b_board_system_info_reg
GENERIC MAP (
g_design_name => g_design_name,
g_stamp_date => g_stamp_date,
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
index 96ae8dc74dd007749a9ceafa6f9b081e45e2085e..3b80d6548698d3f4a776987d8322c77f79185b6d 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
@@ -19,8 +19,8 @@
--
-------------------------------------------------------------------------------
--- Purpose : MMS for unb2_fpga_sens
--- Description: See unb2_fpga_sens.vhd
+-- Purpose : MMS for unb2b_fpga_sens
+-- Description: See unb2b_fpga_sens.vhd
LIBRARY IEEE, technology_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -30,7 +30,7 @@ USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
-ENTITY mms_unb2_fpga_sens IS
+ENTITY mms_unb2b_fpga_sens IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_technology : NATURAL := c_tech_arria10;
@@ -51,10 +51,10 @@ ENTITY mms_unb2_fpga_sens IS
-- Temperature alarm output
temp_alarm : OUT STD_LOGIC
);
-END mms_unb2_fpga_sens;
+END mms_unb2b_fpga_sens;
-ARCHITECTURE str OF mms_unb2_fpga_sens IS
+ARCHITECTURE str OF mms_unb2b_fpga_sens IS
CONSTANT c_sens_nof_result : NATURAL := 1; --
CONSTANT c_temp_high_w : NATURAL := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
@@ -66,7 +66,7 @@ ARCHITECTURE str OF mms_unb2_fpga_sens IS
BEGIN
- u_unb2_fpga_sens_reg : ENTITY work.unb2_fpga_sens_reg
+ u_unb2b_fpga_sens_reg : ENTITY work.unb2b_fpga_sens_reg
GENERIC MAP (
g_sim => g_sim,
g_technology => g_technology,
@@ -93,7 +93,7 @@ BEGIN
temp_high => temp_high
);
--- u_unb2_board_sens : ENTITY work.unb2_board_sens
+-- u_unb2b_board_sens : ENTITY work.unb2b_board_sens
-- GENERIC MAP (
-- g_sim => g_sim,
-- g_clk_freq => g_clk_freq,
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
index 8142ed4527a9840b4b19c806788f9fb1da0b1737..fc6189a85cf47f91ba05411cde51f5b5df4953a8 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
@@ -21,32 +21,32 @@
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
-USE work.unb2_board_pkg.ALL;
+USE work.unb2b_board_pkg.ALL;
-ENTITY unb2_board_back_io IS
+ENTITY unb2b_board_back_io IS
GENERIC (
- g_nof_back_bus : NATURAL := c_unb2_board_tr_back.nof_bus
+ g_nof_back_bus : NATURAL := c_unb2b_board_tr_back.nof_bus
);
PORT (
- serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_back_bus * c_unb2_board_tr_back.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_back_bus * c_unb2_board_tr_back.bus_w-1 DOWNTO 0);
+ serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_back_bus * c_unb2b_board_tr_back.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_back_bus * c_unb2b_board_tr_back.bus_w-1 DOWNTO 0);
-- back transceivers
- BCK_RX : IN t_unb2_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
- BCK_TX : OUT t_unb2_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0);
+ BCK_RX : IN t_unb2b_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+ BCK_TX : OUT t_unb2b_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0);
- BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 DOWNTO 0);
- BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 DOWNTO 0);
- BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 DOWNTO 0)
+ BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_back.i2c_w-1 DOWNTO 0);
+ BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_back.i2c_w-1 DOWNTO 0);
+ BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_back.i2c_w-1 DOWNTO 0)
);
-END unb2_board_back_io;
+END unb2b_board_back_io;
-ARCHITECTURE str OF unb2_board_back_io IS
+ARCHITECTURE str OF unb2b_board_back_io IS
-- help signals so we can iterate through buses
- SIGNAL si_tx_2arr : t_unb2_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0);
- SIGNAL si_rx_2arr : t_unb2_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0);
+ SIGNAL si_tx_2arr : t_unb2b_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0);
+ SIGNAL si_rx_2arr : t_unb2b_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0);
BEGIN
@@ -57,10 +57,10 @@ BEGIN
gen_wire_bus : FOR i IN 0 TO g_nof_back_bus-1 GENERATE
- gen_wire_signals : FOR j IN 0 TO c_unb2_board_tr_back.bus_w-1 GENERATE
+ gen_wire_signals : FOR j IN 0 TO c_unb2b_board_tr_back.bus_w-1 GENERATE
- si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2_board_tr_back.bus_w + j);
- serial_rx_arr(i*c_unb2_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2b_board_tr_back.bus_w + j);
+ serial_rx_arr(i*c_unb2b_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
END GENERATE;
END GENERATE;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
index 858cc68b92013637641691b30cdb7eb3bf206202..9d228fbe3103f5a3b7951bf8a57ea0d344b62af1 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
@@ -33,7 +33,7 @@ USE technology_lib.technology_pkg.ALL;
-- c3 = 125 MHz
--
-ENTITY unb2_board_clk125_pll IS
+ENTITY unb2b_board_clk125_pll IS
GENERIC (
g_technology : NATURAL := c_tech_arria10;
g_use_clkbuf : BOOLEAN := TRUE;
@@ -49,10 +49,10 @@ ENTITY unb2_board_clk125_pll IS
c3_clk125 : OUT STD_LOGIC; -- PLL c3
pll_locked : OUT STD_LOGIC
);
-END unb2_board_clk125_pll;
+END unb2b_board_clk125_pll;
-ARCHITECTURE arria10 OF unb2_board_clk125_pll IS
+ARCHITECTURE arria10 OF unb2b_board_clk125_pll IS
SIGNAL clk125buf : STD_LOGIC;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
index 63e575d26d41b00f75fa42ee937f963b5cf02aac..ebc2bb83203883da147e19b9c8df2b2242e65aae 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
@@ -33,7 +33,7 @@ USE technology_lib.technology_pkg.ALL;
-- clock from the CLK input via c1 = st_clk200p.
-- . The PLL normal mode operation compensates for internal clock network
-- delays of c0. This compensations aligns c0 to inclk0. With
--- tb_unb2_board_clk200_pll.vhd it appears that the phase setting for c0 does
+-- tb_unb2b_board_clk200_pll.vhd it appears that the phase setting for c0 does
-- not influence the compensation. Therefore it is llso possible to use
-- g_clk200_phase_shift /= 0 and touse c0 as processing clock instead of c1.
-- . The phase offset of c0 and c1 in the clk200_pll MegaWizard component
@@ -90,7 +90,7 @@ USE technology_lib.technology_pkg.ALL;
-- . If necessary more 400 M clock phase could be made available, via g_sel.
--
-ENTITY unb2_board_clk200_pll IS
+ENTITY unb2b_board_clk200_pll IS
GENERIC (
g_technology : NATURAL := c_tech_arria10;
g_use_clkbuf : BOOLEAN := TRUE;
@@ -111,10 +111,10 @@ ENTITY unb2_board_clk200_pll IS
st_clk400 : OUT STD_LOGIC; -- PLL c2 = 0 degrees phase offset to input clk200
st_rst400 : OUT STD_LOGIC
);
-END unb2_board_clk200_pll;
+END unb2b_board_clk200_pll;
-ARCHITECTURE arria10 OF unb2_board_clk200_pll IS
+ARCHITECTURE arria10 OF unb2b_board_clk200_pll IS
CONSTANT c_reset_len : NATURAL := c_meta_delay_len;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
index a4f7612305993083e11746a92216ab1586e1126c..df7d873de9da1b25bf32953dcc02889ab09a2061 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
@@ -33,7 +33,7 @@ USE technology_lib.technology_pkg.ALL;
-- c3 = 125 MHz
--
-ENTITY unb2_board_clk25_pll IS
+ENTITY unb2b_board_clk25_pll IS
GENERIC (
g_technology : NATURAL := c_tech_arria10
);
@@ -47,10 +47,10 @@ ENTITY unb2_board_clk25_pll IS
c3_clk125 : OUT STD_LOGIC; -- PLL c3
pll_locked : OUT STD_LOGIC
);
-END unb2_board_clk25_pll;
+END unb2b_board_clk25_pll;
-ARCHITECTURE arria10 OF unb2_board_clk25_pll IS
+ARCHITECTURE arria10 OF unb2b_board_clk25_pll IS
BEGIN
u_pll : ENTITY tech_pll_lib.tech_pll_clk25
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
index 561075cf83b12b408cda4871c1272434f693beeb..290dbe6d2f33767cf20a26f767eed7efded5839c 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
@@ -30,7 +30,7 @@ USE common_lib.common_pkg.ALL;
-- 2) sys_rst released when the sys_clk PLL from the SOPC system has locked,
-- can be used as a system reset for the sys_clk domain.
-ENTITY unb2_board_clk_rst IS
+ENTITY unb2b_board_clk_rst IS
PORT (
-- Reference clock and reset to SOPC system PLL
xo_clk : IN STD_LOGIC; -- reference XO clock (e.g. 25 MHz also use by PLL in SOPC)
@@ -40,10 +40,10 @@ ENTITY unb2_board_clk_rst IS
sys_locked : IN STD_LOGIC; -- system clock PLL locked
sys_rst : OUT STD_LOGIC -- system reset released some cycles after the system clock PLL has in locked
);
-END unb2_board_clk_rst;
+END unb2b_board_clk_rst;
-ARCHITECTURE str OF unb2_board_clk_rst IS
+ARCHITECTURE str OF unb2b_board_clk_rst IS
CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
index 73927379317d0a4639fbd006f8af9da384338e59..638d075375afeb169d227c4b0ea9e93166435dc4 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
@@ -21,36 +21,36 @@
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
-USE work.unb2_board_pkg.ALL;
+USE work.unb2b_board_pkg.ALL;
-ENTITY unb2_board_front_io IS
+ENTITY unb2b_board_front_io IS
GENERIC (
- g_nof_qsfp_bus : NATURAL := c_unb2_board_tr_qsfp.nof_bus
+ g_nof_qsfp_bus : NATURAL := c_unb2b_board_tr_qsfp.nof_bus
);
PORT (
- serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_qsfp_bus * c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_qsfp_bus * c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_qsfp_bus * c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_qsfp_bus * c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
green_led_arr : IN STD_LOGIC_VECTOR(g_nof_qsfp_bus-1 DOWNTO 0) := (OTHERS=>'0');
red_led_arr : IN STD_LOGIC_VECTOR(g_nof_qsfp_bus-1 DOWNTO 0) := (OTHERS=>'0');
- QSFP_RX : IN t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
- QSFP_TX : OUT t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0);
+ QSFP_RX : IN t_unb2b_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+ QSFP_TX : OUT t_unb2b_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0);
- --QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
- --QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ --QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.i2c_w-1 downto 0);
+ --QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.i2c_w-1 downto 0);
--QSFP_RST : INOUT STD_LOGIC;
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
);
-END unb2_board_front_io;
+END unb2b_board_front_io;
-ARCHITECTURE str OF unb2_board_front_io IS
+ARCHITECTURE str OF unb2b_board_front_io IS
-- help signals so we can iterate through buses
- SIGNAL si_tx_2arr : t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0);
- SIGNAL si_rx_2arr : t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0);
+ SIGNAL si_tx_2arr : t_unb2b_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0);
+ SIGNAL si_rx_2arr : t_unb2b_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0);
BEGIN
@@ -67,10 +67,10 @@ BEGIN
gen_wire_bus : FOR i IN 0 TO g_nof_qsfp_bus-1 GENERATE
- gen_wire_signals : FOR j IN 0 TO c_unb2_board_tr_qsfp.bus_w-1 GENERATE
+ gen_wire_signals : FOR j IN 0 TO c_unb2b_board_tr_qsfp.bus_w-1 GENERATE
- si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2_board_tr_qsfp.bus_w + j);
- serial_rx_arr(i*c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2b_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i*c_unb2b_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
END GENERATE;
END GENERATE;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
index 12b817b2abf10ac61c4c575bd3e8bf7301bc8c59..ceed18938e9b874df0a5c5c023a51992bcb158b5 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
@@ -26,7 +26,7 @@ USE i2c_lib.i2c_dev_unb2_pkg.ALL;
USE common_lib.common_pkg.ALL;
-ENTITY unb2_board_hmc_ctrl IS
+ENTITY unb2b_board_hmc_ctrl IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_nof_result : NATURAL := 42;
@@ -50,7 +50,7 @@ ENTITY unb2_board_hmc_ctrl IS
END ENTITY;
-ARCHITECTURE rtl OF unb2_board_hmc_ctrl IS
+ARCHITECTURE rtl OF unb2b_board_hmc_ctrl IS
TYPE t_SEQUENCE IS ARRAY (NATURAL RANGE <>) OF NATURAL;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
index afe1feab4e4d7fc402bc8adc4a0519c823ab754c..7c9a303eba45b95497a6e3baf633f0028b872e05 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
@@ -30,7 +30,7 @@ USE common_lib.common_pkg.ALL;
-- . Extend WDI to avoid watchdog reset during software reload
-- . Pulse every 1 us, 1 ms and 1 s
-ENTITY unb2_board_node_ctrl IS
+ENTITY unb2b_board_node_ctrl IS
GENERIC (
g_pulse_us : NATURAL := 125; -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
g_pulse_ms : NATURAL := 1000; -- nof pulse_us pulses to get ms period (fixed, use less to speed up simulation)
@@ -52,10 +52,10 @@ ENTITY unb2_board_node_ctrl IS
mm_pulse_ms : OUT STD_LOGIC; -- pulses every ms
mm_pulse_s : OUT STD_LOGIC -- pulses every s
);
-END unb2_board_node_ctrl;
+END unb2b_board_node_ctrl;
-ARCHITECTURE str OF unb2_board_node_ctrl IS
+ARCHITECTURE str OF unb2b_board_node_ctrl IS
CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg
@@ -99,7 +99,7 @@ BEGIN
);
-- Toggle the WDI every 1 ms
- u_unb2_board_wdi_extend : ENTITY work.unb2_board_wdi_extend
+ u_unb2b_board_wdi_extend : ENTITY work.unb2b_board_wdi_extend
GENERIC MAP (
g_extend_w => g_wdi_extend_w
)
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
index 18e45198042d4743f27025fb08a8b775157d74f0..cd4e298078c4eab999d77ea15a3fed5ff3b6b5bd 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
@@ -30,10 +30,10 @@
-- use the same widths also for the variable width MM registers. Therefore
-- rather then obtaining the variable MM register widths from local design
-- constants and the fixed widths from module packages, it seems easier to
--- collect them here in t_c_unb2_board_peripherals_mm_reg.
+-- collect them here in t_c_unb2b_board_peripherals_mm_reg.
-- Remarks:
--- . The c_unb2_board_peripherals_mm_reg_default suits most designs, if
--- necessary design specific t_c_unb2_board_peripherals_mm_reg constants
+-- . The c_unb2b_board_peripherals_mm_reg_default suits most designs, if
+-- necessary design specific t_c_unb2b_board_peripherals_mm_reg constants
-- can be defined here as well.
-- . If some design would need different widths for multiple instances, then
-- these widths need to be defined locally in that design.
@@ -41,12 +41,12 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-PACKAGE unb2_board_peripherals_pkg IS
+PACKAGE unb2b_board_peripherals_pkg IS
-- *_adr_w : Actual MM address widths
-- *_dat_w : The default MM data width is c_word_w=32, otherwise it is specified in the record
- TYPE t_c_unb2_board_peripherals_mm_reg IS RECORD
+ TYPE t_c_unb2b_board_peripherals_mm_reg IS RECORD
cross_clock_domain : BOOLEAN; -- = TRUE -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
-- 1GbE
@@ -165,9 +165,9 @@ PACKAGE unb2_board_peripherals_pkg IS
reg_unb_pmbus_adr_w : NATURAL; -- = 6
END RECORD;
- CONSTANT c_unb2_board_peripherals_mm_reg_default : t_c_unb2_board_peripherals_mm_reg := (TRUE, 10, 4, 10, 5, 10, 1, 1, 6, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1, 3, 4, 6);
+ CONSTANT c_unb2b_board_peripherals_mm_reg_default : t_c_unb2b_board_peripherals_mm_reg := (TRUE, 10, 4, 10, 5, 10, 1, 1, 6, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1, 3, 4, 6);
-END unb2_board_peripherals_pkg;
+END unb2b_board_peripherals_pkg;
-PACKAGE BODY unb2_board_peripherals_pkg IS
-END unb2_board_peripherals_pkg;
+PACKAGE BODY unb2b_board_peripherals_pkg IS
+END unb2b_board_peripherals_pkg;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
index a811f49c45e417bdd3488a25b295196c7aeddf1f..18e01b37d7099eb2ed393c77ccf2b160ccdcb1bb 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
@@ -26,78 +26,78 @@ USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-PACKAGE unb2_board_pkg IS
+PACKAGE unb2b_board_pkg IS
-- UniBoard
- CONSTANT c_unb2_board_nof_node : NATURAL := 4; -- number of nodes on UniBoard
- CONSTANT c_unb2_board_nof_node_w : NATURAL := 2; -- = ceil_log2(c_unb2_board_nof_node)
- CONSTANT c_unb2_board_nof_chip : NATURAL := c_unb2_board_nof_node; -- = 4
- CONSTANT c_unb2_board_nof_chip_w : NATURAL := 2; -- = ceil_log2(c_unb2_board_nof_chip)
- CONSTANT c_unb2_board_nof_ddr : NATURAL := 2; -- each node has 2 DDR modules
+ CONSTANT c_unb2b_board_nof_node : NATURAL := 4; -- number of nodes on UniBoard
+ CONSTANT c_unb2b_board_nof_node_w : NATURAL := 2; -- = ceil_log2(c_unb2b_board_nof_node)
+ CONSTANT c_unb2b_board_nof_chip : NATURAL := c_unb2b_board_nof_node; -- = 4
+ CONSTANT c_unb2b_board_nof_chip_w : NATURAL := 2; -- = ceil_log2(c_unb2b_board_nof_chip)
+ CONSTANT c_unb2b_board_nof_ddr : NATURAL := 2; -- each node has 2 DDR modules
-- Subrack
- CONSTANT c_unb2_board_nof_uniboard : NATURAL := 4; -- nof UniBoard in a subrack
- CONSTANT c_unb2_board_nof_uniboard_w : NATURAL := 6; -- Only 2 required for 4 boards; full width is 6.
+ CONSTANT c_unb2b_board_nof_uniboard : NATURAL := 4; -- nof UniBoard in a subrack
+ CONSTANT c_unb2b_board_nof_uniboard_w : NATURAL := 6; -- Only 2 required for 4 boards; full width is 6.
-- Clock frequencies
- CONSTANT c_unb2_board_ext_clk_freq_200M : NATURAL := 200 * 10**6; -- external clock, SMA clock
- CONSTANT c_unb2_board_eth_clk_freq_25M : NATURAL := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
- CONSTANT c_unb2_board_eth_clk_freq_125M : NATURAL := 125 * 10**6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
- CONSTANT c_unb2_board_tse_clk_freq : NATURAL := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
- CONSTANT c_unb2_board_cal_clk_freq : NATURAL := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
- CONSTANT c_unb2_board_mm_clk_freq_10M : NATURAL := 10 * 10**6; -- clock when g_sim=TRUE
- CONSTANT c_unb2_board_mm_clk_freq_25M : NATURAL := 25 * 10**6; -- clock derived from ETH_clk by PLL
- CONSTANT c_unb2_board_mm_clk_freq_50M : NATURAL := 50 * 10**6; -- clock derived from ETH_clk by PLL
- CONSTANT c_unb2_board_mm_clk_freq_100M : NATURAL := 100 * 10**6; -- clock derived from ETH_clk by PLL
- CONSTANT c_unb2_board_mm_clk_freq_125M : NATURAL := 125 * 10**6; -- clock derived from ETH_clk by PLL
+ CONSTANT c_unb2b_board_ext_clk_freq_200M : NATURAL := 200 * 10**6; -- external clock, SMA clock
+ CONSTANT c_unb2b_board_eth_clk_freq_25M : NATURAL := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
+ CONSTANT c_unb2b_board_eth_clk_freq_125M : NATURAL := 125 * 10**6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
+ CONSTANT c_unb2b_board_tse_clk_freq : NATURAL := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
+ CONSTANT c_unb2b_board_cal_clk_freq : NATURAL := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
+ CONSTANT c_unb2b_board_mm_clk_freq_10M : NATURAL := 10 * 10**6; -- clock when g_sim=TRUE
+ CONSTANT c_unb2b_board_mm_clk_freq_25M : NATURAL := 25 * 10**6; -- clock derived from ETH_clk by PLL
+ CONSTANT c_unb2b_board_mm_clk_freq_50M : NATURAL := 50 * 10**6; -- clock derived from ETH_clk by PLL
+ CONSTANT c_unb2b_board_mm_clk_freq_100M : NATURAL := 100 * 10**6; -- clock derived from ETH_clk by PLL
+ CONSTANT c_unb2b_board_mm_clk_freq_125M : NATURAL := 125 * 10**6; -- clock derived from ETH_clk by PLL
-- I2C
- CONSTANT c_unb2_board_reg_sens_adr_w : NATURAL := 3; -- must match ceil_log2(c_mm_nof_dat) in unb2_board_sens_reg.vhd
+ CONSTANT c_unb2b_board_reg_sens_adr_w : NATURAL := 3; -- must match ceil_log2(c_mm_nof_dat) in unb2b_board_sens_reg.vhd
CONSTANT c_i2c_peripheral_sens : NATURAL := 0;
CONSTANT c_i2c_peripheral_pmbus : NATURAL := 1;
CONSTANT c_i2c_peripheral_hmc : NATURAL := 2;
-- ETH
- CONSTANT c_unb2_board_nof_eth : NATURAL := 2; -- number of ETH channels per node
+ CONSTANT c_unb2b_board_nof_eth : NATURAL := 2; -- number of ETH channels per node
-- CONSTANT RECORD DECLARATIONS ---------------------------------------------
- -- c_unb2_board_signature_* : random signature words used for unused status bits to ensure that the software reads the correct interface address
- CONSTANT c_unb2_board_signature_eth1g_slv : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"46e46cbc";
- CONSTANT c_unb2_board_signature_eth10g_slv : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"2bd2e40a";
+ -- c_unb2b_board_signature_* : random signature words used for unused status bits to ensure that the software reads the correct interface address
+ CONSTANT c_unb2b_board_signature_eth1g_slv : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"46e46cbc";
+ CONSTANT c_unb2b_board_signature_eth10g_slv : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"2bd2e40a";
- CONSTANT c_unb2_board_signature_eth1g : INTEGER := TO_SINT(c_unb2_board_signature_eth1g_slv );
- CONSTANT c_unb2_board_signature_eth10g : INTEGER := TO_SINT(c_unb2_board_signature_eth10g_slv );
+ CONSTANT c_unb2b_board_signature_eth1g : INTEGER := TO_SINT(c_unb2b_board_signature_eth1g_slv );
+ CONSTANT c_unb2b_board_signature_eth10g : INTEGER := TO_SINT(c_unb2b_board_signature_eth10g_slv );
-- Transceivers
- TYPE t_c_unb2_board_tr IS RECORD
+ TYPE t_c_unb2b_board_tr IS RECORD
nof_bus : NATURAL;
bus_w : NATURAL;
i2c_w : NATURAL;
END RECORD;
- --CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (2, 24, 3); -- per node: 2 buses with 24 channels
- CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (1, 24, 3); -- per node: 1 buses with 24 channels (testing)
- --CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (2, 12, 3); -- per node: 2 buses with 24 channels (testing)
- --CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (2, 4, 3); -- per node: 2 buses with 24 channels (testing)
+ --CONSTANT c_unb2b_board_tr_back : t_c_unb2b_board_tr := (2, 24, 3); -- per node: 2 buses with 24 channels
+ CONSTANT c_unb2b_board_tr_back : t_c_unb2b_board_tr := (1, 24, 3); -- per node: 1 buses with 24 channels (testing)
+ --CONSTANT c_unb2b_board_tr_back : t_c_unb2b_board_tr := (2, 12, 3); -- per node: 2 buses with 24 channels (testing)
+ --CONSTANT c_unb2b_board_tr_back : t_c_unb2b_board_tr := (2, 4, 3); -- per node: 2 buses with 24 channels (testing)
- CONSTANT c_unb2_board_tr_ring : t_c_unb2_board_tr := (2, 12, 0); -- per node: 2 buses with 12 channels
- --CONSTANT c_unb2_board_tr_ring : t_c_unb2_board_tr := (2, 4, 0); -- per node: 2 buses with 12 channels (testing)
+ CONSTANT c_unb2b_board_tr_ring : t_c_unb2b_board_tr := (2, 12, 0); -- per node: 2 buses with 12 channels
+ --CONSTANT c_unb2b_board_tr_ring : t_c_unb2b_board_tr := (2, 4, 0); -- per node: 2 buses with 12 channels (testing)
- CONSTANT c_unb2_board_tr_qsfp : t_c_unb2_board_tr := (6, 4, 6); -- per node: 6 buses with 4 channels
- CONSTANT c_unb2_board_tr_qsfp_nof_leds : NATURAL := c_unb2_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
+ CONSTANT c_unb2b_board_tr_qsfp : t_c_unb2b_board_tr := (6, 4, 6); -- per node: 6 buses with 4 channels
+ CONSTANT c_unb2b_board_tr_qsfp_nof_leds : NATURAL := c_unb2b_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
- TYPE t_unb2_board_qsfp_bus_2arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
- TYPE t_unb2_board_ring_bus_2arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 DOWNTO 0);
- TYPE t_unb2_board_back_bus_2arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 DOWNTO 0);
+ TYPE t_unb2b_board_qsfp_bus_2arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ TYPE t_unb2b_board_ring_bus_2arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0);
+ TYPE t_unb2b_board_back_bus_2arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_unb2b_board_tr_back.bus_w-1 DOWNTO 0);
-- Auxiliary
-- Test IO Interface
- TYPE t_c_unb2_board_testio IS RECORD
+ TYPE t_c_unb2b_board_testio IS RECORD
tst_w : NATURAL; -- = nof tst = 2; [tst_w-1 +tst_lo : tst_lo] = [5:4],
led_w : NATURAL; -- = nof led = 2; [led_w-1 +led_lo : led_lo] = [3:2],
jmp_w : NATURAL; -- = nof jmp = 2; [jmp_w-1 +jmp_lo : jmp_lo] = [1:0],
@@ -106,28 +106,28 @@ PACKAGE unb2_board_pkg IS
jmp_lo : NATURAL; -- = 0;
END RECORD;
- CONSTANT c_unb2_board_testio : t_c_unb2_board_testio := (2, 2, 2, 2, 2, 0);
- CONSTANT c_unb2_board_testio_led_green : NATURAL := c_unb2_board_testio.led_lo;
- CONSTANT c_unb2_board_testio_led_red : NATURAL := c_unb2_board_testio.led_lo+1;
+ CONSTANT c_unb2b_board_testio : t_c_unb2b_board_testio := (2, 2, 2, 2, 2, 0);
+ CONSTANT c_unb2b_board_testio_led_green : NATURAL := c_unb2b_board_testio.led_lo;
+ CONSTANT c_unb2b_board_testio_led_red : NATURAL := c_unb2b_board_testio.led_lo+1;
- TYPE t_c_unb2_board_aux IS RECORD
+ TYPE t_c_unb2b_board_aux IS RECORD
version_w : NATURAL; -- = 2;
id_w : NATURAL; -- = 8; -- 6+2 bits wide = total node ID for up to 64 UniBoards in a system and 4 nodes per board
chip_id_w : NATURAL; -- = 2; -- board node ID for the 4 FPGA nodes on a UniBoard
testio_w : NATURAL; -- = 6;
- testio : t_c_unb2_board_testio;
+ testio : t_c_unb2b_board_testio;
END RECORD;
- CONSTANT c_unb2_board_aux : t_c_unb2_board_aux := (2, 8, c_unb2_board_nof_chip_w, 6, c_unb2_board_testio);
+ CONSTANT c_unb2b_board_aux : t_c_unb2b_board_aux := (2, 8, c_unb2b_board_nof_chip_w, 6, c_unb2b_board_testio);
- TYPE t_e_unb2_board_node IS (e_any);
+ TYPE t_e_unb2b_board_node IS (e_any);
- TYPE t_unb2_board_fw_version IS RECORD
+ TYPE t_unb2b_board_fw_version IS RECORD
hi : NATURAL; -- = 0..15
lo : NATURAL; -- = 0..15, firmware version is: hi.lo
END RECORD;
- CONSTANT c_unb2_board_fw_version : t_unb2_board_fw_version := (0, 0);
+ CONSTANT c_unb2b_board_fw_version : t_unb2b_board_fw_version := (0, 0);
-- SIGNAL RECORD DECLARATIONS -----------------------------------------------
@@ -135,13 +135,13 @@ PACKAGE unb2_board_pkg IS
-- I2C, MDIO
-- . If no I2C bus arbitration or clock stretching is needed then the SCL only needs to be output.
-- . Can also be used for a PHY Management Data IO interface with serial clock MDC and serial data MDIO
- TYPE t_unb2_board_i2c_inout IS RECORD
+ TYPE t_unb2b_board_i2c_inout IS RECORD
scl : STD_LOGIC; -- serial clock
sda : STD_LOGIC; -- serial data
END RECORD;
-- System info
- TYPE t_c_unb2_board_system_info IS RECORD
+ TYPE t_c_unb2b_board_system_info IS RECORD
version : NATURAL; -- UniBoard board HW version (2 bit value)
id : NATURAL; -- UniBoard FPGA node id (8 bit value)
-- Derived ID info:
@@ -151,17 +151,17 @@ PACKAGE unb2_board_pkg IS
is_node2 : NATURAL; -- 1 for Node 2, else 0.
END RECORD;
- FUNCTION func_unb2_board_system_info(VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0)) RETURN t_c_unb2_board_system_info;
+ FUNCTION func_unb2b_board_system_info(VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0)) RETURN t_c_unb2b_board_system_info;
-END unb2_board_pkg;
+END unb2b_board_pkg;
-PACKAGE BODY unb2_board_pkg IS
+PACKAGE BODY unb2b_board_pkg IS
- FUNCTION func_unb2_board_system_info(VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0)) RETURN t_c_unb2_board_system_info IS
- VARIABLE v_system_info : t_c_unb2_board_system_info;
+ FUNCTION func_unb2b_board_system_info(VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0)) RETURN t_c_unb2b_board_system_info IS
+ VARIABLE v_system_info : t_c_unb2b_board_system_info;
BEGIN
v_system_info.version := TO_INTEGER(UNSIGNED(VERSION));
v_system_info.id := TO_INTEGER(UNSIGNED(ID));
@@ -172,4 +172,4 @@ PACKAGE BODY unb2_board_pkg IS
RETURN v_system_info;
END;
-END unb2_board_pkg;
+END unb2b_board_pkg;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
index 934ac9f4beb8ca5a97cf3803134d19477c0a57fa..5eda1fcfe07cbbe6b5cc29ba74f2d82dd66f299c 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
@@ -26,7 +26,7 @@ USE i2c_lib.i2c_dev_unb2_pkg.ALL;
USE common_lib.common_pkg.ALL;
-ENTITY unb2_board_pmbus_ctrl IS
+ENTITY unb2b_board_pmbus_ctrl IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_nof_result : NATURAL := 42;
@@ -50,7 +50,7 @@ ENTITY unb2_board_pmbus_ctrl IS
END ENTITY;
-ARCHITECTURE rtl OF unb2_board_pmbus_ctrl IS
+ARCHITECTURE rtl OF unb2b_board_pmbus_ctrl IS
TYPE t_SEQUENCE IS ARRAY (NATURAL RANGE <>) OF NATURAL;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
index f90d2dc68961b44125a049a8e170d394778f678e..aea1c16dbf45e173624a4062c1c95f89a4b700b9 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
@@ -64,7 +64,7 @@ USE dp_lib.dp_stream_pkg.ALL;
-- information when less than all 4 lane are connected.
--
-ENTITY unb2_board_qsfp_leds IS
+ENTITY unb2b_board_qsfp_leds IS
GENERIC (
g_sim : BOOLEAN := FALSE; -- when true speed up led toggling in simulation
g_factory_image : BOOLEAN := FALSE; -- distinguish factory image and user images
@@ -86,10 +86,10 @@ ENTITY unb2_board_qsfp_leds IS
green_led_arr : OUT STD_LOGIC_VECTOR(g_nof_qsfp-1 DOWNTO 0);
red_led_arr : OUT STD_LOGIC_VECTOR(g_nof_qsfp-1 DOWNTO 0)
);
-END unb2_board_qsfp_leds;
+END unb2b_board_qsfp_leds;
-ARCHITECTURE str OF unb2_board_qsfp_leds IS
+ARCHITECTURE str OF unb2b_board_qsfp_leds IS
CONSTANT c_nof_ms : NATURAL := sel_a_b(g_sim, 1, 100); -- force off for c_nof_ms and then on for at least c_nof_ms
CONSTANT c_nof_lanes : NATURAL := g_nof_qsfp*c_quad; -- number of transceiver lanes, fixed 4 per Quad-SFP cage
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
index 2c924997a546d3de8092e6107b80f868482b3617..a8a8058ab514d35ec9a25cdd8f7d10caf97ec12e 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
@@ -21,27 +21,27 @@
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
-USE work.unb2_board_pkg.ALL;
+USE work.unb2b_board_pkg.ALL;
-ENTITY unb2_board_ring_io IS
+ENTITY unb2b_board_ring_io IS
GENERIC (
- g_nof_ring_bus : NATURAL := c_unb2_board_tr_ring.nof_bus
+ g_nof_ring_bus : NATURAL := c_unb2b_board_tr_ring.nof_bus
);
PORT (
- serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_ring_bus * c_unb2_board_tr_ring.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_ring_bus * c_unb2_board_tr_ring.bus_w-1 DOWNTO 0);
+ serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_ring_bus * c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_ring_bus * c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0);
- RING_RX : IN t_unb2_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
- RING_TX : OUT t_unb2_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0)
+ RING_RX : IN t_unb2b_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+ RING_TX : OUT t_unb2b_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0)
);
-END unb2_board_ring_io;
+END unb2b_board_ring_io;
-ARCHITECTURE str OF unb2_board_ring_io IS
+ARCHITECTURE str OF unb2b_board_ring_io IS
-- help signals so we can iterate through buses
- SIGNAL si_tx_2arr : t_unb2_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0);
- SIGNAL si_rx_2arr : t_unb2_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0);
+ SIGNAL si_tx_2arr : t_unb2b_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0);
+ SIGNAL si_rx_2arr : t_unb2b_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0);
BEGIN
@@ -52,10 +52,10 @@ BEGIN
gen_wire_bus : FOR i IN 0 TO g_nof_ring_bus-1 GENERATE
- gen_wire_signals : FOR j IN 0 TO c_unb2_board_tr_ring.bus_w-1 GENERATE
+ gen_wire_signals : FOR j IN 0 TO c_unb2b_board_tr_ring.bus_w-1 GENERATE
- si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2_board_tr_ring.bus_w + j);
- serial_rx_arr(i*c_unb2_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2b_board_tr_ring.bus_w + j);
+ serial_rx_arr(i*c_unb2b_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
END GENERATE;
END GENERATE;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
index 6ef9b2c0ccd50fbd649779aa295f69409429b47c..8016884bd89087b56c4ea86cfbe97b10826b905b 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
@@ -23,15 +23,15 @@ LIBRARY IEEE, common_lib, i2c_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
USE i2c_lib.i2c_pkg.ALL;
-USE work.unb2_board_pkg.ALL;
+USE work.unb2b_board_pkg.ALL;
-ENTITY unb2_board_sens is
+ENTITY unb2b_board_sens is
GENERIC (
g_sim : BOOLEAN := FALSE;
g_i2c_peripheral : NATURAL;
g_clk_freq : NATURAL := 100*10**6; -- clk frequency in Hz
g_temp_high : NATURAL := 85;
- g_sens_nof_result : NATURAL; -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
+ g_sens_nof_result : NATURAL; -- Should match nof read bytes via I2C in the unb2b_board_sens_ctrl SEQUENCE list
g_comma_w : NATURAL := 0
);
PORT (
@@ -49,7 +49,7 @@ ENTITY unb2_board_sens is
END ENTITY;
-ARCHITECTURE str OF unb2_board_sens IS
+ARCHITECTURE str OF unb2b_board_sens IS
-- I2C clock rate settings
CONSTANT c_sens_clk_cnt : NATURAL := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq/10**6)); -- define I2C clock rate
@@ -81,8 +81,8 @@ ARCHITECTURE str OF unb2_board_sens IS
BEGIN
- gen_unb2_board_sens_ctrl : IF g_i2c_peripheral=c_i2c_peripheral_sens GENERATE
- u_unb2_board_sens_ctrl : ENTITY work.unb2_board_sens_ctrl
+ gen_unb2b_board_sens_ctrl : IF g_i2c_peripheral=c_i2c_peripheral_sens GENERATE
+ u_unb2b_board_sens_ctrl : ENTITY work.unb2b_board_sens_ctrl
GENERIC MAP (
g_sim => g_sim,
g_nof_result => g_sens_nof_result,
@@ -105,8 +105,8 @@ BEGIN
);
END GENERATE;
- gen_unb2_board_pmbus_ctrl : IF g_i2c_peripheral=c_i2c_peripheral_pmbus GENERATE
- u_unb2_board_pmbus_ctrl : ENTITY work.unb2_board_pmbus_ctrl
+ gen_unb2b_board_pmbus_ctrl : IF g_i2c_peripheral=c_i2c_peripheral_pmbus GENERATE
+ u_unb2b_board_pmbus_ctrl : ENTITY work.unb2b_board_pmbus_ctrl
GENERIC MAP (
g_sim => g_sim,
g_nof_result => g_sens_nof_result,
@@ -129,8 +129,8 @@ BEGIN
);
END GENERATE;
- gen_unb2_board_hmc_ctrl : IF g_i2c_peripheral=c_i2c_peripheral_hmc GENERATE
- u_unb2_board_hmc_ctrl : ENTITY work.unb2_board_hmc_ctrl
+ gen_unb2b_board_hmc_ctrl : IF g_i2c_peripheral=c_i2c_peripheral_hmc GENERATE
+ u_unb2b_board_hmc_ctrl : ENTITY work.unb2b_board_hmc_ctrl
GENERIC MAP (
g_sim => g_sim,
g_nof_result => g_sens_nof_result,
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
index fcaac6c2a37bc42a48a04406b3af61057853699b..8c7077ca92f7d0d2b42f9f78321f1c0b4f51b74b 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
@@ -28,7 +28,7 @@ USE i2c_lib.i2c_dev_unb2_pkg.ALL;
USE common_lib.common_pkg.ALL;
-ENTITY unb2_board_sens_ctrl IS
+ENTITY unb2b_board_sens_ctrl IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_nof_result : NATURAL := 40;
@@ -52,7 +52,7 @@ ENTITY unb2_board_sens_ctrl IS
END ENTITY;
-ARCHITECTURE rtl OF unb2_board_sens_ctrl IS
+ARCHITECTURE rtl OF unb2b_board_sens_ctrl IS
-- I2C slave commands of the devices on the I2C bus on UniBoard
CONSTANT TMP451_LOC_HI : NATURAL := 16#00#;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
index e38265c892ebbcc6bf09e1ba56aaa5eeef87cdb0..839546906b5184e93dad0ff7638663d71420b429 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
--- Purpose: Provide MM slave register for unb2_board_sens
+-- Purpose: Provide MM slave register for unb2b_board_sens
-- Description:
--
-- 31 24 23 16 15 8 7 0 wi
@@ -65,7 +65,7 @@ USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-ENTITY unb2_board_sens_reg IS
+ENTITY unb2b_board_sens_reg IS
GENERIC (
g_sens_nof_result : NATURAL := 4;
g_temp_high : NATURAL := 85
@@ -87,10 +87,10 @@ ENTITY unb2_board_sens_reg IS
temp_high : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
-END unb2_board_sens_reg;
+END unb2b_board_sens_reg;
-ARCHITECTURE rtl OF unb2_board_sens_reg IS
+ARCHITECTURE rtl OF unb2b_board_sens_reg IS
-- Define the actual size of the MM slave register
CONSTANT c_mm_nof_dat : NATURAL := g_sens_nof_result+1+1; -- +1 to fit user set temp_high one additional address
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
index a2be55ca47eb6b352b5cbee26ae7a584d3b23a6e..5f1062f2c1bcd07856191703bd8d4f974a977f01 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
@@ -23,18 +23,18 @@
LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
-USE work.unb2_board_pkg.ALL;
+USE work.unb2b_board_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
-- Keep the UniBoard system info knowledge in this HDL entity and in the
-- corresponding software functions in unb_common.c,h. This avoids having to
-- define named constants for indexing the fields in the info word.
-ENTITY unb2_board_system_info IS
+ENTITY unb2b_board_system_info IS
GENERIC (
g_sim : BOOLEAN := FALSE;
- g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version; -- firmware version x.y (4b.4b)
- g_aux : t_c_unb2_board_aux := c_unb2_board_aux; -- aux contains the hardware version
+ g_fw_version : t_unb2b_board_fw_version := c_unb2b_board_fw_version; -- firmware version x.y (4b.4b)
+ g_aux : t_c_unb2b_board_aux := c_unb2b_board_aux; -- aux contains the hardware version
g_rom_version: NATURAL := 1;
g_technology : NATURAL := c_tech_arria10
);
@@ -43,15 +43,15 @@ ENTITY unb2_board_system_info IS
hw_version : IN STD_LOGIC_VECTOR(g_aux.version_w-1 DOWNTO 0);
id : IN STD_LOGIC_VECTOR(g_aux.id_w-1 DOWNTO 0);
info : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- bck_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_uniboard_w-1 DOWNTO 0); -- ID[7:2]
- chip_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_chip_w-1 DOWNTO 0); -- ID[1:0]
- node_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_node_w-1 DOWNTO 0); -- ID[1:0]
+ bck_id : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_uniboard_w-1 DOWNTO 0); -- ID[7:2]
+ chip_id : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_chip_w-1 DOWNTO 0); -- ID[1:0]
+ node_id : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_node_w-1 DOWNTO 0); -- ID[1:0]
is_node2 : OUT STD_LOGIC -- '1' for Node 2, else '0'.
);
-END unb2_board_system_info;
+END unb2b_board_system_info;
-ARCHITECTURE str OF unb2_board_system_info IS
+ARCHITECTURE str OF unb2b_board_system_info IS
SIGNAL cs_sim : STD_LOGIC;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
index 08e9c515ba5ee06a3cbe13078105adcb0c14f806..53069eb29e865d0d4bba87ca25619bd48301323b 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
@@ -28,7 +28,7 @@
-- FR FIFO read
-- FW FIFO write
--
--- wi Bits R/W Name Default Description |REG_UNB2_BOARD_SYSTEM_INFO|
+-- wi Bits R/W Name Default Description |REG_unb2b_BOARD_SYSTEM_INFO|
-- =============================================================================
-- 0 [31..0] RO info
-- 1 [7..0] RO 0
@@ -48,9 +48,9 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_str_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE work.unb2_board_pkg.ALL;
+USE work.unb2b_board_pkg.ALL;
-ENTITY unb2_board_system_info_reg IS
+ENTITY unb2b_board_system_info_reg IS
GENERIC (
g_design_name : STRING;
g_stamp_date : NATURAL := 0;
@@ -69,10 +69,10 @@ ENTITY unb2_board_system_info_reg IS
info : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)
);
-END unb2_board_system_info_reg;
+END unb2b_board_system_info_reg;
-ARCHITECTURE rtl OF unb2_board_system_info_reg IS
+ARCHITECTURE rtl OF unb2b_board_system_info_reg IS
CONSTANT c_nof_fixed_regs : NATURAL := 2; -- info, use_phy
CONSTANT c_nof_design_name_regs : NATURAL := 13; -- design_name
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
index ffc5345b51204581561602c2e42a2cf28f7bece8..2f3357549dabda4e412c9a9cb77f05999457d235 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
@@ -30,7 +30,7 @@ USE common_lib.common_pkg.ALL;
-- the HDL image. This component extends the last input WDI by toggling the
-- output WDI for about 2**(g_extend_w-1) ms more.
-ENTITY unb2_board_wdi_extend IS
+ENTITY unb2b_board_wdi_extend IS
GENERIC (
g_extend_w : NATURAL := 14
);
@@ -41,10 +41,10 @@ ENTITY unb2_board_wdi_extend IS
wdi_in : IN STD_LOGIC;
wdi_out : OUT STD_LOGIC
);
-END unb2_board_wdi_extend;
+END unb2b_board_wdi_extend;
-ARCHITECTURE str OF unb2_board_wdi_extend IS
+ARCHITECTURE str OF unb2b_board_wdi_extend IS
SIGNAL wdi_evt : STD_LOGIC;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
index 42a42742a54008100adefd7cc0b25a5df68ba5fa..f62464f5f80f089380e5254605f8c0d1f0ea25b8 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
@@ -28,7 +28,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-ENTITY unb2_board_wdi_reg IS
+ENTITY unb2b_board_wdi_reg IS
PORT (
-- Clocks and reset
mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
@@ -41,10 +41,10 @@ ENTITY unb2_board_wdi_reg IS
-- MM registers in st_clk domain
wdi_override : OUT STD_LOGIC
);
-END unb2_board_wdi_reg;
+END unb2b_board_wdi_reg;
-ARCHITECTURE rtl OF unb2_board_wdi_reg IS
+ARCHITECTURE rtl OF unb2b_board_wdi_reg IS
-- Define the actual size of the MM slave register
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_fpga_sens_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_fpga_sens_reg.vhd
index eb233b1ac5546e80db457f343112f05d94548181..11dc73c393f704ef8c43addd8961186eaf41d425 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_fpga_sens_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_fpga_sens_reg.vhd
@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
--- Purpose: Provide MM slave register for unb2_fpga_sens
+-- Purpose: Provide MM slave register for unb2b_fpga_sens
--
LIBRARY IEEE, common_lib, technology_lib, fpga_sense_lib;
@@ -30,7 +30,7 @@ USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
-ENTITY unb2_fpga_sens_reg IS
+ENTITY unb2b_fpga_sens_reg IS
GENERIC (
g_sim : BOOLEAN;
g_technology : NATURAL := c_tech_arria10;
@@ -57,10 +57,10 @@ ENTITY unb2_fpga_sens_reg IS
-- Max temp output
temp_high : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
-END unb2_fpga_sens_reg;
+END unb2b_fpga_sens_reg;
-ARCHITECTURE str OF unb2_fpga_sens_reg IS
+ARCHITECTURE str OF unb2b_fpga_sens_reg IS
--SIGNAL i_temp_high : STD_LOGIC_VECTOR(6 DOWNTO 0);
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
index 8d4444e6ec52404e78df2d8a4af7000658e82be4..1d4d9e7b50c60a4d80bbae1570c8cd4fe065834f 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
--- Purpose: Test bench for mms_unb2_board_sens
+-- Purpose: Test bench for mms_unb2b_board_sens
--
-- Features:
-- . Verify that the UniBoard sensors are read.
@@ -28,8 +28,8 @@
-- . > as 10
-- . > run -all
-ENTITY tb_mms_unb2_board_sens IS
-END tb_mms_unb2_board_sens;
+ENTITY tb_mms_unb2b_board_sens IS
+END tb_mms_unb2b_board_sens;
LIBRARY IEEE, common_lib, i2c_lib;
USE IEEE.std_logic_1164.ALL;
@@ -37,9 +37,9 @@ USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
-USE work.unb2_board_pkg.ALL;
+USE work.unb2b_board_pkg.ALL;
-ARCHITECTURE tb OF tb_mms_unb2_board_sens IS
+ARCHITECTURE tb OF tb_mms_unb2b_board_sens IS
CONSTANT c_sim : BOOLEAN := TRUE; --FALSE;
CONSTANT c_repeat : NATURAL := 2;
@@ -61,7 +61,7 @@ ARCHITECTURE tb OF tb_mms_unb2_board_sens IS
CONSTANT c_uniboard_adin : REAL := -1.0; -- = NC on UniBoard
CONSTANT c_sens_nof_result : NATURAL := 4 + 1;
- CONSTANT c_sens_expected : t_natural_arr(0 TO c_sens_nof_result-1) := (60, 40, 167, 120, 0); -- 4 bytes as read by c_SEQ in unb2_board_sens_ctrl + sens_err
+ CONSTANT c_sens_expected : t_natural_arr(0 TO c_sens_nof_result-1) := (60, 40, 167, 120, 0); -- 4 bytes as read by c_SEQ in unb2b_board_sens_ctrl + sens_err
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '0';
@@ -152,7 +152,7 @@ BEGIN
-- I2C sensors master
- u_mms_unb2_board_sens : ENTITY work.mms_unb2_board_sens
+ u_mms_unb2b_board_sens : ENTITY work.mms_unb2b_board_sens
GENERIC MAP (
g_sim => c_sim,
g_i2c_peripheral => c_i2c_peripheral_sens,
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
index 13f29d91913a0a613615e253ad05da073e3e694c..7a30d4d4249a5ee487ca21569a3ee3c7b639c0f8 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
@@ -32,11 +32,11 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
-ENTITY tb_unb2_board_clk125_pll IS
-END tb_unb2_board_clk125_pll;
+ENTITY tb_unb2b_board_clk125_pll IS
+END tb_unb2b_board_clk125_pll;
-ARCHITECTURE tb OF tb_unb2_board_clk125_pll IS
+ARCHITECTURE tb OF tb_unb2b_board_clk125_pll IS
CONSTANT c_ext_clk_period : TIME := 8 ns; -- 125 MHz
@@ -56,7 +56,7 @@ BEGIN
ext_clk <= NOT ext_clk OR tb_end AFTER c_ext_clk_period/2;
ext_rst <= '1', '0' AFTER c_ext_clk_period*7;
- dut_0 : ENTITY work.unb2_board_clk125_pll
+ dut_0 : ENTITY work.unb2b_board_clk125_pll
PORT MAP (
arst => ext_rst,
clk125 => ext_clk,
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
index a2e442c17a96dc1432cee7897a8e1f79917bea4d..9f4692fa1d35586b2c700f4f65b255e71c1c4246 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
@@ -32,11 +32,11 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
-ENTITY tb_unb2_board_clk200_pll IS
-END tb_unb2_board_clk200_pll;
+ENTITY tb_unb2b_board_clk200_pll IS
+END tb_unb2b_board_clk200_pll;
-ARCHITECTURE tb OF tb_unb2_board_clk200_pll IS
+ARCHITECTURE tb OF tb_unb2b_board_clk200_pll IS
CONSTANT c_ext_clk_period : TIME := 5 ns; -- 200 MHz
CONSTANT c_clk_vec_w : NATURAL := 6;
@@ -71,7 +71,7 @@ BEGIN
ext_clk <= NOT ext_clk OR tb_end AFTER c_ext_clk_period/2;
ext_rst <= '1', '0' AFTER c_ext_clk_period*7;
- dut_0 : ENTITY work.unb2_board_clk200_pll
+ dut_0 : ENTITY work.unb2b_board_clk200_pll
GENERIC MAP (
g_clk200_phase_shift => "0"
)
@@ -86,7 +86,7 @@ BEGIN
st_rst400 => st_rst400
);
- dut_45 : ENTITY work.unb2_board_clk200_pll
+ dut_45 : ENTITY work.unb2b_board_clk200_pll
GENERIC MAP (
g_clk200_phase_shift => "625",
g_clk200p_phase_shift => "625"
@@ -102,7 +102,7 @@ BEGIN
st_rst400 => OPEN
);
- dut_p6 : ENTITY work.unb2_board_clk200_pll
+ dut_p6 : ENTITY work.unb2b_board_clk200_pll
GENERIC MAP (
g_clk200_phase_shift => "0"
)
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
index cbd3d0290147c376a450c5b718e38c57f8d652db..156d431f5b32e765da27d99142683a7f052cf6c8 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
@@ -32,11 +32,11 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
-ENTITY tb_unb2_board_clk25_pll IS
-END tb_unb2_board_clk25_pll;
+ENTITY tb_unb2b_board_clk25_pll IS
+END tb_unb2b_board_clk25_pll;
-ARCHITECTURE tb OF tb_unb2_board_clk25_pll IS
+ARCHITECTURE tb OF tb_unb2b_board_clk25_pll IS
CONSTANT c_ext_clk_period : TIME := 40 ns; -- 25 MHz
@@ -56,7 +56,7 @@ BEGIN
ext_clk <= NOT ext_clk OR tb_end AFTER c_ext_clk_period/2;
ext_rst <= '1', '0' AFTER c_ext_clk_period*7;
- dut_0 : ENTITY work.unb2_board_clk25_pll
+ dut_0 : ENTITY work.unb2b_board_clk25_pll
PORT MAP (
arst => ext_rst,
clk25 => ext_clk,
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
index a5dbd064dc9a2edc29f28336cfbba3bc4270b09c..99fe67d99bfbe8fa7e24940bf260968562a053c9 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
@@ -25,11 +25,11 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
-ENTITY tb_unb2_board_node_ctrl IS
-END tb_unb2_board_node_ctrl;
+ENTITY tb_unb2b_board_node_ctrl IS
+END tb_unb2b_board_node_ctrl;
-ARCHITECTURE tb OF tb_unb2_board_node_ctrl IS
+ARCHITECTURE tb OF tb_unb2b_board_node_ctrl IS
CONSTANT c_scale : NATURAL := 100; -- scale to speed up simulation
@@ -75,7 +75,7 @@ BEGIN
wdi_in <= wdi AND sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
- dut : ENTITY work.unb2_board_node_ctrl
+ dut : ENTITY work.unb2b_board_node_ctrl
GENERIC MAP (
g_pulse_us => c_pulse_us,
g_pulse_ms => c_pulse_ms,
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
index 06f7e52d03b4c4be727e5f18049b20f9778e2ebd..69d6427370d695765868b9d4d6ae31a92a406c1c 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
--- Purpose: Test bench for unb2_board_qsfp_leds
+-- Purpose: Test bench for unb2b_board_qsfp_leds
-- Description:
-- The test bench is self-stopping but not self-checking. Manually obeserve
-- in the wave window that:
@@ -42,10 +42,10 @@ USE common_lib.common_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-ENTITY tb_unb2_board_qsfp_leds IS
-END tb_unb2_board_qsfp_leds;
+ENTITY tb_unb2b_board_qsfp_leds IS
+END tb_unb2b_board_qsfp_leds;
-ARCHITECTURE tb OF tb_unb2_board_qsfp_leds IS
+ARCHITECTURE tb OF tb_unb2b_board_qsfp_leds IS
CONSTANT c_clk_freq_hz : NATURAL := 200 * 10**6;
CONSTANT c_clk_period_ns : NATURAL := 10**9 / c_clk_freq_hz;
@@ -141,7 +141,7 @@ BEGIN
WAIT;
END PROCESS;
- u_unb2_factory_qsfp_leds : ENTITY work.unb2_board_qsfp_leds
+ u_unb2b_factory_qsfp_leds : ENTITY work.unb2b_board_qsfp_leds
GENERIC MAP (
g_sim => TRUE, -- when true speed up led toggling in simulation
g_factory_image => TRUE, -- distinguish factory image and user images
@@ -164,7 +164,7 @@ BEGIN
red_led_arr => factory_red_led_arr
);
- u_unb2_user_qsfp_leds : ENTITY work.unb2_board_qsfp_leds
+ u_unb2b_user_qsfp_leds : ENTITY work.unb2b_board_qsfp_leds
GENERIC MAP (
g_sim => TRUE, -- when true speed up led toggling in simulation
g_factory_image => FALSE, -- distinguish factory image and user images
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
index 1d9473211b4f12c609a38297f04888887af9304f..21621a58dff936de7f1420b870172d9caca69434 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
@@ -1,35 +1,23 @@
-# TCL File Generated by Component Editor 11.1sp2
-# Wed Jul 23 09:36:00 CEST 2014
+# TCL File Generated by Component Editor 17.0.1
+# Thu Jul 13 11:06:59 CEST 2017
# DO NOT MODIFY
-# +-----------------------------------
-# |
-# | avs2_eth_coe "avs2_eth_coe" v1.0
-# | ASTRON 2014.07.23.09:36:00
-# | MM slave port to conduit for the ETH module
-# |
-# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
-# |
-# | ./avs2_eth_coe.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
-# | ./eth_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
-# |
-# +-----------------------------------
-
-# +-----------------------------------
-# | request TCL package from ACDS 11.0
-# |
-package require -exact sopc 11.0
-# |
-# +-----------------------------------
-
-# +-----------------------------------
-# | module avs2_eth_coe
-# |
+#
+# avs2_eth_coe "avs2_eth_coe" v1.0
+# ASTRON 2017.07.13.11:06:59
+# MM slave port to conduit for the ETH module
+#
+
+#
+# request TCL package from ACDS 17.0
+#
+package require -exact qsys 17.0
+
+
+#
+# module avs2_eth_coe
+#
set_module_property DESCRIPTION "MM slave port to conduit for the ETH module"
set_module_property NAME avs2_eth_coe
set_module_property VERSION 1.0
@@ -38,90 +26,107 @@ set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP Uniboard
set_module_property AUTHOR ASTRON
set_module_property DISPLAY_NAME avs2_eth_coe
-set_module_property TOP_LEVEL_HDL_FILE avs2_eth_coe.vhd
-set_module_property TOP_LEVEL_HDL_MODULE avs2_eth_coe
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
-set_module_property ANALYZE_HDL TRUE
-set_module_property STATIC_TOP_LEVEL_MODULE_NAME ""
-set_module_property FIX_110_VIP_PATH false
-# |
-# +-----------------------------------
-
-# +-----------------------------------
-# | files
-# |
-# | UniBoard_FP7/UniBoard/trunk/Firmware/modules
-# | RadioHDL/trunk/libraries/io/eth/src/vhdl/
-add_file avs2_eth_coe.vhd {SYNTHESIS SIMULATION}
-add_file ../../../../base/common/src/vhdl/common_pkg.vhd {SYNTHESIS SIMULATION}
-add_file ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd {SYNTHESIS SIMULATION}
-add_file ../../../../technology/tse/tech_tse_pkg.vhd {SYNTHESIS SIMULATION}
-add_file eth_pkg.vhd {SYNTHESIS SIMULATION}
-add_file ../../../../base/common/src/vhdl/common_network_layers_pkg.vhd {SYNTHESIS SIMULATION}
-# |
-# +-----------------------------------
-
-# +-----------------------------------
-# | parameters
-# |
-# |
-# +-----------------------------------
-
-# +-----------------------------------
-# | display items
-# |
-# |
-# +-----------------------------------
-
-# +-----------------------------------
-# | connection point mm
-# |
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+#
+# file sets
+#
+add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
+set_fileset_property quartus_synth TOP_LEVEL avs2_eth_coe
+set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property quartus_synth ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd TOP_LEVEL_FILE
+add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
+add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
+add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
+add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
+add_fileset_file common_network_layers_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_network_layers_pkg.vhd
+
+add_fileset sim_vhdl SIM_VHDL "" "VHDL Simulation"
+set_fileset_property sim_vhdl ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property sim_vhdl ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd
+add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
+add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
+add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
+add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
+add_fileset_file common_network_layers_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_network_layers_pkg.vhd
+
+
+#
+# parameters
+#
+
+
+#
+# display items
+#
+
+
+#
+# connection point mm
+#
add_interface mm clock end
set_interface_property mm clockRate 0
-
set_interface_property mm ENABLED true
+set_interface_property mm EXPORT_OF ""
+set_interface_property mm PORT_NAME_MAP ""
+set_interface_property mm CMSIS_SVD_VARIABLES ""
+set_interface_property mm SVD_ADDRESS_GROUP ""
add_interface_port mm csi_mm_clk clk Input 1
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point mm_reset
-# |
+
+#
+# connection point mm_reset
+#
add_interface mm_reset reset end
set_interface_property mm_reset associatedClock mm
set_interface_property mm_reset synchronousEdges DEASSERT
-
set_interface_property mm_reset ENABLED true
+set_interface_property mm_reset EXPORT_OF ""
+set_interface_property mm_reset PORT_NAME_MAP ""
+set_interface_property mm_reset CMSIS_SVD_VARIABLES ""
+set_interface_property mm_reset SVD_ADDRESS_GROUP ""
add_interface_port mm_reset csi_mm_reset reset Input 1
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point mms_tse
-# |
+
+#
+# connection point mms_tse
+#
add_interface mms_tse avalon end
-set_interface_property mms_tse addressAlignment DYNAMIC
set_interface_property mms_tse addressUnits WORDS
set_interface_property mms_tse associatedClock mm
set_interface_property mms_tse associatedReset mm_reset
+set_interface_property mms_tse bitsPerSymbol 8
+set_interface_property mms_tse bridgedAddressOffset ""
+set_interface_property mms_tse bridgesToMaster ""
set_interface_property mms_tse burstOnBurstBoundariesOnly false
+set_interface_property mms_tse burstcountUnits WORDS
set_interface_property mms_tse explicitAddressSpan 0
set_interface_property mms_tse holdTime 0
-set_interface_property mms_tse isMemoryDevice false
-set_interface_property mms_tse isNonVolatileStorage false
set_interface_property mms_tse linewrapBursts false
set_interface_property mms_tse maximumPendingReadTransactions 0
-set_interface_property mms_tse printableDevice false
+set_interface_property mms_tse maximumPendingWriteTransactions 0
+set_interface_property mms_tse minimumResponseLatency 1
set_interface_property mms_tse readLatency 0
set_interface_property mms_tse readWaitTime 1
set_interface_property mms_tse setupTime 0
set_interface_property mms_tse timingUnits Cycles
+set_interface_property mms_tse transparentBridge false
+set_interface_property mms_tse waitrequestAllowance 0
set_interface_property mms_tse writeWaitTime 0
-
set_interface_property mms_tse ENABLED true
+set_interface_property mms_tse EXPORT_OF ""
+set_interface_property mms_tse PORT_NAME_MAP ""
+set_interface_property mms_tse CMSIS_SVD_VARIABLES ""
+set_interface_property mms_tse SVD_ADDRESS_GROUP ""
add_interface_port mms_tse mms_tse_address address Input 10
add_interface_port mms_tse mms_tse_write write Input 1
@@ -129,294 +134,397 @@ add_interface_port mms_tse mms_tse_read read Input 1
add_interface_port mms_tse mms_tse_writedata writedata Input 32
add_interface_port mms_tse mms_tse_readdata readdata Output 32
add_interface_port mms_tse mms_tse_waitrequest waitrequest Output 1
-# |
-# +-----------------------------------
+set_interface_assignment mms_tse embeddedsw.configuration.isFlash 0
+set_interface_assignment mms_tse embeddedsw.configuration.isMemoryDevice false
+set_interface_assignment mms_tse embeddedsw.configuration.isNonVolatileStorage false
+set_interface_assignment mms_tse embeddedsw.configuration.isPrintableDevice false
+
-# +-----------------------------------
-# | connection point mms_reg
-# |
+#
+# connection point mms_reg
+#
add_interface mms_reg avalon end
-set_interface_property mms_reg addressAlignment DYNAMIC
set_interface_property mms_reg addressUnits WORDS
set_interface_property mms_reg associatedClock mm
set_interface_property mms_reg associatedReset mm_reset
+set_interface_property mms_reg bitsPerSymbol 8
+set_interface_property mms_reg bridgedAddressOffset ""
+set_interface_property mms_reg bridgesToMaster ""
set_interface_property mms_reg burstOnBurstBoundariesOnly false
+set_interface_property mms_reg burstcountUnits WORDS
set_interface_property mms_reg explicitAddressSpan 0
set_interface_property mms_reg holdTime 0
-set_interface_property mms_reg isMemoryDevice false
-set_interface_property mms_reg isNonVolatileStorage false
set_interface_property mms_reg linewrapBursts false
set_interface_property mms_reg maximumPendingReadTransactions 0
-set_interface_property mms_reg printableDevice false
+set_interface_property mms_reg maximumPendingWriteTransactions 0
+set_interface_property mms_reg minimumResponseLatency 1
set_interface_property mms_reg readLatency 1
set_interface_property mms_reg readWaitStates 0
set_interface_property mms_reg readWaitTime 0
set_interface_property mms_reg setupTime 0
set_interface_property mms_reg timingUnits Cycles
+set_interface_property mms_reg transparentBridge false
+set_interface_property mms_reg waitrequestAllowance 0
set_interface_property mms_reg writeWaitTime 0
-
set_interface_property mms_reg ENABLED true
+set_interface_property mms_reg EXPORT_OF ""
+set_interface_property mms_reg PORT_NAME_MAP ""
+set_interface_property mms_reg CMSIS_SVD_VARIABLES ""
+set_interface_property mms_reg SVD_ADDRESS_GROUP ""
add_interface_port mms_reg mms_reg_address address Input 4
add_interface_port mms_reg mms_reg_write write Input 1
add_interface_port mms_reg mms_reg_read read Input 1
add_interface_port mms_reg mms_reg_writedata writedata Input 32
add_interface_port mms_reg mms_reg_readdata readdata Output 32
-# |
-# +-----------------------------------
+set_interface_assignment mms_reg embeddedsw.configuration.isFlash 0
+set_interface_assignment mms_reg embeddedsw.configuration.isMemoryDevice false
+set_interface_assignment mms_reg embeddedsw.configuration.isNonVolatileStorage false
+set_interface_assignment mms_reg embeddedsw.configuration.isPrintableDevice false
+
-# +-----------------------------------
-# | connection point mms_ram
-# |
+#
+# connection point mms_ram
+#
add_interface mms_ram avalon end
-set_interface_property mms_ram addressAlignment DYNAMIC
set_interface_property mms_ram addressUnits WORDS
set_interface_property mms_ram associatedClock mm
set_interface_property mms_ram associatedReset mm_reset
+set_interface_property mms_ram bitsPerSymbol 8
+set_interface_property mms_ram bridgedAddressOffset ""
+set_interface_property mms_ram bridgesToMaster ""
set_interface_property mms_ram burstOnBurstBoundariesOnly false
+set_interface_property mms_ram burstcountUnits WORDS
set_interface_property mms_ram explicitAddressSpan 0
set_interface_property mms_ram holdTime 0
-set_interface_property mms_ram isMemoryDevice false
-set_interface_property mms_ram isNonVolatileStorage false
set_interface_property mms_ram linewrapBursts false
set_interface_property mms_ram maximumPendingReadTransactions 0
-set_interface_property mms_ram printableDevice false
+set_interface_property mms_ram maximumPendingWriteTransactions 0
+set_interface_property mms_ram minimumResponseLatency 1
set_interface_property mms_ram readLatency 2
set_interface_property mms_ram readWaitStates 0
set_interface_property mms_ram readWaitTime 0
set_interface_property mms_ram setupTime 0
set_interface_property mms_ram timingUnits Cycles
+set_interface_property mms_ram transparentBridge false
+set_interface_property mms_ram waitrequestAllowance 0
set_interface_property mms_ram writeWaitTime 0
-
set_interface_property mms_ram ENABLED true
+set_interface_property mms_ram EXPORT_OF ""
+set_interface_property mms_ram PORT_NAME_MAP ""
+set_interface_property mms_ram CMSIS_SVD_VARIABLES ""
+set_interface_property mms_ram SVD_ADDRESS_GROUP ""
add_interface_port mms_ram mms_ram_address address Input 10
add_interface_port mms_ram mms_ram_write write Input 1
add_interface_port mms_ram mms_ram_read read Input 1
add_interface_port mms_ram mms_ram_writedata writedata Input 32
add_interface_port mms_ram mms_ram_readdata readdata Output 32
-# |
-# +-----------------------------------
+set_interface_assignment mms_ram embeddedsw.configuration.isFlash 0
+set_interface_assignment mms_ram embeddedsw.configuration.isMemoryDevice false
+set_interface_assignment mms_ram embeddedsw.configuration.isNonVolatileStorage false
+set_interface_assignment mms_ram embeddedsw.configuration.isPrintableDevice false
+
-# +-----------------------------------
-# | connection point interrupt
-# |
+#
+# connection point interrupt
+#
add_interface interrupt interrupt end
set_interface_property interrupt associatedAddressablePoint mms_reg
set_interface_property interrupt associatedClock mm
set_interface_property interrupt associatedReset mm_reset
-
+set_interface_property interrupt bridgedReceiverOffset ""
+set_interface_property interrupt bridgesToReceiver ""
set_interface_property interrupt ENABLED true
+set_interface_property interrupt EXPORT_OF ""
+set_interface_property interrupt PORT_NAME_MAP ""
+set_interface_property interrupt CMSIS_SVD_VARIABLES ""
+set_interface_property interrupt SVD_ADDRESS_GROUP ""
add_interface_port interrupt ins_interrupt_irq irq Output 1
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point reset
-# |
-add_interface reset conduit end
+#
+# connection point reset
+#
+add_interface reset conduit end
+set_interface_property reset associatedClock ""
+set_interface_property reset associatedReset ""
set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset coe_reset_export export Output 1
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point clk
-# |
-add_interface clk conduit end
+#
+# connection point clk
+#
+add_interface clk conduit end
+set_interface_property clk associatedClock ""
+set_interface_property clk associatedReset ""
set_interface_property clk ENABLED true
+set_interface_property clk EXPORT_OF ""
+set_interface_property clk PORT_NAME_MAP ""
+set_interface_property clk CMSIS_SVD_VARIABLES ""
+set_interface_property clk SVD_ADDRESS_GROUP ""
add_interface_port clk coe_clk_export export Output 1
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point tse_address
-# |
-add_interface tse_address conduit end
+#
+# connection point tse_address
+#
+add_interface tse_address conduit end
+set_interface_property tse_address associatedClock ""
+set_interface_property tse_address associatedReset ""
set_interface_property tse_address ENABLED true
+set_interface_property tse_address EXPORT_OF ""
+set_interface_property tse_address PORT_NAME_MAP ""
+set_interface_property tse_address CMSIS_SVD_VARIABLES ""
+set_interface_property tse_address SVD_ADDRESS_GROUP ""
add_interface_port tse_address coe_tse_address_export export Output 10
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point tse_write
-# |
-add_interface tse_write conduit end
+#
+# connection point tse_write
+#
+add_interface tse_write conduit end
+set_interface_property tse_write associatedClock ""
+set_interface_property tse_write associatedReset ""
set_interface_property tse_write ENABLED true
+set_interface_property tse_write EXPORT_OF ""
+set_interface_property tse_write PORT_NAME_MAP ""
+set_interface_property tse_write CMSIS_SVD_VARIABLES ""
+set_interface_property tse_write SVD_ADDRESS_GROUP ""
add_interface_port tse_write coe_tse_write_export export Output 1
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point tse_read
-# |
-add_interface tse_read conduit end
+#
+# connection point tse_read
+#
+add_interface tse_read conduit end
+set_interface_property tse_read associatedClock ""
+set_interface_property tse_read associatedReset ""
set_interface_property tse_read ENABLED true
+set_interface_property tse_read EXPORT_OF ""
+set_interface_property tse_read PORT_NAME_MAP ""
+set_interface_property tse_read CMSIS_SVD_VARIABLES ""
+set_interface_property tse_read SVD_ADDRESS_GROUP ""
add_interface_port tse_read coe_tse_read_export export Output 1
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point tse_writedata
-# |
-add_interface tse_writedata conduit end
+#
+# connection point tse_writedata
+#
+add_interface tse_writedata conduit end
+set_interface_property tse_writedata associatedClock ""
+set_interface_property tse_writedata associatedReset ""
set_interface_property tse_writedata ENABLED true
+set_interface_property tse_writedata EXPORT_OF ""
+set_interface_property tse_writedata PORT_NAME_MAP ""
+set_interface_property tse_writedata CMSIS_SVD_VARIABLES ""
+set_interface_property tse_writedata SVD_ADDRESS_GROUP ""
add_interface_port tse_writedata coe_tse_writedata_export export Output 32
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point tse_readdata
-# |
-add_interface tse_readdata conduit end
+#
+# connection point tse_readdata
+#
+add_interface tse_readdata conduit end
+set_interface_property tse_readdata associatedClock ""
+set_interface_property tse_readdata associatedReset ""
set_interface_property tse_readdata ENABLED true
+set_interface_property tse_readdata EXPORT_OF ""
+set_interface_property tse_readdata PORT_NAME_MAP ""
+set_interface_property tse_readdata CMSIS_SVD_VARIABLES ""
+set_interface_property tse_readdata SVD_ADDRESS_GROUP ""
add_interface_port tse_readdata coe_tse_readdata_export export Input 32
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point tse_waitrequest
-# |
-add_interface tse_waitrequest conduit end
+#
+# connection point tse_waitrequest
+#
+add_interface tse_waitrequest conduit end
+set_interface_property tse_waitrequest associatedClock ""
+set_interface_property tse_waitrequest associatedReset ""
set_interface_property tse_waitrequest ENABLED true
+set_interface_property tse_waitrequest EXPORT_OF ""
+set_interface_property tse_waitrequest PORT_NAME_MAP ""
+set_interface_property tse_waitrequest CMSIS_SVD_VARIABLES ""
+set_interface_property tse_waitrequest SVD_ADDRESS_GROUP ""
add_interface_port tse_waitrequest coe_tse_waitrequest_export export Input 1
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point reg_address
-# |
-add_interface reg_address conduit end
+#
+# connection point reg_address
+#
+add_interface reg_address conduit end
+set_interface_property reg_address associatedClock ""
+set_interface_property reg_address associatedReset ""
set_interface_property reg_address ENABLED true
+set_interface_property reg_address EXPORT_OF ""
+set_interface_property reg_address PORT_NAME_MAP ""
+set_interface_property reg_address CMSIS_SVD_VARIABLES ""
+set_interface_property reg_address SVD_ADDRESS_GROUP ""
add_interface_port reg_address coe_reg_address_export export Output 4
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point reg_write
-# |
-add_interface reg_write conduit end
+#
+# connection point reg_write
+#
+add_interface reg_write conduit end
+set_interface_property reg_write associatedClock ""
+set_interface_property reg_write associatedReset ""
set_interface_property reg_write ENABLED true
+set_interface_property reg_write EXPORT_OF ""
+set_interface_property reg_write PORT_NAME_MAP ""
+set_interface_property reg_write CMSIS_SVD_VARIABLES ""
+set_interface_property reg_write SVD_ADDRESS_GROUP ""
add_interface_port reg_write coe_reg_write_export export Output 1
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point reg_read
-# |
-add_interface reg_read conduit end
+#
+# connection point reg_read
+#
+add_interface reg_read conduit end
+set_interface_property reg_read associatedClock ""
+set_interface_property reg_read associatedReset ""
set_interface_property reg_read ENABLED true
+set_interface_property reg_read EXPORT_OF ""
+set_interface_property reg_read PORT_NAME_MAP ""
+set_interface_property reg_read CMSIS_SVD_VARIABLES ""
+set_interface_property reg_read SVD_ADDRESS_GROUP ""
add_interface_port reg_read coe_reg_read_export export Output 1
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point reg_writedata
-# |
-add_interface reg_writedata conduit end
+#
+# connection point reg_writedata
+#
+add_interface reg_writedata conduit end
+set_interface_property reg_writedata associatedClock ""
+set_interface_property reg_writedata associatedReset ""
set_interface_property reg_writedata ENABLED true
+set_interface_property reg_writedata EXPORT_OF ""
+set_interface_property reg_writedata PORT_NAME_MAP ""
+set_interface_property reg_writedata CMSIS_SVD_VARIABLES ""
+set_interface_property reg_writedata SVD_ADDRESS_GROUP ""
add_interface_port reg_writedata coe_reg_writedata_export export Output 32
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point reg_readdata
-# |
-add_interface reg_readdata conduit end
+#
+# connection point reg_readdata
+#
+add_interface reg_readdata conduit end
+set_interface_property reg_readdata associatedClock ""
+set_interface_property reg_readdata associatedReset ""
set_interface_property reg_readdata ENABLED true
+set_interface_property reg_readdata EXPORT_OF ""
+set_interface_property reg_readdata PORT_NAME_MAP ""
+set_interface_property reg_readdata CMSIS_SVD_VARIABLES ""
+set_interface_property reg_readdata SVD_ADDRESS_GROUP ""
add_interface_port reg_readdata coe_reg_readdata_export export Input 32
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point ram_address
-# |
-add_interface ram_address conduit end
+#
+# connection point ram_address
+#
+add_interface ram_address conduit end
+set_interface_property ram_address associatedClock ""
+set_interface_property ram_address associatedReset ""
set_interface_property ram_address ENABLED true
+set_interface_property ram_address EXPORT_OF ""
+set_interface_property ram_address PORT_NAME_MAP ""
+set_interface_property ram_address CMSIS_SVD_VARIABLES ""
+set_interface_property ram_address SVD_ADDRESS_GROUP ""
add_interface_port ram_address coe_ram_address_export export Output 10
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point ram_write
-# |
-add_interface ram_write conduit end
+#
+# connection point ram_write
+#
+add_interface ram_write conduit end
+set_interface_property ram_write associatedClock ""
+set_interface_property ram_write associatedReset ""
set_interface_property ram_write ENABLED true
+set_interface_property ram_write EXPORT_OF ""
+set_interface_property ram_write PORT_NAME_MAP ""
+set_interface_property ram_write CMSIS_SVD_VARIABLES ""
+set_interface_property ram_write SVD_ADDRESS_GROUP ""
add_interface_port ram_write coe_ram_write_export export Output 1
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point ram_read
-# |
-add_interface ram_read conduit end
+#
+# connection point ram_read
+#
+add_interface ram_read conduit end
+set_interface_property ram_read associatedClock ""
+set_interface_property ram_read associatedReset ""
set_interface_property ram_read ENABLED true
+set_interface_property ram_read EXPORT_OF ""
+set_interface_property ram_read PORT_NAME_MAP ""
+set_interface_property ram_read CMSIS_SVD_VARIABLES ""
+set_interface_property ram_read SVD_ADDRESS_GROUP ""
add_interface_port ram_read coe_ram_read_export export Output 1
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point ram_writedata
-# |
-add_interface ram_writedata conduit end
+#
+# connection point ram_writedata
+#
+add_interface ram_writedata conduit end
+set_interface_property ram_writedata associatedClock ""
+set_interface_property ram_writedata associatedReset ""
set_interface_property ram_writedata ENABLED true
+set_interface_property ram_writedata EXPORT_OF ""
+set_interface_property ram_writedata PORT_NAME_MAP ""
+set_interface_property ram_writedata CMSIS_SVD_VARIABLES ""
+set_interface_property ram_writedata SVD_ADDRESS_GROUP ""
add_interface_port ram_writedata coe_ram_writedata_export export Output 32
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point ram_readdata
-# |
-add_interface ram_readdata conduit end
+#
+# connection point ram_readdata
+#
+add_interface ram_readdata conduit end
+set_interface_property ram_readdata associatedClock ""
+set_interface_property ram_readdata associatedReset ""
set_interface_property ram_readdata ENABLED true
+set_interface_property ram_readdata EXPORT_OF ""
+set_interface_property ram_readdata PORT_NAME_MAP ""
+set_interface_property ram_readdata CMSIS_SVD_VARIABLES ""
+set_interface_property ram_readdata SVD_ADDRESS_GROUP ""
add_interface_port ram_readdata coe_ram_readdata_export export Input 32
-# |
-# +-----------------------------------
-# +-----------------------------------
-# | connection point irq
-# |
-add_interface irq conduit end
+#
+# connection point irq
+#
+add_interface irq conduit end
+set_interface_property irq associatedClock ""
+set_interface_property irq associatedReset ""
set_interface_property irq ENABLED true
+set_interface_property irq EXPORT_OF ""
+set_interface_property irq PORT_NAME_MAP ""
+set_interface_property irq CMSIS_SVD_VARIABLES ""
+set_interface_property irq SVD_ADDRESS_GROUP ""
add_interface_port irq coe_irq_export export Input 1
-# |
-# +-----------------------------------
+