diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd index 57f361f8b5034b6c81c1ea61a79d821b622daecd..c8721bd6fb3a58dba987952d5bfab8680666cb0f 100644 --- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd +++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd @@ -40,14 +40,16 @@ ENTITY tb_dp_bsn_align_v2 IS g_nof_streams : NATURAL := 2; -- number of input and output streams g_bsn_latency_max : NATURAL := 1; -- Maximum travel latency of a remote block in number of block periods T_blk g_bsn_latency_use_node_index : BOOLEAN := FALSE; -- FALSE for align at end node, TRUE for align at every intermediate node - g_block_size : NATURAL := 17; -- > 1, g_block_size=1 is not supported + g_block_size : NATURAL := 11; -- > 1, g_block_size=1 is not supported g_bsn_w : NATURAL := c_dp_stream_bsn_w; -- number of bits in sosi BSN g_data_w : NATURAL := 16; -- number of bits in sosi data g_filler_value : INTEGER := 0; -- output sosi data value for missing input blocks + g_pipeline_input : NATURAL := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure + g_rd_latency : NATURAL := 2; -- 1 or 2, choose 2 to ease timing closure -- TB - g_diff_delay : NATURAL := 20; - g_diff_bsn : NATURAL := 3; -- g_diff_bsn = g_bsn_latency_max can just be aligned + g_diff_delay : NATURAL := 0; + g_diff_bsn : NATURAL := 0; -- g_diff_bsn = g_bsn_latency_max can just be aligned g_nof_repeat : NATURAL := 100 -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli ); END tb_dp_bsn_align_v2; @@ -405,11 +407,15 @@ BEGIN g_nof_streams => g_nof_streams, g_bsn_latency_max => g_bsn_latency_max, g_bsn_latency_use_node_index => g_bsn_latency_use_node_index, + g_node_index_max => 31, -- limit to functional 5 bit range, instead of full 31 bit NATURAL range g_block_size => g_block_size, g_buffer_nof_blocks => c_buffer_nof_blocks, g_bsn_w => g_bsn_w, g_data_w => g_data_w, - g_filler_value => g_filler_value + g_filler_value => g_filler_value, + g_use_mm_output => TRUE, -- output via MM or via streaming DP + g_pipeline_input => g_pipeline_input, -- >= 0, choose 0 for wires, choose 1 to ease timing closure + g_rd_latency => g_rd_latency -- 1 or 2, choose 2 to ease timing closure ) PORT MAP ( dp_rst => rst, @@ -437,6 +443,7 @@ BEGIN g_step_size => 1, g_nof_data => g_block_size, g_data_w => g_data_w, + g_mm_rd_latency => g_rd_latency, g_reverse_word_order => FALSE ) PORT MAP (