diff --git a/tools/oneclick/base/modelsim_config.py b/tools/oneclick/base/modelsim_config.py index 598d4f4113d518ae89c823a6d086a0b9754738e0..8e735ac98bb4cdb5530125ca45225d96de315b61 100755 --- a/tools/oneclick/base/modelsim_config.py +++ b/tools/oneclick/base/modelsim_config.py @@ -29,7 +29,6 @@ import common as cm import hdl_config import sys -import os import os.path import argparse @@ -131,6 +130,44 @@ class ModelsimConfig(hdl_config.HdlConfig): efpn = os.path.expandvars(fpn) fp.write('%s ' % efpn) + + def simulation_configuration(self, list_mode=False): + """Prepare settings for simulation configuration. + The output format is string or list, dependent on list_mode. + Return tuple of project_sim_p_defaults, project_sim_p_search_libraries, project_sim_p_otherargs, project_sim_p_optimization. + """ + # project_sim_p_defaults + project_sim_p_defaults = 'Generics {} timing default -std_output {} -nopsl 0 +notimingchecks 0 selected_du {} -hazards 0 -sdf {} ok 1 -0in 0 -nosva 0 +pulse_r {} -absentisempty 0 -multisource_delay {} +pulse_e {} vopt_env 1 -coverage 0 -sdfnoerror 0 +plusarg {} -vital2.2b 0 -t default -memprof 0 is_vopt_flow 0 -noglitch 0 -nofileshare 0 -wlf {} -assertdebug 0 +no_pulse_msg 0 -0in_options {} -assertfile {} -sdfnowarn 0 -Lf {} -std_input {}' + + # project_sim_p_search_libraries + if list_mode: + project_sim_p_search_libraries = self.tool_dict['modelsim_search_libraries'].split() + else: + project_sim_p_search_libraries = '-L {}' + if 'modelsim_search_libraries' in self.tool_dict: + project_sim_p_search_libraries = '-L {' + for sl in self.tool_dict['modelsim_search_libraries'].split(): + project_sim_p_search_libraries += sl + project_sim_p_search_libraries += ' ' + project_sim_p_search_libraries += '}' + + # project_sim_p_otherargs + otherargs = '' + otherargs = '+nowarn8684 +nowarn8683 -quiet' + otherargs = '+nowarn8684 +nowarn8683' + otherargs = '+nowarn8684 +nowarn8683 +nowarnTFMPC +nowarnPCDPC' # nowarn on verilog IP connection mismatch warnings + if list_mode: + project_sim_p_otherargs = otherargs.split() + else: + project_sim_p_otherargs = 'OtherArgs {' + otherargs + '}' + + # project_sim_p_optimization + project_sim_p_optimization = 'is_vopt_opt_used 2' # = when 'Enable optimization' is not selected in GUI + project_sim_p_optimization = 'is_vopt_opt_used 1 voptargs {OtherVoptArgs {} timing default VoptOutFile {} -vopt_keep_delta 0 -0in 0 -fvopt {} VoptOptimize:method 1 -vopt_00 2 +vopt_notimingcheck 0 -Lfvopt {} VoptOptimize:list .vopt_opt.nb.canvas.notebook.cs.page1.cs.g.spec.listbox -Lvopt {} +vopt_acc {} VoptOptimize .vopt_opt.nb.canvas.notebook.cs.page1.cs -vopt_hazards 0 VoptOptimize:Buttons .vopt_opt.nb.canvas.notebook.cs.page1.cs.g.spec.bf 0InOptionsWgt .vopt_opt.nb.canvas.notebook.cs.page3.cs.zf.ze -0in_options {}}' # = when 'Enable optimization' is selected in GUI for full visibility + + return project_sim_p_defaults, project_sim_p_search_libraries, project_sim_p_otherargs, project_sim_p_optimization + + def create_modelsim_project_file(self, lib_names=None): """Create the Modelsim project file for all technology libraries and RTL HDL libraries. @@ -226,10 +263,10 @@ class ModelsimConfig(hdl_config.HdlConfig): if file_ext=='vhd' or file_ext=='vho' or file_ext=='vhdl': project_file_p_defaults_file_specific = project_file_p_defaults_vhdl elif file_ext=='v': - project_file_p_defaults_file_specific = project_file_p_defaults_verilog + project_file_p_defaults_file_specific = project_file_p_defaults_verilog else: - print '\nERROR - Undefined file extension in test_bench_files:', lib_name, test_bench_files[i] - sys.exit() + print '\nERROR - Undefined file extension in test_bench_files:', lib_name, test_bench_files[i] + sys.exit() fp.write('Project_File_P_%d = folder %s compile_order %d %s\n' % (offset+i, project_folders[-1], offset+i, project_file_p_defaults_hdl+' '+project_file_p_defaults_file_specific)) offset += nof_test_bench_files @@ -250,20 +287,7 @@ class ModelsimConfig(hdl_config.HdlConfig): # - simulation configurations fp.write('Project_Sim_Count = %d\n' % len(test_bench_files)) - project_sim_p_defaults = 'Generics {} timing default -std_output {} -nopsl 0 +notimingchecks 0 selected_du {} -hazards 0 -sdf {} ok 1 -0in 0 -nosva 0 +pulse_r {} -absentisempty 0 -multisource_delay {} +pulse_e {} vopt_env 1 -coverage 0 -sdfnoerror 0 +plusarg {} -vital2.2b 0 -t default -memprof 0 is_vopt_flow 0 -noglitch 0 -nofileshare 0 -wlf {} -assertdebug 0 +no_pulse_msg 0 -0in_options {} -assertfile {} -sdfnowarn 0 -Lf {} -std_input {}' - project_sim_p_search_libraries = '-L {}' - if 'modelsim_search_libraries' in self.tool_dict: - project_sim_p_search_libraries = '-L {' - for sl in self.tool_dict['modelsim_search_libraries'].split(): - project_sim_p_search_libraries += sl - project_sim_p_search_libraries += ' ' - project_sim_p_search_libraries += '}' - project_sim_p_otherargs = 'OtherArgs {}' - project_sim_p_otherargs = 'OtherArgs {+nowarn8684 +nowarn8683 -quiet}' - project_sim_p_otherargs = 'OtherArgs {+nowarn8684 +nowarn8683}' - project_sim_p_otherargs = 'OtherArgs {+nowarn8684 +nowarn8683 +nowarnTFMPC +nowarnPCDPC}' # nowarn on verilog IP connection mismatch warnings - project_sim_p_optimization = 'is_vopt_opt_used 2' # = when 'Enable optimization' is not selected in GUI - project_sim_p_optimization = 'is_vopt_opt_used 1 voptargs {OtherVoptArgs {} timing default VoptOutFile {} -vopt_keep_delta 0 -0in 0 -fvopt {} VoptOptimize:method 1 -vopt_00 2 +vopt_notimingcheck 0 -Lfvopt {} VoptOptimize:list .vopt_opt.nb.canvas.notebook.cs.page1.cs.g.spec.listbox -Lvopt {} +vopt_acc {} VoptOptimize .vopt_opt.nb.canvas.notebook.cs.page1.cs -vopt_hazards 0 VoptOptimize:Buttons .vopt_opt.nb.canvas.notebook.cs.page1.cs.g.spec.bf 0InOptionsWgt .vopt_opt.nb.canvas.notebook.cs.page3.cs.zf.ze -0in_options {}}' # = when 'Enable optimization' is selected in GUI for full visibility + project_sim_p_defaults, project_sim_p_search_libraries, project_sim_p_otherargs, project_sim_p_optimization = self.simulation_configuration() for i, fn in enumerate(test_bench_files): fName = os.path.basename(fn) tbName = os.path.splitext(fName)[0] @@ -310,6 +334,9 @@ if __name__ == '__main__': # Parse command line arguments hdl_args = hdl_config.HdlParseArgs(toolsetSelect=['unb1', 'unb2', 'unb2a']) + if hdl_args.verbosity>=1: + print '' + hdl_args.argparser.print_help() # Read the dictionary info from all HDL tool and library configuration files in the current directory and the sub directories msim = ModelsimConfig(toolRootDir=os.path.expandvars('$RADIOHDL/tools'), libFileName='hdllib.cfg', toolFileName=hdl_args.toolFileName) @@ -325,10 +352,6 @@ if __name__ == '__main__': for p in msim.libs.filePaths: print ' ', p - if hdl_args.verbosity>=1: - print '' - print 'Derive library compile order = ', msim.derive_lib_order('sim') - if hdl_args.verbosity>=2: print '' print 'get_lib_build_dirs for simulation:' @@ -354,7 +377,7 @@ if __name__ == '__main__': print '' print 'Create modelsim project files for technology %s and all HDL libraries in $%s.' % (msim.technologyNames, msim.libRootDir) msim.create_modelsim_project_file() - + if mode==1 and msim.libRootDir=='UNB': lib_name = 'unb_common' # Read compile order from existing <lib_name>.mpf