diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd index cc2945e59b51e5ffdd33d912979885bc2c3b7694..247d55a736de8c0caf054dc6ff1a9e220115eb4f 100644 --- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd +++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd @@ -43,6 +43,7 @@ USE work.dp_stream_pkg.ALL; ENTITY mmp_dp_bsn_align_v2 IS GENERIC ( + -- for dp_bsn_align_v2 g_nof_streams : NATURAL; -- number of input and output streams g_bsn_latency_max : NATURAL; -- Maximum travel latency of a remote block in number of block periods T_blk g_nof_aligners_max : NATURAL := 1; -- 1 when only align at last node, > 1 when align at every intermediate node @@ -50,6 +51,10 @@ ENTITY mmp_dp_bsn_align_v2 IS g_bsn_w : NATURAL := c_dp_stream_bsn_w; -- number of bits in sosi BSN g_data_w : NATURAL; -- number of bits in sosi data g_data_replacement_value : INTEGER := 0; -- output sosi data value for missing input blocks + g_use_mm_output : BOOLEAN := FALSE; -- output via MM or via streaming DP + g_pipeline_input : NATURAL := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure + g_rd_latency : NATURAL := 2; -- 1 or 2, choose 2 to ease timing closure + -- for mms_dp_bsn_monitor_v2 g_nof_clk_per_sync : NATURAL := 200*10**6; g_nof_input_bsn_monitors : NATURAL := 0; g_use_bsn_output_monitor : BOOLEAN := FALSE @@ -59,8 +64,8 @@ ENTITY mmp_dp_bsn_align_v2 IS mm_rst : IN STD_LOGIC; mm_clk : IN STD_LOGIC; - reg_copi : IN t_mem_copi; - reg_cipo : OUT t_mem_cipo; + reg_bsn_align_copi : IN t_mem_copi; + reg_bsn_align_cipo : OUT t_mem_cipo; reg_input_monitor_copi : IN t_mem_copi; reg_input_monitor_cipo : OUT t_mem_cipo; @@ -69,18 +74,21 @@ ENTITY mmp_dp_bsn_align_v2 IS reg_output_monitor_cipo : OUT t_mem_cipo; -- Streaming clock domain - dp_rst : IN STD_LOGIC; - dp_clk : IN STD_LOGIC; + dp_rst : IN STD_LOGIC; + dp_clk : IN STD_LOGIC; - node_index : IN NATURAL := 0; -- only used when g_nof_aligners_max > 1 + node_index : IN NATURAL RANGE 0 TO g_nof_aligners_max-1 := 0; -- only used when g_nof_aligners_max > 1 -- Streaming input - in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); + in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); - -- Output via local MM in dp_clk domain - mm_copi : IN t_mem_copi; -- read access to output block, all output streams share same mm_copi - mm_cipo_arr : OUT t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0); - mm_sosi : OUT t_dp_sosi -- streaming information that signals that an output block can be read + -- Output via local MM interface in dp_clk domain, when g_use_mm_output = TRUE. + mm_sosi : OUT t_dp_sosi; -- streaming information that signals that an output block can be read + mm_copi : IN t_mem_copi := c_mem_copi_rst; -- read access to output block, all output streams share same mm_copi + mm_cipo_arr : OUT t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0); + + -- Output via streaming DP interface, when g_use_mm_output = TRUE. + out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) ); END mmp_dp_bsn_align_v2; @@ -118,8 +126,8 @@ BEGIN st_clk => dp_clk, -- Memory Mapped Slave in mm_clk domain - sla_in => reg_copi, - sla_out => reg_cipo, + sla_in => reg_bsn_align_copi, + sla_out => reg_bsn_align_cipo, -- MM registers in st_clk domain reg_wr_arr => OPEN, @@ -200,7 +208,10 @@ BEGIN g_block_size => g_block_size, g_bsn_w => g_bsn_w, g_data_w => g_data_w, - g_data_replacement_value => g_data_replacement_value + g_data_replacement_value => g_data_replacement_value, + g_use_mm_output => g_use_mm_output, + g_pipeline_input => g_pipeline_input, + g_rd_latency => g_rd_latency ) PORT MAP ( dp_rst => dp_rst, @@ -211,9 +222,11 @@ BEGIN -- Streaming input in_sosi_arr => in_sosi_arr, -- Output via local MM in dp_clk domain + mm_sosi => mm_sosi, mm_copi => mm_copi, mm_cipo_arr => mm_cipo_arr, - mm_sosi => mm_sosi + -- Output via streaming DP interface, when g_use_mm_output = TRUE. + out_sosi_arr => out_sosi_arr ); mm_sosi <= mm_sosi_arr(0);