diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg index 68048b09ca51ee3bdd1be86fb24a382f38b0475d..d5b3b9e323a186e920a597242b22ab491e577e2c 100644 --- a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg +++ b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg @@ -12,12 +12,16 @@ synth_files = test_bench_files = tb/vhdl/tb_lofar2_unb2b_adc.vhd + tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd [modelsim_project_file] modelsim_copy_files = + tb/wave/wave_multichannel.do . + tb/wave/readregs.do . [quartus_project_file] quartus_copy_files = + quartus . diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/jesd.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/jesd.ip new file mode 100644 index 0000000000000000000000000000000000000000..1afabbdcdc3c218a81adca51cb6b48e5b32e3aae --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/jesd.ip @@ -0,0 +1,3276 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>jesd</spirit:library> + <spirit:name>jesd204_0</spirit:name> + <spirit:version>18.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>alldev_lane_aligned</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>alldev_lane_aligned</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>csr_cf</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csr_cf</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>csr_cs</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csr_cs</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>csr_f</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csr_f</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>csr_hd</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csr_hd</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>csr_k</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csr_k</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>csr_l</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csr_l</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>csr_lane_powerdown</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csr_lane_powerdown</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>csr_m</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csr_m</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>csr_n</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csr_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>csr_np</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csr_np</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>csr_rx_testmode</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csr_rx_testmode</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>csr_s</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csr_s</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>dev_lane_aligned</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>dev_lane_aligned</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>dev_sync_n</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>dev_sync_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>jesd204_rx_avs</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_avs_chipselect</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_avs_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_avs_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_avs_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>waitrequest</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_avs_waitrequest</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_avs_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_avs_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">1024</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">jesd204_rx_avs_clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">jesd204_rx_avs_rst_n</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>jesd204_rx_avs_clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_avs_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>jesd204_rx_avs_rst_n</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_avs_rst_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">jesd204_rx_avs_clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>jesd204_rx_dlb_data</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_dlb_data</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>jesd204_rx_dlb_data_valid</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_dlb_data_valid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>jesd204_rx_dlb_disperr</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_dlb_disperr</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>jesd204_rx_dlb_errdetect</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_dlb_errdetect</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>jesd204_rx_dlb_kchar_data</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_dlb_kchar_data</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>jesd204_rx_frame_error</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_frame_error</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>jesd204_rx_int</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="interrupt" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>irq</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_int</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedAddressablePoint</spirit:name> + <spirit:displayName>Associated addressable interface</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">jesd.jesd204_rx_avs</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">jesd204_rx_avs_clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">jesd204_rx_avs_rst_n</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedReceiverOffset</spirit:name> + <spirit:displayName>Bridged receiver offset</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bridgedReceiverOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToReceiver</spirit:name> + <spirit:displayName>Bridges to receiver</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToReceiver"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>irqScheme</spirit:name> + <spirit:displayName>Interrupt scheme</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="irqScheme">NONE</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>jesd204_rx_link</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon_streaming" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>data</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_link_data</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>valid</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_link_valid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>ready</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>jesd204_rx_link_ready</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">rxlink_clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">rxlink_rst_n</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>beatsPerCycle</spirit:name> + <spirit:displayName>Beats Per Cycle</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="beatsPerCycle">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dataBitsPerSymbol</spirit:name> + <spirit:displayName>Data bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="dataBitsPerSymbol">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>emptyWithinPacket</spirit:name> + <spirit:displayName>emptyWithinPacket</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="emptyWithinPacket">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>errorDescriptor</spirit:name> + <spirit:displayName>Error descriptor</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="errorDescriptor"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>firstSymbolInHighOrderBits</spirit:name> + <spirit:displayName>First Symbol In High-Order Bits</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="firstSymbolInHighOrderBits">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>highOrderSymbolAtMSB</spirit:name> + <spirit:displayName>highOrderSymbolAtMSB</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="highOrderSymbolAtMSB">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maxChannel</spirit:name> + <spirit:displayName>Maximum channel</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maxChannel">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>packetDescription</spirit:name> + <spirit:displayName>Packet description </spirit:displayName> + <spirit:value spirit:format="string" spirit:id="packetDescription"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readyAllowance</spirit:name> + <spirit:displayName>Ready allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readyAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readyLatency</spirit:name> + <spirit:displayName>Ready latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readyLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>symbolsPerBeat</spirit:name> + <spirit:displayName>Symbols per beat </spirit:displayName> + <spirit:value spirit:format="long" spirit:id="symbolsPerBeat">1</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>pll_ref_clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>pll_ref_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>rx_analogreset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>rx_analogreset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>rx_analogreset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>rx_cal_busy</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>rx_cal_busy</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>rx_cal_busy</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>rx_digitalreset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>rx_digitalreset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>rx_digitalreset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>rx_islockedtodata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>rx_is_lockedtodata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>rx_islockedtodata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>rx_serial_data</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>rx_serial_data</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>rx_serial_data</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>rxlink_clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>rxlink_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>rxlink_rst_n</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>rxlink_rst_n_reset_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">rxlink_clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>rxphy_clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>rxphy_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>sof</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>sof</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>somf</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>somf</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>sysref</spirit:name> + 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Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ui.blockdiagram.direction</spirit:name> + <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>altera_jesd204</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>alldev_lane_aligned</spirit:name> + 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<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csr_s</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>4</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>dev_lane_aligned</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>dev_sync_n</spirit:name> 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<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>jesd204_rx_avs_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>jesd204_rx_avs_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>jesd204_rx_avs_waitrequest</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>jesd204_rx_avs_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>jesd204_rx_avs_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + 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<spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>jesd204_rx_link_valid</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>jesd204_rx_link_ready</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>pll_ref_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_analogreset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_cal_busy</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_digitalreset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_islockedtodata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_serial_data</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rxlink_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rxlink_rst_n_reset_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rxphy_clk</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sof</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>3</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>somf</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>3</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sysref</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>jesd</spirit:library> + <spirit:name>altera_jesd204</spirit:name> + <spirit:version>18.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>wrapper_opt</spirit:name> + <spirit:displayName>Jesd204b wrapper</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="wrapper_opt">base_phy</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>sdc_constraint</spirit:name> + <spirit:displayName>Set constraint for sdc</spirit:displayName> + <spirit:value spirit:format="float" spirit:id="sdc_constraint">1.0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>DEVICE_FAMILY</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="DEVICE_FAMILY">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>part_trait_dp</spirit:name> + <spirit:displayName>Device Part</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="part_trait_dp">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>DATA_PATH</spirit:name> + <spirit:displayName>Data path</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="DATA_PATH">RX</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SUBCLASSV</spirit:name> + <spirit:displayName>Jesd204b subclass</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="SUBCLASSV">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lane_rate</spirit:name> + <spirit:displayName>Data rate</spirit:displayName> + <spirit:value spirit:format="float" spirit:id="lane_rate">4000.0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PCS_CONFIG</spirit:name> + <spirit:displayName>PCS Option</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="PCS_CONFIG">JESD_PCS_CFG1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>pll_type</spirit:name> + <spirit:displayName>PLL Type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="pll_type">CMU</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonded_mode</spirit:name> + <spirit:displayName>Bonding Mode </spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonded_mode">bonded</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>REFCLK_FREQ</spirit:name> + <spirit:displayName>PLL/CDR Reference Clock Frequency</spirit:displayName> + <spirit:value spirit:format="float" spirit:id="REFCLK_FREQ">200.0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>gui_analog_voltage</spirit:name> + <spirit:displayName>VCCR_GXB and VCCT_GXB supply voltage for the Transceiver</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="gui_analog_voltage">1_0V</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitrev_en</spirit:name> + <spirit:displayName>Enable Bit reversal and Byte reversal</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="bitrev_en">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>pll_reconfig_enable</spirit:name> + <spirit:displayName>Enable Transceiver Dynamic Reconfiguration</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="pll_reconfig_enable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>rcfg_jtag_enable</spirit:name> + <spirit:displayName>Enable Altera Debug Master Endpoint</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="rcfg_jtag_enable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>rcfg_shared</spirit:name> + <spirit:displayName>Share Reconfiguration Interface</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="rcfg_shared">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>rcfg_enable_split_interface</spirit:name> + <spirit:displayName>Provide Separate Reconfiguration Interface for Each Channel</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="rcfg_enable_split_interface">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>set_capability_reg_enable</spirit:name> + <spirit:displayName>Enable Capability Registers</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="set_capability_reg_enable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>set_user_identifier</spirit:name> + <spirit:displayName>Set user-defined IP identifier</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="set_user_identifier">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>set_csr_soft_logic_enable</spirit:name> + <spirit:displayName>Enable Control and Status Registers</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="set_csr_soft_logic_enable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>set_prbs_soft_logic_enable</spirit:name> + <spirit:displayName>Enable PRBS Soft Accumulators</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="set_prbs_soft_logic_enable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>L</spirit:name> + <spirit:displayName>Lanes per converter device (L)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="L">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>M</spirit:name> + <spirit:displayName>Converters per device (M)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="M">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>GUI_EN_CFG_F</spirit:name> + <spirit:displayName>Enable manual F configuration</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="GUI_EN_CFG_F">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>GUI_CFG_F</spirit:name> + <spirit:displayName>Octets per frame (F)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="GUI_CFG_F">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>F</spirit:name> + <spirit:displayName>Octets per frame (F)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="F">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>N</spirit:name> + <spirit:displayName>Converter resolution (N)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="N">14</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>N_PRIME</spirit:name> + <spirit:displayName>Transmitted bits per sample (N')</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="N_PRIME">16</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>S</spirit:name> + <spirit:displayName>Samples per converter per frame (S)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="S">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>K</spirit:name> + <spirit:displayName>Frames per multiframe (K)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="K">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SCR</spirit:name> + <spirit:displayName>Enable scramble (SCR)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="SCR">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CS</spirit:name> + <spirit:displayName>Control Bits (CS)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="CS">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CF</spirit:name> + <spirit:displayName>Control Words (CF)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="CF">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HD</spirit:name> + <spirit:displayName>High Density user data format (HD)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="HD">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ECC_EN</spirit:name> + <spirit:displayName>Enable Error Code Correction (ECC_EN)</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="ECC_EN">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>DLB_TEST</spirit:name> + <spirit:displayName>Enable Digital Loop Back Test (DLB_TEST)</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="DLB_TEST">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHADJ</spirit:name> + <spirit:displayName>Phase adjustment request (PHADJ)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="PHADJ">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADJCNT</spirit:name> + <spirit:displayName>Adjustment resolution step count (ADJCNT)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="ADJCNT">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADJDIR</spirit:name> + <spirit:displayName>Direction of adjustment (ADJDIR)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="ADJDIR">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>OPTIMIZE</spirit:name> + <spirit:displayName>CSR Programmability</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="OPTIMIZE">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>DID</spirit:name> + <spirit:displayName>Device ID</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="DID">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BID</spirit:name> + <spirit:displayName>Bank ID</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="BID">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>LID0</spirit:name> + <spirit:displayName>Lane0 ID</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="LID0">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FCHK0</spirit:name> + <spirit:displayName>Lane0 checksum</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="FCHK0">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>LID1</spirit:name> + <spirit:displayName>Lane1 ID</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="LID1">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FCHK1</spirit:name> + <spirit:displayName>Lane1 checksum</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="FCHK1">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>LID2</spirit:name> + <spirit:displayName>Lane2 ID</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="LID2">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FCHK2</spirit:name> + <spirit:displayName>Lane2 checksum</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="FCHK2">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>LID3</spirit:name> + <spirit:displayName>Lane3 ID</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="LID3">3</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FCHK3</spirit:name> + <spirit:displayName>Lane3 checksum</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="FCHK3">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>LID4</spirit:name> + <spirit:displayName>Lane4 ID</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="LID4">4</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FCHK4</spirit:name> + <spirit:displayName>Lane4 checksum</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="FCHK4">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>LID5</spirit:name> + <spirit:displayName>Lane5 ID</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="LID5">5</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FCHK5</spirit:name> + <spirit:displayName>Lane5 checksum</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="FCHK5">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>LID6</spirit:name> + <spirit:displayName>Lane6 ID</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="LID6">6</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FCHK6</spirit:name> + <spirit:displayName>Lane6 checksum</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="FCHK6">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>LID7</spirit:name> + <spirit:displayName>Lane7 ID</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="LID7">7</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FCHK7</spirit:name> + <spirit:displayName>Lane7 checksum</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="FCHK7">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>d_refclk_freq</spirit:name> + <spirit:displayName>PLL/CDR Reference Clock Frequency</spirit:displayName> + <spirit:value spirit:format="float" spirit:id="d_refclk_freq">200.0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>JESDV</spirit:name> + <spirit:displayName>JESDV</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="JESDV">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PMA_WIDTH</spirit:name> + <spirit:displayName>PMA_WIDTH</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="PMA_WIDTH">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SER_SIZE</spirit:name> + <spirit:displayName>SER_SIZE</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="SER_SIZE">4</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FK</spirit:name> + <spirit:displayName>FK</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="FK">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RES1</spirit:name> + <spirit:displayName>RES1</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="RES1">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RES2</spirit:name> + <spirit:displayName>RES2</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="RES2">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BIT_REVERSAL</spirit:name> + <spirit:displayName>BIT_REVERSAL</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="BIT_REVERSAL">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BYTE_REVERSAL</spirit:name> + <spirit:displayName>BYTE_REVERSAL</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="BYTE_REVERSAL">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ALIGNMENT_PATTERN</spirit:name> + <spirit:displayName>ALIGNMENT_PATTERN</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="ALIGNMENT_PATTERN">658812</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PULSE_WIDTH</spirit:name> + <spirit:displayName>PULSE_WIDTH</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="PULSE_WIDTH">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>LS_FIFO_DEPTH</spirit:name> + <spirit:displayName>LS_FIFO_DEPTH</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="LS_FIFO_DEPTH">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>LS_FIFO_WIDTHU</spirit:name> + <spirit:displayName>LS_FIFO_WIDTHU</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="LS_FIFO_WIDTHU">5</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>UNUSED_TX_PARALLEL_WIDTH</spirit:name> + <spirit:displayName>UNUSED_TX_PARALLEL_WIDTH</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="UNUSED_TX_PARALLEL_WIDTH">92</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>UNUSED_RX_PARALLEL_WIDTH</spirit:name> + <spirit:displayName>UNUSED_RX_PARALLEL_WIDTH</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="UNUSED_RX_PARALLEL_WIDTH">72</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>XCVR_PLL_LOCKED_WIDTH</spirit:name> + <spirit:displayName>XCVR_PLL_LOCKED_WIDTH</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="XCVR_PLL_LOCKED_WIDTH">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RECONFIG_ADDRESS_WIDTH</spirit:name> + <spirit:displayName>RECONFIG_ADDRESS_WIDTH</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="RECONFIG_ADDRESS_WIDTH">10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>DEPTH_PIPE</spirit:name> + <spirit:displayName>Pipeline stages for link_clk domain reset signal</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="DEPTH_PIPE">3</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>xcvr_ip</spirit:name> + <spirit:displayName>xcvr_ip</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="xcvr_ip">ltile</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>die_types</spirit:name> + <spirit:displayName>die_types</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="die_types"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>die_revisions</spirit:name> + <spirit:displayName>die_revisions</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="die_revisions"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>support_c1</spirit:name> + <spirit:displayName>support_c1</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="support_c1">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>support_c2</spirit:name> + <spirit:displayName>support_c2</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="support_c2">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>support_c3</spirit:name> + <spirit:displayName>support_c3</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="support_c3">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>crete_tile_status</spirit:name> + <spirit:displayName>Transceiver Tile</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="crete_tile_status">ltile</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>gui_user_crete_tile</spirit:name> + <spirit:displayName>Transceiver Tile</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="gui_user_crete_tile">etile</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>TEST_COMPONENTS_EN</spirit:name> + <spirit:displayName>Add Test Components</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="TEST_COMPONENTS_EN">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>TERMINATE_RECONFIG_EN</spirit:name> + <spirit:displayName>Terminate Reconfig Signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="TERMINATE_RECONFIG_EN">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ED_TYPE</spirit:name> + <spirit:displayName>Select Design</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ED_TYPE">DATAPATH</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ED_FILESET_SIM</spirit:name> + <spirit:displayName>Simulation</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="ED_FILESET_SIM">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ED_FILESET_SYNTH</spirit:name> + <spirit:displayName>Synthesis</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="ED_FILESET_SYNTH">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ED_HDL_FORMAT_SIM</spirit:name> + <spirit:displayName>HDL Format</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ED_HDL_FORMAT_SIM">VHDL</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ED_SIM_PAT_TESTMODE</spirit:name> + <spirit:displayName>Test pattern</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ED_SIM_PAT_TESTMODE">PRBS_7</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ED_HDL_FORMAT_SYNTH</spirit:name> + <spirit:displayName>HDL Format</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ED_HDL_FORMAT_SYNTH">VERILOG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ED_DEV_KIT</spirit:name> + <spirit:displayName>Select Board</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ED_DEV_KIT">NONE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>GUI_ED_DEV_KIT</spirit:name> + <spirit:displayName>Select Board</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="GUI_ED_DEV_KIT">None</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ED_SINGLE_REFCLK</spirit:name> + <spirit:displayName>Single reference clock (Advanced users only. Not recommended.)</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="ED_SINGLE_REFCLK">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ED_3WIRE_SPI</spirit:name> + <spirit:displayName>Generate 3-wire SPI module</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="ED_3WIRE_SPI">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SELECT_CUSTOM_DEVICE</spirit:name> + <spirit:displayName>Change Target Device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="SELECT_CUSTOM_DEVICE">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_DEVICE</spirit:name> + <spirit:displayName>Auto DEVICE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_DEVICE">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_DEVICE_SPEEDGRADE</spirit:name> + <spirit:displayName>Auto DEVICE_SPEEDGRADE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_DEVICE_SPEEDGRADE">1</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ + element jesd204_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>jesd204_rx_avs</key> + <value> + <connectionPointName>jesd204_rx_avs</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='jesd204_rx_avs' start='0x0' end='0x400' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>10</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="alldev_lane_aligned" altera:internal="jesd204_0.alldev_lane_aligned" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="alldev_lane_aligned" altera:internal="alldev_lane_aligned"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="csr_cf" altera:internal="jesd204_0.csr_cf" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="csr_cf" altera:internal="csr_cf"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="csr_cs" altera:internal="jesd204_0.csr_cs" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="csr_cs" altera:internal="csr_cs"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="csr_f" altera:internal="jesd204_0.csr_f" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="csr_f" altera:internal="csr_f"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="csr_hd" altera:internal="jesd204_0.csr_hd" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="csr_hd" altera:internal="csr_hd"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="csr_k" altera:internal="jesd204_0.csr_k" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="csr_k" altera:internal="csr_k"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="csr_l" altera:internal="jesd204_0.csr_l" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="csr_l" altera:internal="csr_l"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="csr_lane_powerdown" altera:internal="jesd204_0.csr_lane_powerdown" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="csr_lane_powerdown" altera:internal="csr_lane_powerdown"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="csr_m" altera:internal="jesd204_0.csr_m" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="csr_m" altera:internal="csr_m"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="csr_n" altera:internal="jesd204_0.csr_n" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="csr_n" altera:internal="csr_n"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="csr_np" altera:internal="jesd204_0.csr_np" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="csr_np" altera:internal="csr_np"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="csr_rx_testmode" altera:internal="jesd204_0.csr_rx_testmode" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="csr_rx_testmode" altera:internal="csr_rx_testmode"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="csr_s" altera:internal="jesd204_0.csr_s" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="csr_s" altera:internal="csr_s"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="csr_tx_testmode" altera:internal="jesd204_0.csr_tx_testmode"></altera:interface_mapping> + <altera:interface_mapping altera:name="csr_tx_testpattern_a" altera:internal="jesd204_0.csr_tx_testpattern_a"></altera:interface_mapping> + <altera:interface_mapping altera:name="csr_tx_testpattern_b" altera:internal="jesd204_0.csr_tx_testpattern_b"></altera:interface_mapping> + <altera:interface_mapping altera:name="csr_tx_testpattern_c" altera:internal="jesd204_0.csr_tx_testpattern_c"></altera:interface_mapping> + <altera:interface_mapping altera:name="csr_tx_testpattern_d" altera:internal="jesd204_0.csr_tx_testpattern_d"></altera:interface_mapping> + <altera:interface_mapping altera:name="dev_lane_aligned" altera:internal="jesd204_0.dev_lane_aligned" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="dev_lane_aligned" altera:internal="dev_lane_aligned"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="dev_sync_n" altera:internal="jesd204_0.dev_sync_n" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="dev_sync_n" altera:internal="dev_sync_n"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_rx_avs" altera:internal="jesd204_0.jesd204_rx_avs" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="jesd204_rx_avs_address" altera:internal="jesd204_rx_avs_address"></altera:port_mapping> + <altera:port_mapping altera:name="jesd204_rx_avs_chipselect" altera:internal="jesd204_rx_avs_chipselect"></altera:port_mapping> + <altera:port_mapping altera:name="jesd204_rx_avs_read" altera:internal="jesd204_rx_avs_read"></altera:port_mapping> + <altera:port_mapping altera:name="jesd204_rx_avs_readdata" altera:internal="jesd204_rx_avs_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="jesd204_rx_avs_waitrequest" altera:internal="jesd204_rx_avs_waitrequest"></altera:port_mapping> + <altera:port_mapping altera:name="jesd204_rx_avs_write" altera:internal="jesd204_rx_avs_write"></altera:port_mapping> + <altera:port_mapping altera:name="jesd204_rx_avs_writedata" altera:internal="jesd204_rx_avs_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_rx_avs_clk" altera:internal="jesd204_0.jesd204_rx_avs_clk" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="jesd204_rx_avs_clk" altera:internal="jesd204_rx_avs_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_rx_avs_rst_n" altera:internal="jesd204_0.jesd204_rx_avs_rst_n" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="jesd204_rx_avs_rst_n" altera:internal="jesd204_rx_avs_rst_n"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_rx_dlb_data" altera:internal="jesd204_0.jesd204_rx_dlb_data" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="jesd204_rx_dlb_data" altera:internal="jesd204_rx_dlb_data"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_rx_dlb_data_valid" altera:internal="jesd204_0.jesd204_rx_dlb_data_valid" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="jesd204_rx_dlb_data_valid" altera:internal="jesd204_rx_dlb_data_valid"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_rx_dlb_disperr" altera:internal="jesd204_0.jesd204_rx_dlb_disperr" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="jesd204_rx_dlb_disperr" altera:internal="jesd204_rx_dlb_disperr"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_rx_dlb_errdetect" altera:internal="jesd204_0.jesd204_rx_dlb_errdetect" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="jesd204_rx_dlb_errdetect" altera:internal="jesd204_rx_dlb_errdetect"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_rx_dlb_kchar_data" altera:internal="jesd204_0.jesd204_rx_dlb_kchar_data" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="jesd204_rx_dlb_kchar_data" altera:internal="jesd204_rx_dlb_kchar_data"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_rx_frame_error" altera:internal="jesd204_0.jesd204_rx_frame_error" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="jesd204_rx_frame_error" altera:internal="jesd204_rx_frame_error"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_rx_int" altera:internal="jesd204_0.jesd204_rx_int" altera:type="interrupt" altera:dir="end"> + <altera:port_mapping altera:name="jesd204_rx_int" altera:internal="jesd204_rx_int"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_rx_link" altera:internal="jesd204_0.jesd204_rx_link" altera:type="avalon_streaming" altera:dir="start"> + <altera:port_mapping altera:name="jesd204_rx_link_data" altera:internal="jesd204_rx_link_data"></altera:port_mapping> + <altera:port_mapping altera:name="jesd204_rx_link_ready" altera:internal="jesd204_rx_link_ready"></altera:port_mapping> + <altera:port_mapping altera:name="jesd204_rx_link_valid" altera:internal="jesd204_rx_link_valid"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_tx_avs" altera:internal="jesd204_0.jesd204_tx_avs"></altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_tx_avs_clk" altera:internal="jesd204_0.jesd204_tx_avs_clk"></altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_tx_avs_rst_n" altera:internal="jesd204_0.jesd204_tx_avs_rst_n"></altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_tx_dlb_data" altera:internal="jesd204_0.jesd204_tx_dlb_data"></altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_tx_dlb_kchar_data" altera:internal="jesd204_0.jesd204_tx_dlb_kchar_data"></altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_tx_frame_error" altera:internal="jesd204_0.jesd204_tx_frame_error"></altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_tx_frame_ready" altera:internal="jesd204_0.jesd204_tx_frame_ready"></altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_tx_int" altera:internal="jesd204_0.jesd204_tx_int"></altera:interface_mapping> + <altera:interface_mapping altera:name="jesd204_tx_link" altera:internal="jesd204_0.jesd204_tx_link"></altera:interface_mapping> + <altera:interface_mapping altera:name="mdev_sync_n" altera:internal="jesd204_0.mdev_sync_n"></altera:interface_mapping> + <altera:interface_mapping altera:name="pll_locked" altera:internal="jesd204_0.pll_locked"></altera:interface_mapping> + <altera:interface_mapping altera:name="pll_ref_clk" altera:internal="jesd204_0.pll_ref_clk" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="pll_ref_clk" altera:internal="pll_ref_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="rx_analogreset" altera:internal="jesd204_0.rx_analogreset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="rx_analogreset" altera:internal="rx_analogreset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="rx_cal_busy" altera:internal="jesd204_0.rx_cal_busy" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="rx_cal_busy" altera:internal="rx_cal_busy"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="rx_csr_cf" altera:internal="jesd204_0.rx_csr_cf"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_csr_cs" altera:internal="jesd204_0.rx_csr_cs"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_csr_f" altera:internal="jesd204_0.rx_csr_f"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_csr_hd" altera:internal="jesd204_0.rx_csr_hd"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_csr_k" altera:internal="jesd204_0.rx_csr_k"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_csr_l" altera:internal="jesd204_0.rx_csr_l"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_csr_lane_powerdown" altera:internal="jesd204_0.rx_csr_lane_powerdown"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_csr_m" altera:internal="jesd204_0.rx_csr_m"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_csr_n" altera:internal="jesd204_0.rx_csr_n"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_csr_np" altera:internal="jesd204_0.rx_csr_np"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_csr_s" altera:internal="jesd204_0.rx_csr_s"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_dev_sync_n" altera:internal="jesd204_0.rx_dev_sync_n"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_digitalreset" altera:internal="jesd204_0.rx_digitalreset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="rx_digitalreset" altera:internal="rx_digitalreset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="rx_islockedtodata" altera:internal="jesd204_0.rx_islockedtodata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="rx_islockedtodata" altera:internal="rx_islockedtodata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="rx_pll_ref_clk" altera:internal="jesd204_0.rx_pll_ref_clk"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_serial_data" altera:internal="jesd204_0.rx_serial_data" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="rx_serial_data" altera:internal="rx_serial_data"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="rx_seriallpbken" altera:internal="jesd204_0.rx_seriallpbken"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_sof" altera:internal="jesd204_0.rx_sof"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_somf" altera:internal="jesd204_0.rx_somf"></altera:interface_mapping> + <altera:interface_mapping altera:name="rx_sysref" altera:internal="jesd204_0.rx_sysref"></altera:interface_mapping> + <altera:interface_mapping altera:name="rxlink_clk" altera:internal="jesd204_0.rxlink_clk" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="rxlink_clk" altera:internal="rxlink_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="rxlink_rst_n" altera:internal="jesd204_0.rxlink_rst_n" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="rxlink_rst_n_reset_n" altera:internal="rxlink_rst_n_reset_n"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="rxphy_clk" altera:internal="jesd204_0.rxphy_clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="rxphy_clk" altera:internal="rxphy_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="sof" altera:internal="jesd204_0.sof" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="sof" altera:internal="sof"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="somf" altera:internal="jesd204_0.somf" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="somf" altera:internal="somf"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="sync_n" altera:internal="jesd204_0.sync_n"></altera:interface_mapping> + <altera:interface_mapping altera:name="sysref" altera:internal="jesd204_0.sysref" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="sysref" altera:internal="sysref"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="tx_analogreset" altera:internal="jesd204_0.tx_analogreset"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_bonding_clocks_ch0" altera:internal="jesd204_0.tx_bonding_clocks_ch0"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_bonding_clocks_ch1" altera:internal="jesd204_0.tx_bonding_clocks_ch1"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_cal_busy" altera:internal="jesd204_0.tx_cal_busy"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_csr_cf" altera:internal="jesd204_0.tx_csr_cf"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_csr_cs" altera:internal="jesd204_0.tx_csr_cs"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_csr_f" altera:internal="jesd204_0.tx_csr_f"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_csr_hd" altera:internal="jesd204_0.tx_csr_hd"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_csr_k" altera:internal="jesd204_0.tx_csr_k"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_csr_l" altera:internal="jesd204_0.tx_csr_l"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_csr_lane_powerdown" altera:internal="jesd204_0.tx_csr_lane_powerdown"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_csr_m" altera:internal="jesd204_0.tx_csr_m"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_csr_n" altera:internal="jesd204_0.tx_csr_n"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_csr_np" altera:internal="jesd204_0.tx_csr_np"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_csr_s" altera:internal="jesd204_0.tx_csr_s"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_dev_sync_n" altera:internal="jesd204_0.tx_dev_sync_n"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_digitalreset" altera:internal="jesd204_0.tx_digitalreset"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_serial_data" altera:internal="jesd204_0.tx_serial_data"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_somf" altera:internal="jesd204_0.tx_somf"></altera:interface_mapping> + <altera:interface_mapping altera:name="tx_sysref" altera:internal="jesd204_0.tx_sysref"></altera:interface_mapping> + <altera:interface_mapping altera:name="txlink_clk" altera:internal="jesd204_0.txlink_clk"></altera:interface_mapping> + <altera:interface_mapping altera:name="txlink_rst_n" altera:internal="jesd204_0.txlink_rst_n"></altera:interface_mapping> + <altera:interface_mapping altera:name="txphy_clk" altera:internal="jesd204_0.txphy_clk"></altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip new file mode 100644 index 0000000000000000000000000000000000000000..9f3b374bc4341d879dcbd61a6bb3e7a6c56c47aa --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_avs_common_mm_0</spirit:library> + <spirit:name>avs_common_mm_0</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">16384</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>11</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>11</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_avs_common_mm_0</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">12</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>12</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + 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<vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>16384</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + 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<key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>14</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="avs_common_mm_0.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="avs_common_mm_0.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="avs_common_mm_0.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="avs_common_mm_0.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="avs_common_mm_0.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="avs_common_mm_0.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="avs_common_mm_0.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="avs_common_mm_0.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="avs_common_mm_0.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="avs_common_mm_0.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip new file mode 100644 index 0000000000000000000000000000000000000000..c7155e411e87a31691363c096d2991a1516daccb --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_avs_common_mm_1</spirit:library> + <spirit:name>avs_common_mm_1</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">524288</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + 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<spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + 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<spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>17</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + 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<key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x80000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>19</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="avs_common_mm_1.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="avs_common_mm_1.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="avs_common_mm_1.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="avs_common_mm_1.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="avs_common_mm_1.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="avs_common_mm_1.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="avs_common_mm_1.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="avs_common_mm_1.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="avs_common_mm_1.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="avs_common_mm_1.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip new file mode 100644 index 0000000000000000000000000000000000000000..4e21d21150344b6e7ed0b700bb14822d13c23b0b --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip @@ -0,0 +1,3746 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_avs_eth_0</spirit:library> + <spirit:name>avs_eth_0</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>interrupt</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="interrupt" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>irq</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ins_interrupt_irq</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedAddressablePoint</spirit:name> + <spirit:displayName>Associated addressable interface</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">qsys_unb2c_minimal_avs_eth_0.mms_reg</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">mm</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">mm_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedReceiverOffset</spirit:name> + <spirit:displayName>Bridged receiver offset</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bridgedReceiverOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToReceiver</spirit:name> + <spirit:displayName>Bridges to receiver</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToReceiver"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>irqScheme</spirit:name> + <spirit:displayName>Interrupt scheme</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="irqScheme">NONE</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>irq</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_irq_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mm</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_mm_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mm_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_mm_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">mm</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mms_ram</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_ram_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_ram_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_ram_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_ram_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_ram_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">4096</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">mm</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">mm_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mms_reg</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_reg_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_reg_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_reg_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_reg_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_reg_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">mm</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">mm_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mms_tse</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_tse_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_tse_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_tse_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_tse_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_tse_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>waitrequest</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_tse_waitrequest</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">4096</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">mm</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">mm_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>ram_address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_ram_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + 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<spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>ram_readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_ram_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + 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</spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>ram_writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_ram_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reg_address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reg_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reg_read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reg_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reg_readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reg_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reg_write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reg_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reg_writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reg_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>tse_address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_tse_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>tse_read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_tse_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>tse_readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_tse_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>tse_waitrequest</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_tse_waitrequest_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>tse_write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_tse_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>tse_writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_tse_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs2_eth_coe</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_mm_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + 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<key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>2</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mms_reg</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>mms_reg_address</name> + <role>address</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_reg_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_reg_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_reg_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_reg_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>64</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>associatedReset</key> + <value>mm_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mms_tse</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>mms_tse_address</name> + <role>address</role> + <direction>Input</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_tse_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_tse_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_tse_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_tse_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_tse_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4096</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>associatedReset</key> + <value>mm_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_waitrequest</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_waitrequest_export</name> + <role>export</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mms_ram</key> + <value> + <connectionPointName>mms_ram</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mms_ram' start='0x0' end='0x1000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>12</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>mms_reg</key> + <value> + <connectionPointName>mms_reg</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mms_reg' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>mms_tse</key> + <value> + <connectionPointName>mms_tse</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mms_tse' start='0x0' end='0x1000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>12</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="clk" altera:internal="avs_eth_0.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="interrupt" altera:internal="avs_eth_0.interrupt" altera:type="interrupt" altera:dir="end"> + <altera:port_mapping altera:name="ins_interrupt_irq" altera:internal="ins_interrupt_irq"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="irq" altera:internal="avs_eth_0.irq" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_irq_export" altera:internal="coe_irq_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mm" altera:internal="avs_eth_0.mm" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_mm_clk" altera:internal="csi_mm_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mm_reset" altera:internal="avs_eth_0.mm_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_mm_reset" altera:internal="csi_mm_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mms_ram" altera:internal="avs_eth_0.mms_ram" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="mms_ram_address" altera:internal="mms_ram_address"></altera:port_mapping> + <altera:port_mapping altera:name="mms_ram_read" altera:internal="mms_ram_read"></altera:port_mapping> + <altera:port_mapping altera:name="mms_ram_readdata" altera:internal="mms_ram_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="mms_ram_write" altera:internal="mms_ram_write"></altera:port_mapping> + <altera:port_mapping altera:name="mms_ram_writedata" altera:internal="mms_ram_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mms_reg" altera:internal="avs_eth_0.mms_reg" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="mms_reg_address" altera:internal="mms_reg_address"></altera:port_mapping> + <altera:port_mapping altera:name="mms_reg_read" altera:internal="mms_reg_read"></altera:port_mapping> + <altera:port_mapping altera:name="mms_reg_readdata" altera:internal="mms_reg_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="mms_reg_write" altera:internal="mms_reg_write"></altera:port_mapping> + <altera:port_mapping altera:name="mms_reg_writedata" altera:internal="mms_reg_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mms_tse" altera:internal="avs_eth_0.mms_tse" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="mms_tse_address" altera:internal="mms_tse_address"></altera:port_mapping> + <altera:port_mapping altera:name="mms_tse_read" altera:internal="mms_tse_read"></altera:port_mapping> + <altera:port_mapping altera:name="mms_tse_readdata" altera:internal="mms_tse_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="mms_tse_waitrequest" altera:internal="mms_tse_waitrequest"></altera:port_mapping> + <altera:port_mapping altera:name="mms_tse_write" altera:internal="mms_tse_write"></altera:port_mapping> + <altera:port_mapping altera:name="mms_tse_writedata" altera:internal="mms_tse_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="ram_address" altera:internal="avs_eth_0.ram_address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_ram_address_export" altera:internal="coe_ram_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="ram_read" altera:internal="avs_eth_0.ram_read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_ram_read_export" altera:internal="coe_ram_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="ram_readdata" altera:internal="avs_eth_0.ram_readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_ram_readdata_export" altera:internal="coe_ram_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="ram_write" altera:internal="avs_eth_0.ram_write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_ram_write_export" altera:internal="coe_ram_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="ram_writedata" altera:internal="avs_eth_0.ram_writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_ram_writedata_export" altera:internal="coe_ram_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reg_address" altera:internal="avs_eth_0.reg_address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reg_address_export" altera:internal="coe_reg_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reg_read" altera:internal="avs_eth_0.reg_read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reg_read_export" altera:internal="coe_reg_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reg_readdata" altera:internal="avs_eth_0.reg_readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reg_readdata_export" altera:internal="coe_reg_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reg_write" altera:internal="avs_eth_0.reg_write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reg_write_export" altera:internal="coe_reg_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reg_writedata" altera:internal="avs_eth_0.reg_writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reg_writedata_export" altera:internal="coe_reg_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="avs_eth_0.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="tse_address" altera:internal="avs_eth_0.tse_address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_tse_address_export" altera:internal="coe_tse_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="tse_read" altera:internal="avs_eth_0.tse_read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_tse_read_export" altera:internal="coe_tse_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="tse_readdata" altera:internal="avs_eth_0.tse_readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_tse_readdata_export" altera:internal="coe_tse_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="tse_waitrequest" altera:internal="avs_eth_0.tse_waitrequest" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_tse_waitrequest_export" altera:internal="coe_tse_waitrequest_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="tse_write" altera:internal="avs_eth_0.tse_write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_tse_write_export" altera:internal="coe_tse_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="tse_writedata" altera:internal="avs_eth_0.tse_writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_tse_writedata_export" altera:internal="coe_tse_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>true</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip new file mode 100644 index 0000000000000000000000000000000000000000..1c5f2f856736d4dd45540a8c65ed3bfb8dca0ebc --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip @@ -0,0 +1,506 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>Altera Corporation</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_clk_0</spirit:library> + <spirit:name>clk_0</spirit:name> + <spirit:version>18.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>clk_out</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedDirectClock</spirit:name> + <spirit:displayName>Associated direct clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedDirectClock">clk_in</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>clockRateKnown</spirit:name> + <spirit:displayName>Clock rate known</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="clockRateKnown">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk_in</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>in_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>qsys.ui.export_name</spirit:name> + <spirit:value spirit:format="string" spirit:id="qsys.ui.export_name">clk</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk_in_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">NONE</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>qsys.ui.export_name</spirit:name> + <spirit:value spirit:format="string" spirit:id="qsys.ui.export_name">reset</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>reset_n_out</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedDirectReset</spirit:name> + <spirit:displayName>Associated direct reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedDirectReset">clk_in_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedResetSinks</spirit:name> + <spirit:displayName>Associated reset sinks</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedResetSinks">clk_in_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">NONE</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>clock_source</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>in_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>clk_out</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset_n_out</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>Altera Corporation</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_clk_0</spirit:library> + <spirit:name>clock_source</spirit:name> + <spirit:version>18.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockFrequency</spirit:name> + <spirit:displayName>Clock frequency</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockFrequency">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>clockFrequencyKnown</spirit:name> + <spirit:displayName>Clock frequency is known</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="clockFrequencyKnown">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>inputClockFrequency</spirit:name> + <spirit:displayName>inputClockFrequency</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="inputClockFrequency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>resetSynchronousEdges</spirit:name> + <spirit:displayName>Reset synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="resetSynchronousEdges">NONE</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>100000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>100000000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>clk_in</key> + <value> + <connectionPointName>clk_in</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="clk" altera:internal="clk_0.clk" altera:type="clock" altera:dir="start"> + <altera:port_mapping altera:name="clk_out" altera:internal="clk_out"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk_in" altera:internal="clk_0.clk_in" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="in_clk" altera:internal="in_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk_in_reset" altera:internal="clk_0.clk_in_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="reset_n" altera:internal="reset_n"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk_reset" altera:internal="clk_0.clk_reset" altera:type="reset" altera:dir="start"> + <altera:port_mapping altera:name="reset_n_out" altera:internal="reset_n_out"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip new file mode 100644 index 0000000000000000000000000000000000000000..c8bc4033c2bf8ff667b777c725560189d68e366d --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip @@ -0,0 +1,3605 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_cpu_0</spirit:library> + <spirit:name>cpu_0</spirit:name> + <spirit:version>18.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>custom_instruction_master</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="nios_custom_instruction" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readra</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>dummy_ci_port</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>CIName</spirit:name> + <spirit:displayName>CIName</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="CIName"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressWidth</spirit:name> + <spirit:displayName>addressWidth</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressWidth">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>clockCycle</spirit:name> + <spirit:displayName>Clock cycles</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="clockCycle">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>enabled</spirit:name> + <spirit:displayName>enabled</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maxAddressWidth</spirit:name> + <spirit:displayName>maxAddressWidth</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maxAddressWidth">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>opcodeExtension</spirit:name> + <spirit:displayName>opcodeExtension</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="opcodeExtension">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>sharedCombinationalAndMulticycle</spirit:name> + <spirit:displayName>sharedCombinationalAndMulticycle</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="sharedCombinationalAndMulticycle">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>data_master</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>d_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>byteenable</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>d_byteenable</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>d_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>d_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>waitrequest</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>d_waitrequest</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>d_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>d_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>debugaccess</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_debugaccess_to_roms</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>adaptsTo</spirit:name> + <spirit:displayName>Adapts to</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="adaptsTo"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">SYMBOLS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dBSBigEndian</spirit:name> + <spirit:displayName>dBS big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="dBSBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>doStreamReads</spirit:name> + <spirit:displayName>Use flow control for read transfers</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="doStreamReads">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>doStreamWrites</spirit:name> + <spirit:displayName>Use flow control for write transfers</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="doStreamWrites">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isAsynchronous</spirit:name> + <spirit:displayName>Is asynchronous</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isAsynchronous">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Is big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isReadable</spirit:name> + <spirit:displayName>Is readable</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isReadable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isWriteable</spirit:name> + <spirit:displayName>Is writeable</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isWriteable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maxAddressWidth</spirit:name> + <spirit:displayName>Maximum address width</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maxAddressWidth">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>debug.providesServices</spirit:name> + <spirit:value spirit:format="string" spirit:id="debug.providesServices">master</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>debug_mem_slave</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>byteenable</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_byteenable</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>debugaccess</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_debugaccess</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>waitrequest</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_waitrequest</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">2048</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.hideDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.hideDevice">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>qsys.ui.connect</spirit:name> + <spirit:value spirit:format="string" spirit:id="qsys.ui.connect">instruction_master,data_master</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>debug_reset_request</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_reset_request</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedDirectReset</spirit:name> + <spirit:displayName>Associated direct reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedDirectReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedResetSinks</spirit:name> + <spirit:displayName>Associated reset sinks</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedResetSinks">none</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>instruction_master</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>i_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>i_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>i_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>waitrequest</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>i_waitrequest</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>adaptsTo</spirit:name> + <spirit:displayName>Adapts to</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="adaptsTo"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">SYMBOLS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dBSBigEndian</spirit:name> + <spirit:displayName>dBS big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="dBSBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>doStreamReads</spirit:name> + <spirit:displayName>Use flow control for read transfers</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="doStreamReads">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>doStreamWrites</spirit:name> + <spirit:displayName>Use flow control for write transfers</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="doStreamWrites">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isAsynchronous</spirit:name> + <spirit:displayName>Is asynchronous</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isAsynchronous">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Is big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isReadable</spirit:name> + <spirit:displayName>Is readable</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isReadable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isWriteable</spirit:name> + <spirit:displayName>Is writeable</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isWriteable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maxAddressWidth</spirit:name> + <spirit:displayName>Maximum address width</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maxAddressWidth">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>irq</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="interrupt" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + 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<spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>dummy_ci_port</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>d_address</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + 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<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>d_readdata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>d_waitrequest</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>d_write</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>d_writedata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>debug_mem_slave_debugaccess_to_roms</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>debug_mem_slave_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>8</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>debug_mem_slave_byteenable</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>3</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + 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+ </spirit:port> + <spirit:port> + <spirit:name>debug_mem_slave_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>debug_reset_request</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>i_address</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>17</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>i_read</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>i_readdata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>i_waitrequest</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>irq</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset_req</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_cpu_0</spirit:library> + <spirit:name>altera_nios2_gen2</spirit:name> + <spirit:version>18.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>tmr_enabled</spirit:name> + <spirit:displayName>Nios II Triple Mode Redundancy</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="tmr_enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_disable_tmr_inj</spirit:name> + <spirit:displayName>Disabled TMR Error Injection Port</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_disable_tmr_inj">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_showUnpublishedSettings</spirit:name> + <spirit:displayName>Show Unpublished Settings</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_showUnpublishedSettings">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_showInternalSettings</spirit:name> + <spirit:displayName>Show Internal Verification Settings</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_showInternalSettings">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_preciseIllegalMemAccessException</spirit:name> + <spirit:displayName>Misaligned memory access</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_preciseIllegalMemAccessException">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_exportPCB</spirit:name> + <spirit:displayName>setting_exportPCB</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_exportPCB">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_exportdebuginfo</spirit:name> + <spirit:displayName>Export Instruction Execution States</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_exportdebuginfo">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_clearXBitsLDNonBypass</spirit:name> + <spirit:displayName>Clear X data bits</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_clearXBitsLDNonBypass">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_bigEndian</spirit:name> + <spirit:displayName>setting_bigEndian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_bigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_export_large_RAMs</spirit:name> + <spirit:displayName>Export Large RAMs</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_export_large_RAMs">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_asic_enabled</spirit:name> + <spirit:displayName>ASIC enabled</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_asic_enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>register_file_por</spirit:name> + <spirit:displayName>Register File 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+ <spirit:name>setting_oci_version</spirit:name> + <spirit:displayName>Nios II OCI Version</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setting_oci_version">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_fast_register_read</spirit:name> + <spirit:displayName>Fast Register Read</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_fast_register_read">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_exportHostDebugPort</spirit:name> + <spirit:displayName>Export Debug Host Slave</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_exportHostDebugPort">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_oci_export_jtag_signals</spirit:name> + <spirit:displayName>Export JTAG signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_oci_export_jtag_signals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_avalonDebugPortPresent</spirit:name> + <spirit:displayName>Avalon Debug Port Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_avalonDebugPortPresent">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_alwaysEncrypt</spirit:name> + <spirit:displayName>Always encrypt</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_alwaysEncrypt">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>io_regionbase</spirit:name> + <spirit:displayName>Base Address</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="io_regionbase">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>io_regionsize</spirit:name> + <spirit:displayName>Size</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="io_regionsize">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_support31bitdcachebypass</spirit:name> + <spirit:displayName>Use most-significant address bit in processor to bypass data cache</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_support31bitdcachebypass">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_activateTrace</spirit:name> + <spirit:displayName>Generate trace file during RTL simulation</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_activateTrace">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_allow_break_inst</spirit:name> + <spirit:displayName>Allow Break instructions</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_allow_break_inst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_activateTestEndChecker</spirit:name> + <spirit:displayName>Activate test end checker</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_activateTestEndChecker">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_ecc_sim_test_ports</spirit:name> + <spirit:displayName>Enable ECC simulation test ports</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_ecc_sim_test_ports">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_disableocitrace</spirit:name> + <spirit:displayName>Disable comptr generation</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_disableocitrace">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_activateMonitors</spirit:name> + <spirit:displayName>Activate monitors</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_activateMonitors">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_HDLSimCachesCleared</spirit:name> + <spirit:displayName>HDL simulation caches cleared</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_HDLSimCachesCleared">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_HBreakTest</spirit:name> + <spirit:displayName>Add HBreak Request port</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_HBreakTest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_breakslaveoveride</spirit:name> + <spirit:displayName>Manually assign break slave</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_breakslaveoveride">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mpu_useLimit</spirit:name> + <spirit:displayName>Use Limit for region range</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="mpu_useLimit">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mpu_enabled</spirit:name> + <spirit:displayName>Include MPU</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="mpu_enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_enabled</spirit:name> + <spirit:displayName>Include MMU</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="mmu_enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_autoAssignTlbPtrSz</spirit:name> + <spirit:displayName>Optimize TLB entries base on device family</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="mmu_autoAssignTlbPtrSz">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>cpuReset</spirit:name> + <spirit:displayName>Include cpu_resetrequest and cpu_resettaken signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="cpuReset">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>resetrequest_enabled</spirit:name> + <spirit:displayName>Include reset_req signal for OCI RAM and Multi-Cycle Custom Instructions</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="resetrequest_enabled">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_removeRAMinit</spirit:name> + <spirit:displayName>Remove RAM Initialization</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_removeRAMinit">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_tmr_output_disable</spirit:name> + <spirit:displayName>Create a signal to disable TMR outputs</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_tmr_output_disable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_shadowRegisterSets</spirit:name> + <spirit:displayName>Number of shadow register sets (0-63)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setting_shadowRegisterSets">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mpu_numOfInstRegion</spirit:name> + <spirit:displayName> Number of instruction regions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mpu_numOfInstRegion">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mpu_numOfDataRegion</spirit:name> + <spirit:displayName> Number of data regions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mpu_numOfDataRegion">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_TLBMissExcOffset</spirit:name> + <spirit:displayName>Fast TLB Miss Exception vector offset</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mmu_TLBMissExcOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>resetOffset</spirit:name> + <spirit:displayName>Reset vector offset</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="resetOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>exceptionOffset</spirit:name> + <spirit:displayName>Exception vector offset</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="exceptionOffset">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>cpuID</spirit:name> + <spirit:displayName>CPUID control register value</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="cpuID">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>breakOffset</spirit:name> + <spirit:displayName>Break vector offset</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="breakOffset">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>userDefinedSettings</spirit:name> + <spirit:displayName>User Defined Settings</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="userDefinedSettings"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>tracefilename</spirit:name> + <spirit:displayName>Trace File Name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="tracefilename"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>resetSlave</spirit:name> + <spirit:displayName>Reset vector memory</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="resetSlave">onchip_memory2_0.s1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_TLBMissExcSlave</spirit:name> + <spirit:displayName>Fast TLB Miss Exception vector memory</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="mmu_TLBMissExcSlave">None</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>exceptionSlave</spirit:name> + <spirit:displayName>Exception vector memory</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="exceptionSlave">onchip_memory2_0.s1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>breakSlave</spirit:name> + <spirit:displayName>Break vector memory</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="breakSlave">None</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_interruptControllerType</spirit:name> + <spirit:displayName>Interrupt controller</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="setting_interruptControllerType">Internal</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_branchpredictiontype</spirit:name> + <spirit:displayName>Branch prediction type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="setting_branchpredictiontype">Dynamic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_bhtPtrSz</spirit:name> + <spirit:displayName> Number of entries (2-bits wide)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setting_bhtPtrSz">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>cpuArchRev</spirit:name> + <spirit:displayName>Architecture Revision</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="cpuArchRev">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>stratix_dspblock_shift_mul</spirit:name> + <spirit:displayName>stratix_dspblock_shift_mul</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="stratix_dspblock_shift_mul">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>shifterType</spirit:name> + <spirit:displayName>shifterType</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="shifterType">medium_le_shift</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>multiplierType</spirit:name> + <spirit:displayName>multiplierType</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="multiplierType">no_mul</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mul_shift_choice</spirit:name> + <spirit:displayName>Multiply/Shift/Rotate Hardware</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mul_shift_choice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mul_32_impl</spirit:name> + <spirit:displayName>Multiply Implementation</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mul_32_impl">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mul_64_impl</spirit:name> + <spirit:displayName>Multiply Extended Implementation</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mul_64_impl">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>shift_rot_impl</spirit:name> + <spirit:displayName>Shift/Rotate Implementation</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="shift_rot_impl">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dividerType</spirit:name> + <spirit:displayName>Divide Hardware</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="dividerType">no_div</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mpu_minInstRegionSize</spirit:name> + <spirit:displayName> Minimum instruction region size</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mpu_minInstRegionSize">12</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mpu_minDataRegionSize</spirit:name> + <spirit:displayName> Minimum data region size</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mpu_minDataRegionSize">12</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_uitlbNumEntries</spirit:name> + <spirit:displayName> Micro ITLB entries</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mmu_uitlbNumEntries">4</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_udtlbNumEntries</spirit:name> + <spirit:displayName> Micro DTLB entries</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mmu_udtlbNumEntries">6</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_tlbPtrSz</spirit:name> + <spirit:displayName> TLB entries</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mmu_tlbPtrSz">7</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_tlbNumWays</spirit:name> + <spirit:displayName> TLB Set-Associativity</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mmu_tlbNumWays">16</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_processIDNumBits</spirit:name> + <spirit:displayName> Process ID (PID) bits</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mmu_processIDNumBits">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>impl</spirit:name> + <spirit:displayName>Nios II Core</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="impl">Tiny</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>icache_size</spirit:name> + <spirit:displayName>Size</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="icache_size">4096</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>fa_cache_line</spirit:name> + <spirit:displayName>Number of Cache Lines</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="fa_cache_line">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>fa_cache_linesize</spirit:name> + <spirit:displayName>Line Size</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="fa_cache_linesize">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>icache_tagramBlockType</spirit:name> + <spirit:displayName>Tag RAM block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="icache_tagramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>icache_ramBlockType</spirit:name> + <spirit:displayName>Data RAM block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="icache_ramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>icache_numTCIM</spirit:name> + <spirit:displayName>Number of tightly coupled instruction master ports</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="icache_numTCIM">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>icache_burstType</spirit:name> + <spirit:displayName>Add burstcount signal to instruction_master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="icache_burstType">None</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dcache_bursts</spirit:name> + <spirit:displayName>Add burstcount signal to data_master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="dcache_bursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dcache_victim_buf_impl</spirit:name> + <spirit:displayName>Victim buffer implementation</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="dcache_victim_buf_impl">ram</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dcache_size</spirit:name> + <spirit:displayName>Size</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="dcache_size">2048</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dcache_tagramBlockType</spirit:name> + <spirit:displayName>Tag RAM block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="dcache_tagramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dcache_ramBlockType</spirit:name> + <spirit:displayName>Data RAM block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="dcache_ramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dcache_numTCDM</spirit:name> + <spirit:displayName>Number of tightly coupled data master ports</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="dcache_numTCDM">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_exportvectors</spirit:name> + <spirit:displayName>Export Vectors</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_exportvectors">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_usedesignware</spirit:name> + <spirit:displayName>Use Designware Components</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_usedesignware">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_ecc_present</spirit:name> + <spirit:displayName>ECC Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_ecc_present">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_ic_ecc_present</spirit:name> + <spirit:displayName>Instruction Cache ECC Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_ic_ecc_present">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_rf_ecc_present</spirit:name> + <spirit:displayName>Register File ECC Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_rf_ecc_present">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_mmu_ecc_present</spirit:name> + <spirit:displayName>MMU ECC Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_mmu_ecc_present">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_dc_ecc_present</spirit:name> + <spirit:displayName>Data Cache ECC Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_dc_ecc_present">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_itcm_ecc_present</spirit:name> + <spirit:displayName>Instruction TCM ECC Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_itcm_ecc_present">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_dtcm_ecc_present</spirit:name> + <spirit:displayName>Data TCM ECC Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_dtcm_ecc_present">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>regfile_ramBlockType</spirit:name> + <spirit:displayName>RAM block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="regfile_ramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ocimem_ramBlockType</spirit:name> + <spirit:displayName>RAM block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ocimem_ramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ocimem_ramInit</spirit:name> + <spirit:displayName>Initialized OCI RAM</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="ocimem_ramInit">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_ramBlockType</spirit:name> + <spirit:displayName> MMU RAM block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="mmu_ramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bht_ramBlockType</spirit:name> + <spirit:displayName>BHT RAM Block Type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bht_ramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>cdx_enabled</spirit:name> + <spirit:displayName>CDX (Code Density eXtension) Instructions</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="cdx_enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mpx_enabled</spirit:name> + <spirit:displayName>mpx_enabled</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="mpx_enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_enabled</spirit:name> + <spirit:displayName>Include JTAG Debug</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="debug_enabled">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_triggerArming</spirit:name> + <spirit:displayName>Trigger Arming</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="debug_triggerArming">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_debugReqSignals</spirit:name> + <spirit:displayName>Include debugreq and debugack Signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="debug_debugReqSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_assignJtagInstanceID</spirit:name> + <spirit:displayName>Assign JTAG Instance ID for debug core manually</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="debug_assignJtagInstanceID">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_jtagInstanceID</spirit:name> + <spirit:displayName>JTAG Instance ID value</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="debug_jtagInstanceID">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_OCIOnchipTrace</spirit:name> + <spirit:displayName>Onchip Trace Frame Size</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="debug_OCIOnchipTrace">_128</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_hwbreakpoint</spirit:name> + <spirit:displayName>Hardware Breakpoints</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="debug_hwbreakpoint">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_datatrigger</spirit:name> + <spirit:displayName>Data Triggers</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="debug_datatrigger">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_traceType</spirit:name> + <spirit:displayName>Trace Types</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="debug_traceType">none</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_traceStorage</spirit:name> + <spirit:displayName>Trace Storage</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="debug_traceStorage">onchip_trace</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>master_addr_map</spirit:name> + <spirit:displayName>Manually Set Master Base Address and Size</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="master_addr_map">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>instruction_master_paddr_base</spirit:name> + <spirit:displayName>Instruction Master Base Address</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="instruction_master_paddr_base">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>instruction_master_paddr_size</spirit:name> + <spirit:displayName>Instruction Master Size</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="instruction_master_paddr_size">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>flash_instruction_master_paddr_base</spirit:name> + <spirit:displayName>Flash Instruction Master Base Address</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="flash_instruction_master_paddr_base">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>flash_instruction_master_paddr_size</spirit:name> + <spirit:displayName>Flash Instruction Master Size</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="flash_instruction_master_paddr_size">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>data_master_paddr_base</spirit:name> + <spirit:displayName>Data Master Base Address</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="data_master_paddr_base">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>data_master_paddr_size</spirit:name> + <spirit:displayName>Data Master Size</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="data_master_paddr_size">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>tightly_coupled_instruction_master_0_paddr_base</spirit:name> + <spirit:displayName>Tightly coupled Instruction Master 0 Base Address</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="tightly_coupled_instruction_master_0_paddr_base">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>tightly_coupled_instruction_master_0_paddr_size</spirit:name> + <spirit:displayName>Tightly coupled Instruction Master 0 Size</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="tightly_coupled_instruction_master_0_paddr_size">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>tightly_coupled_instruction_master_1_paddr_base</spirit:name> + <spirit:displayName>Tightly coupled Instruction Master 1 Base Address</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="tightly_coupled_instruction_master_1_paddr_base">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>tightly_coupled_instruction_master_1_paddr_size</spirit:name> + <spirit:displayName>Tightly coupled Instruction Master 1 Size</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="tightly_coupled_instruction_master_1_paddr_size">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>tightly_coupled_instruction_master_2_paddr_base</spirit:name> + <spirit:displayName>Tightly coupled Instruction Master 2 Base Address</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="tightly_coupled_instruction_master_2_paddr_base">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>tightly_coupled_instruction_master_2_paddr_size</spirit:name> + <spirit:displayName>Tightly coupled Instruction Master 2 Size</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="tightly_coupled_instruction_master_2_paddr_size">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>tightly_coupled_instruction_master_3_paddr_base</spirit:name> + <spirit:displayName>Tightly coupled Instruction Master 3 Base Address</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="tightly_coupled_instruction_master_3_paddr_base">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + 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HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_BLOCK 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MISSING_PAD_INFO 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QHD_INCREMENTAL_TIMING_CLOSURE_SUPPORT 1 HAS_QHD_IP_REUSE_INTEGRATION_SUPPORT 1 HAS_QHD_PARTITIONS_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_REVC_IO 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMPLIFIED_PARTIAL_RECONFIG_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SIP_TILE_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_DQS_IN_BUFFER_REDUCTION 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 IS_SDM_LITE 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LUTRAM_DATA_IN_FF_MUST_BE_HIPI 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MAC_NEGATE_SUPPORT_DISABLED 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_CLOCK_REGION 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PCF 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 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SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_PW0 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_MIN_CORNER_DMF_GENERATION 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_TIMING_CLOSURE_CORNERS 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORT_UIB 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 U2B2_SUPPORT_NOT_READY 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DETAILED_REDTAX_WITH_DSPF_ROUTING_MODELS 0 USES_DEV 1 USES_DSPF_ROUTING_MODELS 0 USES_DSP_FROM_PREVIOUS_FAMILY 0 USES_ESTIMATED_TIMING 0 USES_EXTRACTION_CORNERS_WITH_DSPF_ROUTING_MODELS 0 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PARASITIC_LOADS_WITH_DSPF_ROUTING_MODELS 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_RAM_FROM_PREVIOUS_FAMILY 0 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_TIMING_ROUTING_DELAYS 0 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SDM_CONFIGURATION 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 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<spirit:value spirit:format="long" spirit:id="AUTO_CLK_RESET_DOMAIN">1</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>debug.hostConnection</spirit:name> + <spirit:value spirit:format="string" spirit:id="debug.hostConnection">type jtag id 70:34|110:135</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.BIG_ENDIAN</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BIG_ENDIAN">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.BREAK_ADDR</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BREAK_ADDR">0x00003820</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</spirit:name> + <spirit:value spirit:format="string" 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<connectionPointName>custom_instruction_master</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CUSTOM_INSTRUCTION_SLAVES</key> + <value></value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>data_master</key> + <value> + <connectionPointName>data_master</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='jesd204b.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_data_buffer_jesd.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_diag_data_buffer_jesd.mem' start='0x100000' end='0x140000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>21</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>debug_mem_slave</key> + <value> + <connectionPointName>debug_mem_slave</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='debug_mem_slave' start='0x0' end='0x800' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>11</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>instruction_master</key> + <value> + <connectionPointName>instruction_master</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>18</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>irq</key> + <value> + <connectionPointName>irq</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>INTERRUPTS_USED</key> + <value>7</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="clk" altera:internal="cpu_0.clk" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="custom_instruction_master" altera:internal="cpu_0.custom_instruction_master" altera:type="nios_custom_instruction" altera:dir="start"> + <altera:port_mapping altera:name="dummy_ci_port" altera:internal="dummy_ci_port"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="data_master" altera:internal="cpu_0.data_master" altera:type="avalon" altera:dir="start"> + <altera:port_mapping altera:name="d_address" altera:internal="d_address"></altera:port_mapping> + <altera:port_mapping altera:name="d_byteenable" altera:internal="d_byteenable"></altera:port_mapping> + <altera:port_mapping altera:name="d_read" altera:internal="d_read"></altera:port_mapping> + <altera:port_mapping altera:name="d_readdata" altera:internal="d_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="d_waitrequest" altera:internal="d_waitrequest"></altera:port_mapping> + <altera:port_mapping altera:name="d_write" altera:internal="d_write"></altera:port_mapping> + <altera:port_mapping altera:name="d_writedata" altera:internal="d_writedata"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_debugaccess_to_roms" altera:internal="debug_mem_slave_debugaccess_to_roms"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="debug_mem_slave" altera:internal="cpu_0.debug_mem_slave" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="debug_mem_slave_address" altera:internal="debug_mem_slave_address"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_byteenable" altera:internal="debug_mem_slave_byteenable"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_debugaccess" altera:internal="debug_mem_slave_debugaccess"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_read" altera:internal="debug_mem_slave_read"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_readdata" altera:internal="debug_mem_slave_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_waitrequest" altera:internal="debug_mem_slave_waitrequest"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_write" altera:internal="debug_mem_slave_write"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_writedata" altera:internal="debug_mem_slave_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="debug_reset_request" altera:internal="cpu_0.debug_reset_request" altera:type="reset" altera:dir="start"> + <altera:port_mapping altera:name="debug_reset_request" altera:internal="debug_reset_request"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="instruction_master" altera:internal="cpu_0.instruction_master" altera:type="avalon" altera:dir="start"> + <altera:port_mapping altera:name="i_address" altera:internal="i_address"></altera:port_mapping> + <altera:port_mapping altera:name="i_read" altera:internal="i_read"></altera:port_mapping> + <altera:port_mapping altera:name="i_readdata" altera:internal="i_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="i_waitrequest" altera:internal="i_waitrequest"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="irq" altera:internal="cpu_0.irq" altera:type="interrupt" altera:dir="start"> + <altera:port_mapping altera:name="irq" altera:internal="irq"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="cpu_0.reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="reset_n" altera:internal="reset_n"></altera:port_mapping> + <altera:port_mapping altera:name="reset_req" altera:internal="reset_req"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip new file mode 100644 index 0000000000000000000000000000000000000000..2c36bb55a9b3d00fdbd3ca724aede8dc93ba5297 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip @@ -0,0 +1,1241 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_jtag_uart_0</spirit:library> + <spirit:name>jtag_uart_0</spirit:name> + <spirit:version>18.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>avalon_jtag_slave</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_chipselect</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_read_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_write_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>waitrequest</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_waitrequest</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">NATIVE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">1</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>irq</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="interrupt" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>irq</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_irq</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedAddressablePoint</spirit:name> + <spirit:displayName>Associated addressable interface</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">qsys_unb2c_minimal_jtag_uart_0.avalon_jtag_slave</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedReceiverOffset</spirit:name> + <spirit:displayName>Bridged receiver offset</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bridgedReceiverOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToReceiver</spirit:name> + <spirit:displayName>Bridges to receiver</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToReceiver"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>irqScheme</spirit:name> + <spirit:displayName>Interrupt scheme</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="irqScheme">NONE</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>rst_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>altera_avalon_jtag_uart</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rst_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_chipselect</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_read_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_write_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_waitrequest</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_irq</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_jtag_uart_0</spirit:library> + <spirit:name>altera_avalon_jtag_uart</spirit:name> + <spirit:version>18.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>allowMultipleConnections</spirit:name> + <spirit:displayName>Allow multiple connections to Avalon JTAG slave</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="allowMultipleConnections">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hubInstanceID</spirit:name> + <spirit:displayName>hubInstanceID</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="hubInstanceID">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readBufferDepth</spirit:name> + <spirit:displayName>Buffer depth (bytes)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readBufferDepth">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readIRQThreshold</spirit:name> + <spirit:displayName>IRQ threshold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readIRQThreshold">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>simInputCharacterStream</spirit:name> + <spirit:displayName>Contents</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="simInputCharacterStream"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>simInteractiveOptions</spirit:name> + <spirit:displayName>Options</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>useRegistersForReadBuffer</spirit:name> + <spirit:displayName>Construct using registers instead of memory blocks</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="useRegistersForReadBuffer">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>useRegistersForWriteBuffer</spirit:name> + <spirit:displayName>Construct using registers instead of memory blocks</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="useRegistersForWriteBuffer">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>useRelativePathForSimFile</spirit:name> + <spirit:displayName>useRelativePathForSimFile</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="useRelativePathForSimFile">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeBufferDepth</spirit:name> + <spirit:displayName>Buffer depth (bytes)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeBufferDepth">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeIRQThreshold</spirit:name> + <spirit:displayName>IRQ threshold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeIRQThreshold">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>clkFreq</spirit:name> + <spirit:displayName>clkFreq</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clkFreq">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>avalonSpec</spirit:name> + <spirit:displayName>avalonSpec</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="avalonSpec">2.0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>legacySignalAllow</spirit:name> + <spirit:displayName>legacySignalAllow</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="legacySignalAllow">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>enableInteractiveInput</spirit:name> + <spirit:displayName>enableInteractiveInput</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="enableInteractiveInput">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>enableInteractiveOutput</spirit:name> + <spirit:displayName>enableInteractiveOutput</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="enableInteractiveOutput">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.READ_DEPTH</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.READ_DEPTH">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.READ_THRESHOLD</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.READ_THRESHOLD">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.WRITE_DEPTH</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.WRITE_DEPTH">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.WRITE_THRESHOLD</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.WRITE_THRESHOLD">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.compatible</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.compatible">altr,juart-1.0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.group</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.group">serial</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.name</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.name">juart</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.vendor</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.vendor">altr</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>avalon_jtag_slave</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_read_n</name> + <role>read_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>av_write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>1</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>2</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>true</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > + <peripherals> + <peripheral> + <name>altera_avalon_jtag_uart</name><baseAddress>0x00000000</baseAddress> + <addressBlock> + <offset>0x0</offset> + <size>8</size> + <usage>registers</usage> + </addressBlock> + <registers> + <register> + <name>DATA</name> + <displayName>Data</displayName> + <description>Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.</description> + <addressOffset>0x0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>data</name> + <description>The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field><name>rvalid</name> + <description>Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.</description> + <bitOffset>0xf</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field><name>ravail</name> + <description>The number of characters remaining in the read FIFO (after the current read).</description> + <bitOffset>0x10</bitOffset> + <bitWidth>16</bitWidth> + <access>read-only</access> + </field> + </fields> + </register> + <register> + <name>CONTROL</name> + <displayName>Control</displayName> + <description>Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.</description> + <addressOffset>0x4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>re</name> + <description>Interrupt-enable bit for read interrupts.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field><name>we</name> + <description>Interrupt-enable bit for write interrupts</description> + <bitOffset>0x1</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field><name>ri</name> + <description>Indicates that the read interrupt is pending.</description> + <bitOffset>0x8</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field><name>wi</name> + <description>Indicates that the write interrupt is pending.</description> + <bitOffset>0x9</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field><name>ac</name> + <description>Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.</description> + <bitOffset>0xa</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field><name>wspace</name> + <description>The number of spaces available in the write FIFO</description> + <bitOffset>0x10</bitOffset> + <bitWidth>16</bitWidth> + <access>read-only</access> + </field> + </fields> + </register> + </registers> + </peripheral> + </peripherals> +</device> </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>qsys_unb2c_minimal_jtag_uart_0.avalon_jtag_slave</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>avalon_jtag_slave</key> + <value> + <connectionPointName>avalon_jtag_slave</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='avalon_jtag_slave' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="avalon_jtag_slave" altera:internal="jtag_uart_0.avalon_jtag_slave" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="av_address" altera:internal="av_address"></altera:port_mapping> + <altera:port_mapping altera:name="av_chipselect" altera:internal="av_chipselect"></altera:port_mapping> + <altera:port_mapping altera:name="av_read_n" altera:internal="av_read_n"></altera:port_mapping> + <altera:port_mapping altera:name="av_readdata" altera:internal="av_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="av_waitrequest" altera:internal="av_waitrequest"></altera:port_mapping> + <altera:port_mapping altera:name="av_write_n" altera:internal="av_write_n"></altera:port_mapping> + <altera:port_mapping altera:name="av_writedata" altera:internal="av_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="jtag_uart_0.clk" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="irq" altera:internal="jtag_uart_0.irq" altera:type="interrupt" altera:dir="end"> + <altera:port_mapping altera:name="av_irq" altera:internal="av_irq"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="jtag_uart_0.reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="rst_n" altera:internal="rst_n"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip new file mode 100644 index 0000000000000000000000000000000000000000..09b10365fa9eb74435bc768b229a528506db5644 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip @@ -0,0 +1,1220 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_onchip_memory2_0</spirit:library> + <spirit:name>onchip_memory2_0</spirit:name> + <spirit:version>18.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>clk1</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset1</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset_req</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>reset_req</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>s1</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clken</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>clken</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>byteenable</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>byteenable</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">131072</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">131072</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + 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+ </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" 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spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>altera_avalon_onchip_memory2</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>14</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>clken</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>chipselect</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>byteenable</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>3</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset_req</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_onchip_memory2_0</spirit:library> + <spirit:name>altera_avalon_onchip_memory2</spirit:name> + <spirit:version>18.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>allowInSystemMemoryContentEditor</spirit:name> + <spirit:displayName>Enable In-System Memory Content Editor feature</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="allowInSystemMemoryContentEditor">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>blockType</spirit:name> + <spirit:displayName>Block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="blockType">AUTO</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dataWidth</spirit:name> + <spirit:displayName>Slave S1 Data width</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="dataWidth">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dataWidth2</spirit:name> + <spirit:displayName>Slave S2 Data width</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="dataWidth2">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dualPort</spirit:name> + <spirit:displayName>Dual-port access</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="dualPort">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>enableDiffWidth</spirit:name> + <spirit:displayName>Enable different width for Dual-port access</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="enableDiffWidth">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_enableDiffWidth</spirit:name> + <spirit:displayName>derived_enableDiffWidth</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_enableDiffWidth">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>initMemContent</spirit:name> + <spirit:displayName>Initialize memory content</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="initMemContent">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>initializationFileName</spirit:name> + <spirit:displayName>User created initialization file</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="initializationFileName">onchip_memory2_0.hex</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>enPRInitMode</spirit:name> + <spirit:displayName>Enable Partial Reconfiguration Initialization Mode</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="enPRInitMode">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>instanceID</spirit:name> + <spirit:displayName>Instance ID</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="instanceID">NONE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>memorySize</spirit:name> + <spirit:displayName>Total memory size</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="memorySize">131072</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readDuringWriteMode</spirit:name> + <spirit:displayName>Read During Write Mode</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="readDuringWriteMode">DONT_CARE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>simAllowMRAMContentsFile</spirit:name> + <spirit:displayName>Allow MRAM contents file for simulation</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="simAllowMRAMContentsFile">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>simMemInitOnlyFilename</spirit:name> + <spirit:displayName>Simulation meminit only has filename</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="simMemInitOnlyFilename">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>singleClockOperation</spirit:name> + <spirit:displayName>Single clock operation</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="singleClockOperation">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_singleClockOperation</spirit:name> + <spirit:displayName>derived_singleClockOperation</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_singleClockOperation">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>slave1Latency</spirit:name> + <spirit:displayName>Slave s1 Latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="slave1Latency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>slave2Latency</spirit:name> + <spirit:displayName>Slave s2 Latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="slave2Latency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>useNonDefaultInitFile</spirit:name> + <spirit:displayName>Enable non-default initialization file</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="useNonDefaultInitFile">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>copyInitFile</spirit:name> + <spirit:displayName> Copy non-default initialization file to generated folder</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="copyInitFile">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>useShallowMemBlocks</spirit:name> + <spirit:displayName>Minimize memory block usage (may impact fmax)</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="useShallowMemBlocks">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writable</spirit:name> + <spirit:displayName>Type</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="writable">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ecc_enabled</spirit:name> + <spirit:displayName>Extend the data width to support ECC bits</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="ecc_enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>resetrequest_enabled</spirit:name> + <spirit:displayName>Reset Request</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="resetrequest_enabled">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>autoInitializationFileName</spirit:name> + <spirit:displayName>autoInitializationFileName</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="autoInitializationFileName">qsys_unb2c_minimal_onchip_memory2_0_onchip_memory2_0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>deviceFamily</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFeatures</spirit:name> + <spirit:displayName>deviceFeatures</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ALLOW_DIFF_SUFFIX_MIGRATION 0 ASSERT_TIMING_ROUTING_DELAYS_HAS_ALL_EXPECTED_DATA 0 ASSERT_TIMING_ROUTING_DELAYS_NO_AUTOFILL 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DISABLE_CRC_ERROR_DETECTION 0 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_HIGH_SPEED_HSSI 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_BLOCK 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MISSING_PAD_INFO 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QHD_INCREMENTAL_TIMING_CLOSURE_SUPPORT 1 HAS_QHD_IP_REUSE_INTEGRATION_SUPPORT 1 HAS_QHD_PARTITIONS_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_REVC_IO 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMPLIFIED_PARTIAL_RECONFIG_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SIP_TILE_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_DQS_IN_BUFFER_REDUCTION 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 IS_SDM_LITE 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LUTRAM_DATA_IN_FF_MUST_BE_HIPI 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MAC_NEGATE_SUPPORT_DISABLED 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_CLOCK_REGION 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PCF 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 PINTABLE_OPTIONAL 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_PW0 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_MIN_CORNER_DMF_GENERATION 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_TIMING_CLOSURE_CORNERS 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORT_UIB 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 U2B2_SUPPORT_NOT_READY 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DETAILED_REDTAX_WITH_DSPF_ROUTING_MODELS 0 USES_DEV 1 USES_DSPF_ROUTING_MODELS 0 USES_DSP_FROM_PREVIOUS_FAMILY 0 USES_ESTIMATED_TIMING 0 USES_EXTRACTION_CORNERS_WITH_DSPF_ROUTING_MODELS 0 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PARASITIC_LOADS_WITH_DSPF_ROUTING_MODELS 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_RAM_FROM_PREVIOUS_FAMILY 0 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_TIMING_ROUTING_DELAYS 0 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SDM_CONFIGURATION 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WORKS_AROUND_MISSING_RED_FLAGS_IN_DSPF_ROUTING_MODELS 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_set_addr_width</spirit:name> + <spirit:displayName>Slave 1 address width</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="derived_set_addr_width">15</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_set_addr_width2</spirit:name> + <spirit:displayName>Slave 2 address width</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="derived_set_addr_width2">15</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_set_data_width</spirit:name> + <spirit:displayName>Slave 1 data width</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="derived_set_data_width">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_set_data_width2</spirit:name> + <spirit:displayName>Slave 2 data width</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="derived_set_data_width2">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_gui_ram_block_type</spirit:name> + <spirit:displayName>derived_gui_ram_block_type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="derived_gui_ram_block_type">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_is_hardcopy</spirit:name> + <spirit:displayName>derived_is_hardcopy</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_is_hardcopy">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_init_file_name</spirit:name> + <spirit:displayName>derived_init_file_name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="derived_init_file_name">onchip_memory2_0.hex</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.CONTENTS_INFO</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.CONTENTS_INFO">""</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.DUAL_PORT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DUAL_PORT">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE">AUTO</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.INIT_CONTENTS_FILE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.INIT_CONTENTS_FILE">onchip_memory2_0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.INIT_MEM_CONTENT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.INIT_MEM_CONTENT">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.INSTANCE_ID</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.INSTANCE_ID">NONE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.RAM_BLOCK_TYPE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.RAM_BLOCK_TYPE">AUTO</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.READ_DURING_WRITE_MODE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.READ_DURING_WRITE_MODE">DONT_CARE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.SINGLE_CLOCK_OP</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.SINGLE_CLOCK_OP">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.SIZE_MULTIPLE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.SIZE_MULTIPLE">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.SIZE_VALUE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.SIZE_VALUE">131072</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.WRITABLE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.WRITABLE">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR">SIM_DIR</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.GENERATE_DAT_SYM">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.memoryInfo.GENERATE_HEX</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.GENERATE_HEX">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.memoryInfo.HAS_BYTE_LANE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.HAS_BYTE_LANE">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.HEX_INSTALL_DIR">QPF_DIR</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.memoryInfo.MEM_INIT_FILENAME</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.MEM_INIT_FILENAME">onchip_memory2_0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>postgeneration.simulation.init_file.param_name</spirit:name> + <spirit:value spirit:format="string" spirit:id="postgeneration.simulation.init_file.param_name">INIT_FILE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>postgeneration.simulation.init_file.type</spirit:name> + <spirit:value spirit:format="string" spirit:id="postgeneration.simulation.init_file.type">MEM_INIT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>clk1</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset1</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>reset_req</name> + <role>reset_req</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk1</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>15</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>clken</name> + <role>clken</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + 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<key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>131072</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk1</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset1</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>131072</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>true</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>s1</key> + <value> + <connectionPointName>s1</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='s1' start='0x0' end='0x20000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>17</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="clk1" altera:internal="onchip_memory2_0.clk1" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset1" altera:internal="onchip_memory2_0.reset1" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="reset" altera:internal="reset"></altera:port_mapping> + <altera:port_mapping altera:name="reset_req" altera:internal="reset_req"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="s1" altera:internal="onchip_memory2_0.s1" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="address" altera:internal="address"></altera:port_mapping> + <altera:port_mapping altera:name="byteenable" altera:internal="byteenable"></altera:port_mapping> + <altera:port_mapping altera:name="chipselect" altera:internal="chipselect"></altera:port_mapping> + <altera:port_mapping altera:name="clken" altera:internal="clken"></altera:port_mapping> + <altera:port_mapping altera:name="readdata" altera:internal="readdata"></altera:port_mapping> + <altera:port_mapping altera:name="write" altera:internal="write"></altera:port_mapping> + <altera:port_mapping altera:name="writedata" altera:internal="writedata"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip new file mode 100644 index 0000000000000000000000000000000000000000..1d2e8bf5dad59d5d29d0720764db4458522ea73e --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip @@ -0,0 +1,1439 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_pio_pps</spirit:library> + <spirit:name>pio_pps</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + 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burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_pio_pps</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="pio_pps.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="pio_pps.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="pio_pps.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="pio_pps.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="pio_pps.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="pio_pps.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="pio_pps.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="pio_pps.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="pio_pps.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="pio_pps.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip new file mode 100644 index 0000000000000000000000000000000000000000..0fc6e8f1bdfdf7cbfa8d01fc2465da3443766f24 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_pio_system_info</spirit:library> + <spirit:name>pio_system_info</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>4</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>4</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_pio_system_info</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>5</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>5</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>128</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>7</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="pio_system_info.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="pio_system_info.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="pio_system_info.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="pio_system_info.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="pio_system_info.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="pio_system_info.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="pio_system_info.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="pio_system_info.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="pio_system_info.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="pio_system_info.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip new file mode 100644 index 0000000000000000000000000000000000000000..b6c98aaa6799fb7df90c035819a393fa46f0ac9c --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip @@ -0,0 +1,1253 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_pio_wdi</spirit:library> + <spirit:name>pio_wdi</spirit:name> + <spirit:version>18.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>external_connection</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>out_port</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>s1</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>write_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">NATIVE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">4</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>altera_avalon_pio</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>1</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>write_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>chipselect</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>out_port</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_pio_wdi</spirit:library> + <spirit:name>altera_avalon_pio</spirit:name> + <spirit:version>18.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>bitClearingEdgeCapReg</spirit:name> + <spirit:displayName>Enable bit-clearing for edge capture register</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="bitClearingEdgeCapReg">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitModifyingOutReg</spirit:name> + <spirit:displayName>Enable individual bit setting/clearing</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="bitModifyingOutReg">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>captureEdge</spirit:name> + <spirit:displayName>Synchronously capture</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="captureEdge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>direction</spirit:name> + <spirit:displayName>Direction</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="direction">Output</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>edgeType</spirit:name> + <spirit:displayName>Edge Type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="edgeType">RISING</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generateIRQ</spirit:name> + <spirit:displayName>Generate IRQ</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="generateIRQ">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>irqType</spirit:name> + <spirit:displayName>IRQ Type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="irqType">LEVEL</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>resetValue</spirit:name> + <spirit:displayName>Output Port Reset Value</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="resetValue">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>simDoTestBenchWiring</spirit:name> + <spirit:displayName>Hardwire PIO inputs in test bench</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="simDoTestBenchWiring">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>simDrivenValue</spirit:name> + <spirit:displayName>Drive inputs to field.</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="simDrivenValue">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>width</spirit:name> + <spirit:displayName>Width (1-32 bits)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="width">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>clockRate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_has_tri</spirit:name> + <spirit:displayName>derived_has_tri</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_has_tri">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_has_out</spirit:name> + <spirit:displayName>derived_has_out</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_has_out">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_has_in</spirit:name> + <spirit:displayName>derived_has_in</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_has_in">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_do_test_bench_wiring</spirit:name> + <spirit:displayName>derived_do_test_bench_wiring</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_do_test_bench_wiring">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_capture</spirit:name> + <spirit:displayName>derived_capture</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_capture">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_edge_type</spirit:name> + <spirit:displayName>derived_edge_type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="derived_edge_type">NONE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_irq_type</spirit:name> + <spirit:displayName>derived_irq_type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="derived_irq_type">NONE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_has_irq</spirit:name> + <spirit:displayName>derived_has_irq</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_has_irq">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.CAPTURE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.CAPTURE">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.DATA_WIDTH</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DATA_WIDTH">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DO_TEST_BENCH_WIRING">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.DRIVEN_SIM_VALUE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DRIVEN_SIM_VALUE">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.EDGE_TYPE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.EDGE_TYPE">NONE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.FREQ</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.FREQ">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.HAS_IN</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HAS_IN">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.HAS_OUT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HAS_OUT">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.HAS_TRI</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HAS_TRI">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.IRQ_TYPE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.IRQ_TYPE">NONE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.RESET_VALUE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.RESET_VALUE">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.compatible</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.compatible">altr,pio-1.0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.group</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.group">gpio</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.name</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.name">pio</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.params.altr,gpio-bank-width</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.altr,gpio-bank-width">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.params.resetvalue</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.resetvalue">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.vendor</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.vendor">altr</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>external_connection</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>out_port</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > + <peripherals> + <peripheral> + <name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress> + <addressBlock> + <offset>0x0</offset> + <size>32</size> + <usage>registers</usage> + </addressBlock> + <registers> + <register> + <name>DATA</name> + <displayName>Data</displayName> + <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description> + <addressOffset>0x0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>data</name> + <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>DIRECTION</name> + <displayName>Direction</displayName> + <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description> + <addressOffset>0x4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>direction</name> + <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>IRQ_MASK</name> + <displayName>Interrupt mask</displayName> + <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description> + <addressOffset>0x8</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>interruptmask</name> + <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>EDGE_CAP</name> + <displayName>Edge capture</displayName> + <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description> + <addressOffset>0xc</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>edgecapture</name> + <description>Edge detection for each input port.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>SET_BIT</name> + <displayName>Outset</displayName> + <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description> + <addressOffset>0x10</addressOffset> + <size>32</size> + <access>write-only</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>outset</name> + <description>Specifies which bit of the output port to set.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>write-only</access> + </field> + </fields> + </register> + <register> + <name>CLEAR_BITS</name> + <displayName>Outclear</displayName> + <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description> + <addressOffset>0x14</addressOffset> + <size>32</size> + <access>write-only</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>outclear</name> + <description>Specifies which output bit to clear.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>write-only</access> + </field> + </fields> + </register> + </registers> + </peripheral> + </peripherals> +</device> </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>s1</key> + <value> + <connectionPointName>s1</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>4</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="clk" altera:internal="pio_wdi.clk" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="external_connection" altera:internal="pio_wdi.external_connection" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="out_port" altera:internal="out_port"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="pio_wdi.reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="reset_n" altera:internal="reset_n"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="s1" altera:internal="pio_wdi.s1" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="address" altera:internal="address"></altera:port_mapping> + <altera:port_mapping altera:name="chipselect" altera:internal="chipselect"></altera:port_mapping> + <altera:port_mapping altera:name="readdata" altera:internal="readdata"></altera:port_mapping> + <altera:port_mapping altera:name="write_n" altera:internal="write_n"></altera:port_mapping> + <altera:port_mapping altera:name="writedata" altera:internal="writedata"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip new file mode 100644 index 0000000000000000000000000000000000000000..eaa2adcc8488d8a80c26c9990d6901d193f7c749 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip @@ -0,0 +1,1439 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_dpmm_ctrl</spirit:library> + <spirit:name>reg_dpmm_ctrl</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_dpmm_ctrl</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_dpmm_ctrl.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_dpmm_ctrl.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_dpmm_ctrl.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_dpmm_ctrl.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_dpmm_ctrl.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_dpmm_ctrl.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_dpmm_ctrl.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_dpmm_ctrl.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_dpmm_ctrl.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_dpmm_ctrl.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip new file mode 100644 index 0000000000000000000000000000000000000000..564b626b4013fe44dee45248c8f7f743b7419c61 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip @@ -0,0 +1,1439 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_dpmm_data</spirit:library> + <spirit:name>reg_dpmm_data</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + 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<spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + 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+ <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_dpmm_data.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_dpmm_data.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_dpmm_data.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_dpmm_data.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_dpmm_data.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_dpmm_data.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_dpmm_data.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_dpmm_data.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_dpmm_data.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_dpmm_data.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip new file mode 100644 index 0000000000000000000000000000000000000000..b07b1b402e172532483dc1ef8d9d09c7095eef71 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_epcs</spirit:library> + <spirit:name>reg_epcs</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>2</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>2</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_epcs</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">3</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_epcs.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_epcs.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_epcs.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_epcs.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_epcs.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_epcs.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_epcs.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_epcs.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_epcs.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_epcs.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip new file mode 100644 index 0000000000000000000000000000000000000000..9efe5c57caeabcbdbfb92af45d701d3dc187068f --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_fpga_temp_sens</spirit:library> + <spirit:name>reg_fpga_temp_sens</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + 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</spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" 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<spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + 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<isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> 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<lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_fpga_temp_sens.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_fpga_temp_sens.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_fpga_temp_sens.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_fpga_temp_sens.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_fpga_temp_sens.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_fpga_temp_sens.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_fpga_temp_sens.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_fpga_temp_sens.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_fpga_temp_sens.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_fpga_temp_sens.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip new file mode 100644 index 0000000000000000000000000000000000000000..4d652f96ceccd7fdbd240e65b5f0ee806000a463 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_fpga_voltage_sens</spirit:library> + <spirit:name>reg_fpga_voltage_sens</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" 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<spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + 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<spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + 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<spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + 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<value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_fpga_voltage_sens.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_fpga_voltage_sens.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_fpga_voltage_sens.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_fpga_voltage_sens.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_fpga_voltage_sens.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_fpga_voltage_sens.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_fpga_voltage_sens.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_fpga_voltage_sens.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_fpga_voltage_sens.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_fpga_voltage_sens.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip new file mode 100644 index 0000000000000000000000000000000000000000..4fff1367f07a2f1261f8e62c4069470bd930e1f2 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip @@ -0,0 +1,1439 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_mmdp_ctrl</spirit:library> + <spirit:name>reg_mmdp_ctrl</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally 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<spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + 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<spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + 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<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_mmdp_ctrl</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_mmdp_ctrl.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_mmdp_ctrl.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_mmdp_ctrl.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_mmdp_ctrl.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_mmdp_ctrl.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_mmdp_ctrl.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_mmdp_ctrl.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_mmdp_ctrl.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_mmdp_ctrl.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_mmdp_ctrl.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip new file mode 100644 index 0000000000000000000000000000000000000000..450ee4447b7ade031675181089797226ea80e01b --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip @@ -0,0 +1,1439 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_mmdp_data</spirit:library> + <spirit:name>reg_mmdp_data</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + 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<spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_mmdp_data</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_mmdp_data.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_mmdp_data.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_mmdp_data.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_mmdp_data.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_mmdp_data.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_mmdp_data.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_mmdp_data.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_mmdp_data.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_mmdp_data.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_mmdp_data.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip new file mode 100644 index 0000000000000000000000000000000000000000..6f360cba7bd7b3657e0d7d1d5428aa2042ceae7c --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip @@ -0,0 +1,1455 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_remu</spirit:library> + <spirit:name>reg_remu</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>2</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>2</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_remu</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">3</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ + element reg_remu + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_remu.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_remu.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_remu.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_remu.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_remu.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_remu.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_remu.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_remu.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_remu.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_remu.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip new file mode 100644 index 0000000000000000000000000000000000000000..b4758115354d88a81255e5a80f01d6eee34f0c5f --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip @@ -0,0 +1,1455 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_unb_pmbus</spirit:library> + <spirit:name>reg_unb_pmbus</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">256</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>5</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>5</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_unb_pmbus</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">6</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ + element reg_unb_pmbus + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>256</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>8</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_unb_pmbus.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_unb_pmbus.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_unb_pmbus.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_unb_pmbus.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_unb_pmbus.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_unb_pmbus.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_unb_pmbus.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_unb_pmbus.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_unb_pmbus.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_unb_pmbus.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip new file mode 100644 index 0000000000000000000000000000000000000000..8494572d5c37c2482118d8e7fe5f926f304d7e21 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip @@ -0,0 +1,1455 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_unb_sens</spirit:library> + <spirit:name>reg_unb_sens</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + 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<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>5</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_unb_sens</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">6</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ + element reg_unb_sens + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>256</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>8</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_unb_sens.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_unb_sens.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_unb_sens.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_unb_sens.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_unb_sens.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_unb_sens.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_unb_sens.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_unb_sens.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_unb_sens.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_unb_sens.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip new file mode 100644 index 0000000000000000000000000000000000000000..9d869abbb1c1d0327f606185d5986fe15b2956cd --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_wdi</spirit:library> + <spirit:name>reg_wdi</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_reg_wdi</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ + element reg_wdi + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_wdi.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_wdi.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_wdi.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_wdi.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_wdi.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_wdi.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_wdi.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_wdi.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_wdi.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_wdi.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip new file mode 100644 index 0000000000000000000000000000000000000000..6a022a4ad6872eb4f018f1a1b7129ba2d000c943 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip @@ -0,0 +1,1455 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_rom_system_info</spirit:library> + <spirit:name>rom_system_info</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">4096</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>9</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>9</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_rom_system_info</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ + element rom_system_info + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4096</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>12</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="rom_system_info.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="rom_system_info.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="rom_system_info.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="rom_system_info.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="rom_system_info.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="rom_system_info.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="rom_system_info.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="rom_system_info.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="rom_system_info.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="rom_system_info.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip new file mode 100644 index 0000000000000000000000000000000000000000..1b867a0f5823e0af3b30bb17b25f2de51a3e5177 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip @@ -0,0 +1,1361 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_timer_0</spirit:library> + <spirit:name>timer_0</spirit:name> + <spirit:version>18.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>irq</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="interrupt" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>irq</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>irq</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedAddressablePoint</spirit:name> + <spirit:displayName>Associated addressable interface</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">qsys_unb2c_minimal_timer_0.s1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedReceiverOffset</spirit:name> + <spirit:displayName>Bridged receiver offset</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bridgedReceiverOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToReceiver</spirit:name> + <spirit:displayName>Bridges to receiver</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToReceiver"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>irqScheme</spirit:name> + <spirit:displayName>Interrupt scheme</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="irqScheme">NONE</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" 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spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + 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<spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>2</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>15</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>15</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>chipselect</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>write_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>irq</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_timer_0</spirit:library> + <spirit:name>altera_avalon_timer</spirit:name> + <spirit:version>18.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>alwaysRun</spirit:name> + <spirit:displayName>No Start/Stop control bits</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysRun">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>counterSize</spirit:name> + <spirit:displayName>Counter Size</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="counterSize">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>fixedPeriod</spirit:name> + <spirit:displayName>Fixed period</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="fixedPeriod">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>period</spirit:name> + <spirit:displayName>Period</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="period">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>periodUnits</spirit:name> + <spirit:displayName>Units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="periodUnits">MSEC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>resetOutput</spirit:name> + <spirit:displayName>System reset on timeout (Watchdog)</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="resetOutput">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>snapshot</spirit:name> + <spirit:displayName>Readable snapshot</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="snapshot">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timeoutPulseOutput</spirit:name> + <spirit:displayName>Timeout pulse (1 clock wide)</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="timeoutPulseOutput">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemFrequency</spirit:name> + <spirit:displayName>systemFrequency</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemFrequency">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>watchdogPulse</spirit:name> + <spirit:displayName>Watchdog Timer Pulse Length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="watchdogPulse">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timerPreset</spirit:name> + <spirit:displayName>Presets</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timerPreset">SIMPLE_PERIODIC_INTERRUPT</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>periodUnitsString</spirit:name> + <spirit:displayName>periodUnitsString</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="periodUnitsString">ms</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>valueInSecond</spirit:name> + <spirit:displayName>valueInSecond</spirit:displayName> + <spirit:value spirit:format="float" spirit:id="valueInSecond">0.001</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>loadValue</spirit:name> + <spirit:displayName>loadValue</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="loadValue">99999</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mult</spirit:name> + <spirit:displayName>mult</spirit:displayName> + <spirit:value spirit:format="float" spirit:id="mult">0.001</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ticksPerSec</spirit:name> + <spirit:displayName>ticksPerSec</spirit:displayName> + <spirit:value spirit:format="float" spirit:id="ticksPerSec">1000.0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>slave_address_width</spirit:name> + <spirit:displayName>slave_address_width</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="slave_address_width">3</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.ALWAYS_RUN</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.ALWAYS_RUN">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.COUNTER_SIZE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.COUNTER_SIZE">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.FIXED_PERIOD</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.FIXED_PERIOD">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.FREQ</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.FREQ">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.LOAD_VALUE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.LOAD_VALUE">99999</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.MULT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.MULT">0.001</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.PERIOD</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.PERIOD">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.PERIOD_UNITS</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.PERIOD_UNITS">ms</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.RESET_OUTPUT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.RESET_OUTPUT">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.SNAPSHOT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.SNAPSHOT">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.TICKS_PER_SEC</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.TICKS_PER_SEC">1000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.vendor</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.vendor">altr</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ + element timer_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>qsys_unb2c_minimal_timer_0.s1</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isTimerDevice</key> + <value>1</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > + <peripherals> + <peripheral> + <name>altera_avalon_timer</name><baseAddress>0x00000000</baseAddress> + <addressBlock> + <offset>0x0</offset> + <size>16</size> + <usage>registers</usage> + </addressBlock> + <registers> + <register> + <name>status</name> + <displayName>Status</displayName> + <description>The status register has two defined bits. TO (timeout), RUN</description> + <addressOffset>0x0</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + <fields> + <field><name>TO</name> + <description>The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + <readAction>clear</readAction> + </field> + <field><name>RUN</name> + <description>The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by + a write operation to the status register.</description> + <bitOffset>1</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field> + <name>Reserved</name> + <description>Reserved</description> + <bitOffset>2</bitOffset> + <bitWidth>14</bitWidth> + <access>read-write</access> + <parameters> + <parameter> + <name>Reserved</name> + <value>true</value> + </parameter> + </parameters> + </field> + </fields> + </register> + <register> + <name>control</name> + <description>The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP</description> + <addressOffset>0x1</addressOffset> + <size>16</size> + <access>read-write</access> + <reset> + <value>0x0</value> + </reset> + <field> + <name>ITO</name> + <description>If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CONT</name> + <description>The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.</description> + <bitOffset>1</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>START</name> + <description>Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.</description> + <bitOffset>2</bitOffset> + <bitWidth>1</bitWidth> + <access>write-only</access> + </field> + <field> + <name>STOP</name> + <description>Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.</description> + <bitOffset>3</bitOffset> + <bitWidth>1</bitWidth> + <access>write-only</access> + </field> + <field> + <name>Reserved</name> + <description>Reserved</description> + <bitOffset>4</bitOffset> + <bitWidth>12</bitWidth> + <access>read-write</access> + <parameters> + <parameter> + <name>Reserved</name> + <value>true</value> + </parameter> + </parameters> + </field> + </register> + <register> + <name>${period_name_0}</name> + <description>The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.</description> + <addressOffset>0x2</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_name_0_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${period_name_1}</name> + <description></description> + <addressOffset>0x3</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_name_1_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${period_snap_0}</name> + <description></description> + <addressOffset>0x4</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_snap_0_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${period_snap_1}</name> + <description></description> + <addressOffset>0x5</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_snap_1_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_0}</name> + <description>A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.</description> + <addressOffset>0x6</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_1}</name> + <description></description> + <addressOffset>0x7</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_2}</name> + <description></description> + <addressOffset>0x8</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_3}</name> + <description></description> + <addressOffset>0x9</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + </registers> + </peripheral> + </peripherals> +</device> </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars> + <entry> + <key>period_name_1_reset_value</key> + <value>0x1</value> + </entry> + <entry> + <key>snap_0</key> + <value>Reserved</value> + </entry> + <entry> + <key>period_name_0_reset_value</key> + <value>0x869f</value> + </entry> + <entry> + <key>snap_2</key> + <value>Reserved</value> + </entry> + <entry> + <key>snap_1</key> + <value>Reserved</value> + </entry> + <entry> + <key>snap_3</key> + <value>Reserved</value> + </entry> + <entry> + <key>period_name_0</key> + <value>periodl</value> + </entry> + <entry> + <key>period_name_1</key> + <value>periodh</value> + </entry> + <entry> + <key>period_snap_1</key> + <value>snaph</value> + </entry> + <entry> + <key>period_snap_1_reset_value</key> + <value>0x0</value> + </entry> + <entry> + <key>period_snap_0_reset_value</key> + <value>0x0</value> + </entry> + <entry> + <key>period_snap_0</key> + <value>snapl</value> + </entry> + </cmsisVars> + </cmsisInfo> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>s1</key> + <value> + <connectionPointName>s1</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='s1' start='0x0' end='0x20' datawidth='16' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>16</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="clk" altera:internal="timer_0.clk" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="irq" altera:internal="timer_0.irq" altera:type="interrupt" altera:dir="end"> + <altera:port_mapping altera:name="irq" altera:internal="irq"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="timer_0.reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="reset_n" altera:internal="reset_n"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="s1" altera:internal="timer_0.s1" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="address" altera:internal="address"></altera:port_mapping> + <altera:port_mapping altera:name="chipselect" altera:internal="chipselect"></altera:port_mapping> + <altera:port_mapping altera:name="readdata" altera:internal="readdata"></altera:port_mapping> + <altera:port_mapping altera:name="write_n" altera:internal="write_n"></altera:port_mapping> + <altera:port_mapping altera:name="writedata" altera:internal="writedata"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl index da85c19f6523141cbbe5eb02ad1bd1dc0e4f2fdb..017b557ecc8f8ead2595600a59d30ed20f839f95 100644 --- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl @@ -20,4 +20,4 @@ ############################################################################### source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl -source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl +source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys new file mode 100644 index 0000000000000000000000000000000000000000..5e57d9ace3faa9147156e9fa3609c1fb0adc14f9 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys @@ -0,0 +1,18395 @@ +<?xml version="1.0" encoding="UTF-8"?> +<system name="qsys_lofar2_unb2b_adc"> + <component + name="$${FILENAME}" + displayName="$${FILENAME}" + version="1.0" + description="" + tags="" + categories="System" + tool="QsysPro" /> + <parameter name="bonusData"><![CDATA[bonusData +{ + element $system + { + } + element avs_eth_0 + { + datum _sortIndex + { + value = "6"; + type = "int"; + } + } + element avs_eth_0.mms_ram + { + datum baseAddress + { + value = "16384"; + type = "String"; + } + } + element avs_eth_0.mms_reg + { + datum baseAddress + { + value = "128"; + type = "String"; + } + } + element avs_eth_0.mms_tse + { + datum baseAddress + { + value = "8192"; + type = "String"; + } + } + element clk_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } + element cpu_0 + { + datum _sortIndex + { + value = "1"; + type = "int"; + } + } + element cpu_0.debug_mem_slave + { + datum baseAddress + { + value = "14336"; + type = "String"; + } + } + element jesd204b + { + datum _sortIndex + { + value = "23"; + type = "int"; + } + } + element jesd204b.mem + { + datum baseAddress + { + value = "262144"; + type = "String"; + } + } + element jtag_uart_0 + { + datum _sortIndex + { + value = "3"; + type = "int"; + } + } + element jtag_uart_0.avalon_jtag_slave + { + datum baseAddress + { + value = "952"; + type = "String"; + } + } + element jtag_uart_0.irq + { + datum _tags + { + value = ""; + type = "String"; + } + } + element onchip_memory2_0 + { + datum _sortIndex + { + value = "2"; + type = "int"; + } + } + element onchip_memory2_0.s1 + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "131072"; + type = "String"; + } + } + element pio_pps + { + datum _sortIndex + { + value = "12"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element pio_pps.mem + { + datum baseAddress + { + value = "944"; + type = "String"; + } + } + element pio_system_info + { + datum _sortIndex + { + value = "11"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element pio_system_info.mem + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + } + element pio_wdi + { + datum _sortIndex + { + value = "4"; + type = "int"; + } + } + element pio_wdi.s1 + { + datum baseAddress + { + value = "896"; + type = "String"; + } + } + element ram_diag_data_buffer_jesd + { + datum _sortIndex + { + value = "22"; + type = "int"; + } + } + element ram_diag_data_buffer_jesd.mem + { + datum baseAddress + { + value = "524288"; + type = "String"; + } + } + element reg_diag_data_buffer_jesd + { + datum _sortIndex + { + value = "21"; + type = "int"; + } + } + element reg_diag_data_buffer_jesd.mem + { + datum baseAddress + { + value = "1048576"; + type = "String"; + } + } + element reg_dpmm_ctrl + { + datum _sortIndex + { + value = "16"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_dpmm_ctrl.mem + { + datum baseAddress + { + value = "936"; + type = "String"; + } + } + element reg_dpmm_data + { + datum _sortIndex + { + value = "17"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_dpmm_data.mem + { + datum baseAddress + { + value = "928"; + type = "String"; + } + } + element reg_epcs + { + datum _sortIndex + { + value = "15"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_epcs.mem + { + datum baseAddress + { + value = "832"; + type = "String"; + } + } + element reg_fpga_temp_sens + { + datum _sortIndex + { + value = "9"; + type = "int"; + } + } + element reg_fpga_temp_sens.mem + { + datum baseAddress + { + value = "800"; + type = "String"; + } + } + element reg_fpga_voltage_sens + { + datum _sortIndex + { + value = "20"; + type = "int"; + } + datum sopceditor_expanded + { + value = "1"; + type = "boolean"; + } + } + element reg_fpga_voltage_sens.mem + { + datum baseAddress + { + value = "192"; + type = "String"; + } + } + element reg_mmdp_ctrl + { + datum _sortIndex + { + value = "18"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_mmdp_ctrl.mem + { + datum baseAddress + { + value = "920"; + type = "String"; + } + } + element reg_mmdp_data + { + datum _sortIndex + { + value = "19"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_mmdp_data.mem + { + datum baseAddress + { + value = "912"; + type = "String"; + } + } + element reg_remu + { + datum _sortIndex + { + value = "14"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_remu.mem + { + datum baseAddress + { + value = "864"; + type = "String"; + } + } + element reg_unb_pmbus + { + datum _sortIndex + { + value = "8"; + type = "int"; + } + } + element reg_unb_pmbus.mem + { + datum baseAddress + { + value = "256"; + type = "String"; + } + } + element reg_unb_sens + { + datum _sortIndex + { + value = "7"; + type = "int"; + } + } + element reg_unb_sens.mem + { + datum baseAddress + { + value = "512"; + type = "String"; + } + } + element reg_wdi + { + datum _sortIndex + { + value = "13"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_wdi.mem + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "12288"; + type = "String"; + } + } + element rom_system_info + { + datum _sortIndex + { + value = "10"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element rom_system_info.mem + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "4096"; + type = "String"; + } + } + element timer_0 + { + datum _sortIndex + { + value = "5"; + type = "int"; + } + } + element timer_0.s1 + { + datum baseAddress + { + value = "768"; + type = "String"; + } + } +} +]]></parameter> + <parameter name="device" value="10AX115U2F45E1SG" /> + <parameter name="deviceFamily" value="Arria 10" /> + <parameter name="deviceSpeedGrade" value="1" /> + <parameter name="fabricMode" value="QSYS" /> + <parameter name="generateLegacySim" value="false" /> + <parameter name="generationId" value="0" /> + <parameter name="globalResetBus" value="false" /> + <parameter name="hdlLanguage" value="VERILOG" /> + <parameter name="hideFromIPCatalog" value="false" /> + <parameter name="lockedInterfaceDefinition" value="" /> + <parameter name="sopcBorderPoints" value="false" /> + <parameter name="systemHash" value="0" /> + <parameter name="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></parameter> + <parameter name="systemScripts" value="" /> + <parameter name="testBenchDutName" value="" /> + <parameter name="timeStamp" value="0" /> + <parameter name="useTestBenchNamingPattern" value="false" /> + <instanceScript></instanceScript> + <interface + name="avs_eth_0_clk" + internal="avs_eth_0.clk" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_irq" + internal="avs_eth_0.irq" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_ram_address" + internal="avs_eth_0.ram_address" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_ram_read" + internal="avs_eth_0.ram_read" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_ram_readdata" + internal="avs_eth_0.ram_readdata" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_ram_write" + internal="avs_eth_0.ram_write" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_ram_writedata" + internal="avs_eth_0.ram_writedata" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_reg_address" + internal="avs_eth_0.reg_address" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_reg_read" + internal="avs_eth_0.reg_read" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_reg_readdata" + internal="avs_eth_0.reg_readdata" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_reg_write" + internal="avs_eth_0.reg_write" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_reg_writedata" + internal="avs_eth_0.reg_writedata" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_reset" + internal="avs_eth_0.reset" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_tse_address" + internal="avs_eth_0.tse_address" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_tse_read" + internal="avs_eth_0.tse_read" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_tse_readdata" + internal="avs_eth_0.tse_readdata" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_tse_waitrequest" + internal="avs_eth_0.tse_waitrequest" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_tse_write" + internal="avs_eth_0.tse_write" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_tse_writedata" + internal="avs_eth_0.tse_writedata" + type="conduit" + dir="end" /> + <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" /> + <interface + name="jesd204b_address" + internal="jesd204b.address" + type="conduit" + dir="end" /> + <interface name="jesd204b_clk" internal="jesd204b.clk" type="conduit" dir="end" /> + <interface + name="jesd204b_read" + internal="jesd204b.read" + type="conduit" + dir="end" /> + <interface + name="jesd204b_readdata" + internal="jesd204b.readdata" + type="conduit" + dir="end" /> + <interface + name="jesd204b_reset" + internal="jesd204b.reset" + type="conduit" + dir="end" /> + <interface + name="jesd204b_write" + internal="jesd204b.write" + type="conduit" + dir="end" /> + <interface + name="jesd204b_writedata" + internal="jesd204b.writedata" + type="conduit" + dir="end" /> + <interface + name="pio_pps_address" + internal="pio_pps.address" + type="conduit" + dir="end" /> + <interface name="pio_pps_clk" internal="pio_pps.clk" type="conduit" dir="end" /> + <interface name="pio_pps_read" internal="pio_pps.read" type="conduit" dir="end" /> + <interface + name="pio_pps_readdata" + internal="pio_pps.readdata" + type="conduit" + dir="end" /> + <interface + name="pio_pps_reset" + internal="pio_pps.reset" + type="conduit" + dir="end" /> + <interface + name="pio_pps_write" + internal="pio_pps.write" + type="conduit" + dir="end" /> + <interface + name="pio_pps_writedata" + internal="pio_pps.writedata" + type="conduit" + dir="end" /> + <interface + name="pio_system_info_address" + internal="pio_system_info.address" + type="conduit" + dir="end" /> + <interface + name="pio_system_info_clk" + internal="pio_system_info.clk" + type="conduit" + dir="end" /> + <interface + name="pio_system_info_read" + internal="pio_system_info.read" + type="conduit" + dir="end" /> + <interface + name="pio_system_info_readdata" + internal="pio_system_info.readdata" + type="conduit" + dir="end" /> + <interface + name="pio_system_info_reset" + internal="pio_system_info.reset" + type="conduit" + dir="end" /> + <interface + name="pio_system_info_write" + internal="pio_system_info.write" + type="conduit" + dir="end" /> + <interface + name="pio_system_info_writedata" + internal="pio_system_info.writedata" + type="conduit" + dir="end" /> + <interface + name="pio_wdi_external_connection" + internal="pio_wdi.external_connection" + type="conduit" + dir="end" /> + <interface + name="ram_diag_data_buf_jesd_address" + internal="ram_diag_data_buffer_jesd.address" + type="conduit" + dir="end" /> + <interface + name="ram_diag_data_buf_jesd_clk" + internal="ram_diag_data_buffer_jesd.clk" + type="conduit" + dir="end" /> + <interface + name="ram_diag_data_buf_jesd_read" + internal="ram_diag_data_buffer_jesd.read" + type="conduit" + dir="end" /> + <interface + name="ram_diag_data_buf_jesd_readdata" + internal="ram_diag_data_buffer_jesd.readdata" + type="conduit" + dir="end" /> + <interface + name="ram_diag_data_buf_jesd_reset" + internal="ram_diag_data_buffer_jesd.reset" + type="conduit" + dir="end" /> + <interface + name="ram_diag_data_buf_jesd_write" + internal="ram_diag_data_buffer_jesd.write" + type="conduit" + dir="end" /> + <interface + name="ram_diag_data_buf_jesd_writedata" + internal="ram_diag_data_buffer_jesd.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_diag_data_buf_jesd_address" + internal="reg_diag_data_buffer_jesd.address" + type="conduit" + dir="end" /> + <interface + name="reg_diag_data_buf_jesd_clk" + internal="reg_diag_data_buffer_jesd.clk" + type="conduit" + dir="end" /> + <interface + name="reg_diag_data_buf_jesd_read" + internal="reg_diag_data_buffer_jesd.read" + type="conduit" + dir="end" /> + <interface + name="reg_diag_data_buf_jesd_readdata" + internal="reg_diag_data_buffer_jesd.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_diag_data_buf_jesd_reset" + internal="reg_diag_data_buffer_jesd.reset" + type="conduit" + dir="end" /> + <interface + name="reg_diag_data_buf_jesd_write" + internal="reg_diag_data_buffer_jesd.write" + type="conduit" + dir="end" /> + <interface + name="reg_diag_data_buf_jesd_writedata" + internal="reg_diag_data_buffer_jesd.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_ctrl_address" + internal="reg_dpmm_ctrl.address" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_ctrl_clk" + internal="reg_dpmm_ctrl.clk" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_ctrl_read" + internal="reg_dpmm_ctrl.read" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_ctrl_readdata" + internal="reg_dpmm_ctrl.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_ctrl_reset" + internal="reg_dpmm_ctrl.reset" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_ctrl_write" + internal="reg_dpmm_ctrl.write" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_ctrl_writedata" + internal="reg_dpmm_ctrl.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_data_address" + internal="reg_dpmm_data.address" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_data_clk" + internal="reg_dpmm_data.clk" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_data_read" + internal="reg_dpmm_data.read" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_data_readdata" + internal="reg_dpmm_data.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_data_reset" + internal="reg_dpmm_data.reset" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_data_write" + internal="reg_dpmm_data.write" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_data_writedata" + internal="reg_dpmm_data.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_epcs_address" + internal="reg_epcs.address" + type="conduit" + dir="end" /> + <interface name="reg_epcs_clk" internal="reg_epcs.clk" type="conduit" dir="end" /> + <interface + name="reg_epcs_read" + internal="reg_epcs.read" + type="conduit" + dir="end" /> + <interface + name="reg_epcs_readdata" + internal="reg_epcs.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_epcs_reset" + internal="reg_epcs.reset" + type="conduit" + dir="end" /> + <interface + name="reg_epcs_write" + internal="reg_epcs.write" + type="conduit" + dir="end" /> + <interface + name="reg_epcs_writedata" + internal="reg_epcs.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_temp_sens_address" + internal="reg_fpga_temp_sens.address" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_temp_sens_clk" + internal="reg_fpga_temp_sens.clk" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_temp_sens_read" + internal="reg_fpga_temp_sens.read" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_temp_sens_readdata" + internal="reg_fpga_temp_sens.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_temp_sens_reset" + internal="reg_fpga_temp_sens.reset" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_temp_sens_write" + internal="reg_fpga_temp_sens.write" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_temp_sens_writedata" + internal="reg_fpga_temp_sens.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_voltage_sens_address" + internal="reg_fpga_voltage_sens.address" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_voltage_sens_clk" + internal="reg_fpga_voltage_sens.clk" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_voltage_sens_read" + internal="reg_fpga_voltage_sens.read" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_voltage_sens_readdata" + internal="reg_fpga_voltage_sens.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_voltage_sens_reset" + internal="reg_fpga_voltage_sens.reset" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_voltage_sens_write" + internal="reg_fpga_voltage_sens.write" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_voltage_sens_writedata" + internal="reg_fpga_voltage_sens.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_ctrl_address" + internal="reg_mmdp_ctrl.address" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_ctrl_clk" + internal="reg_mmdp_ctrl.clk" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_ctrl_read" + internal="reg_mmdp_ctrl.read" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_ctrl_readdata" + internal="reg_mmdp_ctrl.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_ctrl_reset" + internal="reg_mmdp_ctrl.reset" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_ctrl_write" + internal="reg_mmdp_ctrl.write" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_ctrl_writedata" + internal="reg_mmdp_ctrl.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_data_address" + internal="reg_mmdp_data.address" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_data_clk" + internal="reg_mmdp_data.clk" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_data_read" + internal="reg_mmdp_data.read" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_data_readdata" + internal="reg_mmdp_data.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_data_reset" + internal="reg_mmdp_data.reset" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_data_write" + internal="reg_mmdp_data.write" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_data_writedata" + internal="reg_mmdp_data.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_remu_address" + internal="reg_remu.address" + type="conduit" + dir="end" /> + <interface name="reg_remu_clk" internal="reg_remu.clk" type="conduit" dir="end" /> + <interface + name="reg_remu_read" + internal="reg_remu.read" + type="conduit" + dir="end" /> + <interface + name="reg_remu_readdata" + internal="reg_remu.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_remu_reset" + internal="reg_remu.reset" + type="conduit" + dir="end" /> + <interface + name="reg_remu_write" + internal="reg_remu.write" + type="conduit" + dir="end" /> + <interface + name="reg_remu_writedata" + internal="reg_remu.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_unb_pmbus_address" + internal="reg_unb_pmbus.address" + type="conduit" + dir="end" /> + <interface + name="reg_unb_pmbus_clk" + internal="reg_unb_pmbus.clk" + type="conduit" + dir="end" /> + <interface + name="reg_unb_pmbus_read" + internal="reg_unb_pmbus.read" + type="conduit" + dir="end" /> + <interface + name="reg_unb_pmbus_readdata" + internal="reg_unb_pmbus.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_unb_pmbus_reset" + internal="reg_unb_pmbus.reset" + type="conduit" + dir="end" /> + <interface + name="reg_unb_pmbus_write" + internal="reg_unb_pmbus.write" + type="conduit" + dir="end" /> + <interface + name="reg_unb_pmbus_writedata" + internal="reg_unb_pmbus.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_unb_sens_address" + internal="reg_unb_sens.address" + type="conduit" + dir="end" /> + <interface + name="reg_unb_sens_clk" + internal="reg_unb_sens.clk" + type="conduit" + dir="end" /> + <interface + name="reg_unb_sens_read" + internal="reg_unb_sens.read" + type="conduit" + dir="end" /> + <interface + name="reg_unb_sens_readdata" + internal="reg_unb_sens.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_unb_sens_reset" + internal="reg_unb_sens.reset" + type="conduit" + dir="end" /> + <interface + name="reg_unb_sens_write" + internal="reg_unb_sens.write" + type="conduit" + dir="end" /> + <interface + name="reg_unb_sens_writedata" + internal="reg_unb_sens.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_wdi_address" + internal="reg_wdi.address" + type="conduit" + dir="end" /> + <interface name="reg_wdi_clk" internal="reg_wdi.clk" type="conduit" dir="end" /> + <interface name="reg_wdi_read" internal="reg_wdi.read" type="conduit" dir="end" /> + <interface + name="reg_wdi_readdata" + internal="reg_wdi.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_wdi_reset" + internal="reg_wdi.reset" + type="conduit" + dir="end" /> + <interface + name="reg_wdi_write" + internal="reg_wdi.write" + type="conduit" + dir="end" /> + <interface + name="reg_wdi_writedata" + internal="reg_wdi.writedata" + type="conduit" + dir="end" /> + <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" /> + <interface + name="rom_system_info_address" + internal="rom_system_info.address" + type="conduit" + dir="end" /> + <interface + name="rom_system_info_clk" + internal="rom_system_info.clk" + type="conduit" + dir="end" /> + <interface + name="rom_system_info_read" + internal="rom_system_info.read" + type="conduit" + dir="end" /> + <interface + name="rom_system_info_readdata" + internal="rom_system_info.readdata" + type="conduit" + dir="end" /> + <interface + name="rom_system_info_reset" + internal="rom_system_info.reset" + type="conduit" + dir="end" /> + <interface + name="rom_system_info_write" + internal="rom_system_info.write" + type="conduit" + dir="end" /> + <interface + name="rom_system_info_writedata" + internal="rom_system_info.writedata" + type="conduit" + dir="end" /> + <module + name="avs_eth_0" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>interrupt</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>ins_interrupt_irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>avs_eth_0.mms_reg</value> + </entry> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>associatedReset</key> + <value>mm_reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_irq_export</name> + <role>export</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mm</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_mm_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mm_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_mm_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mms_ram</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>mms_ram_address</name> + <role>address</role> + <direction>Input</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_ram_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_ram_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_ram_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_ram_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4096</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>associatedReset</key> + <value>mm_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>2</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mms_reg</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>mms_reg_address</name> + <role>address</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_reg_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_reg_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_reg_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_reg_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>64</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>associatedReset</key> + <value>mm_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mms_tse</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>mms_tse_address</name> + <role>address</role> + <direction>Input</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_tse_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_tse_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_tse_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_tse_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_tse_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4096</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>associatedReset</key> + <value>mm_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_waitrequest</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_waitrequest_export</name> + <role>export</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs2_eth_coe</className> + <version>1.0</version> + <displayName>avs2_eth_coe</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mms_ram</key> + <value> + <connectionPointName>mms_ram</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mms_ram' start='0x0' end='0x1000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>12</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>mms_reg</key> + <value> + <connectionPointName>mms_reg</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mms_reg' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>mms_tse</key> + <value> + <connectionPointName>mms_tse</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mms_tse' start='0x0' end='0x1000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>12</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_avs_eth_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="clk_0" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>100000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>100000000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>clock_source</className> + <displayName>Clock Source</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>inputClockFrequency</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk_in</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>clk_in</key> + <value> + <connectionPointName>clk_in</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>100000000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>100000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_clk_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_clk_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_clk_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_clk_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_clk_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_clk_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_clk_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="cpu_0" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>custom_instruction_master</name> + <type>nios_custom_instruction</type> + <isStart>true</isStart> + <ports> + <port> + <name>dummy_ci_port</name> + <role>readra</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>CIName</key> + <value></value> + </entry> + <entry> + <key>addressWidth</key> + <value>8</value> + </entry> + <entry> + <key>clockCycle</key> + <value>0</value> + </entry> + <entry> + <key>enabled</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>8</value> + </entry> + <entry> + <key>opcodeExtension</key> + <value>0</value> + </entry> + <entry> + <key>sharedCombinationalAndMulticycle</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>data_master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>d_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>d_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>d_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>d_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>d_address</name> + <role>address</role> + <direction>Output</direction> + <width>21</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>d_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>d_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>debug_mem_slave_debugaccess_to_roms</name> + <role>debugaccess</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>debug.providesServices</key> + <value>master</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>1</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>true</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>true</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>debug_mem_slave</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>debug_mem_slave_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>debug_mem_slave_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>debug_mem_slave_address</name> + <role>address</role> + <direction>Input</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>debug_mem_slave_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>debug_mem_slave_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>debug_mem_slave_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>debug_mem_slave_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>debug_mem_slave_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.hideDevice</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>qsys.ui.connect</key> + <value>instruction_master,data_master</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>2048</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>true</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>true</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>debug_reset_request</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>debug_reset_request</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>none</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>instruction_master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>i_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>i_address</name> + <role>address</role> + <direction>Output</direction> + <width>18</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>i_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>i_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>1</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>true</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>true</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>true</isStart> + <ports> + <port> + <name>irq</name> + <role>irq</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>cpu_0.data_master</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>irqMap</key> + </entry> + <entry> + <key>irqScheme</key> + <value>INDIVIDUAL_REQUESTS</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>reset_req</name> + <role>reset_req</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_nios2_gen2</className> + <version>18.0</version> + <displayName>Nios II Processor</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_CLK_CLOCK_DOMAIN</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_DOMAIN</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_CLK_RESET_DOMAIN</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>RESET_DOMAIN</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>AUTO_DEVICE</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>50000000</parameterDefaultValue> + <parameterName>clockFrequency</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>customInstSlavesSystemInfo</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>custom_instruction_master</systemInfoArgs> + <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>customInstSlavesSystemInfo_nios_a</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>custom_instruction_master_a</systemInfoArgs> + <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>customInstSlavesSystemInfo_nios_b</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>custom_instruction_master_b</systemInfoArgs> + <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>customInstSlavesSystemInfo_nios_c</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>custom_instruction_master_c</systemInfoArgs> + <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>dataAddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>data_master</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>dataMasterHighPerformanceAddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>data_master_high_performance</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>dataMasterHighPerformanceMapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>data_master_high_performance</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>dataSlaveMapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>data_master</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>STRATIXIV</parameterDefaultValue> + <parameterName>deviceFamilyName</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_FAMILY</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>deviceFeaturesSystemInfo</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_FEATURES</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>faAddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>flash_instruction_master</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>faSlaveMapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>flash_instruction_master</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>instAddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>instruction_master</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>instSlaveMapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>instruction_master</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>instructionMasterHighPerformanceAddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>instruction_master_high_performance</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>instructionMasterHighPerformanceMapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>instruction_master_high_performance</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>internalIrqMaskSystemInfo</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>irq</systemInfoArgs> + <systemInfotype>INTERRUPTS_USED</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster0AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_data_master_0</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster0MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_data_master_0</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster1AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_data_master_1</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster1MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_data_master_1</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster2AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_data_master_2</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster2MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_data_master_2</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster3AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_data_master_3</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster3MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_data_master_3</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster0AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_0</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster0MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_0</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster1AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_1</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster1MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_1</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster2AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_2</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster2MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_2</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster3AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_3</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster3MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_3</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_DOMAIN</key> + <value>1</value> + </entry> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + <entry> + <key>RESET_DOMAIN</key> + <value>1</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>custom_instruction_master</key> + <value> + <connectionPointName>custom_instruction_master</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CUSTOM_INSTRUCTION_SLAVES</key> + <value></value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>data_master</key> + <value> + <connectionPointName>data_master</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='jesd204b.mem' start='0x40000' end='0x44000' datawidth='32' /><slave name='ram_diag_data_buffer_jesd.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_diag_data_buffer_jesd.mem' start='0x100000' end='0x104000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>21</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>debug_mem_slave</key> + <value> + <connectionPointName>debug_mem_slave</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='debug_mem_slave' start='0x0' end='0x800' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>11</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>instruction_master</key> + <value> + <connectionPointName>instruction_master</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>18</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>irq</key> + <value> + <connectionPointName>irq</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>INTERRUPTS_USED</key> + <value>7</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_cpu_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_cpu_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_cpu_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_cpu_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_cpu_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_cpu_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_cpu_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap> + <entry> + <key>debug.hostConnection</key> + <value>type jtag id 70:34|110:135</value> + </entry> + <entry> + <key>embeddedsw.CMacro.BIG_ENDIAN</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.BREAK_ADDR</key> + <value>0x00003820</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</key> + <value></value> + </entry> + <entry> + <key>embeddedsw.CMacro.CPU_FREQ</key> + <value>100000000u</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CPU_ID_SIZE</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CPU_ID_VALUE</key> + <value>0x00000000</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CPU_IMPLEMENTATION</key> + <value>"tiny"</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DATA_ADDR_WIDTH</key> + <value>21</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DCACHE_LINE_SIZE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DCACHE_SIZE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.EXCEPTION_ADDR</key> + <value>0x00020020</value> + </entry> + <entry> + <key>embeddedsw.CMacro.FLASH_ACCELERATOR_LINES</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.FLUSHDA_SUPPORTED</key> + <value></value> + </entry> + <entry> + <key>embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HARDWARE_MULX_PRESENT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_DEBUG_CORE</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_DEBUG_STUB</key> + <value></value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION</key> + <value></value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_JMPI_INSTRUCTION</key> + <value></value> + </entry> + <entry> + <key>embeddedsw.CMacro.ICACHE_LINE_SIZE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.ICACHE_SIZE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.INST_ADDR_WIDTH</key> + <value>18</value> + </entry> + <entry> + <key>embeddedsw.CMacro.OCI_VERSION</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.RESET_ADDR</key> + <value>0x00020000</value> + </entry> + <entry> + <key>embeddedsw.configuration.DataCacheVictimBufImpl</key> + <value>ram</value> + </entry> + <entry> + <key>embeddedsw.configuration.HDLSimCachesCleared</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.breakOffset</key> + <value>32</value> + </entry> + <entry> + <key>embeddedsw.configuration.breakSlave</key> + <value>cpu_0.debug_mem_slave</value> + </entry> + <entry> + <key>embeddedsw.configuration.cpuArchitecture</key> + <value>Nios II</value> + </entry> + <entry> + <key>embeddedsw.configuration.exceptionOffset</key> + <value>32</value> + </entry> + <entry> + <key>embeddedsw.configuration.exceptionSlave</key> + <value>onchip_memory2_0.s1</value> + </entry> + <entry> + <key>embeddedsw.configuration.resetOffset</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.resetSlave</key> + <value>onchip_memory2_0.s1</value> + </entry> + <entry> + <key>embeddedsw.dts.compatible</key> + <value>altr,nios2-1.1</value> + </entry> + <entry> + <key>embeddedsw.dts.group</key> + <value>cpu</value> + </entry> + <entry> + <key>embeddedsw.dts.name</key> + <value>nios2</value> + </entry> + <entry> + <key>embeddedsw.dts.params.altr,exception-addr</key> + <value>0x00020020</value> + </entry> + <entry> + <key>embeddedsw.dts.params.altr,implementation</key> + <value>"tiny"</value> + </entry> + <entry> + <key>embeddedsw.dts.params.altr,reset-addr</key> + <value>0x00020000</value> + </entry> + <entry> + <key>embeddedsw.dts.params.clock-frequency</key> + <value>100000000u</value> + </entry> + <entry> + <key>embeddedsw.dts.params.dcache-line-size</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.params.dcache-size</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.params.icache-line-size</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.params.icache-size</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.vendor</key> + <value>altr</value> + </entry> + </assignmentValueMap> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="jesd204b" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>12</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>12</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>16384</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>14</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_avs_common_mm_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="jtag_uart_0" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>avalon_jtag_slave</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_read_n</name> + <role>read_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>av_write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>1</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>2</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>true</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > + <peripherals> + <peripheral> + <name>altera_avalon_jtag_uart</name><baseAddress>0x00000000</baseAddress> + <addressBlock> + <offset>0x0</offset> + <size>8</size> + <usage>registers</usage> + </addressBlock> + <registers> + <register> + <name>DATA</name> + <displayName>Data</displayName> + <description>Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.</description> + <addressOffset>0x0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>data</name> + <description>The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field><name>rvalid</name> + <description>Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.</description> + <bitOffset>0xf</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field><name>ravail</name> + <description>The number of characters remaining in the read FIFO (after the current read).</description> + <bitOffset>0x10</bitOffset> + <bitWidth>16</bitWidth> + <access>read-only</access> + </field> + </fields> + </register> + <register> + <name>CONTROL</name> + <displayName>Control</displayName> + <description>Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.</description> + <addressOffset>0x4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>re</name> + <description>Interrupt-enable bit for read interrupts.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field><name>we</name> + <description>Interrupt-enable bit for write interrupts</description> + <bitOffset>0x1</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field><name>ri</name> + <description>Indicates that the read interrupt is pending.</description> + <bitOffset>0x8</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field><name>wi</name> + <description>Indicates that the write interrupt is pending.</description> + <bitOffset>0x9</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field><name>ac</name> + <description>Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.</description> + <bitOffset>0xa</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field><name>wspace</name> + <description>The number of spaces available in the write FIFO</description> + <bitOffset>0x10</bitOffset> + <bitWidth>16</bitWidth> + <access>read-only</access> + </field> + </fields> + </register> + </registers> + </peripheral> + </peripherals> +</device> </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>jtag_uart_0.avalon_jtag_slave</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_avalon_jtag_uart</className> + <version>18.0</version> + <displayName>JTAG UART Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>avalonSpec</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>AVALON_SPEC</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>clkFreq</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>avalon_jtag_slave</key> + <value> + <connectionPointName>avalon_jtag_slave</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='avalon_jtag_slave' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_jtag_uart_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap> + <entry> + <key>embeddedsw.CMacro.READ_DEPTH</key> + <value>64</value> + </entry> + <entry> + <key>embeddedsw.CMacro.READ_THRESHOLD</key> + <value>8</value> + </entry> + <entry> + <key>embeddedsw.CMacro.WRITE_DEPTH</key> + <value>64</value> + </entry> + <entry> + <key>embeddedsw.CMacro.WRITE_THRESHOLD</key> + <value>8</value> + </entry> + <entry> + <key>embeddedsw.dts.compatible</key> + <value>altr,juart-1.0</value> + </entry> + <entry> + <key>embeddedsw.dts.group</key> + <value>serial</value> + </entry> + <entry> + <key>embeddedsw.dts.name</key> + <value>juart</value> + </entry> + <entry> + <key>embeddedsw.dts.vendor</key> + <value>altr</value> + </entry> + </assignmentValueMap> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="onchip_memory2_0" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk1</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset1</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>reset_req</name> + <role>reset_req</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk1</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>15</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>clken</name> + <role>clken</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>131072</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk1</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset1</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>131072</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>true</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_avalon_onchip_memory2</className> + <version>18.0</version> + <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>autoInitializationFileName</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>UNIQUE_ID</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>NONE</parameterDefaultValue> + <parameterName>deviceFamily</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_FAMILY</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>NONE</parameterDefaultValue> + <parameterName>deviceFeatures</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_FEATURES</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>s1</key> + <value> + <connectionPointName>s1</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='s1' start='0x0' end='0x20000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>17</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_onchip_memory2_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap> + <entry> + <key>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CONTENTS_INFO</key> + <value>""</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DUAL_PORT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</key> + <value>AUTO</value> + </entry> + <entry> + <key>embeddedsw.CMacro.INIT_CONTENTS_FILE</key> + <value>onchip_memory2_0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.INIT_MEM_CONTENT</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.INSTANCE_ID</key> + <value>NONE</value> + </entry> + <entry> + <key>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.RAM_BLOCK_TYPE</key> + <value>AUTO</value> + </entry> + <entry> + <key>embeddedsw.CMacro.READ_DURING_WRITE_MODE</key> + <value>DONT_CARE</value> + </entry> + <entry> + <key>embeddedsw.CMacro.SINGLE_CLOCK_OP</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.SIZE_MULTIPLE</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.SIZE_VALUE</key> + <value>131072</value> + </entry> + <entry> + <key>embeddedsw.CMacro.WRITABLE</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</key> + <value>SIM_DIR</value> + </entry> + <entry> + <key>embeddedsw.memoryInfo.GENERATE_DAT_SYM</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.memoryInfo.GENERATE_HEX</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.memoryInfo.HAS_BYTE_LANE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.memoryInfo.HEX_INSTALL_DIR</key> + <value>QPF_DIR</value> + </entry> + <entry> + <key>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</key> + <value>32</value> + </entry> + <entry> + <key>embeddedsw.memoryInfo.MEM_INIT_FILENAME</key> + <value>onchip_memory2_0</value> + </entry> + <entry> + <key>postgeneration.simulation.init_file.param_name</key> + <value>INIT_FILE</value> + </entry> + <entry> + <key>postgeneration.simulation.init_file.type</key> + <value>MEM_INIT</value> + </entry> + </assignmentValueMap> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="pio_pps" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_pio_pps</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_pio_pps</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_pps</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_pio_pps</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_pps</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_pio_pps</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_pps</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="pio_system_info" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>5</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>5</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>128</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>7</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_pio_system_info</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="pio_wdi" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>external_connection</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>out_port</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > + <peripherals> + <peripheral> + <name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress> + <addressBlock> + <offset>0x0</offset> + <size>32</size> + <usage>registers</usage> + </addressBlock> + <registers> + <register> + <name>DATA</name> + <displayName>Data</displayName> + <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description> + <addressOffset>0x0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>data</name> + <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>DIRECTION</name> + <displayName>Direction</displayName> + <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description> + <addressOffset>0x4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>direction</name> + <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>IRQ_MASK</name> + <displayName>Interrupt mask</displayName> + <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description> + <addressOffset>0x8</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>interruptmask</name> + <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>EDGE_CAP</name> + <displayName>Edge capture</displayName> + <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description> + <addressOffset>0xc</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>edgecapture</name> + <description>Edge detection for each input port.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>SET_BIT</name> + <displayName>Outset</displayName> + <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description> + <addressOffset>0x10</addressOffset> + <size>32</size> + <access>write-only</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>outset</name> + <description>Specifies which bit of the output port to set.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>write-only</access> + </field> + </fields> + </register> + <register> + <name>CLEAR_BITS</name> + <displayName>Outclear</displayName> + <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description> + <addressOffset>0x14</addressOffset> + <size>32</size> + <access>write-only</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>outclear</name> + <description>Specifies which output bit to clear.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>write-only</access> + </field> + </fields> + </register> + </registers> + </peripheral> + </peripherals> +</device> </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_avalon_pio</className> + <version>18.0</version> + <displayName>PIO (Parallel I/O) Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>clockRate</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>s1</key> + <value> + <connectionPointName>s1</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>4</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_pio_wdi</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap> + <entry> + <key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CAPTURE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DATA_WIDTH</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.EDGE_TYPE</key> + <value>NONE</value> + </entry> + <entry> + <key>embeddedsw.CMacro.FREQ</key> + <value>100000000</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_IN</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_OUT</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_TRI</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.IRQ_TYPE</key> + <value>NONE</value> + </entry> + <entry> + <key>embeddedsw.CMacro.RESET_VALUE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.compatible</key> + <value>altr,pio-1.0</value> + </entry> + <entry> + <key>embeddedsw.dts.group</key> + <value>gpio</value> + </entry> + <entry> + <key>embeddedsw.dts.name</key> + <value>pio</value> + </entry> + <entry> + <key>embeddedsw.dts.params.altr,gpio-bank-width</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.dts.params.resetvalue</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.vendor</key> + <value>altr</value> + </entry> + </assignmentValueMap> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="ram_diag_data_buffer_jesd" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>17</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>17</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>524288</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x80000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>19</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_avs_common_mm_1</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_1</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_1</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_1</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_1</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_1</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_1</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_diag_data_buffer_jesd" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>12</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>12</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>16384</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>14</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_avs_common_mm_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_dpmm_ctrl" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_dpmm_data" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_dpmm_data</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_epcs" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_epcs</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_fpga_temp_sens" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_fpga_voltage_sens" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>64</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_mmdp_ctrl" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_mmdp_data" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_mmdp_data</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_remu" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_remu</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_remu</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_remu</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_remu</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_remu</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_remu</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_remu</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_unb_pmbus" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>256</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>8</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_unb_sens" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>256</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>8</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_unb_sens</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_wdi" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_wdi</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="rom_system_info" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4096</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>12</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_rom_system_info</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_rom_system_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_rom_system_info</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_rom_system_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_rom_system_info</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_rom_system_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_rom_system_info</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="timer_0" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>timer_0.s1</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isTimerDevice</key> + <value>1</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > + <peripherals> + <peripheral> + <name>altera_avalon_timer</name><baseAddress>0x00000000</baseAddress> + <addressBlock> + <offset>0x0</offset> + <size>16</size> + <usage>registers</usage> + </addressBlock> + <registers> + <register> + <name>status</name> + <displayName>Status</displayName> + <description>The status register has two defined bits. TO (timeout), RUN</description> + <addressOffset>0x0</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + <fields> + <field><name>TO</name> + <description>The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + <readAction>clear</readAction> + </field> + <field><name>RUN</name> + <description>The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by + a write operation to the status register.</description> + <bitOffset>1</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field> + <name>Reserved</name> + <description>Reserved</description> + <bitOffset>2</bitOffset> + <bitWidth>14</bitWidth> + <access>read-write</access> + <parameters> + <parameter> + <name>Reserved</name> + <value>true</value> + </parameter> + </parameters> + </field> + </fields> + </register> + <register> + <name>control</name> + <description>The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP</description> + <addressOffset>0x1</addressOffset> + <size>16</size> + <access>read-write</access> + <reset> + <value>0x0</value> + </reset> + <field> + <name>ITO</name> + <description>If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CONT</name> + <description>The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.</description> + <bitOffset>1</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>START</name> + <description>Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.</description> + <bitOffset>2</bitOffset> + <bitWidth>1</bitWidth> + <access>write-only</access> + </field> + <field> + <name>STOP</name> + <description>Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.</description> + <bitOffset>3</bitOffset> + <bitWidth>1</bitWidth> + <access>write-only</access> + </field> + <field> + <name>Reserved</name> + <description>Reserved</description> + <bitOffset>4</bitOffset> + <bitWidth>12</bitWidth> + <access>read-write</access> + <parameters> + <parameter> + <name>Reserved</name> + <value>true</value> + </parameter> + </parameters> + </field> + </register> + <register> + <name>${period_name_0}</name> + <description>The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.</description> + <addressOffset>0x2</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_name_0_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${period_name_1}</name> + <description></description> + <addressOffset>0x3</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_name_1_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${period_snap_0}</name> + <description></description> + <addressOffset>0x4</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_snap_0_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${period_snap_1}</name> + <description></description> + <addressOffset>0x5</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_snap_1_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_0}</name> + <description>A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.</description> + <addressOffset>0x6</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_1}</name> + <description></description> + <addressOffset>0x7</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_2}</name> + <description></description> + <addressOffset>0x8</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_3}</name> + <description></description> + <addressOffset>0x9</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + </registers> + </peripheral> + </peripherals> +</device> </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars> + <entry> + <key>period_name_1_reset_value</key> + <value>0x1</value> + </entry> + <entry> + <key>snap_0</key> + <value>Reserved</value> + </entry> + <entry> + <key>period_name_0_reset_value</key> + <value>0x869f</value> + </entry> + <entry> + <key>snap_2</key> + <value>Reserved</value> + </entry> + <entry> + <key>snap_1</key> + <value>Reserved</value> + </entry> + <entry> + <key>snap_3</key> + <value>Reserved</value> + </entry> + <entry> + <key>period_name_0</key> + <value>periodl</value> + </entry> + <entry> + <key>period_name_1</key> + <value>periodh</value> + </entry> + <entry> + <key>period_snap_1</key> + <value>snaph</value> + </entry> + <entry> + <key>period_snap_1_reset_value</key> + <value>0x0</value> + </entry> + <entry> + <key>period_snap_0_reset_value</key> + <value>0x0</value> + </entry> + <entry> + <key>period_snap_0</key> + <value>snapl</value> + </entry> + </cmsisVars> + </cmsisInfo> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_avalon_timer</className> + <version>18.0</version> + <displayName>Interval Timer Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>systemFrequency</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>s1</key> + <value> + <connectionPointName>s1</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='s1' start='0x0' end='0x20' datawidth='16' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>16</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="defaultBoundary" value="" /> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_adc_timer_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_timer_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_timer_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_timer_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_timer_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_adc_timer_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_adc_timer_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap> + <entry> + <key>embeddedsw.CMacro.ALWAYS_RUN</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.COUNTER_SIZE</key> + <value>32</value> + </entry> + <entry> + <key>embeddedsw.CMacro.FIXED_PERIOD</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.FREQ</key> + <value>100000000</value> + </entry> + <entry> + <key>embeddedsw.CMacro.LOAD_VALUE</key> + <value>99999</value> + </entry> + <entry> + <key>embeddedsw.CMacro.MULT</key> + <value>0.001</value> + </entry> + <entry> + <key>embeddedsw.CMacro.PERIOD</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.PERIOD_UNITS</key> + <value>ms</value> + </entry> + <entry> + <key>embeddedsw.CMacro.RESET_OUTPUT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.SNAPSHOT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.TICKS_PER_SEC</key> + <value>1000</value> + </entry> + <entry> + <key>embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.vendor</key> + <value>altr</value> + </entry> + </assignmentValueMap> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="jtag_uart_0.avalon_jtag_slave"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x03b8" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="cpu_0.debug_mem_slave"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x3800" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="reg_unb_sens.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0200" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="rom_system_info.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x1000" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="pio_system_info.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="pio_pps.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x03b0" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="reg_wdi.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x3000" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="reg_remu.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0360" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="reg_epcs.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0340" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="reg_dpmm_ctrl.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x03a8" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="reg_dpmm_data.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x03a0" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="reg_mmdp_ctrl.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0398" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="reg_mmdp_data.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0390" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="reg_fpga_temp_sens.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0320" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="reg_unb_pmbus.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0100" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="reg_fpga_voltage_sens.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x00c0" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="reg_diag_data_buffer_jesd.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x00100000" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="ram_diag_data_buffer_jesd.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x00080000" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="jesd204b.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x00040000" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="avs_eth_0.mms_ram"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x4000" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="avs_eth_0.mms_reg"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0080" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="avs_eth_0.mms_tse"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x2000" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="onchip_memory2_0.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x00020000" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="pio_wdi.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0380" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.data_master" + end="timer_0.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0300" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.instruction_master" + end="cpu_0.debug_mem_slave"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x3800" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection + kind="avalon" + version="19.4" + start="cpu_0.instruction_master" + end="onchip_memory2_0.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x00020000" /> + <parameter name="defaultConnection" value="false" /> + <parameter name="domainAlias" value="" /> + <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" /> + <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="qsys_mm.enableEccProtection" value="FALSE" /> + <parameter name="qsys_mm.enableInstrumentation" value="FALSE" /> + <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" /> + <parameter name="qsys_mm.interconnectType" value="STANDARD" /> + <parameter name="qsys_mm.maxAdditionalLatency" value="1" /> + <parameter name="qsys_mm.syncResets" value="FALSE" /> + <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" /> + </connection> + <connection kind="clock" version="19.4" start="clk_0.clk" end="jtag_uart_0.clk" /> + <connection kind="clock" version="19.4" start="clk_0.clk" end="pio_wdi.clk" /> + <connection kind="clock" version="19.4" start="clk_0.clk" end="timer_0.clk" /> + <connection kind="clock" version="19.4" start="clk_0.clk" end="cpu_0.clk" /> + <connection + kind="clock" + version="19.4" + start="clk_0.clk" + end="onchip_memory2_0.clk1" /> + <connection kind="clock" version="19.4" start="clk_0.clk" end="avs_eth_0.mm" /> + <connection + kind="clock" + version="19.4" + start="clk_0.clk" + end="reg_unb_sens.system" /> + <connection + kind="clock" + version="19.4" + start="clk_0.clk" + end="rom_system_info.system" /> + <connection + kind="clock" + version="19.4" + start="clk_0.clk" + end="pio_system_info.system" /> + <connection kind="clock" version="19.4" start="clk_0.clk" end="pio_pps.system" /> + <connection kind="clock" version="19.4" start="clk_0.clk" end="reg_wdi.system" /> + <connection kind="clock" version="19.4" start="clk_0.clk" end="reg_remu.system" /> + <connection kind="clock" version="19.4" start="clk_0.clk" end="reg_epcs.system" /> + <connection + kind="clock" + version="19.4" + start="clk_0.clk" + end="reg_dpmm_ctrl.system" /> + <connection + kind="clock" + version="19.4" + start="clk_0.clk" + end="reg_mmdp_data.system" /> + <connection + kind="clock" + version="19.4" + start="clk_0.clk" + end="reg_dpmm_data.system" /> + <connection + kind="clock" + version="19.4" + start="clk_0.clk" + end="reg_mmdp_ctrl.system" /> + <connection + kind="clock" + version="19.4" + start="clk_0.clk" + end="reg_fpga_temp_sens.system" /> + <connection + kind="clock" + version="19.4" + start="clk_0.clk" + end="reg_unb_pmbus.system" /> + <connection + kind="clock" + version="19.4" + start="clk_0.clk" + end="reg_fpga_voltage_sens.system" /> + <connection + kind="clock" + version="19.4" + start="clk_0.clk" + end="reg_diag_data_buffer_jesd.system" /> + <connection + kind="clock" + version="19.4" + start="clk_0.clk" + end="ram_diag_data_buffer_jesd.system" /> + <connection kind="clock" version="19.4" start="clk_0.clk" end="jesd204b.system" /> + <connection + kind="interrupt" + version="19.4" + start="cpu_0.irq" + end="avs_eth_0.interrupt"> + <parameter name="irqNumber" value="0" /> + </connection> + <connection + kind="interrupt" + version="19.4" + start="cpu_0.irq" + end="jtag_uart_0.irq"> + <parameter name="irqNumber" value="1" /> + </connection> + <connection kind="interrupt" version="19.4" start="cpu_0.irq" end="timer_0.irq"> + <parameter name="irqNumber" value="2" /> + </connection> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="avs_eth_0.mm_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="jtag_uart_0.reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="pio_wdi.reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="timer_0.reset" /> + <connection kind="reset" version="19.4" start="clk_0.clk_reset" end="cpu_0.reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="onchip_memory2_0.reset1" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="reg_unb_sens.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="rom_system_info.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="pio_system_info.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="pio_pps.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="reg_wdi.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="reg_remu.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="reg_epcs.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="reg_dpmm_ctrl.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="reg_mmdp_data.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="reg_mmdp_ctrl.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="reg_dpmm_data.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="reg_fpga_temp_sens.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="reg_unb_pmbus.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="reg_fpga_voltage_sens.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="reg_diag_data_buffer_jesd.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="ram_diag_data_buffer_jesd.system_reset" /> + <connection + kind="reset" + version="19.4" + start="clk_0.clk_reset" + end="jesd204b.system_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="avs_eth_0.mm_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="jtag_uart_0.reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="pio_wdi.reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="timer_0.reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="cpu_0.reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="onchip_memory2_0.reset1" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="reg_unb_sens.system_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="rom_system_info.system_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="pio_system_info.system_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="pio_pps.system_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="reg_wdi.system_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="reg_remu.system_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="reg_epcs.system_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="reg_dpmm_ctrl.system_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="reg_mmdp_data.system_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="reg_dpmm_data.system_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="reg_mmdp_ctrl.system_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="reg_fpga_temp_sens.system_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="reg_unb_pmbus.system_reset" /> + <connection + kind="reset" + version="19.4" + start="cpu_0.debug_reset_request" + end="reg_fpga_voltage_sens.system_reset" /> +</system> diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg index 768c2d6fb33db36c272c76b6829cc510a40b772b..b464691b6fce14b05a122c808f46b4a5d935fc82 100644 --- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg +++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg @@ -29,45 +29,45 @@ quartus_copy_files = ../../src/hex hex quartus_qsf_files = - $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf + $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf quartus_sdc_pre_files = - ../../quartus/lofar_unb2b_adc.sdc + ../../quartus/lofar2_unb2b_adc.sdc quartus_sdc_files = $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc quartus_tcl_files = - ../../quartus/lofar_unb2b_adc_pins.tcl + ../../quartus/lofar2_unb2b_adc_pins.tcl quartus_vhdl_files = quartus_qip_files = - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar_unb2b_adc_full/qsys_lofar_unb2b_adc/qsys_lofar_unb2b_adc.qip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_full/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip quartus_ip_files = - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2 diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg index a26f0fb9ee70e88b0cadb265c7292943f5c3dccb..1d2a4835d5ece5aafd05140e6ba10604d0b77a57 100644 --- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg +++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg @@ -27,45 +27,45 @@ quartus_copy_files = ../../src/hex hex quartus_qsf_files = - $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf + $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf quartus_sdc_pre_files = - ../../quartus/lofar_unb2b_adc.sdc + ../../quartus/lofar2_unb2b_adc.sdc quartus_sdc_files = $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc quartus_tcl_files = - ../../quartus/lofar_unb2b_adc_pins.tcl + ../../quartus/lofar2_unb2b_adc_pins.tcl quartus_vhdl_files = quartus_qip_files = - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar_unb2b_adc_one_node/qsys_lofar_unb2b_adc/qsys_lofar_unb2b_adc.qip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_one_node/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip quartus_ip_files = - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip - $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2 diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd index c76f0c9a933305a65da4d5efc905b888f923ca46..45374605192106d7e7d3becb415cb8f3718292c6 100644 --- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd +++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd @@ -121,7 +121,7 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS SIGNAL xo_rst : STD_LOGIC; SIGNAL xo_rst_n : STD_LOGIC; SIGNAL mm_clk : STD_LOGIC; - SIGNAL mm_rst : STD_LOGIC; + SIGNAL mm_rst : STD_LOGIC := '0'; SIGNAL st_rst : STD_LOGIC; SIGNAL st_clk : STD_LOGIC; @@ -192,8 +192,8 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS SIGNAL reg_remu_miso : t_mem_miso; -- JESD - SIGNAL jesd204b_mosi : t_mem_mosi; - SIGNAL jesd204b_miso : t_mem_miso; + SIGNAL jesd204b_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL jesd204b_miso : t_mem_miso := c_mem_miso_rst; -- WG SIGNAL reg_wg_mosi_arr : t_mem_mosi_arr(c_nof_streams_input-1 DOWNTO 0); @@ -443,7 +443,6 @@ BEGIN u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b GENERIC MAP( g_sim => g_sim, - g_sim_level => 1, g_nof_channels => c_nof_streams_jesd204b ) PORT MAP( diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd new file mode 100644 index 0000000000000000000000000000000000000000..7b201d484f6a7be52d9e2ed83a3eadbac3488f50 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd @@ -0,0 +1,502 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2018 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +-- Author: Jonathan Hargreaves +-- Purpose: Tb to show that lofar2_unb2b_adc can simulate +-- Description: +-- Must use c_sim = TRUE to speed up simulation +-- This is a compile-only test bench +-- Usage: +-- Load sim # check that design can load in vsim +-- > as 10 # check that the hierarchy for g_design_name is complete +-- > run -a # check that design can simulate some us without error + +LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, ip_arria10_e1sg_jesd204b_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_lib.common_pkg.ALL; +USE unb2b_board_lib.unb2b_board_pkg.ALL; +USE common_lib.tb_common_pkg.ALL; +USE ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.ALL; + +ENTITY tb_lofar2_unb2b_adc_multichannel IS +END tb_lofar2_unb2b_adc_multichannel; + +ARCHITECTURE tb OF tb_lofar2_unb2b_adc_multichannel IS + + CONSTANT c_sim : BOOLEAN := TRUE; + CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0 + CONSTANT c_node_nr : NATURAL := 0; -- Back node 3 + CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; + CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0); + + CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard + CONSTANT c_ext_clk_period : TIME := 5 ns; + CONSTANT c_jesd204b_sampclk_period : TIME := 5 ns; + CONSTANT c_pps_period : NATURAL := 1000; + CONSTANT c_bondingclk_period : TIME := 10 ns; + CONSTANT c_sysref_period : NATURAL := 10000; -- number of sample clocks between sysref pulses + + -- Transport delays + TYPE t_time_arr IS ARRAY (0 TO 11) OF TIME; + CONSTANT c_nof_jesd204b_tx : NATURAL := 3; -- number of jesd204b input sources to instantiate + CONSTANT c_delay_data_arr : t_time_arr := (4000 ps, + 5000 ps, + 6000 ps, + 5000 ps, + 5000 ps, + 5000 ps, + 5000 ps, + 5000 ps, + 5000 ps, + 5000 ps, + 5000 ps, + 5000 ps) ; -- transport delays tx to rx data + CONSTANT c_delay_sysreftoadc_arr : t_time_arr := (4000 ps, + 5000 ps, + 6000 ps, + 1000 ps, + 1000 ps, + 1000 ps, + 1000 ps, + 1000 ps, + 1000 ps, + 1000 ps, + 1000 ps, + 1000 ps) ; -- transport delays clock source to adc(tx) + CONSTANT c_delay_sysreftofpga : TIME := 10200 ps; + + + + -- clocks and resets for the jesd204b tx + SIGNAL txlink_clk : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0); + SIGNAL dev_sync_n : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0); + SIGNAL txphy_clk : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0); + SIGNAL mm_rst : STD_LOGIC; + SIGNAL avs_rst_n : STD_LOGIC; + SIGNAL txlink_rst_n : STD_LOGIC; + SIGNAL tx_analogreset : STD_LOGIC_VECTOR(0 downto 0); + SIGNAL tx_digitalreset : STD_LOGIC_VECTOR(0 downto 0); + SIGNAL tx_bonding_clocks : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); + SIGNAL bonding_clock_0 : STD_LOGIC := '0'; + SIGNAL bonding_clock_1 : STD_LOGIC := '0'; + SIGNAL bonding_clock_2 : STD_LOGIC := '0'; + SIGNAL bonding_clock_3 : STD_LOGIC := '0'; + SIGNAL bonding_clock_4 : STD_LOGIC := '0'; + SIGNAL bonding_clock_5 : STD_LOGIC := '0'; + SIGNAL pll_locked : STD_LOGIC_VECTOR(0 downto 0); + + CONSTANT c_mm_clk_period : TIME := 20 ns; + SIGNAL mm_clk : STD_LOGIC := '0'; + + -- Tb + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL sim_done : STD_LOGIC := '0'; + + -- DUT + SIGNAL ext_clk : STD_LOGIC := '0'; + SIGNAL pps : STD_LOGIC := '0'; + SIGNAL pps_rst : STD_LOGIC := '0'; + + SIGNAL WDI : STD_LOGIC; + SIGNAL INTA : STD_LOGIC; + SIGNAL INTB : STD_LOGIC; + + SIGNAL eth_clk : STD_LOGIC := '0'; + SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0); + SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0); + + SIGNAL sens_scl : STD_LOGIC; + SIGNAL sens_sda : STD_LOGIC; + SIGNAL pmbus_scl : STD_LOGIC; + SIGNAL pmbus_sda : STD_LOGIC; + + -- serial transceivers + SIGNAL serial_tx : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0); + SIGNAL bck_rx : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0) := (others => '0'); + + -- jesd204b syncronization signals and delayed copies + SIGNAL jesd204b_sysref : STD_LOGIC; + SIGNAL jesd204b_sampclk : STD_LOGIC := '0'; + + SIGNAL jesd204b_sampclk_fpga : STD_LOGIC := '1'; + SIGNAL jesd204b_sampclk_adc : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL jesd204b_sysref_fpga : STD_LOGIC; + SIGNAL jesd204b_sysref_adc : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL jesd204b_sysref_adc_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL jesd204b_sysref_adc_2 : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL jesd204b_sync_adc : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL jesd204b_sync_fpga : STD_LOGIC_VECTOR(11 DOWNTO 0); + + -- Test bench data + SIGNAL jesd204b_tx_link_data_arr : t_slv_32_arr(11 DOWNTO 0); + SIGNAL jesd204b_tx_link_valid : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL jesd204b_tx_link_ready : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL jesd204b_tx_frame_ready : STD_LOGIC_VECTOR(11 DOWNTO 0); + + -- Diagnostic signals + SIGNAL avs_chipselect : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL avs_read : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL avs_readdata : t_slv_32_arr(11 DOWNTO 0); + SIGNAL avs_address : t_slv_8_arr(11 DOWNTO 0); + +BEGIN + + + ---------------------------------------------------------------------------- + -- System setup + ---------------------------------------------------------------------------- + ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz) + eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz) + + INTA <= 'H'; -- pull up + INTB <= 'H'; -- pull up + + sens_scl <= 'H'; -- pull up + sens_sda <= 'H'; -- pull up + pmbus_scl <= 'H'; -- pull up + pmbus_sda <= 'H'; -- pull up + + ------------------------------------------------------------------------------ + -- External PPS + ------------------------------------------------------------------------------ + proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps); + --jesd204b_sysref <= pps; + + ------------------------------------------------------------------------------ + -- DUT + ------------------------------------------------------------------------------ + u_lofar_unb2b_adc : ENTITY work.lofar2_unb2b_adc + GENERIC MAP ( + g_design_name => "lofar2_unb2b_adc_one_node", + g_design_note => "Lofar2 adc with one node", + g_sim => c_sim, + g_sim_unb_nr => c_unb_nr, + g_sim_node_nr => c_node_nr + ) + PORT MAP ( + -- GENERAL + CLK => ext_clk, + PPS => pps, + WDI => WDI, + INTA => INTA, + INTB => INTB, + + -- Others + VERSION => c_version, + ID => c_id, + TESTIO => open, + + -- I2C Interface to Sensors + SENS_SC => sens_scl, + SENS_SD => sens_sda, + + PMBUS_SC => pmbus_scl, + PMBUS_SD => pmbus_sda, + PMBUS_ALERT => open, + + -- 1GbE Control Interface + ETH_CLK => eth_clk, + ETH_SGIN => eth_rxp, + ETH_SGOUT => eth_txp, + + -- LEDs + QSFP_LED => open, + + -- back transceivers + BCK_RX => bck_rx, + BCK_REF_CLK => jesd204b_sampclk_fpga, + + -- jesd204b syncronization signals + JESD204B_SYSREF => jesd204b_sysref_fpga, + JESD204B_SYNC => jesd204b_sync_fpga + ); + + + ----------------------------------------------------------------------------- + -- Transport + ----------------------------------------------------------------------------- + + gen_transport : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE + jesd204b_sampclk_adc(i) <= transport jesd204b_sampclk after c_delay_sysreftoadc_arr(i); + jesd204b_sysref_adc(i) <= transport jesd204b_sysref after c_delay_sysreftoadc_arr(i); +-- txlink_clk(i) <= jesd204b_sampclk_div2 after c_delay_sysreftoadc_arr(i); + bck_rx(i) <= transport serial_tx(i) after c_delay_data_arr(i); + jesd204b_sync_adc(i) <= transport jesd204b_sync_fpga(i) after c_delay_data_arr(i); + END GENERATE; + + jesd204b_sampclk_fpga <= transport jesd204b_sampclk after c_delay_sysreftofpga; + jesd204b_sysref_fpga <= transport jesd204b_sysref after c_delay_sysreftofpga; + + ----------------------------------------------------------------------------- + -- Use a jesd204b instance in TX-ONLY modeTransmit Only. + ----------------------------------------------------------------------------- + + gen_jesd204b_tx : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE + u_ip_arria10_e1sg_jesd204b_tx : ip_arria10_e1sg_jesd204b_tx + PORT MAP + ( + csr_cf => OPEN, + csr_cs => OPEN, + csr_f => OPEN, + csr_hd => OPEN, + csr_k => OPEN, + csr_l => OPEN, + csr_lane_powerdown => open, --out + csr_m => OPEN, + csr_n => OPEN, + csr_np => OPEN, + csr_tx_testmode => OPEN, + csr_tx_testpattern_a => OPEN, + csr_tx_testpattern_b => OPEN, + csr_tx_testpattern_c => OPEN, + csr_tx_testpattern_d => OPEN, + csr_s => OPEN, + dev_sync_n => dev_sync_n(i), --out + jesd204_tx_avs_chipselect => avs_chipselect(i), --jesd204b_mosi_arr(i).chipselect, + jesd204_tx_avs_address => avs_address(i), + jesd204_tx_avs_read => avs_read(i), + jesd204_tx_avs_readdata => avs_readdata(i), + jesd204_tx_avs_waitrequest => open, + jesd204_tx_avs_write => '0', + jesd204_tx_avs_writedata => (others => '0'), + jesd204_tx_avs_clk => mm_clk, + jesd204_tx_avs_rst_n => avs_rst_n, + jesd204_tx_dlb_data => open, -- debug/loopback testing + jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing + jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i), + jesd204_tx_frame_error => '0', + jesd204_tx_int => OPEN, -- Connected to status IO in example design + jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), --in + jesd204_tx_link_valid => jesd204b_tx_link_valid(i), --in + jesd204_tx_link_ready => jesd204b_tx_link_ready(i), --out + mdev_sync_n => dev_sync_n(i), --in + pll_locked => pll_locked, --in + sync_n => jesd204b_sync_adc(i), --in + tx_analogreset => tx_analogreset, + tx_bonding_clocks => tx_bonding_clocks,--: in std_logic_vector(5 downto 0) := (others => 'X'); -- clk + tx_cal_busy => open, + tx_digitalreset => tx_digitalreset, + tx_serial_data => serial_tx(i downto i), + txlink_clk => txlink_clk(i), + txlink_rst_n_reset_n => txlink_rst_n, + txphy_clk => txphy_clk(i downto i), + somf => OPEN, + sysref => jesd204b_sysref_adc(i) + ); + + -- Generate test pattern at each ADC + + proc_data : PROCESS (jesd204b_sampclk_adc(i), mm_rst) + VARIABLE data : INTEGER := 0; + VARIABLE even_sample : BOOLEAN := TRUE; + BEGIN + IF mm_rst = '1' THEN + jesd204b_tx_link_data_arr(i) <= (others => '0'); + jesd204b_tx_link_valid(i) <= '0'; + txlink_clk(i) <= '0'; + data := 0; + even_sample := TRUE; + ELSE + IF rising_edge(jesd204b_sampclk_adc(i)) THEN + txlink_clk(i) <= not txlink_clk(i); + jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i); + jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i); + IF (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') THEN + data := 1000; + ELSIF (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') THEN + data := -1000; + ELSE + data := 0; + END IF; + + -- Frame the data to 32 bits at half the rate + IF(jesd204b_tx_link_ready(i) = '0') THEN + even_sample := TRUE; + ELSE + even_sample := not even_sample; + END IF; + IF (even_sample = TRUE) THEN + jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(data, 16); + jesd204b_tx_link_valid(i) <= '0'; + ELSE + jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16); + jesd204b_tx_link_valid(i) <= '1'; + END IF; + + END IF; + END IF; + END PROCESS; + + + + END GENERATE; + + + ----------------------------------------------------------------------------- + -- Stimulii + ----------------------------------------------------------------------------- + + -- Clocks and resets + mm_clk <= not mm_clk after c_mm_clk_period/2; + mm_rst <= '1', '0' after 800 ns; + avs_rst_n <= '0', '1' after 23500 ns; + tx_analogreset(0) <= '1', '0' after 18500 ns; + tx_digitalreset(0) <= '1', '0' after 23000 ns; + txlink_rst_n <= '0', '1' after 25500 ns; + pll_locked(0) <= '0', '1' after 1000 ns; + + bonding_clock_5 <= not bonding_clock_5 after 250 ps; + bonding_clock_4 <= not bonding_clock_4 after 250 ps; + bonding_clock_3 <= not bonding_clock_3 after 500 ps; + bonding_clock_2 <= not bonding_clock_2 after 500 ps; + bonding_clock_0 <= not bonding_clock_0 after 2500 ps; + + bonding_clock_1_process : process + begin + bonding_clock_1 <= '0'; + wait for 4000 ps; + bonding_clock_1 <= '1'; + wait for 1000 ps; + end process; + + tx_bonding_clocks(5) <= transport bonding_clock_5 after 4890 ps; + tx_bonding_clocks(4) <= transport bonding_clock_4 after 4640 ps; + tx_bonding_clocks(3) <= transport bonding_clock_3 after 4920 ps; + tx_bonding_clocks(2) <= transport bonding_clock_2 after 4930 ps; + tx_bonding_clocks(1) <= transport bonding_clock_1 after 7490 ps; + tx_bonding_clocks(0) <= transport bonding_clock_0 after 4000 ps; + + -- Sample Clock + jesd204b_sampclk <= NOT jesd204b_sampclk AFTER c_jesd204b_sampclk_period/2; -- JESD sample clock (200MHz) + + -- clock source process + + proc_sysref : PROCESS (jesd204b_sampclk, mm_rst) + VARIABLE count : NATURAL := 0; + BEGIN + IF mm_rst = '1' THEN + jesd204b_sysref <= '0'; + count := 0; + ELSE + IF rising_edge(jesd204b_sampclk) THEN + IF (count = c_sysref_period-1) THEN + count := 0; + ELSE + count := count + 1; + END IF; + + IF count > c_sysref_period-8 THEN + jesd204b_sysref <= '1'; + ELSE + jesd204b_sysref <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + + ------------------------------------------------------------------------------ + -- Diagnostics + ------------------------------------------------------------------------------ + proc_read_avs_regs : PROCESS + BEGIN + wait for 100ns; + avs_address(0) <= (others => '0'); + avs_chipselect(0) <= '0'; + avs_read(0) <= '0'; + wait until avs_rst_n = '1'; + while true loop + wait until rising_edge(mm_clk); + avs_address(0) <= X"14"; -- dll control + avs_chipselect(0) <= '1'; + avs_read(0) <= '1'; + wait for c_mm_clk_period * 1; + wait until rising_edge(mm_clk); + avs_address(0) <= (others => '0'); + avs_chipselect(0) <= '0'; + avs_read(0) <= '0'; + wait for c_mm_clk_period * 32; + wait until rising_edge(mm_clk); + avs_address(0) <= X"15"; -- syncn_sysref control + avs_chipselect(0) <= '1'; + avs_read(0) <= '1'; + wait for c_mm_clk_period * 1; + wait until rising_edge(mm_clk); + avs_address(0) <= (others => '0'); + avs_chipselect(0) <= '0'; + avs_read(0) <= '0'; + wait for c_mm_clk_period * 32; + wait until rising_edge(mm_clk); + + avs_address(0) <= X"18"; -- syncn_sysref control + avs_chipselect(0) <= '1'; + avs_read(0) <= '1'; + wait for c_mm_clk_period * 1; + wait until rising_edge(mm_clk); + avs_address(0) <= (others => '0'); + avs_chipselect(0) <= '0'; + avs_read(0) <= '0'; + wait for c_mm_clk_period * 32; + wait until rising_edge(mm_clk); + avs_address(0) <= X"19"; -- syncn_sysref control + avs_chipselect(0) <= '1'; + avs_read(0) <= '1'; + wait for c_mm_clk_period * 1; + wait until rising_edge(mm_clk); + avs_address(0) <= (others => '0'); + avs_chipselect(0) <= '0'; + avs_read(0) <= '0'; + wait for c_mm_clk_period * 32; + wait until rising_edge(mm_clk); + + avs_address(0) <= X"20"; -- tx control0 + avs_chipselect(0) <= '1'; + avs_read(0) <= '1'; + wait for c_mm_clk_period * 1; + wait until rising_edge(mm_clk); + avs_address(0) <= (others => '0'); + avs_chipselect(0) <= '0'; + avs_read(0) <= '0'; + wait for c_mm_clk_period * 32; + wait until rising_edge(mm_clk); + avs_address(0) <= X"26"; -- tx control0 + avs_chipselect(0) <= '1'; + avs_read(0) <= '1'; + wait for c_mm_clk_period * 1; + wait until rising_edge(mm_clk); + avs_address(0) <= (others => '0'); + avs_chipselect(0) <= '0'; + avs_read(0) <= '0'; + wait for c_mm_clk_period * 32; + END LOOP; + END PROCESS; + + ------------------------------------------------------------------------------ + -- Simulation end + ------------------------------------------------------------------------------ + --sim_done <= '0', '1' AFTER 1 us; + sim_done <= '0'; + + proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end); + +END tb; diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/wave/readregs.do b/applications/lofar2/designs/lofar2_unb2b_adc/tb/wave/readregs.do new file mode 100644 index 0000000000000000000000000000000000000000..46ad43e16b6ef53f161dddfcb40cc23f69cf0d57 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/wave/readregs.do @@ -0,0 +1,61 @@ +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_read 1 0 + +force -drive sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_chipselect 1 0 + +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h14 0 +run 200ns + +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h15 0 +run 200ns + +# 0x60 rx_err0 +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h18 0 +run 200ns + +# 0x64 rx_err1 +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h19 0 +run 200ns + +# 0x80 rx_status0 +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h20 0 +run 200ns + +# 0x84 rx_status1 +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h21 0 +run 200ns + +# 0x88 rx_status2 +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h22 0 +run 200ns + +# 0x8C rx_status2 +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h23 0 +run 200ns + +# 0x94 ilas_data1 +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h25 0 +run 200ns + +# 0x98 ilas_data2 +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h26 0 +run 200ns + +# 0xF0 rx_status4 +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h3C 0 +run 200ns + +# 0xF4 rx_status5 +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h3D 0 +run 200ns + +# 0xF8 rx_status6 +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h3E 0 +run 200ns + +# 0xFC rx_status7 +force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h3F 0 +run 200ns + +noforce sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_chipselect +noforce sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address +noforce sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_read diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/wave/wave_multichannel.do b/applications/lofar2/designs/lofar2_unb2b_adc/tb/wave/wave_multichannel.do new file mode 100644 index 0000000000000000000000000000000000000000..74f3adec49b040418438efe1c4d0b8cf9599987e --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/wave/wave_multichannel.do @@ -0,0 +1,680 @@ +onerror {resume} +quietly virtual signal -install /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc { /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_rx_src_out_arr(0).data(15 downto 0)} jesd204b_rx_src_out_arr_0 +quietly virtual signal -install /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc { /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_rx_src_out_arr(1).data(15 downto 0)} jesd204b_rx_src_out_arr_1 +quietly virtual signal -install /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc { /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_rx_src_out_arr(2).data(15 downto 0)} jesd204b_rx_src_out_arr_2 +quietly virtual signal -install /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc { /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_rx_src_out_arr(0).channel(1 downto 0)} jesd204b_rx_src_out_arr_0_somf +quietly WaveActivateNextPane {} 0 +add wave -noupdate -group #vsim_capacity# -format Analog-Step -height 500 -radix decimal /#vsim_capacity#/totals +add wave -noupdate -group #vsim_capacity# -radix unsigned /#vsim_capacity#/classes +add wave -noupdate -group #vsim_capacity# -radix unsigned /#vsim_capacity#/qdas +add wave -noupdate -group #vsim_capacity# -radix unsigned /#vsim_capacity#/assertions +add wave -noupdate -group #vsim_capacity# -radix unsigned /#vsim_capacity#/covergroups +add wave -noupdate -group #vsim_capacity# -radix unsigned /#vsim_capacity#/solver +add wave -noupdate -group #vsim_capacity# -radix unsigned /#vsim_capacity#/memories +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_cf +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_cs +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_f +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_hd +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_k +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_l +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_lane_powerdown +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_m +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_np +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_s +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testmode +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testpattern_a +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testpattern_b +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testpattern_c +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testpattern_d +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/dev_sync_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_chipselect +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_address +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_read +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_readdata +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_waitrequest +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_write +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_writedata +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_rst_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_dlb_data +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_dlb_kchar_data +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_frame_error +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_frame_ready +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_int +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_link_data +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_link_valid +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_link_ready +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/mdev_sync_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/pll_locked +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/somf +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/sync_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/sysref +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/tx_analogreset +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/tx_bonding_clocks +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/tx_cal_busy +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/tx_digitalreset +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/tx_serial_data +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/txlink_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/txlink_rst_n_reset_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(0) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/txphy_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_cf +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_cs +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_f +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_hd +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_k +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_l +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_lane_powerdown +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_m +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_np +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_s +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testmode +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testpattern_a +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testpattern_b +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testpattern_c +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testpattern_d +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/dev_sync_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_chipselect +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_address +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_read +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_readdata +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_waitrequest +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_write +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_writedata +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_rst_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_dlb_data +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_dlb_kchar_data +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_frame_error +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_frame_ready +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_int +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_link_data +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_link_valid +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_link_ready +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/mdev_sync_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/pll_locked +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/somf +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/sync_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/sysref +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/tx_analogreset +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/tx_bonding_clocks +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/tx_cal_busy +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/tx_digitalreset +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/tx_serial_data +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/txlink_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/txlink_rst_n_reset_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(1) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(1)/u_ip_arria10_e1sg_jesd204b_tx/txphy_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_cf +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_cs +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_f +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_hd +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_k +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_l +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_lane_powerdown +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_m +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_np +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_s +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testmode +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testpattern_a +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testpattern_b +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testpattern_c +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/csr_tx_testpattern_d +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/dev_sync_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_chipselect +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_address +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_read +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_readdata +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_waitrequest +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_write +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_writedata +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_avs_rst_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_dlb_data +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_dlb_kchar_data +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_frame_error +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_frame_ready +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_int +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_link_data +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_link_valid +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_tx_link_ready +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/mdev_sync_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/pll_locked +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/somf +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/sync_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/sysref +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/tx_analogreset +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/tx_bonding_clocks +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/tx_cal_busy +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/tx_digitalreset +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/tx_serial_data +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/txlink_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/txlink_rst_n_reset_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group gen_jesd204b_tx(2) -group u_ip_arria10_e1sg_jesd204b_tx -radix unsigned /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(2)/u_ip_arria10_e1sg_jesd204b_tx/txphy_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/mm_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/mm_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/reg_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/reg_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/dp_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/dp_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/sync_in +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/in_siso_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/mon_evt_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/mon_sync_timeout_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/mon_ready_stable_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/mon_xon_stable_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/mon_bsn_at_sync_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/mon_nof_sop_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/mon_nof_err_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/mon_nof_valid_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/mon_bsn_first_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/mon_bsn_first_cycle_cnt_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/reg_mosi_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_bsn_monitor -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_bsn_monitor/reg_miso_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/cs_sim +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/xo_ethclk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/xo_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/xo_rst_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/ext_clk200 +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/ext_rst200 +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/mm_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/mm_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/dp_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/dp_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/dp_pps +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/dp_rst_in +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/dp_clk_in +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/mb_I_ref_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/mb_II_ref_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/this_chip_id +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/this_bck_id +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/app_led_red +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/app_led_green +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/pout_wdi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_wdi_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_wdi_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_remu_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_remu_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_dpmm_data_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_dpmm_data_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_dpmm_ctrl_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_dpmm_ctrl_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_mmdp_data_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_mmdp_data_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_mmdp_ctrl_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_mmdp_ctrl_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_epcs_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_epcs_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_unb_system_info_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_unb_system_info_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/rom_unb_system_info_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/rom_unb_system_info_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_unb_sens_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_unb_sens_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_unb_pmbus_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_unb_pmbus_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_fpga_temp_sens_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_fpga_temp_sens_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_fpga_voltage_sens_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_fpga_voltage_sens_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_ppsh_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/reg_ppsh_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_mm_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_tse_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_tse_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_reg_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_reg_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_reg_interrupt +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_ram_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_ram_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/udp_tx_sosi_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/udp_tx_siso_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/udp_rx_sosi_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/udp_rx_siso_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/CLK +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/PPS +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/WDI +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/INTA +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/INTB +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/VERSION +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/ID +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/TESTIO +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/SENS_SC +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/SENS_SD +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/PMBUS_SC +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/PMBUS_SD +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/PMBUS_ALERT +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/MB_I_REF_CLK +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/MB_II_REF_CLK +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/ETH_CLK +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/ETH_SGIN +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/ETH_SGOUT +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/i_ext_clk200 +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/ext_pps +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/common_areset_in_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/i_xo_ethclk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/i_xo_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/i_mm_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/i_mm_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/mm_locked +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/mm_sim_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/epcs_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/clk125 +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/clk100 +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/clk50 +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/mm_wdi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_st_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_st_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/mm_pulse_ms +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/mm_pulse_s +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/mm_board_sens_start +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/led_toggle +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/led_toggle_red +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/led_toggle_green +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/i_tse_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_led +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/wdi_override +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/temp_alarm +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_udp_tx_sosi_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_udp_tx_siso_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_udp_rx_sosi_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_ctrl -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_ctrl/eth1g_udp_rx_siso_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/mm_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/mm_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/dp_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/dp_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/reg_data_buf_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/reg_data_buf_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/ram_data_buf_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/ram_data_buf_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/reg_rx_seq_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/reg_rx_seq_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/in_sync +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/in_sosi_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/in_data_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/ram_data_buf_mosi_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/ram_data_buf_miso_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/reg_data_buf_mosi_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_diag_data_buffer -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_diag_data_buffer/reg_data_buf_miso_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_jesd204b -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/jesd204b_refclk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_jesd204b -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/jesd204b_sysref +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_jesd204b -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/jesd204b_sync_n_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_jesd204b -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/jesd204b_frame_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_jesd204b -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/mm_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_jesd204b -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/mm_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_jesd204b -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/jesd204b_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_jesd204b -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/jesd204b_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_jesd204b -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/serial_tx_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_jesd204b -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/serial_rx_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/mm_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/mm_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/pout_wdi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_wdi_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_wdi_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_unb_system_info_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_unb_system_info_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/rom_unb_system_info_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/rom_unb_system_info_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_unb_sens_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_unb_sens_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_fpga_temp_sens_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_fpga_temp_sens_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_fpga_voltage_sens_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_fpga_voltage_sens_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_unb_pmbus_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_unb_pmbus_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_ppsh_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_ppsh_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/eth1g_mm_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/eth1g_tse_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/eth1g_tse_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/eth1g_reg_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/eth1g_reg_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/eth1g_reg_interrupt +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/eth1g_ram_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/eth1g_ram_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_dpmm_data_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_dpmm_data_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_dpmm_ctrl_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_dpmm_ctrl_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_mmdp_data_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_mmdp_data_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_mmdp_ctrl_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_mmdp_ctrl_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_epcs_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_epcs_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_remu_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_remu_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/jesd204b_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/jesd204b_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/ram_diag_data_buf_jesd_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/ram_diag_data_buf_jesd_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_diag_data_buf_jesd_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/reg_diag_data_buf_jesd_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -group u_mmm -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_mmm/i_reset_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/CLK +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/PPS +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/WDI +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/INTA +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/INTB +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/VERSION +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/ID +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/TESTIO +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/SENS_SC +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/SENS_SD +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/PMBUS_SC +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/PMBUS_SD +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/PMBUS_ALERT +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/ETH_CLK +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/ETH_SGIN +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/ETH_SGOUT +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/QSFP_LED +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/BCK_RX +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/BCK_REF_CLK +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/JESD204B_SYSREF +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/JESD204B_SYNC +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/wg_out_ovr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/wg_out_val +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/wg_out_data +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/wg_out_sync +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/wg_sosi_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/mux_sosi_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/nxt_mux_sosi_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/cs_sim +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/xo_ethclk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/xo_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/xo_rst_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/mm_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/mm_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/st_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/st_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/st_pps +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/dp_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/dp_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/pout_wdi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_wdi_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_wdi_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_ppsh_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_ppsh_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_unb_system_info_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_unb_system_info_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/rom_unb_system_info_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/rom_unb_system_info_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_unb_sens_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_unb_sens_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_unb_pmbus_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_unb_pmbus_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_fpga_temp_sens_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_fpga_temp_sens_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_fpga_voltage_sens_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_fpga_voltage_sens_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/eth1g_mm_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/eth1g_tse_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/eth1g_tse_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/eth1g_reg_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/eth1g_reg_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/eth1g_reg_interrupt +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/eth1g_ram_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/eth1g_ram_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_dpmm_data_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_dpmm_data_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_dpmm_ctrl_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_dpmm_ctrl_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_mmdp_data_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_mmdp_data_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_mmdp_ctrl_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_mmdp_ctrl_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_epcs_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_epcs_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_remu_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_remu_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_wg_mosi_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_wg_miso_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/ram_wg_mosi_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/ram_wg_miso_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_bsn_monitor_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_bsn_monitor_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/qsfp_green_led_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/qsfp_red_led_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/ram_diag_data_buf_jesd_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/ram_diag_data_buf_jesd_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_diag_data_buf_jesd_mosi +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/reg_diag_data_buf_jesd_miso +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/diag_data_buf_snk_in_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -group u_lofar_unb2b_adc -radix unsigned /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_frame_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel /tb_lofar2_unb2b_adc_multichannel/avs_chipselect +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel /tb_lofar2_unb2b_adc_multichannel/avs_read +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel /tb_lofar2_unb2b_adc_multichannel/avs_readdata +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel /tb_lofar2_unb2b_adc_multichannel/avs_address +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned -childformat {{/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(11) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(10) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(9) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(8) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(7) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(6) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(5) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(4) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(3) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(2) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(1) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(0) -radix unsigned}} -subitemconfig {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(11) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(10) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(9) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(8) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(7) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(6) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(5) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(4) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(3) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(2) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(1) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(0) {-height 16 -radix unsigned}} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned -childformat {{/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(11) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(10) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(9) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(8) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(7) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(6) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(5) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(4) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(3) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(2) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(1) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(0) -radix unsigned}} -subitemconfig {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(11) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(10) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(9) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(8) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(7) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(6) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(5) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(4) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(3) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(2) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(1) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(0) {-height 16 -radix unsigned}} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned -childformat {{/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(11) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(10) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(9) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(8) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(7) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(6) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(5) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(4) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(3) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(2) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(1) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(0) -radix unsigned}} -subitemconfig {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(11) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(10) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(9) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(8) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(7) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(6) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(5) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(4) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(3) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(2) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(1) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(0) {-height 16 -radix unsigned}} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned -childformat {{/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(11) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(10) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(9) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(8) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(7) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(6) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(5) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(4) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(3) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(2) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(1) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(0) -radix unsigned}} -subitemconfig {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(11) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(10) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(9) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(8) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(7) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(6) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(5) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(4) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(3) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(2) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(1) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(0) {-height 16 -radix unsigned}} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned -childformat {{/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(11) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(10) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(9) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(8) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(7) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(6) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(5) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(4) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(3) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(2) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(1) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0) -radix unsigned -childformat {{/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(31) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(30) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(29) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(28) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(27) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(26) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(25) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(24) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(23) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(22) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(21) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(20) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(19) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(18) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(17) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(16) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(15) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(14) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(13) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(12) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(11) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(10) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(9) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(8) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(7) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(6) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(5) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(4) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(3) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(2) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(1) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(0) -radix unsigned}}}} -expand -subitemconfig {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(11) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(10) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(9) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(8) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(7) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(6) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(5) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(4) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(3) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(2) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(1) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0) {-height 16 -radix unsigned -childformat {{/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(31) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(30) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(29) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(28) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(27) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(26) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(25) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(24) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(23) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(22) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(21) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(20) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(19) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(18) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(17) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(16) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(15) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(14) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(13) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(12) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(11) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(10) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(9) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(8) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(7) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(6) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(5) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(4) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(3) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(2) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(1) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(0) -radix unsigned}}} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(31) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(30) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(29) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(28) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(27) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(26) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(25) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(24) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(23) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(22) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(21) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(20) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(19) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(18) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(17) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(16) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(15) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(14) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(13) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(12) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(11) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(10) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(9) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(8) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(7) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(6) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(5) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(4) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(3) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(2) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(1) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0)(0) {-height 16 -radix unsigned}} /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned -childformat {{/tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(11) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(10) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(9) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(8) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(7) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(6) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(5) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(4) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(3) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(2) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(1) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(0) -radix unsigned}} -subitemconfig {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(11) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(10) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(9) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(8) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(7) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(6) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(5) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(4) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(3) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(2) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(1) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(0) {-height 16 -radix unsigned}} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned /tb_lofar2_unb2b_adc_multichannel/dev_sync_n +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned /tb_lofar2_unb2b_adc_multichannel/tx_analogreset +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned /tb_lofar2_unb2b_adc_multichannel/tx_digitalreset +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned -childformat {{/tb_lofar2_unb2b_adc_multichannel/tx_bonding_clocks(5) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/tx_bonding_clocks(4) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/tx_bonding_clocks(3) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/tx_bonding_clocks(2) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/tx_bonding_clocks(1) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/tx_bonding_clocks(0) -radix unsigned}} -subitemconfig {/tb_lofar2_unb2b_adc_multichannel/tx_bonding_clocks(5) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/tx_bonding_clocks(4) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/tx_bonding_clocks(3) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/tx_bonding_clocks(2) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/tx_bonding_clocks(1) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/tx_bonding_clocks(0) {-height 16 -radix unsigned}} /tb_lofar2_unb2b_adc_multichannel/tx_bonding_clocks +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned /tb_lofar2_unb2b_adc_multichannel/pll_locked +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned /tb_lofar2_unb2b_adc_multichannel/mm_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned /tb_lofar2_unb2b_adc_multichannel/tb_end +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned /tb_lofar2_unb2b_adc_multichannel/sim_done +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned /tb_lofar2_unb2b_adc_multichannel/ext_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned /tb_lofar2_unb2b_adc_multichannel/pps +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned /tb_lofar2_unb2b_adc_multichannel/pps_rst +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned -childformat {{/tb_lofar2_unb2b_adc_multichannel/serial_tx(2) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/serial_tx(1) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/serial_tx(0) -radix unsigned}} -subitemconfig {/tb_lofar2_unb2b_adc_multichannel/serial_tx(2) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/serial_tx(1) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/serial_tx(0) {-height 16 -radix unsigned}} /tb_lofar2_unb2b_adc_multichannel/serial_tx +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned -childformat {{/tb_lofar2_unb2b_adc_multichannel/bck_rx(11) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/bck_rx(10) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/bck_rx(9) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/bck_rx(8) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/bck_rx(7) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/bck_rx(6) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/bck_rx(5) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/bck_rx(4) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/bck_rx(3) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/bck_rx(2) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/bck_rx(1) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/bck_rx(0) -radix unsigned}} -subitemconfig {/tb_lofar2_unb2b_adc_multichannel/bck_rx(11) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/bck_rx(10) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/bck_rx(9) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/bck_rx(8) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/bck_rx(7) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/bck_rx(6) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/bck_rx(5) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/bck_rx(4) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/bck_rx(3) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/bck_rx(2) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/bck_rx(1) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/bck_rx(0) {-height 16 -radix unsigned}} /tb_lofar2_unb2b_adc_multichannel/bck_rx +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned -childformat {{/tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(11) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(10) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(9) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(8) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(7) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(6) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(5) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(4) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(3) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(2) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(1) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(0) -radix unsigned}} -subitemconfig {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(11) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(10) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(9) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(8) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(7) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(6) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(5) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(4) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(3) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(2) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(1) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(0) {-height 16 -radix unsigned}} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc_1 +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc_2 +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_rx_src_out_arr +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -divider {rx data outputs} +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_rx_src_out_arr(2).valid +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_rx_src_out_arr(1).valid +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_rx_src_out_arr(0).valid +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_rx_src_out_arr_2 +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_rx_src_out_arr_1 +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_rx_src_out_arr_0 +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -radix hexadecimal -expand /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_rx_src_out_arr_0_somf +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_frame_clk +add wave -noupdate -expand -group tb_lofar2_unb2b_adc_multichannel -divider Clocks +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/mm_rst +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/txlink_rst_n +add wave -noupdate -radix unsigned -childformat {{/tb_lofar2_unb2b_adc_multichannel/txlink_clk(2) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/txlink_clk(1) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/txlink_clk(0) -radix unsigned}} -expand -subitemconfig {/tb_lofar2_unb2b_adc_multichannel/txlink_clk(2) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/txlink_clk(1) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/txlink_clk(0) {-height 16 -radix unsigned}} /tb_lofar2_unb2b_adc_multichannel/txlink_clk +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk +add wave -noupdate -divider FPGA +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_fpga +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_fpga +add wave -noupdate -radix unsigned -childformat {{/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(11) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(10) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(9) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(8) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(7) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(6) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(5) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(4) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(3) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(2) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(1) -radix unsigned} {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(0) -radix unsigned}} -subitemconfig {/tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(11) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(10) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(9) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(8) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(7) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(6) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(5) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(4) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(3) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(2) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(1) {-height 16 -radix unsigned} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga(0) {-height 16 -radix unsigned}} /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_fpga +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/txphy_clk +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/bck_rx(2) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/bck_rx(1) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/bck_rx(0) +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/jesd204b_frame_clk +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/somf +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(1)/u_ip_arria10_e1sg_jesd204b_rx/somf +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(2)/u_ip_arria10_e1sg_jesd204b_rx/somf +add wave -noupdate -divider {ADC 0} +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(0) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(0) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(0) +add wave -noupdate -radix decimal /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(0) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_frame_ready(0) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_ready(0) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_valid(0) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(1) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/serial_tx(0) +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/pll_locked +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/somf +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/csr_tx_testmode +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/jesd204_tx_avs_rst_n +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/tx_analogreset +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/tx_digitalreset +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/txlink_rst_n_reset_n +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/txphy_clk +add wave -noupdate -divider {ADC 1} +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(1) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(1) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(1) +add wave -noupdate -radix decimal /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(1) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(1) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/serial_tx(1) +add wave -noupdate -divider {ADC 2} +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(2) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sampclk_adc(2) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sync_adc(2) +add wave -noupdate -radix decimal /tb_lofar2_unb2b_adc_multichannel/jesd204b_tx_link_data_arr(2) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/jesd204b_sysref_adc(2) +add wave -noupdate -radix unsigned /tb_lofar2_unb2b_adc_multichannel/serial_tx(2) +add wave -noupdate -divider {Rx channel 0 in FPGA} +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/xcvr_rst_arr +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/xcvr_rst_ctrl_rx_ready_arr +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/rx_csr_lane_powerdown_arr +add wave -noupdate -divider {reset sequencer (0)} +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/av_address +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/av_readdata +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/av_read +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/av_writedata +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/av_write +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/irq +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/clk +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/csr_reset +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/reset1_dsrt_qual +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/reset2_dsrt_qual +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/reset5_dsrt_qual +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/reset_in0 +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/reset_out0 +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/reset_out1 +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/reset_out2 +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/reset_out3 +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/reset_out4 +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/reset_out5 +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/reset_out6 +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx_reset_seq/reset_out7 +add wave -noupdate -divider {altjesd rx (0)} +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/csr_cf +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/csr_cs +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/csr_f +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/csr_hd +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/csr_k +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/csr_l +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/csr_lane_powerdown +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/csr_m +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/csr_n +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/csr_np +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/csr_rx_testmode +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/csr_s +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/dev_lane_aligned +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/dev_sync_n +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_chipselect +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_read +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_readdata +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_waitrequest +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_write +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_writedata +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_clk +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_rst_n +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_dlb_data +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_dlb_data_valid +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_dlb_disperr +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_dlb_errdetect +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_dlb_kchar_data +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_frame_error +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_int +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_link_data +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_link_valid +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_link_ready +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/pll_ref_clk +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/rx_analogreset +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/rx_cal_busy +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/rx_digitalreset +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/rx_islockedtodata +add wave -noupdate -expand /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/rx_serial_data +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/rxlink_clk +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/rxlink_rst_n_reset_n +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/rxphy_clk +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/sof +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/somf +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/sysref +add wave -noupdate -divider {altjesd rx phy} +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/csr_lane_polarity +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/csr_lane_powerdown +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/jesd204_rx_pcs_data +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/jesd204_rx_pcs_data_valid +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/jesd204_rx_pcs_disperr +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/jesd204_rx_pcs_errdetect +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/jesd204_rx_pcs_kchar_data +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/patternalign_en +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/phy_csr_rx_cal_busy +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/phy_csr_rx_locked_to_data +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/phy_csr_rx_pcfifo_empty +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/phy_csr_rx_pcfifo_full +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/pll_ref_clk +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/rx_analogreset +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/rx_digitalreset +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/rx_serial_data +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/rxlink_clk +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/rxlink_rst_n +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/rxphy_clk +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_phy_adapter_rxphy_clk_export +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_phy_adapter_phy_rxlink_clk_export +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_phy_adapter_phy_rxlink_rst_n_export +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_phy_adapter_rx_refclk_phy_clk +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_phy_adapter_phy_rx_coreclkin_clk +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_clkout_clk +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_parallel_data_rx_parallel_data +add wave -noupdate -radix hexadecimal -childformat {{/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_datak_rx_datak(3) -radix hexadecimal} {/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_datak_rx_datak(2) -radix hexadecimal} {/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_datak_rx_datak(1) -radix hexadecimal} {/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_datak_rx_datak(0) -radix hexadecimal}} -expand -subitemconfig {/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_datak_rx_datak(3) {-height 16 -radix hexadecimal} /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_datak_rx_datak(2) {-height 16 -radix hexadecimal} /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_datak_rx_datak(1) {-height 16 -radix hexadecimal} /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_datak_rx_datak(0) {-height 16 -radix hexadecimal}} /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_datak_rx_datak +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_errdetect_rx_errdetect +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_disperr_rx_disperr +add wave -noupdate -radix hexadecimal -childformat {{/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_syncstatus_rx_syncstatus(3) -radix hexadecimal} {/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_syncstatus_rx_syncstatus(2) -radix hexadecimal} {/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_syncstatus_rx_syncstatus(1) -radix hexadecimal} {/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_syncstatus_rx_syncstatus(0) -radix hexadecimal}} -subitemconfig {/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_syncstatus_rx_syncstatus(3) {-height 16 -radix hexadecimal} /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_syncstatus_rx_syncstatus(2) {-height 16 -radix hexadecimal} /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_syncstatus_rx_syncstatus(1) {-height 16 -radix hexadecimal} /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_syncstatus_rx_syncstatus(0) {-height 16 -radix hexadecimal}} /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_syncstatus_rx_syncstatus +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_is_lockedtodata_rx_is_lockedtodata +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_cal_busy_rx_cal_busy +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_std_pcfifo_full_rx_std_pcfifo_full +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_std_pcfifo_empty_rx_std_pcfifo_empty +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_rx_mlpcs_phy_lane_polarity_rx_polinv +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_rx_mlpcs_phy_bit_reversal_rx_std_bitrev_ena +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_rx_mlpcs_phy_byte_reversal_rx_std_byterev_ena +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_rx_mlpcs_phy_patternalign_en_rx_std_wa_patternalign +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_runningdisp_rx_runningdisp +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_patterndetect_rx_patterndetect +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_unused_rx_parallel_data_unused_rx_parallel_data +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/inst_phy/inst_xcvr_rx_parallel_data +add wave -noupdate -divider {jesd ip} +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/xcvr_rst_ctrl_rx_ready_arr +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/rx_csr_lane_powerdown_arr +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/rx_xcvr_ready_in_arr +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/mm_rst +add wave -noupdate -divider {altjesd tx (0)} +add wave -noupdate -radix hexadecimal /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/jesd204_tx_link_data +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/jesd204_tx_link_valid +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/jesd204_tx_link_ready +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/mdev_sync_n +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/pll_locked +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/somf +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/sync_n +add wave -noupdate /tb_lofar2_unb2b_adc_multichannel/gen_jesd204b_tx(0)/u_ip_arria10_e1sg_jesd204b_tx/jesd204_0/sysref +add wave -noupdate -divider {ADC(0) test signal} +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {100774483841 fs} 0} {{Cursor 2} {400801605107 fs} 0} {{Cursor 3} {200763500000 fs} 0} {{Cursor 4} {51751500000 fs} 0} {{Cursor 5} {51751500000 fs} 0} +quietly wave cursor active 5 +configure wave -namecolwidth 442 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits fs +update +WaveRestoreZoom {51316330112 fs} {52186669888 fs} diff --git a/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl b/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl new file mode 100644 index 0000000000000000000000000000000000000000..7a94d38a0baa75959bed9c86a9d34323cf6b8fbf --- /dev/null +++ b/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl @@ -0,0 +1,2515 @@ +# Assignments for unb2c arria10 10GbE pins when the jesd204b interface is used +# Use this in place of unb2c_10GbE_pins.tcl + + +# Pins needed for the 12 channel JESD204B interface to the ADCs +set_instance_assignment -name IO_STANDARD LVDS -to JESD204B_SYSREF +set_instance_assignment -name IO_STANDARD LVDS -to "JESD204B_SYSREF(n)" +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[11] + + +# The following is copied from unb2c_10GbE_pins.tcl. +# Settings for BCK_RX[0..11] are modified to suit the JESD204B protocol + +set_location_assignment PIN_AL32 -to CLKUSR + + +set_location_assignment PIN_Y36 -to SA_CLK +set_instance_assignment -name IO_STANDARD LVDS -to SA_CLK +# internal termination should be enabled. +set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SA_CLK + + +set_location_assignment PIN_AH9 -to SB_CLK +set_instance_assignment -name IO_STANDARD LVDS -to SB_CLK +# internal termination should be enabled. +set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SB_CLK + + +#set_location_assignment PIN_V9 -to BCK_REF_CLK +#set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)" +#set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK +#set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)" + + + +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON + +# QSFP_0_RX +set_location_assignment PIN_AN38 -to QSFP_0_RX[0] +set_location_assignment PIN_AM40 -to QSFP_0_RX[1] +set_location_assignment PIN_AK40 -to QSFP_0_RX[2] +set_location_assignment PIN_AJ38 -to QSFP_0_RX[3] + +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_RX[0] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_RX[1] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_RX[2] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_RX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[3] + +# QSFP_0_TX +set_location_assignment PIN_AN42 -to QSFP_0_TX[0] +set_location_assignment PIN_AM44 -to QSFP_0_TX[1] +set_location_assignment PIN_AK44 -to QSFP_0_TX[2] +set_location_assignment PIN_AJ42 -to QSFP_0_TX[3] + +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_TX[0] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_TX[1] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_TX[2] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_TX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[0] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[0] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[1] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[1] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[2] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[2] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[3] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[3] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[3] + + +# QSFP_1_RX +set_location_assignment PIN_AC38 -to QSFP_1_RX[0] +set_location_assignment PIN_AD40 -to QSFP_1_RX[1] +set_location_assignment PIN_AF40 -to QSFP_1_RX[2] +set_location_assignment PIN_AG38 -to QSFP_1_RX[3] + +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_RX[0] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_RX[1] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_RX[2] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_RX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[3] + + +# +# QSFP_1_TX +set_location_assignment PIN_AC42 -to QSFP_1_TX[0] +set_location_assignment PIN_AD44 -to QSFP_1_TX[1] +set_location_assignment PIN_AF44 -to QSFP_1_TX[2] +set_location_assignment PIN_AG42 -to QSFP_1_TX[3] + +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_TX[0] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_TX[1] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_TX[2] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_TX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[0] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[0] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[1] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[1] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[2] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[2] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[3] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[3] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[3] + + + + +# QSFP_2_RX +set_location_assignment PIN_AL38 -to QSFP_2_RX[0] +set_location_assignment PIN_AH40 -to QSFP_2_RX[1] +set_location_assignment PIN_AE38 -to QSFP_2_RX[2] +set_location_assignment PIN_AB40 -to QSFP_2_RX[3] + +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_RX[0] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_RX[1] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_RX[2] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_RX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_RX[0] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_2_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_2_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_2_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_2_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_2_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_2_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_2_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_2_RX[0] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_2_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_2_RX[0] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_2_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_2_RX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_RX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_RX[1] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_2_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_2_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_2_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_2_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_2_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_2_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_2_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_2_RX[1] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_2_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_2_RX[1] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_2_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_2_RX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_RX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_RX[2] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_2_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_2_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_2_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_2_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_2_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_2_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_2_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_2_RX[2] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_2_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_2_RX[2] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_2_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_2_RX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_RX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_RX[3] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_2_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_2_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_2_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_2_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_2_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_2_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_2_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_2_RX[3] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_2_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_2_RX[3] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_2_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_2_RX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_RX[3] + + + +# QSFP_2_TX +set_location_assignment PIN_AL42 -to QSFP_2_TX[0] +set_location_assignment PIN_AH44 -to QSFP_2_TX[1] +set_location_assignment PIN_AE42 -to QSFP_2_TX[2] +set_location_assignment PIN_AB44 -to QSFP_2_TX[3] + +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_TX[0] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_TX[1] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_TX[2] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_TX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_TX[0] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_2_TX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_TX[0] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_2_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_2_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_2_TX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_TX[1] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_2_TX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_TX[1] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_2_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_2_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_2_TX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_TX[2] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_2_TX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_TX[2] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_2_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_2_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_2_TX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_TX[3] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_2_TX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_TX[3] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_2_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_2_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_2_TX[3] + + + +# QSFP_3_RX +set_location_assignment PIN_W38 -to QSFP_3_RX[0] +set_location_assignment PIN_T40 -to QSFP_3_RX[1] +set_location_assignment PIN_N38 -to QSFP_3_RX[2] +set_location_assignment PIN_K40 -to QSFP_3_RX[3] + +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_RX[0] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_RX[1] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_RX[2] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_RX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_RX[0] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_3_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_3_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_3_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_3_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_3_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_3_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_3_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_3_RX[0] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_3_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_3_RX[0] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_3_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_3_RX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_RX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_RX[1] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_3_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_3_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_3_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_3_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_3_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_3_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_3_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_3_RX[1] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_3_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_3_RX[1] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_3_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_3_RX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_RX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_RX[2] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_3_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_3_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_3_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_3_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_3_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_3_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_3_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_3_RX[2] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_3_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_3_RX[2] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_3_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_3_RX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_RX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_RX[3] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_3_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_3_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_3_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_3_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_3_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_3_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_3_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_3_RX[3] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_3_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_3_RX[3] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_3_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_3_RX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_RX[3] + + +# QSFP_3_TX +set_location_assignment PIN_W42 -to QSFP_3_TX[0] +set_location_assignment PIN_T44 -to QSFP_3_TX[1] +set_location_assignment PIN_N42 -to QSFP_3_TX[2] +set_location_assignment PIN_K44 -to QSFP_3_TX[3] + +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_TX[0] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_TX[1] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_TX[2] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_TX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_TX[0] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_3_TX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_TX[0] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_3_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_3_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_3_TX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_TX[1] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_3_TX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_TX[1] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_3_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_3_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_3_TX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_TX[2] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_3_TX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_TX[2] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_3_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_3_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_3_TX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_TX[3] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_3_TX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_TX[3] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_3_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_3_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_3_TX[3] + + +# QSFP_4_RX +set_location_assignment PIN_AA38 -to QSFP_4_RX[0] +set_location_assignment PIN_Y40 -to QSFP_4_RX[1] +set_location_assignment PIN_V40 -to QSFP_4_RX[2] +set_location_assignment PIN_U38 -to QSFP_4_RX[3] + +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_RX[0] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_RX[1] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_RX[2] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_RX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_RX[0] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_4_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_4_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_4_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_4_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_4_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_4_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_4_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_4_RX[0] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_4_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_4_RX[0] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_4_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_4_RX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_RX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_RX[1] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_4_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_4_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_4_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_4_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_4_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_4_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_4_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_4_RX[1] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_4_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_4_RX[1] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_4_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_4_RX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_RX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_RX[2] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_4_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_4_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_4_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_4_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_4_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_4_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_4_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_4_RX[2] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_4_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_4_RX[2] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_4_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_4_RX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_RX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_RX[3] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_4_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_4_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_4_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_4_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_4_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_4_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_4_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_4_RX[3] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_4_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_4_RX[3] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_4_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_4_RX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_RX[3] + + +# QSFP_4_TX +set_location_assignment PIN_AA42 -to QSFP_4_TX[0] +set_location_assignment PIN_Y44 -to QSFP_4_TX[1] +set_location_assignment PIN_V44 -to QSFP_4_TX[2] +set_location_assignment PIN_U42 -to QSFP_4_TX[3] + +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_TX[0] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_TX[1] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_TX[2] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_TX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_TX[0] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_4_TX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_TX[0] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_4_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_4_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_4_TX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_TX[1] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_4_TX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_TX[1] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_4_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_4_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_4_TX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_TX[2] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_4_TX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_TX[2] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_4_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_4_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_4_TX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_TX[3] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_4_TX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_TX[3] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_4_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_4_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_4_TX[3] + + +# QSFP_5_RX +set_location_assignment PIN_L38 -to QSFP_5_RX[0] +set_location_assignment PIN_M40 -to QSFP_5_RX[1] +set_location_assignment PIN_P40 -to QSFP_5_RX[2] +set_location_assignment PIN_R38 -to QSFP_5_RX[3] + +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_RX[0] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_RX[1] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_RX[2] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_RX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_RX[0] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_5_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_5_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_5_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_5_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_5_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_5_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_5_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_5_RX[0] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_5_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_5_RX[0] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_5_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_5_RX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_RX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_RX[1] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_5_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_5_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_5_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_5_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_5_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_5_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_5_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_5_RX[1] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_5_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_5_RX[1] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_5_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_5_RX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_RX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_RX[2] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_5_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_5_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_5_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_5_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_5_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_5_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_5_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_5_RX[2] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_5_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_5_RX[2] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_5_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_5_RX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_RX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_RX[3] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_5_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_5_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_5_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_5_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_5_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_5_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_5_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_5_RX[3] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_5_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_5_RX[3] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_5_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_5_RX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_RX[3] + + + +# QSFP_5_TX +set_location_assignment PIN_L42 -to QSFP_5_TX[0] +set_location_assignment PIN_M44 -to QSFP_5_TX[1] +set_location_assignment PIN_P44 -to QSFP_5_TX[2] +set_location_assignment PIN_R42 -to QSFP_5_TX[3] + +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_TX[0] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_TX[1] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_TX[2] +#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_TX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_TX[0] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_5_TX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_TX[0] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_5_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_5_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_5_TX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_TX[1] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_5_TX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_TX[1] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_5_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_5_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_5_TX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_TX[2] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_5_TX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_TX[2] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_5_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_5_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_5_TX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_TX[3] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_5_TX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_TX[3] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_5_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_5_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_5_TX[3] + + + + + + +#set_location_assignment PIN_B9 -to BCK_RX[0] +#set_location_assignment PIN_D9 -to BCK_RX[1] +#set_location_assignment PIN_C11 -to BCK_RX[2] +#set_location_assignment PIN_F9 -to BCK_RX[3] +#set_location_assignment PIN_C7 -to BCK_RX[4] +#set_location_assignment PIN_E11 -to BCK_RX[5] +#set_location_assignment PIN_E7 -to BCK_RX[6] +#set_location_assignment PIN_D5 -to BCK_RX[7] +#set_location_assignment PIN_G7 -to BCK_RX[8] +#set_location_assignment PIN_F5 -to BCK_RX[9] +#set_location_assignment PIN_J7 -to BCK_RX[10] +#set_location_assignment PIN_H5 -to BCK_RX[11] +set_location_assignment PIN_L7 -to BCK_RX[12] +set_location_assignment PIN_K5 -to BCK_RX[13] +set_location_assignment PIN_N7 -to BCK_RX[14] +set_location_assignment PIN_M5 -to BCK_RX[15] +set_location_assignment PIN_R7 -to BCK_RX[16] +set_location_assignment PIN_P5 -to BCK_RX[17] +set_location_assignment PIN_U7 -to BCK_RX[18] +set_location_assignment PIN_T5 -to BCK_RX[19] +set_location_assignment PIN_W7 -to BCK_RX[20] +set_location_assignment PIN_V5 -to BCK_RX[21] +set_location_assignment PIN_AA7 -to BCK_RX[22] +set_location_assignment PIN_Y5 -to BCK_RX[23] +set_location_assignment PIN_AC7 -to BCK_RX[24] +set_location_assignment PIN_AB5 -to BCK_RX[25] +set_location_assignment PIN_AE7 -to BCK_RX[26] +set_location_assignment PIN_AD5 -to BCK_RX[27] +set_location_assignment PIN_AG7 -to BCK_RX[28] +set_location_assignment PIN_AF5 -to BCK_RX[29] +set_location_assignment PIN_AJ7 -to BCK_RX[30] +set_location_assignment PIN_AH5 -to BCK_RX[31] +set_location_assignment PIN_AL7 -to BCK_RX[32] +set_location_assignment PIN_AK5 -to BCK_RX[33] +set_location_assignment PIN_AN7 -to BCK_RX[34] +set_location_assignment PIN_AM5 -to BCK_RX[35] +set_location_assignment PIN_AR7 -to BCK_RX[36] +set_location_assignment PIN_AP5 -to BCK_RX[37] +set_location_assignment PIN_AU7 -to BCK_RX[38] +set_location_assignment PIN_AT5 -to BCK_RX[39] +set_location_assignment PIN_AW7 -to BCK_RX[40] +set_location_assignment PIN_AV5 -to BCK_RX[41] +set_location_assignment PIN_BA7 -to BCK_RX[42] +set_location_assignment PIN_AY5 -to BCK_RX[43] +set_location_assignment PIN_BC7 -to BCK_RX[44] +set_location_assignment PIN_BB5 -to BCK_RX[45] +set_location_assignment PIN_AY9 -to BCK_RX[46] +set_location_assignment PIN_BB9 -to BCK_RX[47] + + +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[0] +#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[0] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[0] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[0] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[0] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[0] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[0] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[0] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[0] +#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[0] +#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[0] +#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[0] +#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[0] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[0] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[1] +#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[1] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[1] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[1] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[1] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[1] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[1] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[1] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[1] +#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[1] +#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[1] +#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[1] +#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[1] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[1] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[2] +#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[2] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[2] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[2] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[2] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[2] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[2] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[2] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[2] +#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[2] +#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[2] +#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[2] +#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[2] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[2] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[3] +#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[3] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[3] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[3] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[3] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[3] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[3] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[3] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[3] +#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[3] +#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[3] +#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[3] +#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[3] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[3] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[4] +#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[4] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[4] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[4] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[4] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[4] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[4] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[4] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[4] +#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[4] +#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[4] +#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[4] +#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[4] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[4] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[5] +#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[5] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[5] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[5] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[5] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[5] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[5] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[5] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[5] +#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[5] +#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[5] +#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[5] +#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[5] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[5] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[6] +#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[6] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[6] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[6] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[6] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[6] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[6] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[6] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[6] +#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[6] +#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[6] +#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[6] +#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[6] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[6] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[7] +#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[7] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[7] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[7] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[7] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[7] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[7] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[7] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[7] +#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[7] +#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[7] +#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[7] +#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[7] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[7] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[8] +#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[8] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[8] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[8] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[8] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[8] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[8] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[8] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[8] +#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[8] +#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[8] +#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[8] +#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[8] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[8] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[9] +#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[9] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[9] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[9] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[9] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[9] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[9] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[9] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[9] +#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[9] +#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[9] +#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[9] +#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[9] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[9] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[10] +#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[10] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[10] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[10] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[10] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[10] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[10] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[10] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[10] +#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[10] +#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[10] +#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[10] +#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[10] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[10] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[11] +#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[11] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[11] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[11] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[11] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[11] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[11] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[11] +#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[11] +#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[11] +#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[11] +#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[11] +#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[11] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[11] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[12] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[12] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[12] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[12] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[12] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[12] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[12] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[12] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[12] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[12] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[12] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[12] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[12] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[12] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[13] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[13] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[13] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[13] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[13] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[13] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[13] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[13] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[13] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[13] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[13] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[13] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[13] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[13] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[14] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[14] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[14] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[14] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[14] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[14] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[14] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[14] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[14] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[14] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[14] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[14] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[14] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[14] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[15] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[15] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[15] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[15] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[15] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[15] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[15] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[15] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[15] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[15] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[15] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[15] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[15] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[15] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[16] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[16] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[16] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[16] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[16] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[16] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[16] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[16] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[16] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[16] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[16] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[16] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[16] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[16] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[17] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[17] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[17] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[17] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[17] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[17] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[17] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[17] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[17] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[17] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[17] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[17] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[17] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[17] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[18] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[18] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[18] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[18] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[18] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[18] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[18] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[18] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[18] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[18] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[18] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[18] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[18] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[18] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[19] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[19] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[19] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[19] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[19] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[19] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[19] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[19] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[19] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[19] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[19] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[19] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[19] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[19] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[20] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[20] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[20] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[20] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[20] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[20] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[20] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[20] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[20] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[20] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[20] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[20] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[20] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[20] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[21] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[21] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[21] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[21] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[21] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[21] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[21] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[21] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[21] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[21] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[21] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[21] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[21] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[21] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[22] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[22] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[22] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[22] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[22] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[22] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[22] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[22] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[22] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[22] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[22] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[22] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[22] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[22] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[23] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[23] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[23] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[23] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[23] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[23] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[23] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[23] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[23] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[23] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[23] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[23] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[23] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[23] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[24] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[24] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[24] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[24] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[24] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[24] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[24] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[24] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[24] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[24] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[24] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[24] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[24] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[24] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[25] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[25] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[25] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[25] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[25] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[25] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[25] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[25] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[25] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[25] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[25] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[25] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[25] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[25] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[26] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[26] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[26] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[26] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[26] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[26] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[26] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[26] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[26] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[26] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[26] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[26] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[26] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[26] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[27] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[27] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[27] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[27] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[27] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[27] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[27] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[27] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[27] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[27] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[27] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[27] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[27] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[27] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[28] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[28] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[28] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[28] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[28] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[28] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[28] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[28] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[28] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[28] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[28] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[28] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[28] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[28] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[29] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[29] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[29] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[29] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[29] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[29] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[29] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[29] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[29] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[29] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[29] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[29] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[29] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[29] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[30] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[30] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[30] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[30] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[30] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[30] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[30] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[30] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[30] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[30] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[30] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[30] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[30] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[30] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[31] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[31] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[31] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[31] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[31] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[31] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[31] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[31] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[31] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[31] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[31] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[31] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[31] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[31] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[32] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[32] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[32] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[32] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[32] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[32] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[32] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[32] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[32] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[32] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[32] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[32] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[32] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[32] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[33] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[33] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[33] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[33] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[33] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[33] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[33] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[33] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[33] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[33] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[33] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[33] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[33] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[33] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[34] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[34] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[34] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[34] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[34] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[34] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[34] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[34] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[34] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[34] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[34] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[34] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[34] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[34] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[35] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[35] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[35] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[35] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[35] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[35] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[35] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[35] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[35] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[35] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[35] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[35] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[35] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[35] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[36] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[36] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[36] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[36] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[36] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[36] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[36] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[36] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[36] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[36] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[36] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[36] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[36] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[36] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[37] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[37] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[37] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[37] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[37] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[37] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[37] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[37] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[37] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[37] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[37] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[37] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[37] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[37] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[38] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[38] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[38] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[38] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[38] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[38] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[38] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[38] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[38] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[38] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[38] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[38] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[38] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[38] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[39] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[39] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[39] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[39] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[39] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[39] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[39] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[39] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[39] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[39] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[39] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[39] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[39] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[39] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[40] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[40] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[40] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[40] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[40] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[40] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[40] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[40] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[40] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[40] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[40] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[40] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[40] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[40] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[41] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[41] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[41] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[41] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[41] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[41] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[41] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[41] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[41] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[41] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[41] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[41] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[41] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[41] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[42] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[42] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[42] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[42] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[42] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[42] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[42] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[42] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[42] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[42] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[42] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[42] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[42] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[42] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[43] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[43] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[43] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[43] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[43] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[43] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[43] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[43] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[43] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[43] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[43] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[43] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[43] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[43] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[44] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[44] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[44] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[44] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[44] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[44] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[44] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[44] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[44] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[44] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[44] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[44] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[44] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[44] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[45] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[45] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[45] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[45] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[45] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[45] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[45] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[45] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[45] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[45] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[45] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[45] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[45] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[45] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[46] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[46] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[46] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[46] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[46] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[46] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[46] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[46] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[46] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[46] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[46] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[46] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[46] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[46] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[47] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[47] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[47] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[47] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[47] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[47] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[47] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[47] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[47] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[47] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[47] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[47] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[47] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[47] + + + + +#set_location_assignment PIN_B5 -to BCK_TX[0] +#set_location_assignment PIN_A3 -to BCK_TX[1] +#set_location_assignment PIN_A11 -to BCK_TX[2] +#set_location_assignment PIN_B1 -to BCK_TX[3] +#set_location_assignment PIN_C3 -to BCK_TX[4] +#set_location_assignment PIN_A7 -to BCK_TX[5] +#set_location_assignment PIN_D1 -to BCK_TX[6] +#set_location_assignment PIN_E3 -to BCK_TX[7] +#set_location_assignment PIN_F1 -to BCK_TX[8] +#set_location_assignment PIN_G3 -to BCK_TX[9] +#set_location_assignment PIN_J3 -to BCK_TX[10] +#set_location_assignment PIN_H1 -to BCK_TX[11] +set_location_assignment PIN_L3 -to BCK_TX[12] +set_location_assignment PIN_K1 -to BCK_TX[13] +set_location_assignment PIN_N3 -to BCK_TX[14] +set_location_assignment PIN_M1 -to BCK_TX[15] +set_location_assignment PIN_R3 -to BCK_TX[16] +set_location_assignment PIN_P1 -to BCK_TX[17] +set_location_assignment PIN_U3 -to BCK_TX[18] +set_location_assignment PIN_T1 -to BCK_TX[19] +set_location_assignment PIN_W3 -to BCK_TX[20] +set_location_assignment PIN_V1 -to BCK_TX[21] +set_location_assignment PIN_AA3 -to BCK_TX[22] +set_location_assignment PIN_Y1 -to BCK_TX[23] +set_location_assignment PIN_AC3 -to BCK_TX[24] +set_location_assignment PIN_AB1 -to BCK_TX[25] +set_location_assignment PIN_AE3 -to BCK_TX[26] +set_location_assignment PIN_AD1 -to BCK_TX[27] +set_location_assignment PIN_AG3 -to BCK_TX[28] +set_location_assignment PIN_AF1 -to BCK_TX[29] +set_location_assignment PIN_AJ3 -to BCK_TX[30] +set_location_assignment PIN_AH1 -to BCK_TX[31] +set_location_assignment PIN_AL3 -to BCK_TX[32] +set_location_assignment PIN_AK1 -to BCK_TX[33] +set_location_assignment PIN_AN3 -to BCK_TX[34] +set_location_assignment PIN_AM1 -to BCK_TX[35] +set_location_assignment PIN_AR3 -to BCK_TX[36] +set_location_assignment PIN_AP1 -to BCK_TX[37] +set_location_assignment PIN_AU3 -to BCK_TX[38] +set_location_assignment PIN_AT1 -to BCK_TX[39] +set_location_assignment PIN_AW3 -to BCK_TX[40] +set_location_assignment PIN_AV1 -to BCK_TX[41] +set_location_assignment PIN_BB1 -to BCK_TX[42] +set_location_assignment PIN_AY1 -to BCK_TX[43] +set_location_assignment PIN_BD5 -to BCK_TX[44] +set_location_assignment PIN_BA3 -to BCK_TX[45] +set_location_assignment PIN_BC3 -to BCK_TX[46] +set_location_assignment PIN_BD9 -to BCK_TX[47] + + +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[0] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[0] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[0] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[0] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[0] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[0] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[1] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[1] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[1] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[1] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[1] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[1] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[2] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[2] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[2] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[2] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[2] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[2] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[3] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[3] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[3] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[3] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[3] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[3] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[4] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[4] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[4] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[4] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[4] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[4] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[5] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[5] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[5] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[5] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[5] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[5] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[6] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[6] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[6] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[6] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[6] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[6] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[7] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[7] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[7] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[7] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[7] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[7] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[8] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[8] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[8] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[8] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[8] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[8] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[9] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[9] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[9] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[9] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[9] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[9] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[10] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[10] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[10] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[10] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[10] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[10] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[11] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[11] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[11] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[11] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[11] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[11] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[12] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[12] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[12] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[12] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[12] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[12] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[13] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[13] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[13] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[13] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[13] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[13] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[14] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[14] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[14] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[14] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[14] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[14] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[15] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[15] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[15] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[15] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[15] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[15] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[16] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[16] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[16] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[16] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[16] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[16] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[17] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[17] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[17] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[17] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[17] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[17] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[18] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[18] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[18] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[18] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[18] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[18] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[19] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[19] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[19] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[19] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[19] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[19] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[20] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[20] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[20] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[20] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[20] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[20] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[21] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[21] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[21] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[21] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[21] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[21] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[22] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[22] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[22] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[22] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[22] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[22] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[23] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[23] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[23] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[23] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[23] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[23] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[24] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[24] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[24] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[24] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[24] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[24] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[25] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[25] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[25] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[25] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[25] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[25] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[26] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[26] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[26] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[26] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[26] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[26] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[27] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[27] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[27] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[27] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[27] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[27] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[28] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[28] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[28] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[28] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[28] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[28] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[29] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[29] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[29] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[29] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[29] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[29] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[30] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[30] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[30] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[30] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[30] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[30] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[31] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[31] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[31] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[31] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[31] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[31] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[32] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[32] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[32] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[32] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[32] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[32] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[33] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[33] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[33] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[33] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[33] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[33] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[34] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[34] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[34] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[34] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[34] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[34] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[35] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[35] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[35] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[35] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[35] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[35] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[36] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[36] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[36] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[36] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[36] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[36] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[37] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[37] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[37] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[37] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[37] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[37] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[38] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[38] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[38] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[38] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[38] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[38] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[39] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[39] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[39] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[39] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[39] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[39] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[40] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[40] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[40] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[40] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[40] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[40] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[41] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[41] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[41] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[41] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[41] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[41] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[42] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[42] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[42] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[42] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[42] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[42] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[43] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[43] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[43] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[43] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[43] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[43] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[44] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[44] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[44] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[44] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[44] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[44] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[45] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[45] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[45] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[45] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[45] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[45] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[46] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[46] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[46] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[46] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[46] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[46] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[47] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[47] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[47] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[47] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[47] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[47] + + + + + +set_location_assignment PIN_AP40 -to RING_0_RX[0] +set_location_assignment PIN_AR38 -to RING_0_RX[1] +set_location_assignment PIN_AT40 -to RING_0_RX[2] +set_location_assignment PIN_AU38 -to RING_0_RX[3] +set_location_assignment PIN_AP44 -to RING_0_TX[0] +set_location_assignment PIN_AR42 -to RING_0_TX[1] +set_location_assignment PIN_AT44 -to RING_0_TX[2] +set_location_assignment PIN_AU42 -to RING_0_TX[3] +set_location_assignment PIN_H40 -to RING_1_RX[0] +set_location_assignment PIN_J38 -to RING_1_RX[1] +set_location_assignment PIN_F40 -to RING_1_RX[2] +set_location_assignment PIN_G38 -to RING_1_RX[3] +set_location_assignment PIN_H44 -to RING_1_TX[0] +set_location_assignment PIN_J42 -to RING_1_TX[1] +set_location_assignment PIN_G42 -to RING_1_TX[2] +set_location_assignment PIN_F44 -to RING_1_TX[3] + +set_location_assignment PIN_AV40 -to RING_0_RX[4] +set_location_assignment PIN_AW38 -to RING_0_RX[5] +set_location_assignment PIN_AY40 -to RING_0_RX[6] +set_location_assignment PIN_BA38 -to RING_0_RX[7] +set_location_assignment PIN_BB40 -to RING_0_RX[8] +set_location_assignment PIN_BC38 -to RING_0_RX[9] +set_location_assignment PIN_AY36 -to RING_0_RX[10] +set_location_assignment PIN_BB36 -to RING_0_RX[11] +set_location_assignment PIN_AV44 -to RING_0_TX[4] +set_location_assignment PIN_AW42 -to RING_0_TX[5] +set_location_assignment PIN_AY44 -to RING_0_TX[6] +set_location_assignment PIN_BB44 -to RING_0_TX[7] +set_location_assignment PIN_BA42 -to RING_0_TX[8] +set_location_assignment PIN_BD40 -to RING_0_TX[9] +set_location_assignment PIN_BC42 -to RING_0_TX[10] +set_location_assignment PIN_BD36 -to RING_0_TX[11] +set_location_assignment PIN_D40 -to RING_1_RX[4] +set_location_assignment PIN_E38 -to RING_1_RX[5] +set_location_assignment PIN_F36 -to RING_1_RX[6] +set_location_assignment PIN_C38 -to RING_1_RX[7] +set_location_assignment PIN_B36 -to RING_1_RX[8] +set_location_assignment PIN_D36 -to RING_1_RX[9] +set_location_assignment PIN_E34 -to RING_1_RX[10] +set_location_assignment PIN_C34 -to RING_1_RX[11] +set_location_assignment PIN_E42 -to RING_1_TX[4] +set_location_assignment PIN_D44 -to RING_1_TX[5] +set_location_assignment PIN_B44 -to RING_1_TX[6] +set_location_assignment PIN_C42 -to RING_1_TX[7] +set_location_assignment PIN_B40 -to RING_1_TX[8] +set_location_assignment PIN_A42 -to RING_1_TX[9] +set_location_assignment PIN_A38 -to RING_1_TX[10] +set_location_assignment PIN_A34 -to RING_1_TX[11] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[4] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[4] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[4] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[4] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[4] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[5] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[5] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[5] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[5] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[5] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[6] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[6] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[6] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[6] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[6] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[7] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[7] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[7] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[7] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[7] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[8] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[8] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[8] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[8] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[8] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[9] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[9] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[9] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[9] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[9] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[10] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[10] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[10] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[10] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[10] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[11] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[11] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[11] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[11] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[11] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[1] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[2] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[3] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[4] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[4] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[4] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[4] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[4] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[4] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[5] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[5] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[5] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[5] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[5] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[5] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[6] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[6] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[6] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[6] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[6] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[6] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[7] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[7] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[7] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[7] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[7] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[7] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[8] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[8] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[8] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[8] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[8] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[8] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[9] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[9] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[9] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[9] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[9] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[9] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[10] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[10] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[10] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[10] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[10] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[10] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[11] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[11] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[11] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[11] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[11] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[11] + + + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[1] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[1] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[2] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[2] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[3] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[3] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[4] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[4] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[4] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[4] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[4] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[4] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[5] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[5] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[5] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[5] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[5] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[5] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[6] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[6] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[6] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[6] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[6] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[6] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[7] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[7] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[7] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[7] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[7] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[7] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[8] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[8] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[8] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[8] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[8] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[8] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[9] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[9] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[9] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[9] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[9] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[9] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[10] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[10] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[10] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[10] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[10] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[10] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[11] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[11] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[11] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[11] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[11] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[11] + + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[0] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[0] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[1] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[1] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[1] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[1] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[1] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[2] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[2] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[2] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[2] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[2] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[3] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[3] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[3] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[3] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[3] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[4] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[4] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[4] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[4] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[4] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[4] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[5] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[5] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[5] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[5] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[5] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[5] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[6] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[6] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[6] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[6] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[6] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[6] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[7] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[7] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[7] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[7] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[7] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[7] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[8] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[8] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[8] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[8] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[8] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[8] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[9] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[9] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[9] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[9] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[9] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[9] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[10] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[10] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[10] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[10] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[10] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[10] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[11] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[11] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[11] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[11] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[11] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[11] + + + +#set_location_assignment PIN_BA25 -to PMBUS_SC +#set_location_assignment PIN_BD25 -to PMBUS_SD +#set_location_assignment PIN_BD26 -to PMBUS_ALERT +#set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SC +#set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SD +#set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_ALERT + + + + + +set_location_assignment PIN_AT31 -to QSFP_RST + +set_location_assignment PIN_AY33 -to QSFP_SCL[0] +set_location_assignment PIN_AY32 -to QSFP_SCL[1] +set_location_assignment PIN_AY30 -to QSFP_SCL[2] +set_location_assignment PIN_AN33 -to QSFP_SCL[3] +set_location_assignment PIN_AN31 -to QSFP_SCL[4] +set_location_assignment PIN_AJ33 -to QSFP_SCL[5] +set_location_assignment PIN_BA32 -to QSFP_SDA[0] +set_location_assignment PIN_BA31 -to QSFP_SDA[1] +set_location_assignment PIN_AP33 -to QSFP_SDA[2] +set_location_assignment PIN_AM33 -to QSFP_SDA[3] +set_location_assignment PIN_AK33 -to QSFP_SDA[4] +set_location_assignment PIN_AH32 -to QSFP_SDA[5] + +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl index c55c9c297abf87133483b340a561c94f3edeeed9..aed590371dba5adf6990f70c2e06c0485fe42418 100644 --- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl @@ -38,4 +38,6 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim" vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_180_qkytlfy.vo" -work altera_iopll_180 - + +set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll/sim" + vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.vo" -work altera_iopll_180 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl index 5c4256f75c2c011ebceced00007eb7acb7b27d6b..9020d9e3737906bae36b678ec98d61962eaa940f 100644 --- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl @@ -96,3 +96,13 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim" vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_180_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180 vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180 + +# jesd204b rx +set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx/sim" + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_jesd204b_rx_altera_xcvr_native_a10_180_vcpx3ja.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_vcpx3ja.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180 + +# jesd204b tx +set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim" + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_xcvr_native_a10_180_q3qhp5a.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_q3qhp5a.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180 diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg index 490c7856894a13b331814d24e3b19f0acfd3ad1e..f02a98b5525a951ff980b04accbc2185f969ed18 100644 --- a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg +++ b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg @@ -1,14 +1,18 @@ hdl_lib_name = ip_arria10_e1sg_jesd204b hdl_library_clause_name = ip_arria10_e1sg_jesd204b_lib hdl_lib_uses_synth = technology tech_pll common dp -hdl_lib_uses_sim = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_180 ip_arria10_e1sg_altera_xcvr_reset_control_180 hdl_lib_technology = ip_arria10_e1sg synth_files = + ip_arria10_e1sg_jesd204b_component_pkg.vhd ip_arria10_e1sg_jesd204b.vhd test_bench_files = +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/jesd204b/compile_ip.tcl + [modelsim_project_file] [quartus_project_file] @@ -17,6 +21,7 @@ quartus_qip_files = $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qip $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/ip_arria10_e1sg_jesd204b_rx_reset_seq.qip $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.qip + $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx/ip_arria10_e1sg_jesd204b_rx.qip [generate_ip_libs] qsys-generate_ip_files = @@ -24,5 +29,6 @@ qsys-generate_ip_files = ip_arria10_e1sg_jesd204b_rx_core_pll.ip ip_arria10_e1sg_jesd204b_rx_reset_seq.ip ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.ip + ip_arria10_e1sg_jesd204b_tx.ip diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd index fa5d74a806b9b8cc328b7481a8d747d0c8de2ad4..8f51551b8db170520bae645cc241cc9e32bbd99b 100644 --- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd +++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd @@ -34,11 +34,11 @@ USE technology_lib.technology_pkg.ALL; USE common_lib.common_pkg.ALL; USE common_lib.common_mem_pkg.ALL; USE dp_lib.dp_stream_pkg.ALL; +USE ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.ALL; ENTITY ip_arria10_e1sg_jesd204b IS GENERIC ( g_sim : BOOLEAN := FALSE; - g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model g_nof_channels : NATURAL := 1; g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY" ); @@ -68,15 +68,23 @@ END ip_arria10_e1sg_jesd204b; ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS + -- JESD IP constants + CONSTANT c_jesd204b_mm_addr_w : NATURAL :=8; + CONSTANT c_jesd204b_rx_data_w : NATURAL :=32; + CONSTANT c_jesd204b_rx_framer_data_w : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel + CONSTANT c_jesd204b_rx_somf_w : NATURAL :=c_jesd204b_rx_data_w/8; -- One somf bit per octet + CONSTANT c_jesd204b_rx_framer_somf_w : NATURAL :=c_jesd204b_rx_somf_w/2; -- IP outputs two samples in parallel + -- JESD204 control status registers SIGNAL jesd204b_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0); SIGNAL jesd204b_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0); - SIGNAL reset_seq_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0); - SIGNAL reset_seq_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0); + SIGNAL reset_seq_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst); + SIGNAL reset_seq_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst); -- Clocks SIGNAL rxframe_clk : STD_LOGIC; SIGNAL rxlink_clk : STD_LOGIC; + SIGNAL jesd204b_avs_clk : STD_LOGIC; -- Reset and control signals SIGNAL dev_lane_aligned : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 1 bit, each interface channel has 1 lane @@ -89,7 +97,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS SIGNAL xcvr_rst_ctrl_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); SIGNAL rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); SIGNAL pll_reset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); - SIGNAL xcvr_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); + SIGNAL xcvr_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS => '1'); SIGNAL rx_avs_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); SIGNAL rxlink_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); SIGNAL rxframe_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); @@ -99,64 +107,17 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS SIGNAL f2_div1_cnt_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); SIGNAL core_pll_locked : STD_LOGIC; SIGNAL core_pll_locked_reg : STD_LOGIC; + SIGNAL jesd204b_sysref_1 : STD_LOGIC; + SIGNAL jesd204b_sysref_2 : STD_LOGIC; -- Data path - SIGNAL jesd204b_rx_link_data_arr : STD_LOGIC_VECTOR(32*g_nof_channels-1 DOWNTO 0); + SIGNAL jesd204b_rx_link_data_arr : STD_LOGIC_VECTOR(c_jesd204b_rx_data_w*g_nof_channels-1 DOWNTO 0); SIGNAL jesd204b_rx_link_valid_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); + SIGNAL jesd204b_rx_somf_arr : STD_LOGIC_VECTOR(c_jesd204b_rx_somf_w*g_nof_channels-1 DOWNTO 0); -- Component declarations for the IP blocks --- component ip_arria10_e1sg_jesd204b_rx is --- port ( --- jesd204_0_alldev_lane_aligned_export : in std_logic := 'X'; -- export --- csr_cf_export : out std_logic_vector(4 downto 0); -- export --- csr_cs_export : out std_logic_vector(1 downto 0); -- export --- csr_f_export : out std_logic_vector(7 downto 0); -- export --- csr_hd_export : out std_logic; -- export --- csr_k_export : out std_logic_vector(4 downto 0); -- export --- csr_l_export : out std_logic_vector(4 downto 0); -- export --- csr_lane_powerdown_export : out std_logic_vector(0 downto 0); -- export --- csr_m_export : out std_logic_vector(7 downto 0); -- export --- csr_n_export : out std_logic_vector(4 downto 0); -- export --- csr_np_export : out std_logic_vector(4 downto 0); -- export --- csr_rx_testmode_export : out std_logic_vector(3 downto 0); -- export --- csr_s_export : out std_logic_vector(4 downto 0); -- export --- dev_lane_aligned_export : out std_logic; -- export --- dev_sync_n_export : out std_logic; -- export --- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect --- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address --- jesd204_rx_avs_read : in std_logic := 'X'; -- read --- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata --- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest --- jesd204_rx_avs_write : in std_logic := 'X'; -- write --- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata --- jesd204_rx_avs_clk_clk : in std_logic := 'X'; -- clk --- jesd204_rx_avs_rst_n_reset_n : in std_logic := 'X'; -- reset_n --- jesd204_rx_dlb_data_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export --- jesd204_rx_dlb_data_valid_export : in std_logic_vector(0 downto 0) := (others => 'X'); -- export --- jesd204_rx_dlb_disperr_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export --- jesd204_rx_dlb_errdetect_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export --- jesd204_rx_dlb_kchar_data_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export --- jesd204_rx_frame_error_export : in std_logic := 'X'; -- export --- jesd204_rx_int_irq : out std_logic; -- irq --- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data --- jesd204_rx_link_valid : out std_logic; -- valid --- jesd204_rx_link_ready : in std_logic := 'X'; -- ready --- pll_ref_clk_clk : in std_logic := 'X'; -- clk --- rx_analogreset_rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset --- rx_cal_busy_rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy --- rx_digitalreset_rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset --- rx_islockedtodata_rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata --- rx_serial_data_rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data --- rxlink_clk_clk : in std_logic := 'X'; -- clk --- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n --- rxphy_clk_export : out std_logic_vector(0 downto 0); -- export --- sof_export : out std_logic_vector(3 downto 0); -- export --- somf_export : out std_logic_vector(3 downto 0); -- export --- sysref_export : in std_logic := 'X' -- export --- ); --- end component ip_arria10_e1sg_jesd204b_rx; component ip_arria10_e1sg_jesd204b_rx is port ( @@ -176,7 +137,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS dev_lane_aligned : out std_logic; -- export dev_sync_n : out std_logic; -- export jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect - jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address + jesd204_rx_avs_address : in std_logic_vector(c_jesd204b_mm_addr_w-1 downto 0) := (others => 'X'); -- address jesd204_rx_avs_read : in std_logic := 'X'; -- read jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest @@ -190,11 +151,11 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export jesd204_rx_frame_error : in std_logic := 'X'; -- export - jesd204_rx_int : out std_logic; -- irq - jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data - jesd204_rx_link_valid : out std_logic; -- valid - jesd204_rx_link_ready : in std_logic := 'X'; -- ready - pll_ref_clk : in std_logic := 'X'; -- clk + jesd204_rx_int : out std_logic; -- irq + jesd204_rx_link_data : out std_logic_vector(c_jesd204b_rx_data_w-1 downto 0); -- data + jesd204_rx_link_valid : out std_logic; -- valid + jesd204_rx_link_ready : in std_logic := 'X'; -- ready + pll_ref_clk : in std_logic := 'X'; -- clk rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset @@ -204,7 +165,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n rxphy_clk : out std_logic_vector(0 downto 0); -- export sof : out std_logic_vector(3 downto 0); -- export - somf : out std_logic_vector(3 downto 0); -- export + somf : out std_logic_vector(c_jesd204b_rx_somf_w-1 downto 0); -- export sysref : in std_logic := 'X' -- export ); end component ip_arria10_e1sg_jesd204b_rx; @@ -220,63 +181,6 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS end component ip_arria10_e1sg_jesd204b_rx_core_pll; component ip_arria10_e1sg_jesd204b_rx_reset_seq is - generic ( - NUM_OUTPUTS : integer := 3; - ENABLE_DEASSERTION_INPUT_QUAL : integer := 0; - ENABLE_ASSERTION_SEQUENCE : integer := 0; - ENABLE_DEASSERTION_SEQUENCE : integer := 0; - MIN_ASRT_TIME : integer := 0; - ASRT_DELAY0 : integer := 0; - DSRT_DELAY0 : integer := 0; - ASRT_REMAP0 : integer := 0; - DSRT_REMAP0 : integer := 0; - DSRT_QUALCNT_0 : integer := 0; - ASRT_DELAY1 : integer := 0; - DSRT_DELAY1 : integer := 0; - ASRT_REMAP1 : integer := 1; - DSRT_REMAP1 : integer := 1; - DSRT_QUALCNT_1 : integer := 0; - ASRT_DELAY2 : integer := 0; - DSRT_DELAY2 : integer := 0; - ASRT_REMAP2 : integer := 2; - DSRT_REMAP2 : integer := 2; - DSRT_QUALCNT_2 : integer := 0; - ASRT_DELAY3 : integer := 0; - DSRT_DELAY3 : integer := 0; - ASRT_REMAP3 : integer := 3; - DSRT_REMAP3 : integer := 3; - DSRT_QUALCNT_3 : integer := 0; - ASRT_DELAY4 : integer := 0; - DSRT_DELAY4 : integer := 0; - ASRT_REMAP4 : integer := 4; - DSRT_REMAP4 : integer := 4; - DSRT_QUALCNT_4 : integer := 0; - ASRT_DELAY5 : integer := 0; - DSRT_DELAY5 : integer := 0; - ASRT_REMAP5 : integer := 5; - DSRT_REMAP5 : integer := 5; - DSRT_QUALCNT_5 : integer := 0; - ASRT_DELAY6 : integer := 0; - DSRT_DELAY6 : integer := 0; - ASRT_REMAP6 : integer := 6; - DSRT_REMAP6 : integer := 6; - DSRT_QUALCNT_6 : integer := 0; - ASRT_DELAY7 : integer := 0; - DSRT_DELAY7 : integer := 0; - ASRT_REMAP7 : integer := 7; - DSRT_REMAP7 : integer := 7; - DSRT_QUALCNT_7 : integer := 0; - ASRT_DELAY8 : integer := 0; - DSRT_DELAY8 : integer := 0; - ASRT_REMAP8 : integer := 8; - DSRT_REMAP8 : integer := 8; - DSRT_QUALCNT_8 : integer := 0; - ASRT_DELAY9 : integer := 0; - DSRT_DELAY9 : integer := 0; - ASRT_REMAP9 : integer := 9; - DSRT_REMAP9 : integer := 9; - DSRT_QUALCNT_9 : integer := 0 - ); port ( av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address av_readdata : out std_logic_vector(31 downto 0); -- readdata @@ -318,6 +222,18 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS BEGIN jesd204b_frame_clk <= rxframe_clk; + + -- The avs clock is driven by the rxlink_clk for simulation. This is a workaround for a bug + -- in the Q18.0 IP where the jesd receiver fails to recognize the SYSREF pulse + gen_simclock : IF g_sim = TRUE GENERATE + jesd204b_avs_clk <= rxlink_clk; + END GENERATE; + + -- For synthesis the avs clock is driven by the mm_clk as usual + gen_synthclock : IF g_sim = FALSE GENERATE + jesd204b_avs_clk <= mm_clk; + END GENERATE; + gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE @@ -325,56 +241,6 @@ BEGIN ----------------------------------------------------------------------------- -- The JESD204 IP (rx only) ----------------------------------------------------------------------------- --- u_ip_arria10_e1sg_jesd204b_rx : ip_arria10_e1sg_jesd204b_rx --- PORT MAP --- ( --- jesd204_0_alldev_lane_aligned_export => dev_lane_aligned_arr(i), --- csr_cf_export => OPEN, --- csr_cs_export => OPEN, --- csr_f_export => OPEN, --- csr_hd_export => OPEN, --- csr_k_export => OPEN, --- csr_l_export => OPEN, --- csr_lane_powerdown_export => rx_csr_lane_powerdown_arr(i downto i), --- csr_m_export => OPEN, --- csr_n_export => OPEN, --- csr_np_export => OPEN, --- csr_rx_testmode_export => OPEN, --- csr_s_export => OPEN, --- dev_lane_aligned_export => dev_lane_aligned_arr(i), --- dev_sync_n_export => jesd204b_sync_n_arr(i), --- jesd204_rx_avs_chipselect => '0', --jesd204b_mosi_arr(i).chipselect, --- jesd204_rx_avs_address => jesd204b_mosi_arr(i).address(7 downto 0), --- jesd204_rx_avs_read => jesd204b_mosi_arr(i).rd, --- jesd204_rx_avs_readdata => jesd204b_miso_arr(i).rddata(31 downto 0), --- jesd204_rx_avs_waitrequest => jesd204b_miso_arr(i).waitrequest, --- jesd204_rx_avs_write => jesd204b_mosi_arr(i).wr, --- jesd204_rx_avs_writedata => jesd204b_mosi_arr(i).wrdata(31 downto 0), --- jesd204_rx_avs_clk_clk => mm_clk, --- jesd204_rx_avs_rst_n_reset_n => rx_avs_rst_n_arr(i), -- Todo: Check if this could use mm_rst, --- jesd204_rx_dlb_data_export => (others => '0'), -- debug/loopback testing --- jesd204_rx_dlb_data_valid_export => (others => '0'), -- debug/loopback testing --- jesd204_rx_dlb_disperr_export => (others => '0'), -- debug/loopback testing --- jesd204_rx_dlb_errdetect_export => (others => '0'), -- debug/loopback testing --- jesd204_rx_dlb_kchar_data_export => (others => '0'), -- debug/loopback testing --- jesd204_rx_frame_error_export => '0', -- jesd204_rx_frame_error.export --- jesd204_rx_int_irq => OPEN, -- Connected to status IO in example design --- jesd204_rx_link_data => jesd204b_rx_link_data_arr(i*32+31 DOWNTO i*32), --- jesd204_rx_link_valid => jesd204b_rx_link_valid_arr(i), --- jesd204_rx_link_ready => '1', --- pll_ref_clk_clk => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63) --- rx_analogreset_rx_analogreset => rx_analogreset_arr(I DOWNTO I), --- rx_cal_busy_rx_cal_busy => rx_cal_busy_arr(I DOWNTO I), --- rx_digitalreset_rx_digitalreset => rx_digitalreset_arr(I DOWNTO I), --- rx_islockedtodata_rx_is_lockedtodata => rx_islockedtodata_arr(I DOWNTO I), --- rx_serial_data_rx_serial_data => serial_rx_arr(i downto i), --- rxlink_clk_clk => rxlink_clk, -- TODO: still not clear if this should be 100MHz or 200MHz (Intel JESD204B-UG p63) --- rxlink_rst_n_reset_n => rxlink_rst_n_arr(i), -- Assoc with rxlink_clk (Intel JESD204B-UG p69) --- rxphy_clk_export => OPEN, -- Not used in Subclass 0 (Intel JESD204B-UG p63) --- sof_export => OPEN, --- somf_export => OPEN, --- sysref_export => jesd204b_sysref --- ); u_ip_arria10_e1sg_jesd204b_rx : ip_arria10_e1sg_jesd204b_rx PORT MAP @@ -395,13 +261,13 @@ BEGIN dev_lane_aligned => dev_lane_aligned_arr(i), dev_sync_n => jesd204b_sync_n_arr(i), jesd204_rx_avs_chipselect => '0', --jesd204b_mosi_arr(i).chipselect, - jesd204_rx_avs_address => jesd204b_mosi_arr(i).address(7 downto 0), + jesd204_rx_avs_address => jesd204b_mosi_arr(i).address(c_jesd204b_mm_addr_w-1 downto 0), jesd204_rx_avs_read => jesd204b_mosi_arr(i).rd, jesd204_rx_avs_readdata => jesd204b_miso_arr(i).rddata(31 downto 0), jesd204_rx_avs_waitrequest => jesd204b_miso_arr(i).waitrequest, jesd204_rx_avs_write => jesd204b_mosi_arr(i).wr, jesd204_rx_avs_writedata => jesd204b_mosi_arr(i).wrdata(31 downto 0), - jesd204_rx_avs_clk => mm_clk, + jesd204_rx_avs_clk => jesd204b_avs_clk, --mm_clk, jesd204_rx_avs_rst_n => rx_avs_rst_n_arr(i), -- Todo: Check if this could use mm_rst, jesd204_rx_dlb_data => (others => '0'), -- debug/loopback testing jesd204_rx_dlb_data_valid => (others => '0'), -- debug/loopback testing @@ -410,7 +276,7 @@ BEGIN jesd204_rx_dlb_kchar_data => (others => '0'), -- debug/loopback testing jesd204_rx_frame_error => '0', -- jesd204_rx_frame_error.export jesd204_rx_int => OPEN, -- Connected to status IO in example design - jesd204_rx_link_data => jesd204b_rx_link_data_arr(i*32+31 DOWNTO i*32), + jesd204_rx_link_data => jesd204b_rx_link_data_arr(i*c_jesd204b_rx_data_w+c_jesd204b_rx_data_w-1 DOWNTO i*c_jesd204b_rx_data_w), jesd204_rx_link_valid => jesd204b_rx_link_valid_arr(i), jesd204_rx_link_ready => '1', pll_ref_clk => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63) @@ -423,8 +289,8 @@ BEGIN rxlink_rst_n_reset_n => rxlink_rst_n_arr(i), -- Assoc with rxlink_clk (Intel JESD204B-UG p69) rxphy_clk => OPEN, -- Not used in Subclass 0 (Intel JESD204B-UG p63) sof => OPEN, - somf => OPEN, - sysref => jesd204b_sysref + somf => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_somf_w-1 downto c_jesd204b_rx_somf_w*i), + sysref => jesd204b_sysref_2 ); ----------------------------------------------------------------------------- @@ -454,7 +320,8 @@ BEGIN reset_out7 => rxframe_rst_arr(i) ); - rx_xcvr_ready_in_arr(i) <= rx_csr_lane_powerdown_arr(i) OR xcvr_rst_ctrl_rx_ready_arr(i); + --rx_xcvr_ready_in_arr(i) <= rx_csr_lane_powerdown_arr(i) OR xcvr_rst_ctrl_rx_ready_arr(i); + rx_xcvr_ready_in_arr(i) <= '1' when rx_csr_lane_powerdown_arr(i)='1' OR xcvr_rst_ctrl_rx_ready_arr(i)='1' else '0'; -- Invert thr active-low resets rx_avs_rst_n_arr(i) <= not rx_avs_rst_arr(i); @@ -462,6 +329,7 @@ BEGIN rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i); + ----------------------------------------------------------------------------- -- Minimal deframer (transport layer) ----------------------------------------------------------------------------- @@ -469,17 +337,21 @@ BEGIN BEGIN IF rising_edge(rxframe_clk) THEN IF rxframe_rst_n_arr(i) = '0' THEN - rx_src_out_arr(i).data(15 downto 0) <= (OTHERS => '0'); + rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w-1 downto 0) <= (OTHERS => '0'); + rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w-1 downto 0) <= (OTHERS => '0'); f2_div1_cnt_arr(i) <= '0'; ELSE rx_src_out_arr(i).valid <= jesd204b_rx_link_valid_arr(i); IF jesd204b_rx_link_valid_arr(i) = '0' THEN - rx_src_out_arr(i).data(15 downto 0) <= (OTHERS => '0'); + rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w-1 downto 0) <= (OTHERS => '0'); + rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w-1 downto 0) <= (OTHERS => '0'); ELSE IF f2_div1_cnt_arr(i) = '1' THEN - rx_src_out_arr(i).data(15 downto 0) <= jesd204b_rx_link_data_arr(32*i+15 downto 32*i); + rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w-1 downto 0) <= jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w*i+c_jesd204b_rx_framer_data_w-1 downto c_jesd204b_rx_data_w*i); + rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w-1 downto 0) <= jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_framer_somf_w-1 downto c_jesd204b_rx_somf_w*i); ELSE - rx_src_out_arr(i).data(15 downto 0) <= jesd204b_rx_link_data_arr(32*i+31 downto 32*i+16); + rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w-1 downto 0) <= jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w*i+c_jesd204b_rx_data_w-1 downto c_jesd204b_rx_data_w*i+c_jesd204b_rx_framer_data_w); + rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w-1 downto 0) <= jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_somf_w-1 downto c_jesd204b_rx_somf_w*i+c_jesd204b_rx_framer_somf_w); END IF; f2_div1_cnt_arr(i) <= not f2_div1_cnt_arr(i); END IF; @@ -488,6 +360,23 @@ BEGIN END PROCESS; END GENERATE; + + ----------------------------------------------------------------------------- + -- Reclock sysref + ----------------------------------------------------------------------------- + p_reclocksysref : PROCESS (rxlink_clk, core_pll_locked) + BEGIN + IF core_pll_locked = '0' THEN + jesd204b_sysref_1 <= '0'; + jesd204b_sysref_2 <= '0'; + ELSE + IF rising_edge(rxlink_clk) THEN + jesd204b_sysref_1 <= jesd204b_sysref; + jesd204b_sysref_2 <= jesd204b_sysref_1; + END IF; + END IF; + END PROCESS; + -- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66) u_ip_arria10_e1sg_jesd204b_rx_corepll : ip_arria10_e1sg_jesd204b_rx_core_pll @@ -533,7 +422,7 @@ BEGIN u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux GENERIC MAP ( g_nof_mosi => g_nof_channels, - g_mult_addr_w => 8 + g_mult_addr_w => c_jesd204b_mm_addr_w ) PORT MAP ( mosi => jesd204b_mosi, @@ -542,5 +431,8 @@ BEGIN miso_arr => jesd204b_miso_arr ); + END str; + + diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd index 6b6c7c4079db703c9ebb085753f1560c8691e818..057261fec54a73fb1038df1447d472be7803f9be 100644 --- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd +++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd @@ -37,7 +37,6 @@ USE dp_lib.dp_stream_pkg.ALL; ENTITY ip_arria10_e2sg_jesd204b IS GENERIC ( g_sim : BOOLEAN := FALSE; - g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model g_nof_channels : NATURAL := 1; g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY" ); diff --git a/libraries/technology/jesd204b/hdllib.cfg b/libraries/technology/jesd204b/hdllib.cfg index 527eb616fd1e5bf8b5ef40d71c7dd46832af8c31..622e2554b8ff8e95c0575a225af553ac3e376839 100644 --- a/libraries/technology/jesd204b/hdllib.cfg +++ b/libraries/technology/jesd204b/hdllib.cfg @@ -1,6 +1,6 @@ hdl_lib_name = tech_jesd204b hdl_library_clause_name = tech_jesd204b_lib -hdl_lib_uses_synth = technology common dp +hdl_lib_uses_synth = technology common dp ip_arria10_e1sg_jesd204b ip_arria10_e2sg_jesd204b hdl_lib_uses_ip = ip_arria10_e1sg_jesd204b ip_arria10_e2sg_jesd204b hdl_lib_uses_sim = #hdl_lib_technology = ip_arria10_e1sg ip_arria10_e2sg diff --git a/libraries/technology/jesd204b/tech_jesd204b.vhd b/libraries/technology/jesd204b/tech_jesd204b.vhd index 3f9277b48a7329ef1dccfb00f6f2ddf694a00327..23c308cfe0b5948a2236af47149271df9b649c39 100644 --- a/libraries/technology/jesd204b/tech_jesd204b.vhd +++ b/libraries/technology/jesd204b/tech_jesd204b.vhd @@ -56,7 +56,6 @@ USE work.tech_jesd204b_component_pkg.ALL; ENTITY tech_jesd204b IS GENERIC ( g_sim : BOOLEAN := FALSE; - g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model g_technology : NATURAL := c_tech_arria10_e1sg; g_nof_channels : NATURAL := 12; g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY" @@ -92,7 +91,6 @@ BEGIN u0 : ENTITY work.tech_jesd204b_arria10_e1sg GENERIC MAP( g_sim => g_sim, - g_sim_level => g_sim_level, g_nof_channels => g_nof_channels, g_direction => g_direction ) @@ -121,7 +119,6 @@ BEGIN u0 : ENTITY work.tech_jesd204b_arria10_e2sg GENERIC MAP( g_sim => g_sim, - g_sim_level => g_sim_level, g_nof_channels => g_nof_channels, g_direction => g_direction ) diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd index d876d44c17c081377af7ea65636b0e5dea25e7c8..c61ec365e8a64d87da5482dd1585141211758bf0 100644 --- a/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd +++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd @@ -38,7 +38,6 @@ USE work.tech_jesd204b_component_pkg.ALL; ENTITY tech_jesd204b_arria10_e1sg IS GENERIC ( g_sim : BOOLEAN := FALSE; - g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model g_nof_channels : NATURAL := 12; g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY" ); @@ -72,7 +71,6 @@ BEGIN u_ip_arria10_e1sg_jesd204b : ip_arria10_e1sg_jesd204b GENERIC MAP( g_sim => g_sim, - g_sim_level => g_sim_level, g_nof_channels => g_nof_channels, g_direction => g_direction ) diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd index b1476dadaf00c34d07943cb7d05dd7909328d112..e92e465237ed17cc5c6c251a86c6b144772c969c 100644 --- a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd +++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd @@ -38,7 +38,6 @@ USE work.tech_jesd204b_component_pkg.ALL; ENTITY tech_jesd204b_arria10_e2sg IS GENERIC ( g_sim : BOOLEAN := FALSE; - g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model g_nof_channels : NATURAL := 12; g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY" ); @@ -72,7 +71,6 @@ BEGIN u_ip_arria10_e2sg_jesd204b : ip_arria10_e2sg_jesd204b GENERIC MAP( g_sim => g_sim, - g_sim_level => g_sim_level, g_nof_channels => g_nof_channels, g_direction => g_direction ) diff --git a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd index 5ec26377673de0b9e17f26aa45b46c2379c0133f..eb6077a69411a3ad8f3dfbb9d30f47cb68a9fc5b 100644 --- a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd +++ b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd @@ -38,7 +38,6 @@ PACKAGE tech_jesd204b_component_pkg IS COMPONENT ip_arria10_e1sg_jesd204b IS GENERIC ( g_sim : BOOLEAN := FALSE; - g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model g_nof_channels : NATURAL := 1; g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY" ); @@ -72,7 +71,6 @@ PACKAGE tech_jesd204b_component_pkg IS COMPONENT ip_arria10_e2sg_jesd204b IS GENERIC ( g_sim : BOOLEAN := FALSE; - g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model g_nof_channels : NATURAL := 1; g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY" );