From 19bcdafe5dc08f4ab4ee974d14d3579a445b5d0e Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Mon, 16 Feb 2015 16:11:20 +0000
Subject: [PATCH] Added ip_arria10_transceiver_reset_controller_24.qsys that
generates a component with transceiver reset controller for 24 transceivers.
---
.../ip_arria10/phy_10gbase_r_24/hdllib.cfg | 2 +-
.../compile_ip.tcl | 43 +++++
.../generate_ip.sh | 44 +++++
.../hdllib.cfg | 19 ++
...ria10_transceiver_reset_controller_24.qsys | 177 ++++++++++++++++++
5 files changed, 284 insertions(+), 1 deletion(-)
create mode 100644 libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
create mode 100755 libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh
create mode 100644 libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
create mode 100644 libraries/technology/ip_arria10/transceiver_reset_controller_24/ip_arria10_transceiver_reset_controller_24.qsys
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
index 1868519661..335b117171 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_phy_10gbase_r_24
-hdl_library_clause_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+hdl_library_clause_name = ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_141
hdl_lib_uses_synth =
hdl_lib_uses_sim =
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
new file mode 100644
index 0000000000..9407f8a630
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
@@ -0,0 +1,43 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_controller_24/generated/sim"
+
+#vlib ./work/ ;# Assume library work already exists
+
+vmap ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_141 ./work/
+
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/altera_xcvr_functions.sv" -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_141
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/mentor/altera_xcvr_functions.sv" -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_141
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/alt_xcvr_resync.sv" -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_141
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_141
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/altera_xcvr_reset_control.sv" -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_141
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/alt_xcvr_reset_counter.sv" -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_141
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/mentor/altera_xcvr_reset_control.sv" -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_141
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/mentor/alt_xcvr_reset_counter.sv" -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_141
+vcom "$IP_DIR/ip_arria10_transceiver_reset_controller_24.vhd"
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh
new file mode 100755
index 0000000000..0b67c011a2
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_transceiver_reset_controller_24.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
new file mode 100644
index 0000000000..21ca44c5ce
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_transceiver_reset_controller_24
+hdl_library_clause_name = ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_141
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+
+synth_files =
+
+test_bench_files =
+
+quartus_qip_files =
+ generated/ip_arria10_transceiver_reset_controller_24.qip
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/ip_arria10_transceiver_reset_controller_24.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_24/ip_arria10_transceiver_reset_controller_24.qsys
new file mode 100644
index 0000000000..258ab5f218
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/ip_arria10_transceiver_reset_controller_24.qsys
@@ -0,0 +1,177 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element transceiver_reset_controller_inst
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="transceiver_reset_controller_inst.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="transceiver_reset_controller_inst.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
+ type="conduit"
+ dir="end">
+ <port name="pll_select" internal="pll_select" />
+ </interface>
+ <interface
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
+ type="conduit"
+ dir="end">
+ <port name="rx_ready" internal="rx_ready" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
+ type="conduit"
+ dir="end">
+ <port name="tx_ready" internal="tx_ready" />
+ </interface>
+ <module
+ name="transceiver_reset_controller_inst"
+ kind="altera_xcvr_reset_control"
+ version="14.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CHANNELS" value="24" />
+ <parameter name="PLLS" value="1" />
+ <parameter name="REDUCED_SIM_TIME" value="1" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="0" />
+ <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="200" />
+ <parameter name="TX_ENABLE" value="1" />
+ <parameter name="TX_PER_CHANNEL" value="0" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
+ <parameter name="T_PLL_LOCK_HYST" value="0" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="T_RX_ANALOGRESET" value="40" />
+ <parameter name="T_RX_DIGITALRESET" value="4000" />
+ <parameter name="T_TX_DIGITALRESET" value="20" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="1" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
--
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