diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index c76cdd229d33c17ce3e6f5b82be5b3f95308a1fd..1267361805fdf188d63b8b7a94ee43d42e12e713 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -171,7 +171,7 @@ ENTITY ctrl_unb2_board IS
     reg_epcs_mosi          : IN  t_mem_mosi := c_mem_mosi_rst;
     reg_epcs_miso          : OUT t_mem_miso;
 
-    -- MM buses to/from mms_unb1_board_system_info
+    -- MM buses to/from mms_unb2_board_system_info
     reg_unb_system_info_mosi : IN  t_mem_mosi := c_mem_mosi_rst;
     reg_unb_system_info_miso : OUT t_mem_miso;
 
@@ -313,7 +313,7 @@ BEGIN
   dp_dis <= i_mm_rst;       -- could use software control for this instead
 
   gen_pll: IF g_dp_clk_use_pll = TRUE GENERATE
-    u_unb2_board_clk200_pll : ENTITY work.unb1_board_clk200_pll
+    u_unb2_board_clk200_pll : ENTITY work.unb2_board_clk200_pll
     GENERIC MAP (
       g_technology          => g_technology,
       g_sel                 => c_dp_clk_pll_sel,
@@ -346,7 +346,7 @@ BEGIN
     node_ctrl_dp_clk_in <= dp_clk_in;
   END GENERATE;
 
-  u_unb2_board_node_ctrl : ENTITY work.unb1_board_node_ctrl
+  u_unb2_board_node_ctrl : ENTITY work.unb2_board_node_ctrl
   GENERIC MAP (
     g_pulse_us => g_mm_clk_freq / (10**6)   -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
   )
@@ -370,11 +370,10 @@ BEGIN
   -- System info
   cs_sim <= is_true(g_sim);
   
-  u_mms_unb2_board_system_info : ENTITY work.mms_unb1_board_system_info
+  u_mms_unb2_board_system_info : ENTITY work.mms_unb2_board_system_info
   GENERIC MAP (
     g_sim         => g_sim,
     g_design_name => g_design_name,
-    g_use_phy     => g_use_phy,
     g_fw_version  => g_fw_version,
     g_stamp_date  => g_stamp_date,
     g_stamp_time  => g_stamp_time,
@@ -462,9 +461,10 @@ BEGIN
   -- Actively reset watchdog from software when used, else disable watchdog by leaving the WDI at tri-state level.
   -- A high temp_alarm will keep WDI asserted, causing the watch dog to reset the FPGA.
   -- A third option is to override the WDI manually using the output of a dedicated reg_wdi.
-  WDI <= sel_a_b(g_use_phy.wdi, mm_wdi OR temp_alarm OR wdi_override, 'Z'); 
+  --WDI <= sel_a_b(g_use_phy.wdi, mm_wdi OR temp_alarm OR wdi_override, 'Z'); 
+  WDI <= mm_wdi OR temp_alarm OR wdi_override; 
 
-  u_unb2_board_wdi_reg : ENTITY work.unb1_board_wdi_reg
+  u_unb2_board_wdi_reg : ENTITY work.unb2_board_wdi_reg
   PORT MAP (
     mm_rst              => i_mm_rst,
     mm_clk              => mm_clk,
@@ -553,7 +553,7 @@ BEGIN
   
   mm_board_sens_start <= mm_pulse_s WHEN g_sim=FALSE ELSE mm_pulse_ms;  -- speed up in simulation
   
-  u_mms_unb2_board_sens : ENTITY work.mms_unb1_board_sens
+  u_mms_unb2_board_sens : ENTITY work.mms_unb2_board_sens
   GENERIC MAP (
     g_sim       => g_sim,
     g_clk_freq  => g_mm_clk_freq,
@@ -582,15 +582,6 @@ BEGIN
   -- Ethernet 1GbE
   ------------------------------------------------------------------------------
   
-  no_eth1g : IF g_use_phy.eth1g=0 GENERATE
-    eth1g_reg_interrupt <= '0';
-    eth1g_tse_miso <= c_mem_miso_rst;
-    eth1g_reg_miso <= c_mem_miso_rst;
-    eth1g_ram_miso <= c_mem_miso_rst;
-  END GENERATE;
-  
-  use_eth1g : IF g_use_phy.eth1g/=0 GENERATE
-
     gen_same_clk: IF g_udp_offload=TRUE GENERATE
 
       eth1g_st_clk <= dp_clk_in;
@@ -647,6 +638,5 @@ BEGIN
       -- LED interface
       tse_led           => eth1g_led
     );
-  END GENERATE;
   
 END str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
index 260f43faffca16ffa2c2158b6176dc52ce229abe..d64cdb04f2a6ae303b2e8845bb8c1d0de0855a85 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
@@ -19,8 +19,8 @@
 --
 -------------------------------------------------------------------------------
 
--- Purpose : MMS for unb1_board_sens
--- Description: See unb1_board_sens.vhd
+-- Purpose : MMS for unb2_board_sens
+-- Description: See unb2_board_sens.vhd
 
 LIBRARY IEEE, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
@@ -29,7 +29,7 @@ USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 
 
-ENTITY mms_unb1_board_sens IS
+ENTITY mms_unb2_board_sens IS
   GENERIC (
     g_sim             : BOOLEAN := FALSE;
     g_clk_freq        : NATURAL := 100*10**6;  -- clk frequency in Hz
@@ -52,12 +52,12 @@ ENTITY mms_unb1_board_sens IS
     -- Temperature alarm output
     temp_alarm        : OUT STD_LOGIC
   );
-END mms_unb1_board_sens;
+END mms_unb2_board_sens;
 
 
-ARCHITECTURE str OF mms_unb1_board_sens IS
+ARCHITECTURE str OF mms_unb2_board_sens IS
 
-  CONSTANT c_sens_nof_result : NATURAL := 4;  -- Should match nof read bytes via I2C in the unb1_board_sens_ctrl SEQUENCE list
+  CONSTANT c_sens_nof_result : NATURAL := 4;  -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
   CONSTANT c_temp_high_w     : NATURAL := 7;  -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
 
   SIGNAL sens_err  : STD_LOGIC;
@@ -67,7 +67,7 @@ ARCHITECTURE str OF mms_unb1_board_sens IS
 
 BEGIN
 
-  u_unb1_board_sens_reg : ENTITY work.unb1_board_sens_reg
+  u_unb2_board_sens_reg : ENTITY work.unb2_board_sens_reg
   GENERIC MAP (
     g_sens_nof_result => c_sens_nof_result,
     g_temp_high       => g_temp_high  
@@ -89,7 +89,7 @@ BEGIN
     temp_high    => temp_high
   );
   
-  u_unb1_board_sens : ENTITY work.unb1_board_sens
+  u_unb2_board_sens : ENTITY work.unb2_board_sens
   GENERIC MAP (
     g_sim             => g_sim,
     g_clk_freq        => g_clk_freq,
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
index aa1b4d69c46d3a907720ce67f8af8485c4f686cd..4a3752ca6b7163718e24db203625cf121d299f69 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -23,19 +23,18 @@ LIBRARY IEEE, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE work.unb1_board_pkg.ALL;
+USE work.unb2_board_pkg.ALL;
 
-ENTITY mms_unb1_board_system_info IS
+ENTITY mms_unb2_board_system_info IS
   GENERIC (
     g_sim         : BOOLEAN := FALSE;
     g_design_name : STRING;
-    g_use_phy     : t_c_unb1_board_use_phy;
-    g_fw_version  : t_unb1_board_fw_version := c_unb1_board_fw_version;  -- firmware version x.y
+    g_fw_version  : t_unb2_board_fw_version := c_unb2_board_fw_version;  -- firmware version x.y
     g_stamp_date  : NATURAL := 0;
     g_stamp_time  : NATURAL := 0;
     g_stamp_svn   : NATURAL := 0;
     g_design_note : STRING  := "";
-    g_aux         : t_c_unb1_board_aux := c_unb1_board_aux               -- aux contains the hardware version
+    g_aux         : t_c_unb2_board_aux := c_unb2_board_aux               -- aux contains the hardware version
   );
   PORT (
     mm_rst          : IN    STD_LOGIC;
@@ -51,16 +50,16 @@ ENTITY mms_unb1_board_system_info IS
     hw_version      : IN  STD_LOGIC_VECTOR(g_aux.version_w-1 DOWNTO 0);
     id              : IN  STD_LOGIC_VECTOR(g_aux.id_w-1 DOWNTO 0);
 
-    chip_id         : OUT STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0);
-    bck_id          : OUT STD_LOGIC_VECTOR(c_unb1_board_nof_uniboard_w-1 DOWNTO 0);
+    chip_id         : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_chip_w-1 DOWNTO 0);
+    bck_id          : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_uniboard_w-1 DOWNTO 0);
 
     -- Info output still supported for older designs
     info            : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)
     );
-END mms_unb1_board_system_info;
+END mms_unb2_board_system_info;
 
 
-ARCHITECTURE str OF mms_unb1_board_system_info IS
+ARCHITECTURE str OF mms_unb2_board_system_info IS
 
   -- Provide different prefixes (absolute and relative) for the same path. ModelSim understands $UNB, Quartus does not.
   -- Required because the work paths of ModelSim and Quartus are different.
@@ -86,7 +85,7 @@ BEGIN
 
  info <= i_info;
  
-  u_unb1_board_system_info: ENTITY work.unb1_board_system_info
+  u_unb2_board_system_info: ENTITY work.unb2_board_system_info
   GENERIC MAP (
     g_sim        => g_sim,
     g_fw_version => g_fw_version
@@ -100,10 +99,9 @@ BEGIN
     bck_id     => bck_id
    );
 
-  u_unb1_board_system_info_reg: ENTITY work.unb1_board_system_info_reg                   
+  u_unb2_board_system_info_reg: ENTITY work.unb2_board_system_info_reg                   
   GENERIC MAP (
     g_design_name => g_design_name,
-    g_use_phy     => g_use_phy,
     g_stamp_date  => g_stamp_date,
     g_stamp_time  => g_stamp_time,
     g_stamp_svn   => g_stamp_svn,
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
index 7db080bc1c26015a6012bdc935d3b7306ef2b0ac..b5c47130957dfae1d6065c01302af6c2ddbc3795 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
@@ -33,7 +33,7 @@ USE technology_lib.technology_pkg.ALL;
 --   clock from the CLK input via c1 = st_clk200p.
 -- . The PLL normal mode operation compensates for internal clock network
 --   delays of c0. This compensations aligns c0 to inclk0. With
---   tb_unb1_board_clk200_pll.vhd it appears that the phase setting for c0 does
+--   tb_unb2_board_clk200_pll.vhd it appears that the phase setting for c0 does
 --   not influence the compensation. Therefore it is llso possible to use
 --   g_clk200_phase_shift /= 0 and touse c0 as processing clock instead of c1.
 -- . The phase offset of c0 and c1 in the clk200_pll MegaWizard component 
@@ -90,9 +90,9 @@ USE technology_lib.technology_pkg.ALL;
 -- . If necessary more 400 M clock phase could be made available, via g_sel.
 -- 
 
-ENTITY unb1_board_clk200_pll IS
+ENTITY unb2_board_clk200_pll IS
   GENERIC (
-    g_technology          : NATURAL := c_tech_stratixiv;
+    g_technology          : NATURAL := c_tech_arria10;
     g_sel                 : NATURAL := 0;
     g_operation_mode      : STRING  := "NORMAL";  -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
     
@@ -133,10 +133,10 @@ ENTITY unb1_board_clk200_pll IS
     -- . g_sel=1
     st_clk_vec  : OUT STD_LOGIC_VECTOR(g_clk_vec_w-1 DOWNTO 0)  -- PLL c6-c1
   );
-END unb1_board_clk200_pll;
+END unb2_board_clk200_pll;
 
 
-ARCHITECTURE stratix4 OF unb1_board_clk200_pll IS
+ARCHITECTURE arria10 OF unb2_board_clk200_pll IS
 
   CONSTANT c_reset_len : NATURAL := c_meta_delay_len;
   
@@ -260,4 +260,4 @@ BEGIN
     out_rst   => st_rst400
   );
   
-END stratix4;
+END arria10;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
index 2d7247adce1f3d25a407e8e972ece51304dbd32c..2af3d58d604b17d93dbe4dbe86b257049b96f7af 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
@@ -30,7 +30,7 @@ USE common_lib.common_pkg.ALL;
 --   2) sys_rst released when the sys_clk PLL from the SOPC system has locked,
 --      can be used as a system reset for the sys_clk domain.
 
-ENTITY unb1_board_clk_rst IS
+ENTITY unb2_board_clk_rst IS
   PORT (
     -- Reference clock and reset to SOPC system PLL
     xo_clk                 : IN  STD_LOGIC;  -- reference XO clock (e.g. 25 MHz also use by PLL in SOPC)
@@ -40,10 +40,10 @@ ENTITY unb1_board_clk_rst IS
     sys_locked             : IN  STD_LOGIC;  -- system clock PLL locked
     sys_rst                : OUT STD_LOGIC   -- system reset released some cycles after the system clock PLL has in locked
   );
-END unb1_board_clk_rst;
+END unb2_board_clk_rst;
 
 
-ARCHITECTURE str OF unb1_board_clk_rst IS
+ARCHITECTURE str OF unb2_board_clk_rst IS
 
   CONSTANT c_reset_len   : NATURAL := 4;  -- >= c_meta_delay_len from common_pkg
   
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
index 5974d6f3e6fedb1fe0a7424d6dc1185a87a7f115..b658c070242ec6519560f1d44e992463bd5997f4 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
@@ -30,7 +30,7 @@ USE common_lib.common_pkg.ALL;
 --   . pulse every 1 us, 1 ms and 1 s
 --   . extend WDI to avoid watchdog reset during SW reload
 
-ENTITY unb1_board_node_ctrl IS
+ENTITY unb2_board_node_ctrl IS
   GENERIC (
     g_pulse_us     : NATURAL := 125;     -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
     g_pulse_ms     : NATURAL := 1000;    -- nof pulse_us pulses to get ms period (fixed, use less to speed up simulation)
@@ -53,10 +53,10 @@ ENTITY unb1_board_node_ctrl IS
     pulse_ms        : OUT STD_LOGIC;  -- pulses every ms
     pulse_s         : OUT STD_LOGIC   -- pulses every s
   );
-END unb1_board_node_ctrl;
+END unb2_board_node_ctrl;
 
 
-ARCHITECTURE str OF unb1_board_node_ctrl IS
+ARCHITECTURE str OF unb2_board_node_ctrl IS
 
   CONSTANT c_reset_len   : NATURAL := 4;  -- >= c_meta_delay_len from common_pkg
 
@@ -69,7 +69,7 @@ BEGIN
   
   pulse_ms <= i_pulse_ms;
 
-  u_unb1_board_clk_rst : ENTITY work.unb1_board_clk_rst
+  u_unb2_board_clk_rst : ENTITY work.unb2_board_clk_rst
   PORT MAP (
     xo_clk     => xo_clk,
     xo_rst_n   => xo_rst_n,
@@ -100,7 +100,7 @@ BEGIN
     out_rst   => st_rst
   );
   
-  u_unb1_board_pulser : ENTITY work.unb1_board_pulser
+  u_unb2_board_pulser : ENTITY work.unb2_board_pulser
   GENERIC MAP (
     g_pulse_us  => g_pulse_us,
     g_pulse_ms  => g_pulse_ms,
@@ -114,7 +114,7 @@ BEGIN
     pulse_s     => pulse_s
   );
 
-  u_unb1_board_wdi_extend : ENTITY work.unb1_board_wdi_extend
+  u_unb2_board_wdi_extend : ENTITY work.unb2_board_wdi_extend
   GENERIC MAP (
     g_extend_w => g_wdi_extend_w
   )
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pulser.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pulser.vhd
index 41b6c0d21facdabeeccc560dc3772ef6c26f204d..f1b3f63abe2244d0a3868cf8a870149cc1fc95e5 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pulser.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pulser.vhd
@@ -26,7 +26,7 @@ USE common_lib.common_pkg.ALL;
 
 -- Purpose: Provide timing pulses for interval 1 us, 1 ms and 1 s
 
-ENTITY unb1_board_pulser IS
+ENTITY unb2_board_pulser IS
   GENERIC (
     g_pulse_us   : NATURAL := 125/(10**6);  -- nof clk cycles to get us period
     g_pulse_ms   : NATURAL := 1000;         -- nof pulse_us pulses to get ms period
@@ -40,10 +40,10 @@ ENTITY unb1_board_pulser IS
     pulse_ms     : OUT STD_LOGIC;  -- pulses after every g_pulse_us*g_pulse_ms           clock cycles
     pulse_s      : OUT STD_LOGIC   -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
   );
-END unb1_board_pulser;
+END unb2_board_pulser;
 
 
-ARCHITECTURE str OF unb1_board_pulser IS
+ARCHITECTURE str OF unb2_board_pulser IS
 
   SIGNAL pulse_us_pp     : STD_LOGIC;  -- register to align with pulse_ms
   SIGNAL pulse_us_p      : STD_LOGIC;  -- register to align with pulse_s
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
index 69da14c09114c2af39c456b3ff3bc82df7bd381c..7208a5d5b280370557f5f1a043b9cf334b2cb8ad 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
@@ -25,12 +25,12 @@ USE common_lib.common_pkg.ALL;
 USE i2c_lib.i2c_pkg.ALL;
 
 
-ENTITY unb1_board_sens is
+ENTITY unb2_board_sens is
   GENERIC (
     g_sim             : BOOLEAN := FALSE;
     g_clk_freq        : NATURAL := 100*10**6;  -- clk frequency in Hz
     g_temp_high       : NATURAL := 85;
-    g_sens_nof_result : NATURAL := 4  -- Should match nof read bytes via I2C in the unb1_board_sens_ctrl SEQUENCE list
+    g_sens_nof_result : NATURAL := 4  -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
   );
   PORT (
     rst          : IN    STD_LOGIC;
@@ -47,7 +47,7 @@ ENTITY unb1_board_sens is
 END ENTITY;
 
 
-ARCHITECTURE str OF unb1_board_sens IS
+ARCHITECTURE str OF unb2_board_sens IS
 
   -- I2C clock rate settings
   CONSTANT c_sens_clk_cnt      : NATURAL := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq/10**6));  -- define I2C clock rate
@@ -66,7 +66,7 @@ ARCHITECTURE str OF unb1_board_sens IS
 
 BEGIN
 
-  u_unb1_board_sens_ctrl : ENTITY work.unb1_board_sens_ctrl
+  u_unb2_board_sens_ctrl : ENTITY work.unb2_board_sens_ctrl
   GENERIC MAP (
     g_sim        => g_sim,
     g_nof_result => g_sens_nof_result,
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
index 9d134435d00e60a36d5ead0828fe47425c0d3e1e..f9451349bdcd2a9e57ea99b6a318483285b8a84c 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
@@ -27,7 +27,7 @@ USE i2c_lib.i2c_dev_ltc4260_pkg.ALL;
 USE common_lib.common_pkg.ALL;
 
 
-ENTITY unb1_board_sens_ctrl IS
+ENTITY unb2_board_sens_ctrl IS
   GENERIC (
     g_sim        : BOOLEAN := FALSE;
     g_nof_result : NATURAL := 4;
@@ -51,7 +51,7 @@ ENTITY unb1_board_sens_ctrl IS
 END ENTITY;
 
 
-ARCHITECTURE rtl OF unb1_board_sens_ctrl IS
+ARCHITECTURE rtl OF unb2_board_sens_ctrl IS
 
   -- I2C slave addresses of the devices on the I2C bus on UniBoard
   CONSTANT FPGA_MAX1617_ADR     : NATURAL := MAX1617_ADR_LOW_LOW;      -- FPGA temperature sensor, slave address is "0011000"
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
index f1c6bf75ad7b7edfe405d44a58ee80c5d03e05b2..e14e71bce5b7731d1924213f5aded931b5967838 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
@@ -19,7 +19,7 @@
 --
 -------------------------------------------------------------------------------
 
--- Purpose: Provide MM slave register for unb1_board_sens
+-- Purpose: Provide MM slave register for unb2_board_sens
 -- Description:
 --
 --   31             24 23             16 15              8 7               0  wi
@@ -65,7 +65,7 @@ USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 
-ENTITY unb1_board_sens_reg IS
+ENTITY unb2_board_sens_reg IS
   GENERIC (
     g_sens_nof_result : NATURAL := 4;
     g_temp_high       : NATURAL := 85
@@ -87,10 +87,10 @@ ENTITY unb1_board_sens_reg IS
     temp_high  : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
 
   );
-END unb1_board_sens_reg;
+END unb2_board_sens_reg;
 
 
-ARCHITECTURE rtl OF unb1_board_sens_reg IS
+ARCHITECTURE rtl OF unb2_board_sens_reg IS
 
   -- Define the actual size of the MM slave register
   CONSTANT c_mm_nof_dat : NATURAL := g_sens_nof_result+1+1;  -- +1 to fit user set temp_high one additional address
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
index aa946c8accb9ac9a5d1ceb297186c5f57de7f95c..c4b666a06e90e45ead4b8c85810fd871b9099bc1 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
@@ -23,33 +23,32 @@
 LIBRARY IEEE, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
-USE work.unb1_board_pkg.ALL;
+USE work.unb2_board_pkg.ALL;
 
 -- Keep the UniBoard system info knowledge in this HDL entity and in the
 -- corresponding software functions in unb_common.c,h. This avoids having to
 -- define named constants for indexing the fields in the info word.
 
-ENTITY unb1_board_system_info IS
+ENTITY unb2_board_system_info IS
   GENERIC (
     g_sim        : BOOLEAN := FALSE;
-    g_fw_version : t_unb1_board_fw_version := c_unb1_board_fw_version;  -- firmware version x.y (4b.4b)
-    g_aux        : t_c_unb1_board_aux := c_unb1_board_aux               -- aux contains the hardware version
+    g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version;  -- firmware version x.y (4b.4b)
+    g_aux        : t_c_unb2_board_aux := c_unb2_board_aux               -- aux contains the hardware version
   );
   PORT (
     clk         : IN  STD_LOGIC;
     hw_version  : IN  STD_LOGIC_VECTOR(g_aux.version_w-1 DOWNTO 0);
     id          : IN  STD_LOGIC_VECTOR(g_aux.id_w-1 DOWNTO 0);
     info        : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-    bck_id      : OUT STD_LOGIC_VECTOR(c_unb1_board_nof_uniboard_w-1 DOWNTO 0); -- ID[7:3]
-    chip_id     : OUT STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0);     -- ID[2:0]
-    node_id     : OUT STD_LOGIC_VECTOR(c_unb1_board_nof_node_w-1 DOWNTO 0);     -- ID[1:0]
-    is_bn       : OUT STD_LOGIC;  -- '1' for Back Node, else '0' for Front Node 
-    is_bn3      : OUT STD_LOGIC   -- '1' for Back Node 3, else '0'.
+    bck_id      : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_uniboard_w-1 DOWNTO 0); -- ID[7:2]
+    chip_id     : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_chip_w-1 DOWNTO 0);     -- ID[1:0]
+    node_id     : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_node_w-1 DOWNTO 0);     -- ID[1:0]
+    is_n3       : OUT STD_LOGIC   -- '1' for Node 3, else '0'.
   );
-END unb1_board_system_info;
+END unb2_board_system_info;
 
 
-ARCHITECTURE str OF unb1_board_system_info IS
+ARCHITECTURE str OF unb2_board_system_info IS
 
   SIGNAL cs_sim         : STD_LOGIC;
   
@@ -60,8 +59,7 @@ ARCHITECTURE str OF unb1_board_system_info IS
   SIGNAL nxt_bck_id     : STD_LOGIC_VECTOR(bck_id'RANGE);
   SIGNAL nxt_chip_id    : STD_LOGIC_VECTOR(chip_id'RANGE);
   SIGNAL nxt_node_id    : STD_LOGIC_VECTOR(node_id'RANGE);
-  SIGNAL nxt_is_bn      : STD_LOGIC;
-  SIGNAL nxt_is_bn3     : STD_LOGIC;
+  SIGNAL nxt_is_n3      : STD_LOGIC;
   
 BEGIN
 
@@ -76,8 +74,7 @@ BEGIN
       bck_id         <= nxt_bck_id;
       chip_id        <= nxt_chip_id;
       node_id        <= nxt_node_id;
-      is_bn          <= nxt_is_bn;
-      is_bn3         <= nxt_is_bn3;
+      is_n3          <= nxt_is_n3;
     END IF;
   END PROCESS;
   
@@ -93,10 +90,9 @@ BEGIN
     nxt_info(7 DOWNTO 0)   <= id_reg;
   END PROCESS;
  
-  nxt_bck_id  <= id_reg(7 DOWNTO 3);
-  nxt_chip_id <= id_reg(2 DOWNTO 0);
+  nxt_bck_id  <= id_reg(7 DOWNTO 2);
+  nxt_chip_id <= id_reg(1 DOWNTO 0);
   nxt_node_id <= id_reg(1 DOWNTO 0);
-  nxt_is_bn   <= id_reg(2);
-  nxt_is_bn3  <= '1' WHEN TO_UINT(id_reg(2 DOWNTO 0)) = 7 ELSE '0';
+  nxt_is_n3   <= '1' WHEN TO_UINT(id_reg(1 DOWNTO 0)) = 3 ELSE '0';
   
 END str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
index 407bbda4cc931a4d5170ce482d7cf6820a3bcdb4..16f2e81aaa6ae3c318f0a3e3aeeb64086a36e3d4 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -28,10 +28,10 @@
 --  FR  FIFO read
 --  FW  FIFO write
 --
---  wi  Bits    R/W Name          Default  Description      |REG_UNB1_BOARD_SYSTEM_INFO|
+--  wi  Bits    R/W Name          Default  Description      |REG_UNB2_BOARD_SYSTEM_INFO|
 --  =============================================================================
 --  0   [23..0] RO  info          
---  1   [7..0]  RO  use_phy
+--  1   [7..0]  RO  0
 --  2   [31..0] RO  design_name
 --  .   ..      .   ..
 --  9   [31..0] RO  design name
@@ -48,12 +48,11 @@ USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_str_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE work.unb1_board_pkg.ALL;
+USE work.unb2_board_pkg.ALL;
 
-ENTITY unb1_board_system_info_reg IS
+ENTITY unb2_board_system_info_reg IS
   GENERIC (
     g_design_name : STRING;
-    g_use_phy     : t_c_unb1_board_use_phy;
     g_stamp_date  : NATURAL := 0;
     g_stamp_time  : NATURAL := 0;
     g_stamp_svn   : NATURAL := 0;
@@ -70,12 +69,12 @@ ENTITY unb1_board_system_info_reg IS
     
     info        : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)
     );
-END unb1_board_system_info_reg;
+END unb2_board_system_info_reg;
 
 
-ARCHITECTURE rtl OF unb1_board_system_info_reg IS
+ARCHITECTURE rtl OF unb2_board_system_info_reg IS
 
-  CONSTANT c_nof_fixed_regs       : NATURAL := 2; -- info, use_phy
+  CONSTANT c_nof_fixed_regs       : NATURAL := 2; -- info
   CONSTANT c_nof_design_name_regs : NATURAL := 8; -- design_name
   CONSTANT c_nof_stamp_regs       : NATURAL := 3; -- date, time, svn rev
   CONSTANT c_nof_design_note_regs : NATURAL := 8; -- note
@@ -88,16 +87,9 @@ ARCHITECTURE rtl OF unb1_board_system_info_reg IS
                                          nof_dat  => c_nof_regs,
                                          init_sl  => '0');   
 
-  CONSTANT c_use_phy_w     : NATURAL := 8;
-  CONSTANT c_use_phy       : STD_LOGIC_VECTOR(c_use_phy_w-1 DOWNTO 0) := TO_UVEC(g_use_phy.eth1g,   1) &
-                                                                         TO_UVEC(g_use_phy.tr_front,1) & 
-                                                                         TO_UVEC(g_use_phy.tr_mesh, 1) & 
-                                                                         TO_UVEC(g_use_phy.tr_back, 1) & 
-                                                                         TO_UVEC(g_use_phy.ddr3_I,  1) & 
-                                                                         TO_UVEC(g_use_phy.ddr3_II, 1) & 
-                                                                         TO_UVEC(g_use_phy.adc,     1) & 
-                                                                         TO_UVEC(g_use_phy.wdi,     1);
-  
+  CONSTANT c_use_phy_w     : NATURAL := 8; -- FIXME: to be removed
+  CONSTANT c_use_phy       : STD_LOGIC_VECTOR(c_use_phy_w-1 DOWNTO 0) := (OTHERS=> '0'); -- FIXME: to be removed
+
   CONSTANT c_design_name    : t_slv_32_arr(0 TO c_nof_design_name_regs-1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
   CONSTANT c_design_note    : t_slv_32_arr(0 TO c_nof_design_note_regs-1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
  
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
index 75e14ae5a35474004c6492f3d13eb357a1b924c9..3bb48f3595269949384367dd2d59b50912f98b25 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
@@ -30,7 +30,7 @@ USE common_lib.common_pkg.ALL;
 --   the HDL image. This component extends the last input WDI by toggling the
 --   output WDI for about 2**(g_extend_w-1) ms more.
 
-ENTITY unb1_board_wdi_extend IS
+ENTITY unb2_board_wdi_extend IS
   GENERIC (
     g_extend_w : NATURAL := 14
   );
@@ -41,10 +41,10 @@ ENTITY unb1_board_wdi_extend IS
     wdi_in           : IN  STD_LOGIC;
     wdi_out          : OUT STD_LOGIC
   );
-END unb1_board_wdi_extend;
+END unb2_board_wdi_extend;
 
 
-ARCHITECTURE str OF unb1_board_wdi_extend IS
+ARCHITECTURE str OF unb2_board_wdi_extend IS
 
   SIGNAL wdi_evt     : STD_LOGIC;
   
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
index 80578aa8d577629d0b0cc3358ba9e0bb8fd40d57..d904e4a00d384df9fd73a159d5bbe01b92a94415 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
@@ -28,7 +28,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 
-ENTITY unb1_board_wdi_reg IS
+ENTITY unb2_board_wdi_reg IS
   PORT (
     -- Clocks and reset
     mm_rst            : IN  STD_LOGIC;   -- reset synchronous with mm_clk
@@ -41,10 +41,10 @@ ENTITY unb1_board_wdi_reg IS
     -- MM registers in st_clk domain
     wdi_override      : OUT STD_LOGIC
  );
-END unb1_board_wdi_reg;
+END unb2_board_wdi_reg;
 
 
-ARCHITECTURE rtl OF unb1_board_wdi_reg IS
+ARCHITECTURE rtl OF unb2_board_wdi_reg IS
 
   -- Define the actual size of the MM slave register
   CONSTANT c_mm_reg : t_c_mem := (latency  => 1,
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index d3515ad40ebce96a3b69ca7b1bba94405de5b572..cff9de6d184f587fb74ffb80282ed1b9753be8e5 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -19,7 +19,7 @@
 --
 -------------------------------------------------------------------------------
 
--- Purpose: Test bench for mms_unb1_board_sens
+-- Purpose: Test bench for mms_unb2_board_sens
 --
 -- Features:
 -- . Verify that the UniBoard sensors are read.
@@ -28,8 +28,8 @@
 -- . > as 10
 -- . > run -all
 
-ENTITY tb_mms_unb1_board_sens IS
-END tb_mms_unb1_board_sens;
+ENTITY tb_mms_unb2_board_sens IS
+END tb_mms_unb2_board_sens;
 
 LIBRARY IEEE, common_lib, i2c_lib;
 USE IEEE.std_logic_1164.ALL;
@@ -39,7 +39,7 @@ USE common_lib.tb_common_pkg.ALL;
 USE common_lib.tb_common_mem_pkg.ALL;
 
 
-ARCHITECTURE tb OF tb_mms_unb1_board_sens IS
+ARCHITECTURE tb OF tb_mms_unb2_board_sens IS
 
   CONSTANT c_sim              : BOOLEAN := TRUE;  --FALSE;
   CONSTANT c_repeat           : NATURAL := 2;
@@ -61,7 +61,7 @@ ARCHITECTURE tb OF tb_mms_unb1_board_sens IS
   CONSTANT c_uniboard_adin       : REAL := -1.0;  -- = NC on UniBoard
   
   CONSTANT c_sens_nof_result  : NATURAL := 4 + 1;
-  CONSTANT c_sens_expected    : t_natural_arr(0 TO c_sens_nof_result-1) := (60, 40, 167, 120, 0);  -- 4 bytes as read by c_SEQ in unb1_board_sens_ctrl + sens_err
+  CONSTANT c_sens_expected    : t_natural_arr(0 TO c_sens_nof_result-1) := (60, 40, 167, 120, 0);  -- 4 bytes as read by c_SEQ in unb2_board_sens_ctrl + sens_err
   
   SIGNAL tb_end          : STD_LOGIC := '0';
   SIGNAL clk             : STD_LOGIC := '0';
@@ -152,7 +152,7 @@ BEGIN
   
   
   -- I2C sensors master
-  u_mms_unb1_board_sens : ENTITY work.mms_unb1_board_sens
+  u_mms_unb2_board_sens : ENTITY work.mms_unb2_board_sens
   GENERIC MAP (
     g_sim       => c_sim,
     g_clk_freq  => c_clk_freq,
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
index 703de911b4666612274a5476616664234e9e604c..746c6c700db23e45877cbc0af3540ade8c7f1c26 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
@@ -32,11 +32,11 @@ USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
 
 
-ENTITY tb_unb1_board_clk200_pll IS
-END tb_unb1_board_clk200_pll;
+ENTITY tb_unb2_board_clk200_pll IS
+END tb_unb2_board_clk200_pll;
 
 
-ARCHITECTURE tb OF tb_unb1_board_clk200_pll IS
+ARCHITECTURE tb OF tb_unb2_board_clk200_pll IS
 
   CONSTANT c_ext_clk_period    : TIME := 5 ns;               -- 200 MHz
   CONSTANT c_clk_vec_w         : NATURAL := 6;
@@ -73,7 +73,7 @@ BEGIN
   ext_clk <= NOT ext_clk OR tb_end AFTER c_ext_clk_period/2;
   ext_rst <= '1', '0' AFTER c_ext_clk_period*7;
   
-  dut_0 : ENTITY work.unb1_board_clk200_pll
+  dut_0 : ENTITY work.unb2_board_clk200_pll
   GENERIC MAP (
     g_sel                 => 0,  -- g_sel=0 for clk200_pll.vhd
     -- g_sel=0 for clk200_pll.vhd
@@ -91,7 +91,7 @@ BEGIN
     st_rst400  => st_rst400
   );
   
-  dut_45 : ENTITY work.unb1_board_clk200_pll
+  dut_45 : ENTITY work.unb2_board_clk200_pll
   GENERIC MAP (
     g_sel                 => 0,  -- g_sel=0 for clk200_pll.vhd
     -- g_sel=0 for clk200_pll.vhd
@@ -109,7 +109,7 @@ BEGIN
     st_rst400  => OPEN
   );
   
-  dut_p6 : ENTITY work.unb1_board_clk200_pll
+  dut_p6 : ENTITY work.unb2_board_clk200_pll
   GENERIC MAP (
     g_sel                 => 1,  -- g_sel=0 for clk200_pll.vhd
                                  -- g_sel=1 for clk200_pll_p6.vhd
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
index 642d51b167d4368d0d5317d0cf9781d3628b2f18..f39bf1acb55e69966d67fd9b77d00a9d1da2bd47 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
@@ -25,11 +25,11 @@ USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
 
 
-ENTITY tb_unb1_board_node_ctrl IS
-END tb_unb1_board_node_ctrl;
+ENTITY tb_unb2_board_node_ctrl IS
+END tb_unb2_board_node_ctrl;
 
 
-ARCHITECTURE tb OF tb_unb1_board_node_ctrl IS
+ARCHITECTURE tb OF tb_unb2_board_node_ctrl IS
 
   CONSTANT c_scale             : NATURAL := 100;             -- scale to speed up simulation
   
@@ -80,7 +80,7 @@ BEGIN
   
   wdi_in <= wdi AND sw;  -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
   
-  dut : ENTITY work.unb1_board_node_ctrl
+  dut : ENTITY work.unb2_board_node_ctrl
   GENERIC MAP (
     g_pulse_us     => c_pulse_us,
     g_pulse_ms     => c_pulse_ms,