diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
index aac313a366ac765030a0c1d645f0062e78de736b..b46dd29e2790e3b1d4546050c82b2d1257864ee6 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
@@ -1205,7 +1205,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>22</ipxact:right>
+ <ipxact:right>17</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -2157,7 +2157,7 @@
<ipxact:parameter parameterId="breakAbsoluteAddr" type="int">
<ipxact:name>breakAbsoluteAddr</ipxact:name>
<ipxact:displayName>Break vector</ipxact:displayName>
- <ipxact:value>6029344</ipxact:value>
+ <ipxact:value>114720</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="mmu_TLBMissExcAbsAddr" type="int">
<ipxact:name>mmu_TLBMissExcAbsAddr</ipxact:name>
@@ -2227,7 +2227,7 @@
<ipxact:parameter parameterId="instAddrWidth" type="int">
<ipxact:name>instAddrWidth</ipxact:name>
<ipxact:displayName>instAddrWidth</ipxact:displayName>
- <ipxact:value>23</ipxact:value>
+ <ipxact:value>18</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="faAddrWidth" type="int">
<ipxact:name>faAddrWidth</ipxact:name>
@@ -2292,7 +2292,7 @@
<ipxact:parameter parameterId="instSlaveMapParam" type="string">
<ipxact:name>instSlaveMapParam</ipxact:name>
<ipxact:displayName>instSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x5C0000' end='0x5C0800' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="faSlaveMapParam" type="string">
<ipxact:name>faSlaveMapParam</ipxact:name>
@@ -2302,7 +2302,7 @@
<ipxact:parameter parameterId="dataSlaveMapParam" type="string">
<ipxact:name>dataSlaveMapParam</ipxact:name>
<ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_heater.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='avs2_eth_coe_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs2_eth_coe_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x3300' end='0x3380' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x3380' end='0x3400' datawidth='32' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x3400' end='0x3480' datawidth='32' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3480' end='0x3500' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x3500' end='0x3540' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3540' end='0x3580' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3580' end='0x35C0' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x35C0' end='0x35E0' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x35E0' end='0x3600' datawidth='32' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x3600' end='0x3620' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x3620' end='0x3640' datawidth='32' /><slave name='reg_diag_bg_1gbe.mem' start='0x3640' end='0x3660' datawidth='32' /><slave name='reg_epcs.mem' start='0x3660' end='0x3680' datawidth='32' /><slave name='reg_remu.mem' start='0x3680' end='0x36A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x36A0' end='0x36C0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x36C0' end='0x36D0' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x36D0' end='0x36E0' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x36E0' end='0x36F0' datawidth='32' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x36F0' end='0x3700' datawidth='32' /><slave name='pio_pps.mem' start='0x3700' end='0x3710' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3710' end='0x3718' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3718' end='0x3720' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3720' end='0x3728' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3728' end='0x3730' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3730' end='0x3738' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3738' end='0x3740' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_diag_bg_1gbe.mem' start='0x18000' end='0x1A000' datawidth='32' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0x1A000' end='0x1C000' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x1C000' end='0x1E000' datawidth='32' /><slave name='avs2_eth_coe_1.mms_ram' start='0x1E000' end='0x1F000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x1F000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x5C0000' end='0x5C0800' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_eth1g_I_bsn_monitor_v2_rx.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_eth1g_I_strobe_total_count_rx.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='avs2_eth_coe_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs2_eth_coe_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_eth1g_I_bsn_monitor_v2_tx.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_eth1g_I_strobe_total_count_tx.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_eth1g_I_hdr_dat.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x18000' end='0x1A000' datawidth='32' /><slave name='avs2_eth_coe_1.mms_ram' start='0x1A000' end='0x1B000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x1B000' end='0x1C000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x1C800' end='0x1C900' datawidth='32' /><slave name='reg_eth1g_II_strobe_total_count_rx.mem' start='0x1C900' end='0x1C980' datawidth='32' /><slave name='reg_eth1g_II_strobe_total_count_tx.mem' start='0x1C980' end='0x1CA00' datawidth='32' /><slave name='reg_eth1g_II_hdr_dat.mem' start='0x1CA00' end='0x1CA80' datawidth='32' /><slave name='reg_eth1g_I_bg_ctrl.mem' start='0x1CA80' end='0x1CB00' datawidth='32' /><slave name='reg_heater.mem' start='0x1CB00' end='0x1CB80' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x1CB80' end='0x1CC00' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x1CC00' end='0x1CC80' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x1CC80' end='0x1CD00' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x1CD00' end='0x1CD40' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x1CD40' end='0x1CD80' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1CD80' end='0x1CDC0' datawidth='32' /><slave name='reg_eth1g_II_bg_ctrl.mem' start='0x1CDC0' end='0x1CDE0' datawidth='32' /><slave name='reg_eth1g_II_bsn_monitor_v2_rx.mem' start='0x1CDE0' end='0x1CE00' datawidth='32' /><slave name='reg_eth1g_II_bsn_monitor_v2_tx.mem' start='0x1CE00' end='0x1CE20' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x1CE20' end='0x1CE40' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x1CE40' end='0x1CE60' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x1CE60' end='0x1CE80' datawidth='32' /><slave name='reg_epcs.mem' start='0x1CE80' end='0x1CEA0' datawidth='32' /><slave name='reg_remu.mem' start='0x1CEA0' end='0x1CEC0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x1CEC0' end='0x1CEE0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x1CEE0' end='0x1CEF0' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x1CEF0' end='0x1CF00' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x1CF00' end='0x1CF10' datawidth='32' /><slave name='pio_pps.mem' start='0x1CF10' end='0x1CF20' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x1CF20' end='0x1CF28' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x1CF28' end='0x1CF30' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x1CF30' end='0x1CF38' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x1CF38' end='0x1CF40' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x1CF40' end='0x1CF48' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1CF48' end='0x1CF50' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
<ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -2428,7 +2428,7 @@
</ipxact:parameter>
<ipxact:parameter parameterId="embeddedsw.CMacro.BREAK_ADDR" type="string">
<ipxact:name>embeddedsw.CMacro.BREAK_ADDR</ipxact:name>
- <ipxact:value>0x005c0020</ipxact:value>
+ <ipxact:value>0x0001c020</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="embeddedsw.CMacro.CPU_ARCH_NIOS2_R1" type="string">
<ipxact:name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</ipxact:name>
@@ -2524,7 +2524,7 @@
</ipxact:parameter>
<ipxact:parameter parameterId="embeddedsw.CMacro.INST_ADDR_WIDTH" type="string">
<ipxact:name>embeddedsw.CMacro.INST_ADDR_WIDTH</ipxact:name>
- <ipxact:value>23</ipxact:value>
+ <ipxact:value>18</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="embeddedsw.CMacro.OCI_VERSION" type="string">
<ipxact:name>embeddedsw.CMacro.OCI_VERSION</ipxact:name>
@@ -2969,7 +2969,7 @@
<name>i_address</name>
<role>address</role>
<direction>Output</direction>
- <width>23</width>
+ <width>18</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -3584,7 +3584,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_heater.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_eth10g_qsfp_ring.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='avs2_eth_coe_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs2_eth_coe_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_eth10g_back0.mem' start='0x3200' end='0x3300' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x3300' end='0x3380' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_10gbe.mem' start='0x3380' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_1gbe.mem' start='0x3400' end='0x3480' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_1GbE.mem' start='0x3480' end='0x3500' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3500' end='0x3540' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_10gbe.mem' start='0x3540' end='0x3580' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x3580' end='0x35C0' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x35C0' end='0x35E0' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x35E0' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_1gbe.mem' start='0x3600' end='0x3620' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_10gbe.mem' start='0x3620' end='0x3640' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_1gbe.mem' start='0x3640' end='0x3660' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x3660' end='0x3680' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x3680' end='0x36A0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x36A0' end='0x36C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source.mem' start='0x36C0' end='0x36D0' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x36D0' end='0x36E0' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x36E0' end='0x36F0' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_1gbe.mem' start='0x36F0' end='0x3700' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3700' end='0x3710' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x3710' end='0x3718' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x3718' end='0x3720' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x3720' end='0x3728' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3728' end='0x3730' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3730' end='0x3738' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3738' end='0x3740' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='ram_diag_bg_1gbe.mem' start='0x18000' end='0x1A000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_1gbe.mem' start='0x1A000' end='0x1C000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_10GbE.mem' start='0x1C000' end='0x1E000' datawidth='32' /&gt;&lt;slave name='avs2_eth_coe_1.mms_ram' start='0x1E000' end='0x1F000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x1F000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /&gt;&lt;slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x5C0000' end='0x5C0800' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_bsn_monitor_v2_rx.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_strobe_total_count_rx.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='avs2_eth_coe_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs2_eth_coe_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_bsn_monitor_v2_tx.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_strobe_total_count_tx.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_hdr_dat.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_eth10g_qsfp_ring.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_10GbE.mem' start='0x18000' end='0x1A000' datawidth='32' /&gt;&lt;slave name='avs2_eth_coe_1.mms_ram' start='0x1A000' end='0x1B000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x1B000' end='0x1C000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /&gt;&lt;slave name='reg_eth10g_back0.mem' start='0x1C800' end='0x1C900' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_strobe_total_count_rx.mem' start='0x1C900' end='0x1C980' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_strobe_total_count_tx.mem' start='0x1C980' end='0x1CA00' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_hdr_dat.mem' start='0x1CA00' end='0x1CA80' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_bg_ctrl.mem' start='0x1CA80' end='0x1CB00' datawidth='32' /&gt;&lt;slave name='reg_heater.mem' start='0x1CB00' end='0x1CB80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x1CB80' end='0x1CC00' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x1CC00' end='0x1CC80' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_10gbe.mem' start='0x1CC80' end='0x1CD00' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x1CD00' end='0x1CD40' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_10gbe.mem' start='0x1CD40' end='0x1CD80' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x1CD80' end='0x1CDC0' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_bg_ctrl.mem' start='0x1CDC0' end='0x1CDE0' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_bsn_monitor_v2_rx.mem' start='0x1CDE0' end='0x1CE00' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_bsn_monitor_v2_tx.mem' start='0x1CE00' end='0x1CE20' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x1CE20' end='0x1CE40' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x1CE40' end='0x1CE60' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_10gbe.mem' start='0x1CE60' end='0x1CE80' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x1CE80' end='0x1CEA0' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x1CEA0' end='0x1CEC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x1CEC0' end='0x1CEE0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source.mem' start='0x1CEE0' end='0x1CEF0' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x1CEF0' end='0x1CF00' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x1CF00' end='0x1CF10' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x1CF10' end='0x1CF20' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x1CF20' end='0x1CF28' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x1CF28' end='0x1CF30' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x1CF30' end='0x1CF38' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x1CF38' end='0x1CF40' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x1CF40' end='0x1CF48' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x1CF48' end='0x1CF50' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /&gt;&lt;slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -3622,11 +3622,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x5C0000' end='0x5C0800' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>23</value>
+ <value>18</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
index 135d6ae74391c90055fd22b135c6780a0efa5429..dba9399a1b2de24b60fbdb14c7ff6935b74514f0 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_diag_rx_seq_1gbe</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_diag_rx_seq_1gbe</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_diag_rx_seq_1gbe</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_diag_rx_seq_1gbe
+ element qsys_unb2c_test_reg_eth1g_II_bg_ctrl
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_diag_rx_seq_1gbe.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_diag_rx_seq_1gbe.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_diag_rx_seq_1gbe.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_diag_rx_seq_1gbe.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_diag_rx_seq_1gbe.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_diag_rx_seq_1gbe.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_diag_rx_seq_1gbe.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_diag_rx_seq_1gbe.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_diag_rx_seq_1gbe.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_diag_rx_seq_1gbe.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
index 636fcc2c38881fdaf814c6885e242e69e73d6a2f..d2c116b0bd027b938feabf1cb356ba9d8134e463 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_diag_bg_1gbe</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_diag_bg_1gbe</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_diag_bg_1gbe</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_diag_bg_1gbe
+ element qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_diag_bg_1gbe.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_diag_bg_1gbe.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_diag_bg_1gbe.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_diag_bg_1gbe.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_diag_bg_1gbe.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_diag_bg_1gbe.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_diag_bg_1gbe.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_diag_bg_1gbe.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_diag_bg_1gbe.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_diag_bg_1gbe.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
similarity index 97%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
index 8645cb867e66312c9d638a8373bab949ea042460..e5c242e7222ee420cdc187d4acb42685392215ec 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_diag_tx_seq_1gbe</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_diag_tx_seq_1gbe</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>16</ipxact:value>
+ <ipxact:value>32</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>1</ipxact:right>
+ <ipxact:right>2</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>1</ipxact:right>
+ <ipxact:right>2</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_diag_tx_seq_1gbe</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -860,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>2</ipxact:value>
+ <ipxact:value>3</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_diag_tx_seq_1gbe
+ element qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx
{
}
}
@@ -997,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1066,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1295,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1462,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_diag_tx_seq_1gbe.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_diag_tx_seq_1gbe.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_diag_tx_seq_1gbe.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_diag_tx_seq_1gbe.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_diag_tx_seq_1gbe.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_diag_tx_seq_1gbe.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_diag_tx_seq_1gbe.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_diag_tx_seq_1gbe.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_diag_tx_seq_1gbe.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_diag_tx_seq_1gbe.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
index 4b56509a412b945ec2e60b1bb91ca5341570197d..d352a73115098dc4e0143ee126981738369ffc0e 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_1GbE</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_bsn_monitor_1GbE</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_II_hdr_dat</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_eth1g_II_hdr_dat</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_1GbE</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_II_hdr_dat</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_bsn_monitor_1GbE
+ element qsys_unb2c_test_reg_eth1g_II_hdr_dat
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_bsn_monitor_1GbE.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_bsn_monitor_1GbE.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_bsn_monitor_1GbE.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_bsn_monitor_1GbE.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_1GbE.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_1GbE.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_bsn_monitor_1GbE.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_1GbE.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_bsn_monitor_1GbE.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_1GbE.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
new file mode 100644
index 0000000000000000000000000000000000000000..60e87b376412f795566e2890e4c9a48217faa9a8
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>128</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>5</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>125000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>128</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>7</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
new file mode 100644
index 0000000000000000000000000000000000000000..0e21ab78fc7b77fd77d223d96837fc0542686ef5
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>128</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>5</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>125000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>128</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>7</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
new file mode 100644
index 0000000000000000000000000000000000000000..8b5349883e8ed1ae3e5f11e4a8cee2b2f100db1e
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>128</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>5</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>125000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_unb2c_test_reg_eth1g_I_bg_ctrl
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>128</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>7</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
index f86fb9568ec76cd886c81af61a73d910a11b3941..04e5061ee2e05437eb19b7999c3acf4500ae105d 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_diag_data_buffer_1gbe</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_diag_data_buffer_1gbe</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_diag_data_buffer_1gbe</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_diag_data_buffer_1gbe
+ element qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_diag_data_buffer_1gbe.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_diag_data_buffer_1gbe.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_diag_data_buffer_1gbe.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_diag_data_buffer_1gbe.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_diag_data_buffer_1gbe.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_diag_data_buffer_1gbe.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_diag_data_buffer_1gbe.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_diag_data_buffer_1gbe.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_diag_data_buffer_1gbe.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_diag_data_buffer_1gbe.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
similarity index 97%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
index ca4c806db410b0d28ac433a201bd7c364a48234c..969b7f6029a4ffef4df2a607493cf9649e3b5c1d 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_ram_diag_data_buffer_1gbe</ipxact:library>
- <ipxact:name>qsys_unb2c_test_ram_diag_data_buffer_1gbe</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>8192</ipxact:value>
+ <ipxact:value>128</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>10</ipxact:right>
+ <ipxact:right>4</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>10</ipxact:right>
+ <ipxact:right>4</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_ram_diag_data_buffer_1gbe</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -860,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>11</ipxact:value>
+ <ipxact:value>5</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_ram_diag_data_buffer_1gbe
+ element qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx
{
}
}
@@ -997,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>11</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1066,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8192</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1295,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>11</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1462,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x2000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>13</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_ram_diag_data_buffer_1gbe.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_ram_diag_data_buffer_1gbe.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_ram_diag_data_buffer_1gbe.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_ram_diag_data_buffer_1gbe.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_ram_diag_data_buffer_1gbe.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_ram_diag_data_buffer_1gbe.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_ram_diag_data_buffer_1gbe.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_ram_diag_data_buffer_1gbe.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_ram_diag_data_buffer_1gbe.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_ram_diag_data_buffer_1gbe.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
similarity index 97%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
index dcbfeecd90c2c00857282600ec8f37bb7a6328a3..0e9f2b1f5b8adc9145686dcd761143048bbeeca5 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_ram_diag_bg_1gbe</ipxact:library>
- <ipxact:name>qsys_unb2c_test_ram_diag_bg_1gbe</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_I_hdr_dat</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_eth1g_I_hdr_dat</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>8192</ipxact:value>
+ <ipxact:value>512</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>10</ipxact:right>
+ <ipxact:right>6</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>10</ipxact:right>
+ <ipxact:right>6</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_ram_diag_bg_1gbe</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_I_hdr_dat</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -860,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>11</ipxact:value>
+ <ipxact:value>7</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_ram_diag_bg_1gbe
+ element qsys_unb2c_test_reg_eth1g_I_hdr_dat
{
}
}
@@ -997,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>11</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1066,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8192</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1295,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>11</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1462,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x2000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x200' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>13</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_ram_diag_bg_1gbe.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_ram_diag_bg_1gbe.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_ram_diag_bg_1gbe.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_ram_diag_bg_1gbe.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_ram_diag_bg_1gbe.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_ram_diag_bg_1gbe.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_ram_diag_bg_1gbe.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_ram_diag_bg_1gbe.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_ram_diag_bg_1gbe.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_ram_diag_bg_1gbe.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
new file mode 100644
index 0000000000000000000000000000000000000000..d2b0b772d7e6cdfb315ef6e107e7b160abce9372
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>512</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>6</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>6</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>125000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>7</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>512</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>7</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x200' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>9</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
new file mode 100644
index 0000000000000000000000000000000000000000..1cc106178b974d387b36f88acd458bf7fc4ce2a9
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>512</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>6</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>6</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>125000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>7</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>512</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>7</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x200' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>9</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/qsys_unb2c_test.qsys b/boards/uniboard2c/designs/unb2c_test/quartus/qsys_unb2c_test.qsys
index a872aa7ef206e5a2eda9ccae7a64d957cbbbfe27..39f5d5f8ed1479c10720f85597925dbaa40dadc9 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/qsys_unb2c_test.qsys
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/qsys_unb2c_test.qsys
@@ -22,7 +22,7 @@
{
datum baseAddress
{
- value = "122880";
+ value = "106496";
type = "String";
}
}
@@ -54,7 +54,7 @@
{
datum baseAddress
{
- value = "126976";
+ value = "110592";
type = "String";
}
}
@@ -62,7 +62,7 @@
{
datum baseAddress
{
- value = "13568";
+ value = "118016";
type = "String";
}
}
@@ -94,7 +94,7 @@
{
datum baseAddress
{
- value = "6029312";
+ value = "114688";
type = "String";
}
}
@@ -102,7 +102,7 @@
{
datum _sortIndex
{
- value = "52";
+ value = "45";
type = "int";
}
}
@@ -126,7 +126,7 @@
{
datum baseAddress
{
- value = "14136";
+ value = "118600";
type = "String";
}
}
@@ -155,7 +155,7 @@
{
datum _sortIndex
{
- value = "56";
+ value = "49";
type = "int";
}
}
@@ -179,7 +179,7 @@
{
datum baseAddress
{
- value = "14080";
+ value = "118544";
type = "String";
}
}
@@ -224,7 +224,7 @@
{
datum _sortIndex
{
- value = "36";
+ value = "31";
type = "int";
}
}
@@ -236,215 +236,231 @@
type = "String";
}
}
- element ram_diag_bg_1gbe
+ element ram_diag_data_buffer_10gbe
{
datum _sortIndex
{
- value = "35";
+ value = "29";
type = "int";
}
}
- element ram_diag_bg_1gbe.mem
+ element ram_diag_data_buffer_10gbe.mem
{
datum baseAddress
{
- value = "98304";
+ value = "5242880";
type = "String";
}
}
- element ram_diag_data_buffer_10gbe
+ element ram_diag_data_buffer_bsn
{
datum _sortIndex
{
- value = "32";
+ value = "50";
type = "int";
}
}
- element ram_diag_data_buffer_10gbe.mem
+ element ram_diag_data_buffer_bsn.mem
{
datum baseAddress
{
- value = "5242880";
+ value = "8388608";
type = "String";
}
}
- element ram_diag_data_buffer_1gbe
+ element ram_diag_data_buffer_ddr_MB_I
{
datum _sortIndex
{
- value = "31";
+ value = "42";
type = "int";
}
}
- element ram_diag_data_buffer_1gbe.mem
+ element ram_diag_data_buffer_ddr_MB_I.mem
{
datum baseAddress
{
- value = "106496";
+ value = "57344";
type = "String";
}
}
- element ram_diag_data_buffer_bsn
+ element ram_diag_data_buffer_ddr_MB_II
{
datum _sortIndex
{
- value = "57";
+ value = "43";
type = "int";
}
}
- element ram_diag_data_buffer_bsn.mem
+ element ram_diag_data_buffer_ddr_MB_II.mem
{
datum baseAddress
{
- value = "8388608";
+ value = "49152";
type = "String";
}
}
- element ram_diag_data_buffer_ddr_MB_I
+ element ram_scrap
{
datum _sortIndex
{
- value = "49";
+ value = "20";
type = "int";
}
}
- element ram_diag_data_buffer_ddr_MB_I.mem
+ element ram_scrap.mem
{
datum baseAddress
{
- value = "57344";
+ value = "14336";
type = "String";
}
}
- element ram_diag_data_buffer_ddr_MB_II
+ element reg_bsn_monitor_10GbE
{
datum _sortIndex
{
- value = "50";
+ value = "27";
type = "int";
}
}
- element ram_diag_data_buffer_ddr_MB_II.mem
+ element reg_bsn_monitor_10GbE.mem
{
datum baseAddress
{
- value = "49152";
+ value = "98304";
type = "String";
}
}
- element ram_scrap
+ element reg_bsn_monitor_input
{
datum _sortIndex
{
- value = "20";
+ value = "46";
type = "int";
}
}
- element ram_scrap.mem
+ element reg_bsn_monitor_input.mem
{
datum baseAddress
{
- value = "14336";
+ value = "1024";
type = "String";
}
}
- element reg_bsn_monitor_10GbE
+ element reg_bsn_scheduler
{
datum _sortIndex
{
- value = "28";
+ value = "48";
type = "int";
}
}
- element reg_bsn_monitor_10GbE.mem
+ element reg_bsn_scheduler.mem
{
datum baseAddress
{
- value = "114688";
+ value = "118560";
type = "String";
}
}
- element reg_bsn_monitor_1GbE
+ element reg_bsn_source
{
datum _sortIndex
{
- value = "27";
+ value = "47";
type = "int";
}
}
- element reg_bsn_monitor_1GbE.mem
+ element reg_bsn_source.mem
{
datum baseAddress
{
- value = "13440";
+ value = "118496";
type = "String";
}
}
- element reg_bsn_monitor_input
+ element reg_diag_bg_10gbe
{
datum _sortIndex
{
- value = "53";
+ value = "30";
type = "int";
}
}
- element reg_bsn_monitor_input.mem
+ element reg_diag_bg_10gbe.mem
{
datum baseAddress
{
- value = "1024";
+ value = "118368";
type = "String";
}
}
- element reg_bsn_scheduler
+ element reg_diag_data_buffer_10gbe
{
datum _sortIndex
{
- value = "55";
+ value = "28";
type = "int";
}
}
- element reg_bsn_scheduler.mem
+ element reg_diag_data_buffer_10gbe.mem
{
datum baseAddress
{
- value = "14096";
+ value = "256";
type = "String";
}
}
- element reg_bsn_source
+ element reg_diag_data_buffer_bsn
{
datum _sortIndex
{
- value = "54";
+ value = "51";
type = "int";
}
}
- element reg_bsn_source.mem
+ element reg_diag_data_buffer_bsn.mem
{
datum baseAddress
{
- value = "14016";
+ value = "16384";
type = "String";
}
}
- element reg_diag_bg_10gbe
+ element reg_diag_data_buffer_ddr_MB_I
{
datum _sortIndex
{
- value = "34";
+ value = "40";
type = "int";
}
}
- element reg_diag_bg_10gbe.mem
+ element reg_diag_data_buffer_ddr_MB_I.mem
{
datum baseAddress
{
- value = "13856";
+ value = "117760";
type = "String";
}
}
- element reg_diag_bg_1gbe
+ element reg_diag_data_buffer_ddr_MB_II
+ {
+ datum _sortIndex
+ {
+ value = "41";
+ type = "int";
+ }
+ }
+ element reg_diag_data_buffer_ddr_MB_II.mem
+ {
+ datum baseAddress
+ {
+ value = "117632";
+ type = "String";
+ }
+ }
+ element reg_diag_rx_seq_10gbe
{
datum _sortIndex
{
@@ -452,311 +468,359 @@
type = "int";
}
}
- element reg_diag_bg_1gbe.mem
+ element reg_diag_rx_seq_10gbe.mem
{
datum baseAddress
{
- value = "13888";
+ value = "117888";
type = "String";
}
}
- element reg_diag_data_buffer_10gbe
+ element reg_diag_rx_seq_ddr_MB_I
{
datum _sortIndex
{
- value = "30";
+ value = "38";
type = "int";
}
}
- element reg_diag_data_buffer_10gbe.mem
+ element reg_diag_rx_seq_ddr_MB_I.mem
{
datum baseAddress
{
- value = "256";
+ value = "118336";
type = "String";
}
}
- element reg_diag_data_buffer_1gbe
+ element reg_diag_rx_seq_ddr_MB_II
{
datum _sortIndex
{
- value = "29";
+ value = "39";
type = "int";
}
}
- element reg_diag_data_buffer_1gbe.mem
+ element reg_diag_rx_seq_ddr_MB_II.mem
{
datum baseAddress
{
- value = "13312";
+ value = "118304";
type = "String";
}
}
- element reg_diag_data_buffer_bsn
+ element reg_diag_tx_seq_10gbe
{
datum _sortIndex
{
- value = "58";
+ value = "32";
type = "int";
}
}
- element reg_diag_data_buffer_bsn.mem
+ element reg_diag_tx_seq_10gbe.mem
{
datum baseAddress
{
- value = "16384";
+ value = "118080";
type = "String";
}
}
- element reg_diag_data_buffer_ddr_MB_I
+ element reg_diag_tx_seq_ddr_MB_I
{
datum _sortIndex
{
- value = "47";
+ value = "36";
type = "int";
}
}
- element reg_diag_data_buffer_ddr_MB_I.mem
+ element reg_diag_tx_seq_ddr_MB_I.mem
{
datum baseAddress
{
- value = "13056";
+ value = "118528";
type = "String";
}
}
- element reg_diag_data_buffer_ddr_MB_II
+ element reg_diag_tx_seq_ddr_MB_II
{
datum _sortIndex
{
- value = "48";
+ value = "37";
type = "int";
}
}
- element reg_diag_data_buffer_ddr_MB_II.mem
+ element reg_diag_tx_seq_ddr_MB_II.mem
{
datum baseAddress
{
- value = "12416";
+ value = "118512";
type = "String";
}
}
- element reg_diag_rx_seq_10gbe
+ element reg_dpmm_ctrl
{
datum _sortIndex
{
- value = "40";
+ value = "15";
type = "int";
}
}
- element reg_diag_rx_seq_10gbe.mem
+ element reg_dpmm_ctrl.mem
{
datum baseAddress
{
- value = "13184";
+ value = "118592";
type = "String";
}
}
- element reg_diag_rx_seq_1gbe
+ element reg_dpmm_data
{
datum _sortIndex
{
- value = "38";
+ value = "16";
type = "int";
}
}
- element reg_diag_rx_seq_1gbe.mem
+ element reg_dpmm_data.mem
{
datum baseAddress
{
- value = "13824";
+ value = "118584";
type = "String";
}
}
- element reg_diag_rx_seq_ddr_MB_I
+ element reg_epcs
{
datum _sortIndex
{
- value = "45";
+ value = "13";
type = "int";
}
}
- element reg_diag_rx_seq_ddr_MB_I.mem
+ element reg_epcs.mem
{
datum baseAddress
{
- value = "13792";
+ value = "118400";
type = "String";
}
}
- element reg_diag_rx_seq_ddr_MB_II
+ element reg_eth10g_back0
{
datum _sortIndex
{
- value = "46";
+ value = "25";
type = "int";
}
}
- element reg_diag_rx_seq_ddr_MB_II.mem
+ element reg_eth10g_back0.mem
{
datum baseAddress
{
- value = "13760";
+ value = "116736";
type = "String";
}
}
- element reg_diag_tx_seq_10gbe
+ element reg_eth10g_back1
{
datum _sortIndex
{
- value = "39";
+ value = "26";
type = "int";
}
}
- element reg_diag_tx_seq_10gbe.mem
+ element reg_eth10g_back1.mem
{
datum baseAddress
{
- value = "13632";
+ value = "12544";
type = "String";
}
}
- element reg_diag_tx_seq_1gbe
+ element reg_eth10g_qsfp_ring
{
datum _sortIndex
{
- value = "37";
+ value = "24";
type = "int";
}
}
- element reg_diag_tx_seq_1gbe.mem
+ element reg_eth10g_qsfp_ring.mem
{
datum baseAddress
{
- value = "14064";
+ value = "13824";
type = "String";
}
}
- element reg_diag_tx_seq_ddr_MB_I
+ element reg_eth1g_II_bg_ctrl
{
datum _sortIndex
{
- value = "43";
+ value = "63";
type = "int";
}
}
- element reg_diag_tx_seq_ddr_MB_I.mem
+ element reg_eth1g_II_bg_ctrl.mem
{
datum baseAddress
{
- value = "14048";
+ value = "118208";
type = "String";
}
}
- element reg_diag_tx_seq_ddr_MB_II
+ element reg_eth1g_II_bsn_monitor_v2_rx
{
datum _sortIndex
{
- value = "44";
+ value = "56";
type = "int";
}
}
- element reg_diag_tx_seq_ddr_MB_II.mem
+ element reg_eth1g_II_bsn_monitor_v2_rx.mem
{
datum baseAddress
{
- value = "14032";
+ value = "118240";
type = "String";
}
}
- element reg_dpmm_ctrl
+ element reg_eth1g_II_bsn_monitor_v2_tx
{
datum _sortIndex
{
- value = "15";
+ value = "54";
type = "int";
}
}
- element reg_dpmm_ctrl.mem
+ element reg_eth1g_II_bsn_monitor_v2_tx.mem
{
datum baseAddress
{
- value = "14128";
+ value = "118272";
type = "String";
}
}
- element reg_dpmm_data
+ element reg_eth1g_II_hdr_dat
{
datum _sortIndex
{
- value = "16";
+ value = "53";
type = "int";
}
}
- element reg_dpmm_data.mem
+ element reg_eth1g_II_hdr_dat.mem
{
datum baseAddress
{
- value = "14120";
+ value = "117248";
type = "String";
}
}
- element reg_epcs
+ element reg_eth1g_II_strobe_total_count_rx
{
datum _sortIndex
{
- value = "13";
+ value = "57";
type = "int";
}
}
- element reg_epcs.mem
+ element reg_eth1g_II_strobe_total_count_rx.mem
{
datum baseAddress
{
- value = "13920";
+ value = "116992";
type = "String";
}
}
- element reg_eth10g_back0
+ element reg_eth1g_II_strobe_total_count_tx
{
datum _sortIndex
{
- value = "25";
+ value = "55";
type = "int";
}
}
- element reg_eth10g_back0.mem
+ element reg_eth1g_II_strobe_total_count_tx.mem
{
datum baseAddress
{
- value = "12800";
+ value = "117120";
type = "String";
}
}
- element reg_eth10g_back1
+ element reg_eth1g_I_bg_ctrl
{
datum _sortIndex
{
- value = "26";
+ value = "52";
type = "int";
}
}
- element reg_eth10g_back1.mem
+ element reg_eth1g_I_bg_ctrl.mem
{
datum baseAddress
{
- value = "12544";
+ value = "117376";
type = "String";
}
}
- element reg_eth10g_qsfp_ring
+ element reg_eth1g_I_bsn_monitor_v2_rx
{
datum _sortIndex
{
- value = "24";
+ value = "61";
type = "int";
}
}
- element reg_eth10g_qsfp_ring.mem
+ element reg_eth1g_I_bsn_monitor_v2_rx.mem
+ {
+ datum baseAddress
+ {
+ value = "128";
+ type = "String";
+ }
+ }
+ element reg_eth1g_I_bsn_monitor_v2_tx
+ {
+ datum _sortIndex
+ {
+ value = "59";
+ type = "int";
+ }
+ }
+ element reg_eth1g_I_bsn_monitor_v2_tx.mem
+ {
+ datum baseAddress
+ {
+ value = "12416";
+ type = "String";
+ }
+ }
+ element reg_eth1g_I_hdr_dat
+ {
+ datum _sortIndex
+ {
+ value = "58";
+ type = "int";
+ }
+ }
+ element reg_eth1g_I_hdr_dat.mem
+ {
+ datum baseAddress
+ {
+ value = "13312";
+ type = "String";
+ }
+ }
+ element reg_eth1g_I_strobe_total_count_rx
+ {
+ datum _sortIndex
+ {
+ value = "62";
+ type = "int";
+ }
+ }
+ element reg_eth1g_I_strobe_total_count_rx.mem
{
datum baseAddress
{
@@ -764,6 +828,22 @@
type = "String";
}
}
+ element reg_eth1g_I_strobe_total_count_tx
+ {
+ datum _sortIndex
+ {
+ value = "60";
+ type = "int";
+ }
+ }
+ element reg_eth1g_I_strobe_total_count_tx.mem
+ {
+ datum baseAddress
+ {
+ value = "12800";
+ type = "String";
+ }
+ }
element reg_fpga_temp_sens
{
datum _sortIndex
@@ -776,7 +856,7 @@
{
datum baseAddress
{
- value = "13984";
+ value = "118464";
type = "String";
}
}
@@ -792,7 +872,7 @@
{
datum baseAddress
{
- value = "13696";
+ value = "118144";
type = "String";
}
}
@@ -800,7 +880,7 @@
{
datum _sortIndex
{
- value = "51";
+ value = "44";
type = "int";
}
}
@@ -808,7 +888,7 @@
{
datum baseAddress
{
- value = "128";
+ value = "117504";
type = "String";
}
}
@@ -816,7 +896,7 @@
{
datum _sortIndex
{
- value = "41";
+ value = "34";
type = "int";
}
}
@@ -832,7 +912,7 @@
{
datum _sortIndex
{
- value = "42";
+ value = "35";
type = "int";
}
}
@@ -856,7 +936,7 @@
{
datum baseAddress
{
- value = "14112";
+ value = "118576";
type = "String";
}
}
@@ -872,7 +952,7 @@
{
datum baseAddress
{
- value = "14104";
+ value = "118568";
type = "String";
}
}
@@ -888,7 +968,7 @@
{
datum baseAddress
{
- value = "13952";
+ value = "118432";
type = "String";
}
}
@@ -1392,41 +1472,6 @@
internal="ram_diag_bg_10gbe.writedata"
type="conduit"
dir="end" />
- <interface
- name="ram_diag_bg_1gbe_address"
- internal="ram_diag_bg_1gbe.address"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_bg_1gbe_clk"
- internal="ram_diag_bg_1gbe.clk"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_bg_1gbe_read"
- internal="ram_diag_bg_1gbe.read"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_bg_1gbe_readdata"
- internal="ram_diag_bg_1gbe.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_bg_1gbe_reset"
- internal="ram_diag_bg_1gbe.reset"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_bg_1gbe_write"
- internal="ram_diag_bg_1gbe.write"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_bg_1gbe_writedata"
- internal="ram_diag_bg_1gbe.writedata"
- type="conduit"
- dir="end" />
<interface
name="ram_diag_data_buffer_10gbe_address"
internal="ram_diag_data_buffer_10gbe.address"
@@ -1462,41 +1507,6 @@
internal="ram_diag_data_buffer_10gbe.writedata"
type="conduit"
dir="end" />
- <interface
- name="ram_diag_data_buffer_1gbe_address"
- internal="ram_diag_data_buffer_1gbe.address"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_data_buffer_1gbe_clk"
- internal="ram_diag_data_buffer_1gbe.clk"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_data_buffer_1gbe_read"
- internal="ram_diag_data_buffer_1gbe.read"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_data_buffer_1gbe_readdata"
- internal="ram_diag_data_buffer_1gbe.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_data_buffer_1gbe_reset"
- internal="ram_diag_data_buffer_1gbe.reset"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_data_buffer_1gbe_write"
- internal="ram_diag_data_buffer_1gbe.write"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_data_buffer_1gbe_writedata"
- internal="ram_diag_data_buffer_1gbe.writedata"
- type="conduit"
- dir="end" />
<interface
name="ram_diag_data_buffer_bsn_address"
internal="ram_diag_data_buffer_bsn.address"
@@ -1672,41 +1682,6 @@
internal="reg_bsn_monitor_10GbE.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_bsn_monitor_1gbe_address"
- internal="reg_bsn_monitor_1GbE.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_bsn_monitor_1gbe_clk"
- internal="reg_bsn_monitor_1GbE.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_bsn_monitor_1gbe_read"
- internal="reg_bsn_monitor_1GbE.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_bsn_monitor_1gbe_readdata"
- internal="reg_bsn_monitor_1GbE.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_bsn_monitor_1gbe_reset"
- internal="reg_bsn_monitor_1GbE.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_bsn_monitor_1gbe_write"
- internal="reg_bsn_monitor_1GbE.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_bsn_monitor_1gbe_writedata"
- internal="reg_bsn_monitor_1GbE.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_bsn_monitor_input_address"
internal="reg_bsn_monitor_input.address"
@@ -1847,41 +1822,6 @@
internal="reg_diag_bg_10gbe.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_diag_bg_1gbe_address"
- internal="reg_diag_bg_1gbe.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_bg_1gbe_clk"
- internal="reg_diag_bg_1gbe.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_bg_1gbe_read"
- internal="reg_diag_bg_1gbe.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_bg_1gbe_readdata"
- internal="reg_diag_bg_1gbe.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_bg_1gbe_reset"
- internal="reg_diag_bg_1gbe.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_bg_1gbe_write"
- internal="reg_diag_bg_1gbe.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_bg_1gbe_writedata"
- internal="reg_diag_bg_1gbe.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_diag_data_buffer_10gbe_address"
internal="reg_diag_data_buffer_10gbe.address"
@@ -1917,41 +1857,6 @@
internal="reg_diag_data_buffer_10gbe.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_diag_data_buffer_1gbe_address"
- internal="reg_diag_data_buffer_1gbe.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_data_buffer_1gbe_clk"
- internal="reg_diag_data_buffer_1gbe.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_data_buffer_1gbe_read"
- internal="reg_diag_data_buffer_1gbe.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_data_buffer_1gbe_readdata"
- internal="reg_diag_data_buffer_1gbe.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_data_buffer_1gbe_reset"
- internal="reg_diag_data_buffer_1gbe.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_data_buffer_1gbe_write"
- internal="reg_diag_data_buffer_1gbe.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_data_buffer_1gbe_writedata"
- internal="reg_diag_data_buffer_1gbe.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_diag_data_buffer_bsn_address"
internal="reg_diag_data_buffer_bsn.address"
@@ -2092,41 +1997,6 @@
internal="reg_diag_rx_seq_10gbe.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_diag_rx_seq_1gbe_address"
- internal="reg_diag_rx_seq_1gbe.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_rx_seq_1gbe_clk"
- internal="reg_diag_rx_seq_1gbe.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_rx_seq_1gbe_read"
- internal="reg_diag_rx_seq_1gbe.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_rx_seq_1gbe_readdata"
- internal="reg_diag_rx_seq_1gbe.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_rx_seq_1gbe_reset"
- internal="reg_diag_rx_seq_1gbe.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_rx_seq_1gbe_write"
- internal="reg_diag_rx_seq_1gbe.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_rx_seq_1gbe_writedata"
- internal="reg_diag_rx_seq_1gbe.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_diag_rx_seq_ddr_mb_i_address"
internal="reg_diag_rx_seq_ddr_MB_I.address"
@@ -2232,41 +2102,6 @@
internal="reg_diag_tx_seq_10gbe.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_diag_tx_seq_1gbe_address"
- internal="reg_diag_tx_seq_1gbe.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_tx_seq_1gbe_clk"
- internal="reg_diag_tx_seq_1gbe.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_tx_seq_1gbe_read"
- internal="reg_diag_tx_seq_1gbe.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_tx_seq_1gbe_readdata"
- internal="reg_diag_tx_seq_1gbe.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_tx_seq_1gbe_reset"
- internal="reg_diag_tx_seq_1gbe.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_tx_seq_1gbe_write"
- internal="reg_diag_tx_seq_1gbe.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_tx_seq_1gbe_writedata"
- internal="reg_diag_tx_seq_1gbe.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_diag_tx_seq_ddr_mb_i_address"
internal="reg_diag_tx_seq_ddr_MB_I.address"
@@ -2543,6 +2378,426 @@
internal="reg_eth10g_qsfp_ring.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_eth1g_i_bg_ctrl_address"
+ internal="reg_eth1g_I_bg_ctrl.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bg_ctrl_clk"
+ internal="reg_eth1g_I_bg_ctrl.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bg_ctrl_read"
+ internal="reg_eth1g_I_bg_ctrl.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bg_ctrl_readdata"
+ internal="reg_eth1g_I_bg_ctrl.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bg_ctrl_reset"
+ internal="reg_eth1g_I_bg_ctrl.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bg_ctrl_write"
+ internal="reg_eth1g_I_bg_ctrl.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bg_ctrl_writedata"
+ internal="reg_eth1g_I_bg_ctrl.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bsn_monitor_v2_rx_address"
+ internal="reg_eth1g_I_bsn_monitor_v2_rx.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bsn_monitor_v2_rx_clk"
+ internal="reg_eth1g_I_bsn_monitor_v2_rx.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bsn_monitor_v2_rx_read"
+ internal="reg_eth1g_I_bsn_monitor_v2_rx.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bsn_monitor_v2_rx_readdata"
+ internal="reg_eth1g_I_bsn_monitor_v2_rx.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bsn_monitor_v2_rx_reset"
+ internal="reg_eth1g_I_bsn_monitor_v2_rx.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bsn_monitor_v2_rx_write"
+ internal="reg_eth1g_I_bsn_monitor_v2_rx.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bsn_monitor_v2_rx_writedata"
+ internal="reg_eth1g_I_bsn_monitor_v2_rx.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bsn_monitor_v2_tx_address"
+ internal="reg_eth1g_I_bsn_monitor_v2_tx.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bsn_monitor_v2_tx_clk"
+ internal="reg_eth1g_I_bsn_monitor_v2_tx.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bsn_monitor_v2_tx_read"
+ internal="reg_eth1g_I_bsn_monitor_v2_tx.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bsn_monitor_v2_tx_readdata"
+ internal="reg_eth1g_I_bsn_monitor_v2_tx.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bsn_monitor_v2_tx_reset"
+ internal="reg_eth1g_I_bsn_monitor_v2_tx.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bsn_monitor_v2_tx_write"
+ internal="reg_eth1g_I_bsn_monitor_v2_tx.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_bsn_monitor_v2_tx_writedata"
+ internal="reg_eth1g_I_bsn_monitor_v2_tx.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_hdr_dat_address"
+ internal="reg_eth1g_I_hdr_dat.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_hdr_dat_clk"
+ internal="reg_eth1g_I_hdr_dat.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_hdr_dat_read"
+ internal="reg_eth1g_I_hdr_dat.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_hdr_dat_readdata"
+ internal="reg_eth1g_I_hdr_dat.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_hdr_dat_reset"
+ internal="reg_eth1g_I_hdr_dat.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_hdr_dat_write"
+ internal="reg_eth1g_I_hdr_dat.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_hdr_dat_writedata"
+ internal="reg_eth1g_I_hdr_dat.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_strobe_total_count_rx_address"
+ internal="reg_eth1g_I_strobe_total_count_rx.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_strobe_total_count_rx_clk"
+ internal="reg_eth1g_I_strobe_total_count_rx.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_strobe_total_count_rx_read"
+ internal="reg_eth1g_I_strobe_total_count_rx.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_strobe_total_count_rx_readdata"
+ internal="reg_eth1g_I_strobe_total_count_rx.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_strobe_total_count_rx_reset"
+ internal="reg_eth1g_I_strobe_total_count_rx.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_strobe_total_count_rx_write"
+ internal="reg_eth1g_I_strobe_total_count_rx.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_strobe_total_count_rx_writedata"
+ internal="reg_eth1g_I_strobe_total_count_rx.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_strobe_total_count_tx_address"
+ internal="reg_eth1g_I_strobe_total_count_tx.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_strobe_total_count_tx_clk"
+ internal="reg_eth1g_I_strobe_total_count_tx.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_strobe_total_count_tx_read"
+ internal="reg_eth1g_I_strobe_total_count_tx.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_strobe_total_count_tx_readdata"
+ internal="reg_eth1g_I_strobe_total_count_tx.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_strobe_total_count_tx_reset"
+ internal="reg_eth1g_I_strobe_total_count_tx.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_strobe_total_count_tx_write"
+ internal="reg_eth1g_I_strobe_total_count_tx.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_i_strobe_total_count_tx_writedata"
+ internal="reg_eth1g_I_strobe_total_count_tx.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bg_ctrl_address"
+ internal="reg_eth1g_II_bg_ctrl.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bg_ctrl_clk"
+ internal="reg_eth1g_II_bg_ctrl.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bg_ctrl_read"
+ internal="reg_eth1g_II_bg_ctrl.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bg_ctrl_readdata"
+ internal="reg_eth1g_II_bg_ctrl.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bg_ctrl_reset"
+ internal="reg_eth1g_II_bg_ctrl.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bg_ctrl_write"
+ internal="reg_eth1g_II_bg_ctrl.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bg_ctrl_writedata"
+ internal="reg_eth1g_II_bg_ctrl.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bsn_monitor_v2_rx_address"
+ internal="reg_eth1g_II_bsn_monitor_v2_rx.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bsn_monitor_v2_rx_clk"
+ internal="reg_eth1g_II_bsn_monitor_v2_rx.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bsn_monitor_v2_rx_read"
+ internal="reg_eth1g_II_bsn_monitor_v2_rx.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bsn_monitor_v2_rx_readdata"
+ internal="reg_eth1g_II_bsn_monitor_v2_rx.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bsn_monitor_v2_rx_reset"
+ internal="reg_eth1g_II_bsn_monitor_v2_rx.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bsn_monitor_v2_rx_write"
+ internal="reg_eth1g_II_bsn_monitor_v2_rx.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bsn_monitor_v2_rx_writedata"
+ internal="reg_eth1g_II_bsn_monitor_v2_rx.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bsn_monitor_v2_tx_address"
+ internal="reg_eth1g_II_bsn_monitor_v2_tx.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bsn_monitor_v2_tx_clk"
+ internal="reg_eth1g_II_bsn_monitor_v2_tx.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bsn_monitor_v2_tx_read"
+ internal="reg_eth1g_II_bsn_monitor_v2_tx.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bsn_monitor_v2_tx_readdata"
+ internal="reg_eth1g_II_bsn_monitor_v2_tx.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bsn_monitor_v2_tx_reset"
+ internal="reg_eth1g_II_bsn_monitor_v2_tx.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bsn_monitor_v2_tx_write"
+ internal="reg_eth1g_II_bsn_monitor_v2_tx.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_bsn_monitor_v2_tx_writedata"
+ internal="reg_eth1g_II_bsn_monitor_v2_tx.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_hdr_dat_address"
+ internal="reg_eth1g_II_hdr_dat.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_hdr_dat_clk"
+ internal="reg_eth1g_II_hdr_dat.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_hdr_dat_read"
+ internal="reg_eth1g_II_hdr_dat.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_hdr_dat_readdata"
+ internal="reg_eth1g_II_hdr_dat.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_hdr_dat_reset"
+ internal="reg_eth1g_II_hdr_dat.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_hdr_dat_write"
+ internal="reg_eth1g_II_hdr_dat.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_hdr_dat_writedata"
+ internal="reg_eth1g_II_hdr_dat.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_strobe_total_count_rx_address"
+ internal="reg_eth1g_II_strobe_total_count_rx.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_strobe_total_count_rx_clk"
+ internal="reg_eth1g_II_strobe_total_count_rx.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_strobe_total_count_rx_read"
+ internal="reg_eth1g_II_strobe_total_count_rx.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_strobe_total_count_rx_readdata"
+ internal="reg_eth1g_II_strobe_total_count_rx.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_strobe_total_count_rx_reset"
+ internal="reg_eth1g_II_strobe_total_count_rx.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_strobe_total_count_rx_write"
+ internal="reg_eth1g_II_strobe_total_count_rx.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_strobe_total_count_rx_writedata"
+ internal="reg_eth1g_II_strobe_total_count_rx.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_strobe_total_count_tx_address"
+ internal="reg_eth1g_II_strobe_total_count_tx.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_strobe_total_count_tx_clk"
+ internal="reg_eth1g_II_strobe_total_count_tx.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_strobe_total_count_tx_read"
+ internal="reg_eth1g_II_strobe_total_count_tx.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_strobe_total_count_tx_readdata"
+ internal="reg_eth1g_II_strobe_total_count_tx.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_strobe_total_count_tx_reset"
+ internal="reg_eth1g_II_strobe_total_count_tx.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_strobe_total_count_tx_write"
+ internal="reg_eth1g_II_strobe_total_count_tx.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth1g_ii_strobe_total_count_tx_writedata"
+ internal="reg_eth1g_II_strobe_total_count_tx.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_fpga_temp_sens_address"
internal="reg_fpga_temp_sens.address"
@@ -9155,36 +9410,39 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>clk_in</name>
+ <name>clk</name>
<type>clock</type>
- <isStart>false</isStart>
+ <isStart>true</isStart>
<ports>
<port>
- <name>in_clk</name>
+ <name>clk_out</name>
<role>clk</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>clk</value>
- </entry>
- </assignmentValueMap>
+ <assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
+ <entry>
+ <key>associatedDirectClock</key>
+ <value>clk_in</value>
+ </entry>
<entry>
<key>clockRate</key>
<value>125000000</value>
</entry>
+ <entry>
+ <key>clockRateKnown</key>
+ <value>true</value>
+ </entry>
<entry>
<key>externallyDriven</key>
- <value>false</value>
+ <value>true</value>
</entry>
<entry>
<key>ptfSchematicName</key>
@@ -9193,13 +9451,13 @@
</parameters>
</interface>
<interface>
- <name>clk_in_reset</name>
- <type>reset</type>
+ <name>clk_in</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>reset_n</name>
- <role>reset_n</role>
+ <name>in_clk</name>
+ <role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -9210,59 +9468,56 @@
<assignmentValueMap>
<entry>
<key>qsys.ui.export_name</key>
- <value>reset</value>
+ <value>clk</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>125000000</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>true</isStart>
+ <name>clk_in_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
<ports>
<port>
- <name>clk_out</name>
- <role>clk</role>
- <direction>Output</direction>
+ <name>reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
- <assignmentValueMap/>
+ <assignmentValueMap>
+ <entry>
+ <key>qsys.ui.export_name</key>
+ <value>reset</value>
+ </entry>
+ </assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
- <key>associatedDirectClock</key>
- <value>clk_in</value>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>125000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>true</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
@@ -9642,7 +9897,7 @@
<name>i_address</name>
<role>address</role>
<direction>Output</direction>
- <width>23</width>
+ <width>18</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -10525,11 +10780,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_heater.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='avs2_eth_coe_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs2_eth_coe_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x3300' end='0x3380' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x3380' end='0x3400' datawidth='32' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x3400' end='0x3480' datawidth='32' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3480' end='0x3500' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x3500' end='0x3540' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3540' end='0x3580' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3580' end='0x35C0' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x35C0' end='0x35E0' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x35E0' end='0x3600' datawidth='32' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x3600' end='0x3620' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x3620' end='0x3640' datawidth='32' /><slave name='reg_diag_bg_1gbe.mem' start='0x3640' end='0x3660' datawidth='32' /><slave name='reg_epcs.mem' start='0x3660' end='0x3680' datawidth='32' /><slave name='reg_remu.mem' start='0x3680' end='0x36A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x36A0' end='0x36C0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x36C0' end='0x36D0' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x36D0' end='0x36E0' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x36E0' end='0x36F0' datawidth='32' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x36F0' end='0x3700' datawidth='32' /><slave name='pio_pps.mem' start='0x3700' end='0x3710' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3710' end='0x3718' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3718' end='0x3720' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3720' end='0x3728' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3728' end='0x3730' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3730' end='0x3738' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3738' end='0x3740' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_diag_bg_1gbe.mem' start='0x18000' end='0x1A000' datawidth='32' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0x1A000' end='0x1C000' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x1C000' end='0x1E000' datawidth='32' /><slave name='avs2_eth_coe_1.mms_ram' start='0x1E000' end='0x1F000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x1F000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x5C0000' end='0x5C0800' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>24</value>
+ <value>1</value>
</entry>
</consumedSystemInfos>
</value>
@@ -10563,11 +10818,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x5C0000' end='0x5C0800' datawidth='32' /></address-map></value>
+ <value></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>23</value>
+ <value>1</value>
</entry>
</consumedSystemInfos>
</value>
@@ -10888,7 +11143,7 @@
<name>i_address</name>
<role>address</role>
<direction>Output</direction>
- <width>23</width>
+ <width>18</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -11081,7 +11336,7 @@
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
- <value>cpu_0.data_master</value>
+ <value>nios2_gen2_0.data_master</value>
</entry>
<entry>
<key>associatedClock</key>
@@ -11214,21 +11469,9 @@
<key>embeddedsw.configuration.hideDevice</key>
<value>1</value>
</entry>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
+ <value>true</value>
</entry>
<entry>
<key>qsys.ui.connect</key>
@@ -11493,7 +11736,7 @@
</entry>
<entry>
<key>embeddedsw.CMacro.BREAK_ADDR</key>
- <value>0x005c0020</value>
+ <value>0x0001c020</value>
</entry>
<entry>
<key>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</key>
@@ -11589,7 +11832,7 @@
</entry>
<entry>
<key>embeddedsw.CMacro.INST_ADDR_WIDTH</key>
- <value>23</value>
+ <value>18</value>
</entry>
<entry>
<key>embeddedsw.CMacro.OCI_VERSION</key>
@@ -20365,7 +20608,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_diag_bg_1gbe"
+ name="ram_diag_data_buffer_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20444,7 +20687,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>11</width>
+ <width>17</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20513,7 +20756,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8192</value>
+ <value>524288</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20742,7 +20985,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>11</width>
+ <width>17</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20920,11 +21163,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x2000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>13</value>
+ <value>19</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21024,7 +21267,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>11</width>
+ <width>17</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21093,7 +21336,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8192</value>
+ <value>524288</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21322,7 +21565,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>11</width>
+ <width>17</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21476,37 +21719,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_ram_diag_bg_1gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_ram_diag_data_buffer_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_bg_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_bg_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_bg_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_bg_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_bg_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_bg_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_diag_data_buffer_10gbe"
+ name="ram_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21585,7 +21828,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>17</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21654,7 +21897,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>524288</value>
+ <value>8388608</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21883,7 +22126,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>17</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22061,11 +22304,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x800000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>19</value>
+ <value>23</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22165,7 +22408,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>17</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22234,7 +22477,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>524288</value>
+ <value>8388608</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -22463,7 +22706,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>17</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22617,37 +22860,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_ram_diag_data_buffer_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_ram_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_diag_data_buffer_1gbe"
+ name="ram_diag_data_buffer_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23758,37 +24001,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_ram_diag_data_buffer_1gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_diag_data_buffer_bsn"
+ name="ram_diag_data_buffer_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23867,7 +24110,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>21</width>
+ <width>11</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23936,7 +24179,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8388608</value>
+ <value>8192</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24165,7 +24408,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>21</width>
+ <width>11</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24343,11 +24586,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x800000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x2000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>23</value>
+ <value>13</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24447,7 +24690,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>21</width>
+ <width>11</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24516,7 +24759,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8388608</value>
+ <value>8192</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24745,7 +24988,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>21</width>
+ <width>11</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24899,37 +25142,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_ram_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_diag_data_buffer_ddr_MB_I"
+ name="ram_scrap"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -25008,7 +25251,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>11</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25077,7 +25320,5712 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8192</value>
+ <value>2048</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>2</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm_readlatency2</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm_readlatency2</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>11</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>2048</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>2</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_unb2c_test_ram_scrap</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_unb2c_minimal_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_scrap</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2c_minimal_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_scrap</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2c_minimal_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_ram_scrap</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_bsn_monitor_10GbE"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>11</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8192</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>11</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x2000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>13</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>11</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8192</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>11</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_monitor_10GbE</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_10GbE</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_10GbE</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_10GbE</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_10GbE</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_10GbE</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_10GbE</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_bsn_monitor_input"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>1024</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>10</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>1024</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_monitor_input</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_bsn_scheduler"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_scheduler</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_bsn_source"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>4</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_source</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_diag_bg_10gbe"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -25306,7 +31254,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>11</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25484,11 +31432,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x2000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>13</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -25588,7 +31536,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>11</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25657,7 +31605,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8192</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -25886,7 +31834,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>11</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26040,37 +31988,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_bg_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_diag_data_buffer_ddr_MB_II"
+ name="reg_diag_data_buffer_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26149,7 +32097,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>11</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26218,7 +32166,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8192</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26447,7 +32395,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>11</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26625,11 +32573,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x2000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>13</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26729,7 +32677,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>11</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26798,7 +32746,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8192</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27027,7 +32975,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>11</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27181,37 +33129,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_scrap"
+ name="reg_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27290,7 +33238,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>9</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27359,7 +33307,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>2048</value>
+ <value>16384</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27462,7 +33410,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>2</value>
+ <value>1</value>
</entry>
<entry>
<key>readWaitStates</key>
@@ -27588,7 +33536,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>9</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27742,9 +33690,9 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>avs_common_mm_readlatency2</className>
+ <className>avs_common_mm</className>
<version>1.0</version>
- <displayName>avs_common_mm_readlatency2</displayName>
+ <displayName>avs_common_mm</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -27766,11 +33714,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>11</value>
+ <value>14</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27870,7 +33818,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>9</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27939,7 +33887,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>2048</value>
+ <value>16384</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28042,7 +33990,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>2</value>
+ <value>1</value>
</entry>
<entry>
<key>readWaitStates</key>
@@ -28168,7 +34116,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>9</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28322,37 +34270,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_ram_scrap</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_10GbE"
+ name="reg_diag_data_buffer_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -28431,7 +34379,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>11</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28500,7 +34448,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8192</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28729,7 +34677,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>11</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28907,11 +34855,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x2000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>13</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -29011,7 +34959,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>11</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29080,7 +35028,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8192</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29309,7 +35257,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>11</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29463,37 +35411,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_bsn_monitor_10GbE</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_monitor_10GbE</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_10GbE</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_monitor_10GbE</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_10GbE</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_monitor_10GbE</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_10GbE</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_1GbE"
+ name="reg_diag_data_buffer_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30604,37 +36552,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_bsn_monitor_1GbE</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_monitor_1GbE</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_1GbE</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_monitor_1GbE</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_1GbE</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_monitor_1GbE</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_1GbE</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_input"
+ name="reg_diag_rx_seq_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30713,7 +36661,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30782,7 +36730,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31011,7 +36959,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31189,11 +37137,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -31293,7 +37241,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31362,7 +37310,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31591,7 +37539,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31745,37 +37693,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_bsn_monitor_input</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_diag_rx_seq_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -31854,7 +37802,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31923,7 +37871,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32152,7 +38100,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32330,11 +38278,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -32434,7 +38382,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32503,7 +38451,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32732,7 +38680,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32886,37 +38834,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_source"
+ name="reg_diag_rx_seq_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -32995,7 +38943,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33064,7 +39012,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -33293,7 +39241,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33471,11 +39419,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -33575,7 +39523,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33644,7 +39592,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -33873,7 +39821,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34027,37 +39975,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_bsn_source</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_bg_10gbe"
+ name="reg_diag_tx_seq_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34136,7 +40084,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34205,7 +40153,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34434,7 +40382,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34612,11 +40560,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -34716,7 +40664,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34785,7 +40733,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35014,7 +40962,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35168,37 +41116,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_bg_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_bg_1gbe"
+ name="reg_diag_tx_seq_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -35277,7 +41225,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35346,7 +41294,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35575,7 +41523,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35753,11 +41701,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -35857,7 +41805,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35926,7 +41874,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36155,7 +42103,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36309,37 +42257,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_bg_1gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_bg_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_bg_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_bg_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_10gbe"
+ name="reg_diag_tx_seq_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -36418,7 +42366,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36487,7 +42435,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36716,7 +42664,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36894,11 +42842,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -36998,7 +42946,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37067,7 +43015,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -37296,7 +43244,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37450,37 +43398,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_1gbe"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -37559,7 +43507,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37628,7 +43576,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -37857,7 +43805,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38035,11 +43983,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -38139,7 +44087,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38208,7 +44156,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -38437,7 +44385,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38591,37 +44539,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_1gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_bsn"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -38700,7 +44648,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38769,7 +44717,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16384</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -38998,7 +44946,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39176,11 +45124,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>14</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -39280,7 +45228,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39349,7 +45297,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16384</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39578,7 +45526,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39732,37 +45680,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_ddr_MB_I"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -39841,7 +45789,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39910,7 +45858,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -40139,7 +46087,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40317,11 +46265,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -40421,7 +46369,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40490,7 +46438,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -40719,7 +46667,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40873,37 +46821,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_ddr_MB_II"
+ name="reg_eth10g_back0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -40982,7 +46930,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41051,7 +46999,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -41280,7 +47228,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41458,11 +47406,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -41562,7 +47510,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41631,7 +47579,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -41860,7 +47808,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42014,37 +47962,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth10g_back0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_rx_seq_10gbe"
+ name="reg_eth10g_back1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -42123,7 +48071,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42192,7 +48140,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -42421,7 +48369,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42599,11 +48547,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -42703,7 +48651,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42772,7 +48720,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -43001,7 +48949,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43155,37 +49103,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth10g_back1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_rx_seq_1gbe"
+ name="reg_eth10g_qsfp_ring"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -43264,7 +49212,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43333,7 +49281,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -43562,7 +49510,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43740,11 +49688,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -43844,7 +49792,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43913,7 +49861,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -44142,7 +50090,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44296,37 +50244,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_1gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth10g_qsfp_ring</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_rx_seq_ddr_MB_I"
+ name="reg_eth1g_II_bg_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -45437,37 +51385,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_rx_seq_ddr_MB_II"
+ name="reg_eth1g_II_bsn_monitor_v2_rx"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -46578,37 +52526,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_tx_seq_10gbe"
+ name="reg_eth1g_II_bsn_monitor_v2_tx"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -46687,7 +52635,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -46756,7 +52704,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -46985,7 +52933,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47163,11 +53111,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -47267,7 +53215,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47336,7 +53284,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -47565,7 +53513,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47719,37 +53667,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_tx_seq_1gbe"
+ name="reg_eth1g_II_hdr_dat"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -47828,7 +53776,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47897,7 +53845,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -48126,7 +54074,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48304,11 +54252,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -48408,7 +54356,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48477,7 +54425,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -48706,7 +54654,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48860,37 +54808,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_1gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_tx_seq_ddr_MB_I"
+ name="reg_eth1g_II_strobe_total_count_rx"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -48969,7 +54917,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49038,7 +54986,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -49267,7 +55215,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49445,11 +55393,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -49549,7 +55497,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49618,7 +55566,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -49847,7 +55795,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -50001,37 +55949,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_tx_seq_ddr_MB_II"
+ name="reg_eth1g_II_strobe_total_count_tx"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -50110,7 +56058,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -50179,7 +56127,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -50408,7 +56356,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -50586,11 +56534,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -50690,7 +56638,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -50759,7 +56707,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -50988,7 +56936,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51142,37 +57090,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_eth1g_I_bg_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -51251,7 +57199,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51320,7 +57268,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -51549,7 +57497,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51727,11 +57675,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -51831,7 +57779,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51900,7 +57848,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -52129,7 +58077,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52283,37 +58231,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_eth1g_I_bsn_monitor_v2_rx"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -52392,7 +58340,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52461,7 +58409,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -52690,7 +58638,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52868,11 +58816,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -52972,7 +58920,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -53041,7 +58989,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -53270,7 +59218,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -53424,37 +59372,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_eth1g_I_bsn_monitor_v2_tx"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -53533,7 +59481,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -53602,7 +59550,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -53831,7 +59779,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54009,11 +59957,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -54113,7 +60061,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54182,7 +60130,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -54411,7 +60359,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54565,37 +60513,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth10g_back0"
+ name="reg_eth1g_I_hdr_dat"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -54674,7 +60622,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54743,7 +60691,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -54972,7 +60920,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55150,11 +61098,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -55254,7 +61202,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55323,7 +61271,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -55552,7 +61500,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55706,37 +61654,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth10g_back0</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth10g_back1"
+ name="reg_eth1g_I_strobe_total_count_rx"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -55815,7 +61763,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55884,7 +61832,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -56113,7 +62061,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -56291,11 +62239,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -56395,7 +62343,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -56464,7 +62412,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -56693,7 +62641,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -56847,37 +62795,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth10g_back1</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth10g_qsfp_ring"
+ name="reg_eth1g_I_strobe_total_count_tx"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -57988,30 +63936,30 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth10g_qsfp_ring</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -74400,7 +80348,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3738" />
+ <parameter name="baseAddress" value="0x0001cf48" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74420,7 +80368,7 @@
start="cpu_0.data_master"
end="cpu_0.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x005c0000" />
+ <parameter name="baseAddress" value="0x0001c000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74440,7 +80388,7 @@
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x36a0" />
+ <parameter name="baseAddress" value="0x0001cec0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74480,7 +80428,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3700" />
+ <parameter name="baseAddress" value="0x0001cf10" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74520,7 +80468,7 @@
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3680" />
+ <parameter name="baseAddress" value="0x0001cea0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74540,7 +80488,7 @@
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3660" />
+ <parameter name="baseAddress" value="0x0001ce80" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74580,7 +80528,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3730" />
+ <parameter name="baseAddress" value="0x0001cf40" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74600,7 +80548,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3728" />
+ <parameter name="baseAddress" value="0x0001cf38" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74620,7 +80568,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3720" />
+ <parameter name="baseAddress" value="0x0001cf30" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74640,7 +80588,7 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3718" />
+ <parameter name="baseAddress" value="0x0001cf28" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74660,7 +80608,7 @@
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3580" />
+ <parameter name="baseAddress" value="0x0001cd80" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74760,7 +80708,7 @@
start="cpu_0.data_master"
end="reg_eth10g_qsfp_ring.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0200" />
+ <parameter name="baseAddress" value="0x3600" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74780,7 +80728,7 @@
start="cpu_0.data_master"
end="reg_eth10g_back0.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3200" />
+ <parameter name="baseAddress" value="0x0001c800" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74818,9 +80766,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_bsn_monitor_1GbE.mem">
+ end="reg_bsn_monitor_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3480" />
+ <parameter name="baseAddress" value="0x00018000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74838,9 +80786,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_bsn_monitor_10GbE.mem">
+ end="reg_diag_data_buffer_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0001c000" />
+ <parameter name="baseAddress" value="0x0100" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74858,9 +80806,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_data_buffer_1gbe.mem">
+ end="ram_diag_data_buffer_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3400" />
+ <parameter name="baseAddress" value="0x00500000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74878,9 +80826,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_data_buffer_10gbe.mem">
+ end="reg_diag_bg_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0100" />
+ <parameter name="baseAddress" value="0x0001ce60" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74898,9 +80846,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="ram_diag_data_buffer_1gbe.mem">
+ end="ram_diag_bg_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0001a000" />
+ <parameter name="baseAddress" value="0x00080000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74918,9 +80866,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="ram_diag_data_buffer_10gbe.mem">
+ end="reg_diag_tx_seq_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00500000" />
+ <parameter name="baseAddress" value="0x0001cd40" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74938,9 +80886,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_bg_1gbe.mem">
+ end="reg_diag_rx_seq_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3640" />
+ <parameter name="baseAddress" value="0x0001cc80" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74958,9 +80906,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_bg_10gbe.mem">
+ end="reg_io_ddr_MB_I.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3620" />
+ <parameter name="baseAddress" value="0x00580000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74978,9 +80926,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="ram_diag_bg_1gbe.mem">
+ end="reg_io_ddr_MB_II.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00018000" />
+ <parameter name="baseAddress" value="0x00040000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -74998,9 +80946,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="ram_diag_bg_10gbe.mem">
+ end="reg_diag_tx_seq_ddr_MB_I.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00080000" />
+ <parameter name="baseAddress" value="0x0001cf00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75018,9 +80966,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_tx_seq_1gbe.mem">
+ end="reg_diag_tx_seq_ddr_MB_II.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x36f0" />
+ <parameter name="baseAddress" value="0x0001cef0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75038,9 +80986,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_rx_seq_1gbe.mem">
+ end="reg_diag_rx_seq_ddr_MB_I.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3600" />
+ <parameter name="baseAddress" value="0x0001ce40" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75058,9 +81006,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_tx_seq_10gbe.mem">
+ end="reg_diag_rx_seq_ddr_MB_II.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3540" />
+ <parameter name="baseAddress" value="0x0001ce20" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75078,9 +81026,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_rx_seq_10gbe.mem">
+ end="reg_diag_data_buffer_ddr_MB_I.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3380" />
+ <parameter name="baseAddress" value="0x0001cc00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75098,9 +81046,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_io_ddr_MB_I.mem">
+ end="reg_diag_data_buffer_ddr_MB_II.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00580000" />
+ <parameter name="baseAddress" value="0x0001cb80" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75118,9 +81066,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_io_ddr_MB_II.mem">
+ end="ram_diag_data_buffer_ddr_MB_I.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00040000" />
+ <parameter name="baseAddress" value="0xe000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75138,9 +81086,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_tx_seq_ddr_MB_I.mem">
+ end="ram_diag_data_buffer_ddr_MB_II.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x36e0" />
+ <parameter name="baseAddress" value="0xc000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75158,9 +81106,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_tx_seq_ddr_MB_II.mem">
+ end="reg_heater.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x36d0" />
+ <parameter name="baseAddress" value="0x0001cb00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75178,9 +81126,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_rx_seq_ddr_MB_I.mem">
+ end="jesd204b.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x35e0" />
+ <parameter name="baseAddress" value="0x8000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75198,9 +81146,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_rx_seq_ddr_MB_II.mem">
+ end="reg_bsn_monitor_input.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x35c0" />
+ <parameter name="baseAddress" value="0x0400" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75218,9 +81166,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_data_buffer_ddr_MB_I.mem">
+ end="reg_bsn_source.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3300" />
+ <parameter name="baseAddress" value="0x0001cee0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75238,9 +81186,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_data_buffer_ddr_MB_II.mem">
+ end="reg_bsn_scheduler.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3080" />
+ <parameter name="baseAddress" value="0x0001cf20" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75258,9 +81206,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="ram_diag_data_buffer_ddr_MB_I.mem">
+ end="pio_jesd_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xe000" />
+ <parameter name="baseAddress" value="0x3008" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75278,9 +81226,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="ram_diag_data_buffer_ddr_MB_II.mem">
+ end="ram_diag_data_buffer_bsn.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xc000" />
+ <parameter name="baseAddress" value="0x00800000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75298,9 +81246,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_heater.mem">
+ end="reg_diag_data_buffer_bsn.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0080" />
+ <parameter name="baseAddress" value="0x4000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75318,9 +81266,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="jesd204b.mem">
+ end="reg_eth1g_I_bg_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0x0001ca80" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75338,9 +81286,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_bsn_monitor_input.mem">
+ end="reg_eth1g_II_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0400" />
+ <parameter name="baseAddress" value="0x0001ca00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75358,9 +81306,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_bsn_source.mem">
+ end="reg_eth1g_II_bsn_monitor_v2_tx.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x36c0" />
+ <parameter name="baseAddress" value="0x0001ce00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75378,9 +81326,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_bsn_scheduler.mem">
+ end="reg_eth1g_II_strobe_total_count_tx.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3710" />
+ <parameter name="baseAddress" value="0x0001c980" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75398,9 +81346,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="pio_jesd_ctrl.mem">
+ end="reg_eth1g_II_bsn_monitor_v2_rx.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3008" />
+ <parameter name="baseAddress" value="0x0001cde0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75418,9 +81366,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="ram_diag_data_buffer_bsn.mem">
+ end="reg_eth1g_II_strobe_total_count_rx.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00800000" />
+ <parameter name="baseAddress" value="0x0001c900" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75438,9 +81386,109 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_diag_data_buffer_bsn.mem">
+ end="reg_eth1g_I_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x4000" />
+ <parameter name="baseAddress" value="0x3400" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_eth1g_I_bsn_monitor_v2_tx.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3080" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_eth1g_I_strobe_total_count_tx.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3200" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_eth1g_I_bsn_monitor_v2_rx.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0080" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_eth1g_I_strobe_total_count_rx.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0200" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_eth1g_II_bg_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0001cdc0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75460,7 +81508,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_ram">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0001f000" />
+ <parameter name="baseAddress" value="0x0001b000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75480,7 +81528,7 @@
start="cpu_0.data_master"
end="avs2_eth_coe_1.mms_ram">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0001e000" />
+ <parameter name="baseAddress" value="0x0001a000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75500,7 +81548,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3500" />
+ <parameter name="baseAddress" value="0x0001cd00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75640,7 +81688,7 @@
start="cpu_0.instruction_master"
end="cpu_0.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x005c0000" />
+ <parameter name="baseAddress" value="0x0001c000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -75764,154 +81812,179 @@
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_bsn_monitor_1GbE.system" />
+ end="reg_bsn_monitor_10GbE.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_bsn_monitor_10GbE.system" />
+ end="reg_diag_data_buffer_10gbe.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_data_buffer_1gbe.system" />
+ end="ram_diag_data_buffer_10gbe.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_data_buffer_10gbe.system" />
+ end="reg_diag_bg_10gbe.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="ram_diag_data_buffer_1gbe.system" />
+ end="ram_diag_bg_10gbe.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="ram_diag_data_buffer_10gbe.system" />
+ end="reg_diag_tx_seq_10gbe.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_bg_1gbe.system" />
+ end="reg_diag_rx_seq_10gbe.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_bg_10gbe.system" />
+ end="reg_io_ddr_MB_I.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="ram_diag_bg_1gbe.system" />
+ end="reg_io_ddr_MB_II.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="ram_diag_bg_10gbe.system" />
+ end="reg_diag_tx_seq_ddr_MB_I.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_tx_seq_1gbe.system" />
+ end="reg_diag_tx_seq_ddr_MB_II.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_rx_seq_1gbe.system" />
+ end="reg_diag_rx_seq_ddr_MB_I.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_tx_seq_10gbe.system" />
+ end="reg_diag_rx_seq_ddr_MB_II.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_rx_seq_10gbe.system" />
+ end="reg_diag_data_buffer_ddr_MB_I.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_io_ddr_MB_I.system" />
+ end="reg_diag_data_buffer_ddr_MB_II.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_io_ddr_MB_II.system" />
+ end="ram_diag_data_buffer_ddr_MB_I.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_tx_seq_ddr_MB_I.system" />
+ end="ram_diag_data_buffer_ddr_MB_II.system" />
+ <connection kind="clock" version="19.4" start="clk_0.clk" end="reg_heater.system" />
+ <connection kind="clock" version="19.4" start="clk_0.clk" end="jesd204b.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_tx_seq_ddr_MB_II.system" />
+ end="reg_bsn_monitor_input.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_rx_seq_ddr_MB_I.system" />
+ end="reg_bsn_source.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_rx_seq_ddr_MB_II.system" />
+ end="reg_bsn_scheduler.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_data_buffer_ddr_MB_I.system" />
+ end="pio_jesd_ctrl.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_data_buffer_ddr_MB_II.system" />
+ end="ram_diag_data_buffer_bsn.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="ram_diag_data_buffer_ddr_MB_I.system" />
+ end="reg_diag_data_buffer_bsn.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="ram_diag_data_buffer_ddr_MB_II.system" />
- <connection kind="clock" version="19.4" start="clk_0.clk" end="reg_heater.system" />
- <connection kind="clock" version="19.4" start="clk_0.clk" end="jesd204b.system" />
+ end="reg_eth1g_I_bg_ctrl.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_bsn_monitor_input.system" />
+ end="reg_eth1g_II_hdr_dat.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_bsn_source.system" />
+ end="reg_eth1g_II_bsn_monitor_v2_tx.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_bsn_scheduler.system" />
+ end="reg_eth1g_II_strobe_total_count_tx.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="pio_jesd_ctrl.system" />
+ end="reg_eth1g_II_bsn_monitor_v2_rx.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="ram_diag_data_buffer_bsn.system" />
+ end="reg_eth1g_II_strobe_total_count_rx.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_diag_data_buffer_bsn.system" />
+ end="reg_eth1g_I_hdr_dat.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_eth1g_I_bsn_monitor_v2_tx.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_eth1g_I_strobe_total_count_tx.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_eth1g_I_bsn_monitor_v2_rx.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_eth1g_I_strobe_total_count_rx.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_eth1g_II_bg_ctrl.system" />
<connection
kind="interrupt"
version="19.4"
@@ -76066,162 +82139,187 @@
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_bsn_monitor_1GbE.system_reset" />
+ end="reg_bsn_monitor_10GbE.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_bsn_monitor_10GbE.system_reset" />
+ end="reg_diag_data_buffer_10gbe.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_data_buffer_1gbe.system_reset" />
+ end="ram_diag_data_buffer_10gbe.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_data_buffer_10gbe.system_reset" />
+ end="reg_diag_bg_10gbe.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="ram_diag_data_buffer_1gbe.system_reset" />
+ end="ram_diag_bg_10gbe.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="ram_diag_data_buffer_10gbe.system_reset" />
+ end="reg_diag_tx_seq_10gbe.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_bg_1gbe.system_reset" />
+ end="reg_diag_rx_seq_10gbe.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_bg_10gbe.system_reset" />
+ end="reg_io_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="ram_diag_bg_1gbe.system_reset" />
+ end="reg_io_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="ram_diag_bg_10gbe.system_reset" />
+ end="reg_diag_tx_seq_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_tx_seq_1gbe.system_reset" />
+ end="reg_diag_tx_seq_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_rx_seq_1gbe.system_reset" />
+ end="reg_diag_rx_seq_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_tx_seq_10gbe.system_reset" />
+ end="reg_diag_rx_seq_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_rx_seq_10gbe.system_reset" />
+ end="reg_diag_data_buffer_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_io_ddr_MB_I.system_reset" />
+ end="reg_diag_data_buffer_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_io_ddr_MB_II.system_reset" />
+ end="ram_diag_data_buffer_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_tx_seq_ddr_MB_I.system_reset" />
+ end="ram_diag_data_buffer_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_tx_seq_ddr_MB_II.system_reset" />
+ end="reg_heater.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_rx_seq_ddr_MB_I.system_reset" />
+ end="jesd204b.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_rx_seq_ddr_MB_II.system_reset" />
+ end="reg_bsn_monitor_input.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_data_buffer_ddr_MB_I.system_reset" />
+ end="reg_bsn_source.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_data_buffer_ddr_MB_II.system_reset" />
+ end="reg_bsn_scheduler.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="ram_diag_data_buffer_ddr_MB_I.system_reset" />
+ end="pio_jesd_ctrl.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="ram_diag_data_buffer_ddr_MB_II.system_reset" />
+ end="ram_diag_data_buffer_bsn.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_heater.system_reset" />
+ end="reg_diag_data_buffer_bsn.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="jesd204b.system_reset" />
+ end="reg_eth1g_I_bg_ctrl.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_bsn_monitor_input.system_reset" />
+ end="reg_eth1g_II_hdr_dat.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_bsn_source.system_reset" />
+ end="reg_eth1g_II_bsn_monitor_v2_tx.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_bsn_scheduler.system_reset" />
+ end="reg_eth1g_II_strobe_total_count_tx.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="pio_jesd_ctrl.system_reset" />
+ end="reg_eth1g_II_bsn_monitor_v2_rx.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="ram_diag_data_buffer_bsn.system_reset" />
+ end="reg_eth1g_II_strobe_total_count_rx.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_diag_data_buffer_bsn.system_reset" />
+ end="reg_eth1g_I_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_eth1g_I_bsn_monitor_v2_tx.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_eth1g_I_strobe_total_count_tx.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_eth1g_I_bsn_monitor_v2_rx.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_eth1g_I_strobe_total_count_rx.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_eth1g_II_bg_ctrl.system_reset" />
<connection
kind="reset"
version="19.4"
@@ -76356,160 +82454,185 @@
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_bsn_monitor_1GbE.system_reset" />
+ end="reg_bsn_monitor_10GbE.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_bsn_monitor_10GbE.system_reset" />
+ end="reg_diag_data_buffer_10gbe.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_data_buffer_1gbe.system_reset" />
+ end="ram_diag_data_buffer_10gbe.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_data_buffer_10gbe.system_reset" />
+ end="reg_diag_bg_10gbe.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="ram_diag_data_buffer_1gbe.system_reset" />
+ end="ram_diag_bg_10gbe.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="ram_diag_data_buffer_10gbe.system_reset" />
+ end="reg_diag_tx_seq_10gbe.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_bg_1gbe.system_reset" />
+ end="reg_diag_rx_seq_10gbe.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_bg_10gbe.system_reset" />
+ end="reg_io_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="ram_diag_bg_1gbe.system_reset" />
+ end="reg_io_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="ram_diag_bg_10gbe.system_reset" />
+ end="reg_diag_tx_seq_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_tx_seq_1gbe.system_reset" />
+ end="reg_diag_tx_seq_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_rx_seq_1gbe.system_reset" />
+ end="reg_diag_rx_seq_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_tx_seq_10gbe.system_reset" />
+ end="reg_diag_rx_seq_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_rx_seq_10gbe.system_reset" />
+ end="reg_diag_data_buffer_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_io_ddr_MB_I.system_reset" />
+ end="reg_diag_data_buffer_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_io_ddr_MB_II.system_reset" />
+ end="ram_diag_data_buffer_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_tx_seq_ddr_MB_I.system_reset" />
+ end="ram_diag_data_buffer_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_tx_seq_ddr_MB_II.system_reset" />
+ end="reg_heater.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_rx_seq_ddr_MB_I.system_reset" />
+ end="jesd204b.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_rx_seq_ddr_MB_II.system_reset" />
+ end="reg_bsn_monitor_input.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_data_buffer_ddr_MB_I.system_reset" />
+ end="reg_bsn_source.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_data_buffer_ddr_MB_II.system_reset" />
+ end="reg_bsn_scheduler.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="ram_diag_data_buffer_ddr_MB_I.system_reset" />
+ end="pio_jesd_ctrl.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="ram_diag_data_buffer_ddr_MB_II.system_reset" />
+ end="ram_diag_data_buffer_bsn.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_heater.system_reset" />
+ end="reg_diag_data_buffer_bsn.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="jesd204b.system_reset" />
+ end="reg_eth1g_I_bg_ctrl.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_bsn_monitor_input.system_reset" />
+ end="reg_eth1g_II_hdr_dat.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_bsn_source.system_reset" />
+ end="reg_eth1g_II_bsn_monitor_v2_tx.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_bsn_scheduler.system_reset" />
+ end="reg_eth1g_II_strobe_total_count_tx.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="pio_jesd_ctrl.system_reset" />
+ end="reg_eth1g_II_bsn_monitor_v2_rx.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="ram_diag_data_buffer_bsn.system_reset" />
+ end="reg_eth1g_II_strobe_total_count_rx.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_diag_data_buffer_bsn.system_reset" />
+ end="reg_eth1g_I_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="cpu_0.debug_reset_request"
+ end="reg_eth1g_I_bsn_monitor_v2_tx.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="cpu_0.debug_reset_request"
+ end="reg_eth1g_I_strobe_total_count_tx.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="cpu_0.debug_reset_request"
+ end="reg_eth1g_I_bsn_monitor_v2_rx.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="cpu_0.debug_reset_request"
+ end="reg_eth1g_I_strobe_total_count_rx.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="cpu_0.debug_reset_request"
+ end="reg_eth1g_II_bg_ctrl.system_reset" />
</system>
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
index c5794a059dcfc1f2951918fd83ca88f56d630e6b..51e59be80c8c12360df285c66c21e97d1814cead 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
@@ -76,31 +76,24 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
@@ -123,7 +116,17 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-
-
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..75e63c809b3dc59ff7d8244e6b00077e122c918b
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg
@@ -0,0 +1,111 @@
+hdl_lib_name = unb2c_test_1GbE_I
+hdl_library_clause_name = unb2c_test_1GbE_I_lib
+hdl_lib_uses_synth = common mm technology unb2c_board unb2c_test
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+hdl_lib_include_ip =
+
+synth_files =
+ unb2c_test_1GbE_I.vhd
+
+test_bench_files =
+ tb_unb2c_test_1GbE_I.vhd
+
+regression_test_vhdl =
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus .
+ ../../quartus .
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+
+quartus_sdc_pre_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+
+quartus_sdc_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+
+quartus_tcl_files =
+ quartus/unb2c_test_1GbE_I_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/qsys_unb2c_test/qsys_unb2c_test.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/quartus/unb2c_test_1GbE_I_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/quartus/unb2c_test_1GbE_I_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ae417258f888c910d593c6ab6e5117615ebbd36f
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/quartus/unb2c_test_1GbE_I_pins.tcl
@@ -0,0 +1,22 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..098b2f766dd700f483cc27ecb5f6c62d4fcbb321
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
@@ -0,0 +1,83 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author: E. Kooistra
+-- Purpose: Tb to try loading design in simulator
+-- Description:
+-- Usage:
+-- > run 1 us.
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_unb2c_test_1GbE_I IS
+END tb_unb2c_test_1GbE_I;
+
+
+ARCHITECTURE tb OF tb_unb2c_test_1GbE_I IS
+
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL wdi : STD_LOGIC := '0';
+
+ SIGNAL eth_clk : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ SIGNAL eth_sgin : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL eth_sgout : STD_LOGIC_VECTOR(1 DOWNTO 0);
+
+BEGIN
+
+ clk <= NOT clk AFTER 5 ns;
+ eth_clk(0) <= NOT eth_clk(0) AFTER 8 ns;
+ eth_clk(1) <= NOT eth_clk(1) AFTER 8 ns;
+
+ eth_sgin <= eth_sgout; -- loopback eth0 and eth1
+
+ u_unb2c_test_1GbE_I : ENTITY work.unb2c_test_1GbE_I
+ GENERIC MAP (
+ g_sim => TRUE
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => wdi,
+ INTA => OPEN,
+ INTB => OPEN,
+
+ -- Others
+ VERSION => "00",
+ ID => "00000000",
+ TESTIO => OPEN,
+
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_sgin,
+ ETH_SGOUT => eth_sgout,
+
+ QSFP_LED => OPEN
+ );
+
+END tb;
+
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5df27443699abb821c26211f077555e86edcc8fd
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
@@ -0,0 +1,101 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+
+ENTITY unb2c_test_1GbE_I IS
+ GENERIC (
+ g_design_name : STRING := "unb2c_test_1GbE_I";
+ g_design_note : STRING := "Uses only Eth0";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
+
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2c_test_1GbE_I;
+
+
+ARCHITECTURE str OF unb2c_test_1GbE_I IS
+
+BEGIN
+ u_revision : ENTITY unb2c_test_lib.unb2c_test
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ QSFP_LED => QSFP_LED
+ );
+END str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
index 600f12315eb59b30b7264d88dc44778d7be641fb..10ffc4483c97397219a94129b88720b74fc04850 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
@@ -62,31 +62,24 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
@@ -109,7 +102,17 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-
-
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
index d910141160e89ebe414fbd072581e814e1036c20..37ef2d46ea0f70174e026d3a599edd876b4d4768 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
@@ -60,31 +60,24 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
@@ -107,7 +100,17 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-
-
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
index 7a7fa641a158e5bef222f66560f2121bf03bd708..1153dfd5a421d1dce0114c2cca595bd94ed4c2d5 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
@@ -59,31 +59,24 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
@@ -106,6 +99,18 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
index fed5aca8f2e9a297f9c44a818028607ecc7444a0..b2e2e2545cca716c0f6c7554fc9e3faad2a32763 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
@@ -54,31 +54,24 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
@@ -101,7 +94,17 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-
-
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index ef424554b4e06bf1dbca6ab826c64c890c9018b2..cb6ec2cfe0e446e3715c51d3fca55246da38d3f8 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -41,7 +41,6 @@ USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
USE work.unb2c_test_pkg.ALL;
-
ENTITY mmm_unb2c_test IS
GENERIC (
g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
@@ -50,7 +49,6 @@ ENTITY mmm_unb2c_test IS
g_technology : NATURAL := c_tech_arria10_e1sg;
g_bg_block_size : NATURAL;
g_hdr_field_arr : t_common_field_arr;
- g_nof_streams_1GbE : NATURAL;
g_nof_streams_qsfp : NATURAL;
g_nof_streams_ring : NATURAL;
g_nof_streams_back0 : NATURAL
@@ -90,6 +88,20 @@ ENTITY mmm_unb2c_test IS
eth1g_eth0_ram_mosi : OUT t_mem_mosi;
eth1g_eth0_ram_miso : IN t_mem_miso;
+ reg_eth1g_I_bg_ctrl_copi : OUT t_mem_copi;
+ reg_eth1g_I_bg_ctrl_cipo : IN t_mem_cipo;
+ reg_eth1g_I_hdr_dat_copi : OUT t_mem_copi;
+ reg_eth1g_I_hdr_dat_cipo : IN t_mem_cipo;
+ reg_eth1g_I_bsn_monitor_v2_tx_copi : OUT t_mem_copi;
+ reg_eth1g_I_bsn_monitor_v2_tx_cipo : IN t_mem_cipo;
+ reg_eth1g_I_strobe_total_count_tx_copi : OUT t_mem_copi;
+ reg_eth1g_I_strobe_total_count_tx_cipo : IN t_mem_cipo;
+
+ reg_eth1g_I_bsn_monitor_v2_rx_copi : OUT t_mem_copi;
+ reg_eth1g_I_bsn_monitor_v2_rx_cipo : IN t_mem_cipo;
+ reg_eth1g_I_strobe_total_count_rx_copi : OUT t_mem_copi;
+ reg_eth1g_I_strobe_total_count_rx_cipo : IN t_mem_cipo;
+
-- eth1g ch1
eth1g_eth1_mm_rst : OUT STD_LOGIC;
eth1g_eth1_tse_mosi : OUT t_mem_mosi;
@@ -100,6 +112,20 @@ ENTITY mmm_unb2c_test IS
eth1g_eth1_ram_mosi : OUT t_mem_mosi;
eth1g_eth1_ram_miso : IN t_mem_miso;
+ reg_eth1g_II_bg_ctrl_copi : OUT t_mem_copi;
+ reg_eth1g_II_bg_ctrl_cipo : IN t_mem_cipo;
+ reg_eth1g_II_hdr_dat_copi : OUT t_mem_copi;
+ reg_eth1g_II_hdr_dat_cipo : IN t_mem_cipo;
+ reg_eth1g_II_bsn_monitor_v2_tx_copi : OUT t_mem_copi;
+ reg_eth1g_II_bsn_monitor_v2_tx_cipo : IN t_mem_cipo;
+ reg_eth1g_II_strobe_total_count_tx_copi : OUT t_mem_copi;
+ reg_eth1g_II_strobe_total_count_tx_cipo : IN t_mem_cipo;
+
+ reg_eth1g_II_bsn_monitor_v2_rx_copi : OUT t_mem_copi;
+ reg_eth1g_II_bsn_monitor_v2_rx_cipo : IN t_mem_cipo;
+ reg_eth1g_II_strobe_total_count_rx_copi : OUT t_mem_copi;
+ reg_eth1g_II_strobe_total_count_rx_cipo : IN t_mem_cipo;
+
-- EPCS read
reg_dpmm_data_mosi : OUT t_mem_mosi;
reg_dpmm_data_miso : IN t_mem_miso;
@@ -125,13 +151,6 @@ ENTITY mmm_unb2c_test IS
reg_heater_miso : IN t_mem_miso;
-- block gen
- ram_diag_bg_1GbE_mosi : OUT t_mem_mosi;
- ram_diag_bg_1GbE_miso : IN t_mem_miso;
- reg_diag_bg_1GbE_mosi : OUT t_mem_mosi;
- reg_diag_bg_1GbE_miso : IN t_mem_miso;
- reg_diag_tx_seq_1GbE_mosi : OUT t_mem_mosi;
- reg_diag_tx_seq_1GbE_miso : IN t_mem_miso;
-
ram_diag_bg_10GbE_mosi : OUT t_mem_mosi;
ram_diag_bg_10GbE_miso : IN t_mem_miso;
reg_diag_bg_10GbE_mosi : OUT t_mem_mosi;
@@ -140,19 +159,10 @@ ENTITY mmm_unb2c_test IS
reg_diag_tx_seq_10GbE_miso : IN t_mem_miso;
-- bsn
- reg_bsn_monitor_1GbE_mosi : OUT t_mem_mosi;
- reg_bsn_monitor_1GbE_miso : IN t_mem_miso;
reg_bsn_monitor_10GbE_mosi : OUT t_mem_mosi;
reg_bsn_monitor_10GbE_miso : IN t_mem_miso;
-- databuffer
- ram_diag_data_buf_1GbE_mosi : OUT t_mem_mosi;
- ram_diag_data_buf_1GbE_miso : IN t_mem_miso;
- reg_diag_data_buf_1GbE_mosi : OUT t_mem_mosi;
- reg_diag_data_buf_1GbE_miso : IN t_mem_miso;
- reg_diag_rx_seq_1GbE_mosi : OUT t_mem_mosi;
- reg_diag_rx_seq_1GbE_miso : IN t_mem_miso;
-
ram_diag_data_buf_10GbE_mosi : OUT t_mem_mosi;
ram_diag_data_buf_10GbE_miso : IN t_mem_miso;
reg_diag_data_buf_10GbE_mosi : OUT t_mem_mosi;
@@ -233,10 +243,8 @@ ARCHITECTURE str OF mmm_unb2c_test IS
-- Block generator
-- check with python: from common import *
-- ceil_log2(48 * 2**ceil_log2(900))
- CONSTANT c_ram_diag_bg_1GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(ceil_log2(g_bg_block_size)));
CONSTANT c_ram_diag_bg_10GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(ceil_log2(g_bg_block_size)));
CONSTANT c_ram_diag_databuffer_10GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(ceil_log2(g_bg_block_size)));
- CONSTANT c_ram_diag_databuffer_1GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(ceil_log2(g_bg_block_size)));
CONSTANT c_ram_diag_databuffer_ddr_addr_w : NATURAL := ceil_log2(2 * pow2(ceil_log2(g_bg_block_size)));
-- tr_10GbE
@@ -250,7 +258,6 @@ ARCHITECTURE str OF mmm_unb2c_test IS
CONSTANT c_reg_eth10g_back0_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_back0 * pow2(c_reg_eth10g_adr_w));
-- BSN monitors
- CONSTANT c_reg_rsp_bsn_monitor_1GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_unb2c_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
CONSTANT c_reg_rsp_bsn_monitor_10GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_unb2c_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
-- Simulation
@@ -297,13 +304,6 @@ BEGIN
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_reg_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
- u_mm_file_ram_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- PORT MAP(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
- u_mm_file_reg_diag_tx_seq_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
-
u_mm_file_reg_diag_bg_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
PORT MAP(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
u_mm_file_ram_diag_bg_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
@@ -311,18 +311,9 @@ BEGIN
u_mm_file_reg_diag_tx_seq_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
- u_mm_file_reg_bsn_monitor_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
u_mm_file_reg_bsn_monitor_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
- u_mm_file_reg_diag_data_buffer_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
- u_mm_file_ram_diag_data_buffer_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
- u_mm_file_reg_diag_rx_seq_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
-
u_mm_file_reg_diag_data_buffer_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
u_mm_file_ram_diag_data_buffer_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
@@ -373,6 +364,31 @@ BEGIN
u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
PORT MAP(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ u_mm_file_reg_eth1g_I_bg_ctrl : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_BG_CTRL")
+ PORT MAP(mm_rst, mm_clk, reg_eth1g_I_bg_ctrl_copi, reg_eth1g_I_bg_ctrl_cipo );
+ u_mm_file_reg_eth1g_I_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_HDR_DAT")
+ PORT MAP(mm_rst, mm_clk, reg_eth1g_I_hdr_dat_copi, reg_eth1g_I_hdr_dat_cipo );
+ u_mm_file_reg_eth1g_I_bsn_monitor_v2_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_BSN_MONITOR_V2_TX")
+ PORT MAP(mm_rst, mm_clk, reg_eth1g_I_bsn_monitor_v2_tx_copi, reg_eth1g_I_bsn_monitor_v2_tx_cipo );
+ u_mm_file_reg_eth1g_I_strobe_total_count_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_STROBE_TOTAL_COUNT_TX")
+ PORT MAP(mm_rst, mm_clk, reg_eth1g_I_strobe_total_count_tx_copi, reg_eth1g_I_strobe_total_count_tx_cipo );
+ u_mm_file_reg_eth1g_I_bsn_monitor_v2_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_BSN_MONITOR_V2_RX")
+ PORT MAP(mm_rst, mm_clk, reg_eth1g_I_bsn_monitor_v2_rx_copi, reg_eth1g_I_bsn_monitor_v2_rx_cipo );
+ u_mm_file_reg_eth1g_I_strobe_total_count_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_STROBE_TOTAL_COUNT_RX")
+ PORT MAP(mm_rst, mm_clk, reg_eth1g_I_strobe_total_count_rx_copi, reg_eth1g_I_strobe_total_count_rx_cipo );
+
+ u_mm_file_reg_eth1g_II_bg_ctrl : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_BG_CTRL")
+ PORT MAP(mm_rst, mm_clk, reg_eth1g_II_bg_ctrl_copi, reg_eth1g_II_bg_ctrl_cipo );
+ u_mm_file_reg_eth1g_II_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_HDR_DAT")
+ PORT MAP(mm_rst, mm_clk, reg_eth1g_II_hdr_dat_copi, reg_eth1g_II_hdr_dat_cipo );
+ u_mm_file_reg_eth1g_II_bsn_monitor_v2_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_BSN_MONITOR_V2_TX")
+ PORT MAP(mm_rst, mm_clk, reg_eth1g_II_bsn_monitor_v2_tx_copi, reg_eth1g_II_bsn_monitor_v2_tx_cipo );
+ u_mm_file_reg_eth1g_II_strobe_total_count_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_STROBE_TOTAL_COUNT_TX")
+ PORT MAP(mm_rst, mm_clk, reg_eth1g_II_strobe_total_count_tx_copi, reg_eth1g_II_strobe_total_count_tx_cipo );
+ u_mm_file_reg_eth1g_II_bsn_monitor_v2_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_BSN_MONITOR_V2_RX")
+ PORT MAP(mm_rst, mm_clk, reg_eth1g_II_bsn_monitor_v2_rx_copi, reg_eth1g_II_bsn_monitor_v2_rx_cipo );
+ u_mm_file_reg_eth1g_II_strobe_total_count_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_STROBE_TOTAL_COUNT_RX")
+ PORT MAP(mm_rst, mm_clk, reg_eth1g_II_strobe_total_count_rx_copi, reg_eth1g_II_strobe_total_count_rx_cipo );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -597,14 +613,6 @@ BEGIN
reg_eth10g_back0_read_export => reg_eth10g_back0_mosi.rd,
reg_eth10g_back0_readdata_export => reg_eth10g_back0_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_monitor_1gbe_reset_export => OPEN,
- reg_bsn_monitor_1gbe_clk_export => OPEN,
- reg_bsn_monitor_1gbe_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w-1 DOWNTO 0),
- reg_bsn_monitor_1gbe_write_export => reg_bsn_monitor_1GbE_mosi.wr,
- reg_bsn_monitor_1gbe_writedata_export => reg_bsn_monitor_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_monitor_1gbe_read_export => reg_bsn_monitor_1GbE_mosi.rd,
- reg_bsn_monitor_1gbe_readdata_export => reg_bsn_monitor_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
-
reg_bsn_monitor_10gbe_reset_export => OPEN,
reg_bsn_monitor_10gbe_clk_export => OPEN,
reg_bsn_monitor_10gbe_address_export => reg_bsn_monitor_10GbE_mosi.address(c_reg_rsp_bsn_monitor_10GbE_adr_w-1 DOWNTO 0),
@@ -613,14 +621,6 @@ BEGIN
reg_bsn_monitor_10gbe_read_export => reg_bsn_monitor_10GbE_mosi.rd,
reg_bsn_monitor_10gbe_readdata_export => reg_bsn_monitor_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_diag_data_buffer_1gbe_reset_export => OPEN,
- reg_diag_data_buffer_1gbe_clk_export => OPEN,
- reg_diag_data_buffer_1gbe_address_export => reg_diag_data_buf_1gbe_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
- reg_diag_data_buffer_1gbe_write_export => reg_diag_data_buf_1gbe_mosi.wr,
- reg_diag_data_buffer_1gbe_writedata_export => reg_diag_data_buf_1gbe_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_diag_data_buffer_1gbe_read_export => reg_diag_data_buf_1gbe_mosi.rd,
- reg_diag_data_buffer_1gbe_readdata_export => reg_diag_data_buf_1gbe_miso.rddata(c_word_w-1 DOWNTO 0),
-
reg_diag_data_buffer_10gbe_reset_export => OPEN,
reg_diag_data_buffer_10gbe_clk_export => OPEN,
reg_diag_data_buffer_10gbe_address_export => reg_diag_data_buf_10gbe_mosi.address(5 DOWNTO 0),
@@ -629,14 +629,6 @@ BEGIN
reg_diag_data_buffer_10gbe_read_export => reg_diag_data_buf_10gbe_mosi.rd,
reg_diag_data_buffer_10gbe_readdata_export => reg_diag_data_buf_10gbe_miso.rddata(c_word_w-1 DOWNTO 0),
- ram_diag_data_buffer_1gbe_clk_export => OPEN,
- ram_diag_data_buffer_1gbe_reset_export => OPEN,
- ram_diag_data_buffer_1gbe_address_export => ram_diag_data_buf_1gbe_mosi.address(c_ram_diag_databuffer_1GbE_addr_w-1 DOWNTO 0),
- ram_diag_data_buffer_1gbe_write_export => ram_diag_data_buf_1gbe_mosi.wr,
- ram_diag_data_buffer_1gbe_writedata_export => ram_diag_data_buf_1gbe_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_diag_data_buffer_1gbe_read_export => ram_diag_data_buf_1gbe_mosi.rd,
- ram_diag_data_buffer_1gbe_readdata_export => ram_diag_data_buf_1gbe_miso.rddata(c_word_w-1 DOWNTO 0),
-
ram_diag_data_buffer_10gbe_clk_export => OPEN,
ram_diag_data_buffer_10gbe_reset_export => OPEN,
ram_diag_data_buffer_10gbe_address_export => ram_diag_data_buf_10gbe_mosi.address(c_ram_diag_databuffer_10GbE_addr_w-1 DOWNTO 0),
@@ -645,14 +637,6 @@ BEGIN
ram_diag_data_buffer_10gbe_read_export => ram_diag_data_buf_10gbe_mosi.rd,
ram_diag_data_buffer_10gbe_readdata_export => ram_diag_data_buf_10gbe_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_diag_bg_1GbE_reset_export => OPEN,
- reg_diag_bg_1GbE_clk_export => OPEN,
- reg_diag_bg_1GbE_address_export => reg_diag_bg_1GbE_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
- reg_diag_bg_1GbE_write_export => reg_diag_bg_1GbE_mosi.wr,
- reg_diag_bg_1GbE_writedata_export => reg_diag_bg_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_diag_bg_1GbE_read_export => reg_diag_bg_1GbE_mosi.rd,
- reg_diag_bg_1GbE_readdata_export => reg_diag_bg_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
-
reg_diag_bg_10GbE_reset_export => OPEN,
reg_diag_bg_10GbE_clk_export => OPEN,
reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
@@ -661,14 +645,6 @@ BEGIN
reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
- ram_diag_bg_1GbE_reset_export => OPEN,
- ram_diag_bg_1GbE_clk_export => OPEN,
- ram_diag_bg_1GbE_address_export => ram_diag_bg_1GbE_mosi.address(c_ram_diag_bg_1GbE_addr_w-1 DOWNTO 0),
- ram_diag_bg_1GbE_write_export => ram_diag_bg_1GbE_mosi.wr,
- ram_diag_bg_1GbE_writedata_export => ram_diag_bg_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_diag_bg_1GbE_read_export => ram_diag_bg_1GbE_mosi.rd,
- ram_diag_bg_1GbE_readdata_export => ram_diag_bg_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
-
ram_diag_bg_10GbE_reset_export => OPEN,
ram_diag_bg_10GbE_clk_export => OPEN,
ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w-1 DOWNTO 0),
@@ -693,21 +669,21 @@ BEGIN
reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
@@ -757,6 +733,102 @@ BEGIN
ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_eth1g_I_bg_ctrl_reset_export => OPEN,
+ reg_eth1g_I_bg_ctrl_clk_export => OPEN,
+ reg_eth1g_I_bg_ctrl_address_export => reg_eth1g_I_bg_ctrl_copi.address(4 downto 0),
+ reg_eth1g_I_bg_ctrl_write_export => reg_eth1g_I_bg_ctrl_copi.wr,
+ reg_eth1g_I_bg_ctrl_writedata_export => reg_eth1g_I_bg_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth1g_I_bg_ctrl_read_export => reg_eth1g_I_bg_ctrl_copi.rd,
+ reg_eth1g_I_bg_ctrl_readdata_export => reg_eth1g_I_bg_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_eth1g_I_hdr_dat_reset_export => OPEN,
+ reg_eth1g_I_hdr_dat_clk_export => OPEN,
+ reg_eth1g_I_hdr_dat_address_export => reg_eth1g_I_hdr_dat_copi.address(6 downto 0),
+ reg_eth1g_I_hdr_dat_write_export => reg_eth1g_I_hdr_dat_copi.wr,
+ reg_eth1g_I_hdr_dat_writedata_export => reg_eth1g_I_hdr_dat_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth1g_I_hdr_dat_read_export => reg_eth1g_I_hdr_dat_copi.rd,
+ reg_eth1g_I_hdr_dat_readdata_export => reg_eth1g_I_hdr_dat_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_eth1g_I_bsn_monitor_v2_tx_reset_export => OPEN,
+ reg_eth1g_I_bsn_monitor_v2_tx_clk_export => OPEN,
+ reg_eth1g_I_bsn_monitor_v2_tx_address_export => reg_eth1g_I_bsn_monitor_v2_tx_copi.address(4 downto 0),
+ reg_eth1g_I_bsn_monitor_v2_tx_write_export => reg_eth1g_I_bsn_monitor_v2_tx_copi.wr,
+ reg_eth1g_I_bsn_monitor_v2_tx_writedata_export => reg_eth1g_I_bsn_monitor_v2_tx_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth1g_I_bsn_monitor_v2_tx_read_export => reg_eth1g_I_bsn_monitor_v2_tx_copi.rd,
+ reg_eth1g_I_bsn_monitor_v2_tx_readdata_export => reg_eth1g_I_bsn_monitor_v2_tx_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_eth1g_I_strobe_total_count_tx_reset_export => OPEN,
+ reg_eth1g_I_strobe_total_count_tx_clk_export => OPEN,
+ reg_eth1g_I_strobe_total_count_tx_address_export => reg_eth1g_I_strobe_total_count_tx_copi.address(6 downto 0),
+ reg_eth1g_I_strobe_total_count_tx_write_export => reg_eth1g_I_strobe_total_count_tx_copi.wr,
+ reg_eth1g_I_strobe_total_count_tx_writedata_export => reg_eth1g_I_strobe_total_count_tx_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth1g_I_strobe_total_count_tx_read_export => reg_eth1g_I_strobe_total_count_tx_copi.rd,
+ reg_eth1g_I_strobe_total_count_tx_readdata_export => reg_eth1g_I_strobe_total_count_tx_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_eth1g_I_bsn_monitor_v2_rx_reset_export => OPEN,
+ reg_eth1g_I_bsn_monitor_v2_rx_clk_export => OPEN,
+ reg_eth1g_I_bsn_monitor_v2_rx_address_export => reg_eth1g_I_bsn_monitor_v2_rx_copi.address(4 downto 0),
+ reg_eth1g_I_bsn_monitor_v2_rx_write_export => reg_eth1g_I_bsn_monitor_v2_rx_copi.wr,
+ reg_eth1g_I_bsn_monitor_v2_rx_writedata_export => reg_eth1g_I_bsn_monitor_v2_rx_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth1g_I_bsn_monitor_v2_rx_read_export => reg_eth1g_I_bsn_monitor_v2_rx_copi.rd,
+ reg_eth1g_I_bsn_monitor_v2_rx_readdata_export => reg_eth1g_I_bsn_monitor_v2_rx_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_eth1g_I_strobe_total_count_rx_reset_export => OPEN,
+ reg_eth1g_I_strobe_total_count_rx_clk_export => OPEN,
+ reg_eth1g_I_strobe_total_count_rx_address_export => reg_eth1g_I_strobe_total_count_rx_copi.address(6 downto 0),
+ reg_eth1g_I_strobe_total_count_rx_write_export => reg_eth1g_I_strobe_total_count_rx_copi.wr,
+ reg_eth1g_I_strobe_total_count_rx_writedata_export => reg_eth1g_I_strobe_total_count_rx_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth1g_I_strobe_total_count_rx_read_export => reg_eth1g_I_strobe_total_count_rx_copi.rd,
+ reg_eth1g_I_strobe_total_count_rx_readdata_export => reg_eth1g_I_strobe_total_count_rx_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_eth1g_II_bg_ctrl_reset_export => OPEN,
+ reg_eth1g_II_bg_ctrl_clk_export => OPEN,
+ reg_eth1g_II_bg_ctrl_address_export => reg_eth1g_II_bg_ctrl_copi.address(2 downto 0),
+ reg_eth1g_II_bg_ctrl_write_export => reg_eth1g_II_bg_ctrl_copi.wr,
+ reg_eth1g_II_bg_ctrl_writedata_export => reg_eth1g_II_bg_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth1g_II_bg_ctrl_read_export => reg_eth1g_II_bg_ctrl_copi.rd,
+ reg_eth1g_II_bg_ctrl_readdata_export => reg_eth1g_II_bg_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_eth1g_II_hdr_dat_reset_export => OPEN,
+ reg_eth1g_II_hdr_dat_clk_export => OPEN,
+ reg_eth1g_II_hdr_dat_address_export => reg_eth1g_II_hdr_dat_copi.address(4 downto 0),
+ reg_eth1g_II_hdr_dat_write_export => reg_eth1g_II_hdr_dat_copi.wr,
+ reg_eth1g_II_hdr_dat_writedata_export => reg_eth1g_II_hdr_dat_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth1g_II_hdr_dat_read_export => reg_eth1g_II_hdr_dat_copi.rd,
+ reg_eth1g_II_hdr_dat_readdata_export => reg_eth1g_II_hdr_dat_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_eth1g_II_bsn_monitor_v2_tx_reset_export => OPEN,
+ reg_eth1g_II_bsn_monitor_v2_tx_clk_export => OPEN,
+ reg_eth1g_II_bsn_monitor_v2_tx_address_export => reg_eth1g_II_bsn_monitor_v2_tx_copi.address(2 downto 0),
+ reg_eth1g_II_bsn_monitor_v2_tx_write_export => reg_eth1g_II_bsn_monitor_v2_tx_copi.wr,
+ reg_eth1g_II_bsn_monitor_v2_tx_writedata_export => reg_eth1g_II_bsn_monitor_v2_tx_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth1g_II_bsn_monitor_v2_tx_read_export => reg_eth1g_II_bsn_monitor_v2_tx_copi.rd,
+ reg_eth1g_II_bsn_monitor_v2_tx_readdata_export => reg_eth1g_II_bsn_monitor_v2_tx_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_eth1g_II_strobe_total_count_tx_reset_export => OPEN,
+ reg_eth1g_II_strobe_total_count_tx_clk_export => OPEN,
+ reg_eth1g_II_strobe_total_count_tx_address_export => reg_eth1g_II_strobe_total_count_tx_copi.address(4 downto 0),
+ reg_eth1g_II_strobe_total_count_tx_write_export => reg_eth1g_II_strobe_total_count_tx_copi.wr,
+ reg_eth1g_II_strobe_total_count_tx_writedata_export => reg_eth1g_II_strobe_total_count_tx_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth1g_II_strobe_total_count_tx_read_export => reg_eth1g_II_strobe_total_count_tx_copi.rd,
+ reg_eth1g_II_strobe_total_count_tx_readdata_export => reg_eth1g_II_strobe_total_count_tx_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_eth1g_II_bsn_monitor_v2_rx_reset_export => OPEN,
+ reg_eth1g_II_bsn_monitor_v2_rx_clk_export => OPEN,
+ reg_eth1g_II_bsn_monitor_v2_rx_address_export => reg_eth1g_II_bsn_monitor_v2_rx_copi.address(2 downto 0),
+ reg_eth1g_II_bsn_monitor_v2_rx_write_export => reg_eth1g_II_bsn_monitor_v2_rx_copi.wr,
+ reg_eth1g_II_bsn_monitor_v2_rx_writedata_export => reg_eth1g_II_bsn_monitor_v2_rx_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth1g_II_bsn_monitor_v2_rx_read_export => reg_eth1g_II_bsn_monitor_v2_rx_copi.rd,
+ reg_eth1g_II_bsn_monitor_v2_rx_readdata_export => reg_eth1g_II_bsn_monitor_v2_rx_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_eth1g_II_strobe_total_count_rx_reset_export => OPEN,
+ reg_eth1g_II_strobe_total_count_rx_clk_export => OPEN,
+ reg_eth1g_II_strobe_total_count_rx_address_export => reg_eth1g_II_strobe_total_count_rx_copi.address(4 downto 0),
+ reg_eth1g_II_strobe_total_count_rx_write_export => reg_eth1g_II_strobe_total_count_rx_copi.wr,
+ reg_eth1g_II_strobe_total_count_rx_writedata_export => reg_eth1g_II_strobe_total_count_rx_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth1g_II_strobe_total_count_rx_read_export => reg_eth1g_II_strobe_total_count_rx_copi.rd,
+ reg_eth1g_II_strobe_total_count_rx_readdata_export => reg_eth1g_II_strobe_total_count_rx_cipo.rddata(c_word_w-1 DOWNTO 0),
+
reg_heater_reset_export => OPEN,
reg_heater_clk_export => OPEN,
reg_heater_address_export => reg_heater_mosi.address(4 DOWNTO 0),
@@ -781,7 +853,6 @@ BEGIN
pio_jesd_ctrl_read_export => jesd_ctrl_mosi.rd,
pio_jesd_ctrl_readdata_export => jesd_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
-
reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(7 DOWNTO 0),
reg_bsn_monitor_input_clk_export => OPEN,
reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
@@ -790,7 +861,6 @@ BEGIN
reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
reg_bsn_source_clk_export => OPEN,
reg_bsn_source_reset_export => OPEN,
reg_bsn_source_address_export => reg_bsn_source_mosi.address(1 DOWNTO 0),
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
index 750c6c2a88ca56a24a63cab54341ef2798fd7f09..4751e53edb6523fd1646ef7622c75a18de9d4821 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
@@ -24,410 +24,444 @@ USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE qsys_unb2c_test_pkg IS
-
component qsys_unb2c_test is
port (
- avs2_eth_coe_1_reset_export : out std_logic; -- export
- avs2_eth_coe_1_clk_export : out std_logic; -- export
- avs2_eth_coe_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs2_eth_coe_1_tse_write_export : out std_logic; -- export
- avs2_eth_coe_1_tse_read_export : out std_logic; -- export
- avs2_eth_coe_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs2_eth_coe_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs2_eth_coe_1_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs2_eth_coe_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs2_eth_coe_1_reg_write_export : out std_logic; -- export
- avs2_eth_coe_1_reg_read_export : out std_logic; -- export
- avs2_eth_coe_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs2_eth_coe_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs2_eth_coe_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs2_eth_coe_1_ram_write_export : out std_logic; -- export
- avs2_eth_coe_1_ram_read_export : out std_logic; -- export
- avs2_eth_coe_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs2_eth_coe_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs2_eth_coe_1_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_bg_1gbe_write_export : out std_logic; -- export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_1gbe_read_export : out std_logic; -- export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_1gbe_write_export : out std_logic; -- export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_1gbe_read_export : out std_logic; -- export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back0_reset_export : out std_logic; -- export
- reg_eth10g_back0_clk_export : out std_logic; -- export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back0_write_export : out std_logic; -- export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back0_read_export : out std_logic; -- export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back1_reset_export : out std_logic; -- export
- reg_eth10g_back1_clk_export : out std_logic; -- export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back1_write_export : out std_logic; -- export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back1_read_export : out std_logic; -- export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_reset_export : out std_logic; -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back0_write_export : out std_logic; -- export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back0_read_export : out std_logic; -- export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back1_write_export : out std_logic; -- export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back1_read_export : out std_logic; -- export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ avs2_eth_coe_1_reset_export : out std_logic; -- export
+ avs2_eth_coe_1_clk_export : out std_logic; -- export
+ avs2_eth_coe_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs2_eth_coe_1_tse_write_export : out std_logic; -- export
+ avs2_eth_coe_1_tse_read_export : out std_logic; -- export
+ avs2_eth_coe_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs2_eth_coe_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs2_eth_coe_1_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs2_eth_coe_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs2_eth_coe_1_reg_write_export : out std_logic; -- export
+ avs2_eth_coe_1_reg_read_export : out std_logic; -- export
+ avs2_eth_coe_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs2_eth_coe_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs2_eth_coe_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs2_eth_coe_1_ram_write_export : out std_logic; -- export
+ avs2_eth_coe_1_ram_read_export : out std_logic; -- export
+ avs2_eth_coe_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs2_eth_coe_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs2_eth_coe_1_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back0_reset_export : out std_logic; -- export
+ reg_eth10g_back0_clk_export : out std_logic; -- export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back0_write_export : out std_logic; -- export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back0_read_export : out std_logic; -- export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back1_reset_export : out std_logic; -- export
+ reg_eth10g_back1_clk_export : out std_logic; -- export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back1_write_export : out std_logic; -- export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back1_read_export : out std_logic; -- export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth1g_ii_bg_ctrl_reset_export : out std_logic; -- export
+ reg_eth1g_ii_bg_ctrl_clk_export : out std_logic; -- export
+ reg_eth1g_ii_bg_ctrl_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_eth1g_ii_bg_ctrl_write_export : out std_logic; -- export
+ reg_eth1g_ii_bg_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth1g_ii_bg_ctrl_read_export : out std_logic; -- export
+ reg_eth1g_ii_bg_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth1g_ii_bsn_monitor_v2_rx_reset_export : out std_logic; -- export
+ reg_eth1g_ii_bsn_monitor_v2_rx_clk_export : out std_logic; -- export
+ reg_eth1g_ii_bsn_monitor_v2_rx_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_eth1g_ii_bsn_monitor_v2_rx_write_export : out std_logic; -- export
+ reg_eth1g_ii_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth1g_ii_bsn_monitor_v2_rx_read_export : out std_logic; -- export
+ reg_eth1g_ii_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth1g_ii_bsn_monitor_v2_tx_reset_export : out std_logic; -- export
+ reg_eth1g_ii_bsn_monitor_v2_tx_clk_export : out std_logic; -- export
+ reg_eth1g_ii_bsn_monitor_v2_tx_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_eth1g_ii_bsn_monitor_v2_tx_write_export : out std_logic; -- export
+ reg_eth1g_ii_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth1g_ii_bsn_monitor_v2_tx_read_export : out std_logic; -- export
+ reg_eth1g_ii_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth1g_ii_hdr_dat_reset_export : out std_logic; -- export
+ reg_eth1g_ii_hdr_dat_clk_export : out std_logic; -- export
+ reg_eth1g_ii_hdr_dat_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_eth1g_ii_hdr_dat_write_export : out std_logic; -- export
+ reg_eth1g_ii_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth1g_ii_hdr_dat_read_export : out std_logic; -- export
+ reg_eth1g_ii_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth1g_ii_strobe_total_count_rx_reset_export : out std_logic; -- export
+ reg_eth1g_ii_strobe_total_count_rx_clk_export : out std_logic; -- export
+ reg_eth1g_ii_strobe_total_count_rx_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_eth1g_ii_strobe_total_count_rx_write_export : out std_logic; -- export
+ reg_eth1g_ii_strobe_total_count_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth1g_ii_strobe_total_count_rx_read_export : out std_logic; -- export
+ reg_eth1g_ii_strobe_total_count_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth1g_ii_strobe_total_count_tx_reset_export : out std_logic; -- export
+ reg_eth1g_ii_strobe_total_count_tx_clk_export : out std_logic; -- export
+ reg_eth1g_ii_strobe_total_count_tx_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_eth1g_ii_strobe_total_count_tx_write_export : out std_logic; -- export
+ reg_eth1g_ii_strobe_total_count_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth1g_ii_strobe_total_count_tx_read_export : out std_logic; -- export
+ reg_eth1g_ii_strobe_total_count_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth1g_i_bg_ctrl_reset_export : out std_logic; -- export
+ reg_eth1g_i_bg_ctrl_clk_export : out std_logic; -- export
+ reg_eth1g_i_bg_ctrl_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_eth1g_i_bg_ctrl_write_export : out std_logic; -- export
+ reg_eth1g_i_bg_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth1g_i_bg_ctrl_read_export : out std_logic; -- export
+ reg_eth1g_i_bg_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth1g_i_bsn_monitor_v2_rx_reset_export : out std_logic; -- export
+ reg_eth1g_i_bsn_monitor_v2_rx_clk_export : out std_logic; -- export
+ reg_eth1g_i_bsn_monitor_v2_rx_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_eth1g_i_bsn_monitor_v2_rx_write_export : out std_logic; -- export
+ reg_eth1g_i_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth1g_i_bsn_monitor_v2_rx_read_export : out std_logic; -- export
+ reg_eth1g_i_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth1g_i_bsn_monitor_v2_tx_reset_export : out std_logic; -- export
+ reg_eth1g_i_bsn_monitor_v2_tx_clk_export : out std_logic; -- export
+ reg_eth1g_i_bsn_monitor_v2_tx_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_eth1g_i_bsn_monitor_v2_tx_write_export : out std_logic; -- export
+ reg_eth1g_i_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth1g_i_bsn_monitor_v2_tx_read_export : out std_logic; -- export
+ reg_eth1g_i_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth1g_i_hdr_dat_reset_export : out std_logic; -- export
+ reg_eth1g_i_hdr_dat_clk_export : out std_logic; -- export
+ reg_eth1g_i_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_eth1g_i_hdr_dat_write_export : out std_logic; -- export
+ reg_eth1g_i_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth1g_i_hdr_dat_read_export : out std_logic; -- export
+ reg_eth1g_i_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth1g_i_strobe_total_count_rx_reset_export : out std_logic; -- export
+ reg_eth1g_i_strobe_total_count_rx_clk_export : out std_logic; -- export
+ reg_eth1g_i_strobe_total_count_rx_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_eth1g_i_strobe_total_count_rx_write_export : out std_logic; -- export
+ reg_eth1g_i_strobe_total_count_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth1g_i_strobe_total_count_rx_read_export : out std_logic; -- export
+ reg_eth1g_i_strobe_total_count_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth1g_i_strobe_total_count_tx_reset_export : out std_logic; -- export
+ reg_eth1g_i_strobe_total_count_tx_clk_export : out std_logic; -- export
+ reg_eth1g_i_strobe_total_count_tx_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_eth1g_i_strobe_total_count_tx_write_export : out std_logic; -- export
+ reg_eth1g_i_strobe_total_count_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth1g_i_strobe_total_count_tx_read_export : out std_logic; -- export
+ reg_eth1g_i_strobe_total_count_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_reset_export : out std_logic; -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
);
end component qsys_unb2c_test;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index edfd5ffc11273984e5cef97d061139cff4dde46c..8f3ed66cbfd0bba15b5484e037cc4c131816f49e 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -33,6 +33,7 @@ USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE eth_lib.eth_pkg.ALL;
+USE eth_lib.eth_tester_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE work.unb2c_test_pkg.ALL;
USE util_lib.util_heater_pkg.ALL;
@@ -131,8 +132,6 @@ ARCHITECTURE str OF unb2c_test IS
CONSTANT c_fw_version : t_unb2c_board_fw_version := (2, 0);
CONSTANT c_mm_clk_freq : NATURAL := c_unb2c_board_mm_clk_freq_125M;
-
-
-- Revision controlled constants
CONSTANT c_revision_select : t_unb2c_test_config := func_sel_revision_rec(g_design_name);
CONSTANT c_use_loopback : BOOLEAN := c_revision_select.use_loopback;
@@ -156,10 +155,13 @@ ARCHITECTURE str OF unb2c_test IS
CONSTANT c_nof_jesd204b : NATURAL := c_unb2c_board_tr_jesd204b.nof_bus * c_unb2c_board_tr_jesd204b.bus_w;
-- 1GbE
- -- This is the number of UDP offload streams. Fix it to 2 when UDP offload is enabled
--- CONSTANT c_nof_streams_1GbE_UDP : NATURAL := sel_a_b(c_use_1GbE_I,1,0) + sel_a_b(c_use_1GbE_II,1,0);
- CONSTANT c_nof_streams_1GbE_UDP : NATURAL := sel_a_b(c_use_1GbE_I_UDP,2,0);
- CONSTANT c_base_ip_II : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := X"0A64"; -- Placeholder base IP address for eth1 10.100.xx.yy
+ CONSTANT c_nof_udp_streams_1GbE_I : NATURAL := 4; -- <= c_eth_nof_udp_ports = 4, shared with M&C stream
+ CONSTANT c_nof_udp_streams_1GbE_I_w : NATURAL := 2; -- = true_log2(c_nof_udp_streams_1GbE_I), fixed reserve 2 bit extra MM address space
+ CONSTANT c_nof_udp_streams_1GbE_II : NATURAL := 1; -- fixed 1 UDP stream, so no need for dp_mux
+ CONSTANT c_nof_udp_streams_1GbE_II_w : NATURAL := 0; -- = true_log2(c_nof_udp_streams_1GbE_II), fixed reserve no extra MM address space
+ CONSTANT c_base_mac : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := c_eth_tester_eth_src_mac_47_16; -- = X"00228608"
+ CONSTANT c_base_ip : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := c_eth_tester_ip_src_addr_31_16; -- = X"0A63"
+ CONSTANT c_base_udp : STD_LOGIC_VECTOR(8-1 DOWNTO 0) := c_eth_tester_udp_src_port_15_8; -- = X"E0"
-- 10GbE
CONSTANT c_nof_streams_qsfp : NATURAL := sel_a_b(c_use_10GbE_qsfp,c_nof_qsfp,0);
@@ -192,22 +194,20 @@ ARCHITECTURE str OF unb2c_test IS
CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
CONSTANT c_use_jumbo_frames : BOOLEAN := FALSE;
- CONSTANT c_def_1GbE_block_size : NATURAL := 20; -- 0 first so we have time to set RX demux reg in dest. node
CONSTANT c_def_10GbE_block_size : NATURAL := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
CONSTANT c_max_frame_len : NATURAL := sel_a_b(c_use_jumbo_frames, 9018, 1518);
CONSTANT c_nof_header_bytes : NATURAL := field_slv_len(c_hdr_field_arr) / c_byte_w;
CONSTANT c_max_udp_payload_len : NATURAL := c_max_frame_len-c_nof_header_bytes-c_network_eth_crc_len;
- CONSTANT c_max_udp_payload_nof_words_1GbE : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w_32;
CONSTANT c_max_udp_payload_nof_words_10GbE : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w_64;
CONSTANT c_min_nof_words_per_block : NATURAL := 1;
- CONSTANT c_max_nof_blocks_per_packet_1GbE : NATURAL := c_max_udp_payload_nof_words_1GbE/c_min_nof_words_per_block;
CONSTANT c_max_nof_blocks_per_packet_10GbE : NATURAL := c_max_udp_payload_nof_words_10GbE/c_min_nof_words_per_block;
-
-- System
SIGNAL cs_sim : STD_LOGIC;
+
+ SIGNAL gn_index : NATURAL;
SIGNAL ext_clk200 : STD_LOGIC;
SIGNAL ext_rst200 : STD_LOGIC;
@@ -221,6 +221,7 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL dp_clk : STD_LOGIC;
SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL dp_pps : STD_LOGIC;
SIGNAL mb_I_ref_rst : STD_LOGIC;
SIGNAL mb_II_ref_rst : STD_LOGIC;
@@ -319,7 +320,6 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL reg_diag_data_buf_bsn_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_bsn_miso : t_mem_miso;
-
-- Heater
SIGNAL reg_heater_mosi : t_mem_mosi;
SIGNAL reg_heater_miso : t_mem_miso;
@@ -360,13 +360,39 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL reg_eth10g_back0_mosi : t_mem_mosi;
SIGNAL reg_eth10g_back0_miso : t_mem_miso;
- SIGNAL reg_diag_bg_1GbE_mosi : t_mem_mosi;
- SIGNAL reg_diag_bg_1GbE_miso : t_mem_miso;
- SIGNAL ram_diag_bg_1GbE_mosi : t_mem_mosi;
- SIGNAL ram_diag_bg_1GbE_miso : t_mem_miso;
- SIGNAL reg_diag_tx_seq_1GbE_mosi : t_mem_mosi;
- SIGNAL reg_diag_tx_seq_1GbE_miso : t_mem_miso;
+ -- 1GbE I eth_tester (c_nof_udp_streams_1GbE_I_w = 2 bit)
+ -- . Tx
+ SIGNAL reg_eth1g_I_bg_ctrl_copi : t_mem_copi := c_mem_copi_rst; -- c_diag_bg_reg_adr_w = 3 --> w = 5
+ SIGNAL reg_eth1g_I_bg_ctrl_cipo : t_mem_cipo;
+ SIGNAL reg_eth1g_I_hdr_dat_copi : t_mem_copi := c_mem_copi_rst; -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 7
+ SIGNAL reg_eth1g_I_hdr_dat_cipo : t_mem_cipo;
+ SIGNAL reg_eth1g_I_bsn_monitor_v2_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
+ SIGNAL reg_eth1g_I_bsn_monitor_v2_tx_cipo : t_mem_cipo;
+ SIGNAL reg_eth1g_I_strobe_total_count_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
+ SIGNAL reg_eth1g_I_strobe_total_count_tx_cipo : t_mem_cipo;
+ -- . Rx
+ SIGNAL reg_eth1g_I_bsn_monitor_v2_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
+ SIGNAL reg_eth1g_I_bsn_monitor_v2_rx_cipo : t_mem_cipo;
+ SIGNAL reg_eth1g_I_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
+ SIGNAL reg_eth1g_I_strobe_total_count_rx_cipo : t_mem_cipo;
+
+ -- 1GbE II eth_tester (c_nof_udp_streams_1GbE_I_w = 0 bit)
+ -- . Tx
+ SIGNAL reg_eth1g_II_bg_ctrl_copi : t_mem_copi := c_mem_copi_rst; -- c_diag_bg_reg_adr_w = 3 --> w = 3
+ SIGNAL reg_eth1g_II_bg_ctrl_cipo : t_mem_cipo;
+ SIGNAL reg_eth1g_II_hdr_dat_copi : t_mem_copi := c_mem_copi_rst; -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 5
+ SIGNAL reg_eth1g_II_hdr_dat_cipo : t_mem_cipo;
+ SIGNAL reg_eth1g_II_bsn_monitor_v2_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
+ SIGNAL reg_eth1g_II_bsn_monitor_v2_tx_cipo : t_mem_cipo;
+ SIGNAL reg_eth1g_II_strobe_total_count_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
+ SIGNAL reg_eth1g_II_strobe_total_count_tx_cipo : t_mem_cipo;
+ -- . Rx
+ SIGNAL reg_eth1g_II_bsn_monitor_v2_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
+ SIGNAL reg_eth1g_II_bsn_monitor_v2_rx_cipo : t_mem_cipo;
+ SIGNAL reg_eth1g_II_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
+ SIGNAL reg_eth1g_II_strobe_total_count_rx_cipo : t_mem_cipo;
+ -- 10GbE
SIGNAL reg_diag_bg_10GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_10GbE_miso : t_mem_miso;
SIGNAL ram_diag_bg_10GbE_mosi : t_mem_mosi;
@@ -374,18 +400,9 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL reg_diag_tx_seq_10GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_tx_seq_10GbE_miso : t_mem_miso;
- SIGNAL reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_1GbE_miso : t_mem_miso;
SIGNAL reg_bsn_monitor_10GbE_mosi : t_mem_mosi;
SIGNAL reg_bsn_monitor_10GbE_miso : t_mem_miso;
- SIGNAL ram_diag_data_buf_1GbE_mosi : t_mem_mosi;
- SIGNAL ram_diag_data_buf_1GbE_miso : t_mem_miso;
- SIGNAL reg_diag_data_buf_1GbE_mosi : t_mem_mosi;
- SIGNAL reg_diag_data_buf_1GbE_miso : t_mem_miso;
- SIGNAL reg_diag_rx_seq_1GbE_mosi : t_mem_mosi;
- SIGNAL reg_diag_rx_seq_1GbE_miso : t_mem_miso;
-
SIGNAL ram_diag_data_buf_10GbE_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_10GbE_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_10GbE_mosi : t_mem_mosi;
@@ -393,11 +410,6 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL reg_diag_rx_seq_10GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_rx_seq_10GbE_miso : t_mem_miso;
- SIGNAL dp_offload_tx_1GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
- SIGNAL dp_offload_tx_1GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
- SIGNAL dp_offload_rx_1GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
- SIGNAL dp_offload_rx_1GbE_snk_out_arr : t_dp_siso_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
-
SIGNAL dp_offload_tx_10GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
SIGNAL dp_offload_tx_10GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
SIGNAL dp_offload_rx_10GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
@@ -434,11 +446,26 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL ram_diag_data_buf_ddr_MB_II_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_ddr_MB_II_miso : t_mem_miso;
- -- Interface: 1GbE UDP streaming ports
- SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
- SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
+ -- UDP streaming ports for 1GbE I and 1GbE II
+ -- . 1GbE I
+ SIGNAL gn_eth_src_mac_I : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ SIGNAL gn_ip_src_addr_I : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ SIGNAL gn_udp_src_port_I : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+
+ SIGNAL eth1g_I_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0);
+ SIGNAL eth1g_I_udp_tx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0);
+ SIGNAL eth1g_I_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0);
+ SIGNAL eth1g_I_udp_rx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+
+ -- . 1GbE II
+ SIGNAL gn_eth_src_mac_II : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ SIGNAL gn_ip_src_addr_II : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ SIGNAL gn_udp_src_port_II : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+
+ SIGNAL eth1g_II_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0);
+ SIGNAL eth1g_II_udp_tx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0);
+ SIGNAL eth1g_II_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0);
+ SIGNAL eth1g_II_udp_rx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-- QSFP leds
SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.nof_bus-1 DOWNTO 0);
@@ -446,7 +473,10 @@ ARCHITECTURE str OF unb2c_test IS
BEGIN
- ASSERT FALSE REPORT "g_design_name=" & g_design_name SEVERITY WARNING;
+ ASSERT FALSE REPORT "g_design_name = " & g_design_name SEVERITY NOTE;
+
+ gn_index <= TO_UINT(ID);
+
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -463,8 +493,9 @@ BEGIN
g_mm_clk_freq => c_mm_clk_freq,
g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
g_aux => c_unb2c_board_aux,
+ g_base_ip => c_base_ip, -- = X"0A63" is base IP address used by unb_osy: 10.99.xx.yy
g_udp_offload => c_use_1GbE_I_UDP,
- g_udp_offload_nof_streams => c_nof_streams_1GbE_UDP,
+ g_udp_offload_nof_streams => c_nof_udp_streams_1GbE_I,
g_factory_image => g_factory_image,
g_protect_addr_range => g_protect_addr_range
)
@@ -484,7 +515,7 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
- dp_pps => OPEN,
+ dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
@@ -545,10 +576,10 @@ BEGIN
eth1g_ram_miso => eth1g_eth0_ram_miso,
-- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+ udp_tx_sosi_arr => eth1g_I_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_I_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth1g_I_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth1g_I_udp_rx_siso_arr,
-- scrap ram
ram_scrap_mosi => ram_scrap_mosi,
@@ -586,7 +617,6 @@ BEGIN
g_technology => g_technology,
g_bg_block_size => c_bg_block_size,
g_hdr_field_arr => c_hdr_field_arr,
- g_nof_streams_1GbE => c_unb2c_board_nof_eth,
g_nof_streams_qsfp => c_unb2c_board_tr_qsfp.nof_bus * c_unb2c_board_tr_qsfp.bus_w,
g_nof_streams_ring => c_unb2c_board_tr_ring.nof_bus * c_unb2c_board_tr_ring.bus_w,
g_nof_streams_back0 => c_unb2c_board_tr_back.bus_w
@@ -628,6 +658,20 @@ BEGIN
eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
+ reg_eth1g_I_bg_ctrl_copi => reg_eth1g_I_bg_ctrl_copi,
+ reg_eth1g_I_bg_ctrl_cipo => reg_eth1g_I_bg_ctrl_cipo,
+ reg_eth1g_I_hdr_dat_copi => reg_eth1g_I_hdr_dat_copi,
+ reg_eth1g_I_hdr_dat_cipo => reg_eth1g_I_hdr_dat_cipo,
+ reg_eth1g_I_bsn_monitor_v2_tx_copi => reg_eth1g_I_bsn_monitor_v2_tx_copi,
+ reg_eth1g_I_bsn_monitor_v2_tx_cipo => reg_eth1g_I_bsn_monitor_v2_tx_cipo,
+ reg_eth1g_I_strobe_total_count_tx_copi => reg_eth1g_I_strobe_total_count_tx_copi,
+ reg_eth1g_I_strobe_total_count_tx_cipo => reg_eth1g_I_strobe_total_count_tx_cipo,
+
+ reg_eth1g_I_bsn_monitor_v2_rx_copi => reg_eth1g_I_bsn_monitor_v2_rx_copi,
+ reg_eth1g_I_bsn_monitor_v2_rx_cipo => reg_eth1g_I_bsn_monitor_v2_rx_cipo,
+ reg_eth1g_I_strobe_total_count_rx_copi => reg_eth1g_I_strobe_total_count_rx_copi,
+ reg_eth1g_I_strobe_total_count_rx_cipo => reg_eth1g_I_strobe_total_count_rx_cipo,
+
-- eth1g ch1
eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
@@ -638,6 +682,20 @@ BEGIN
eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
+ reg_eth1g_II_bg_ctrl_copi => reg_eth1g_II_bg_ctrl_copi,
+ reg_eth1g_II_bg_ctrl_cipo => reg_eth1g_II_bg_ctrl_cipo,
+ reg_eth1g_II_hdr_dat_copi => reg_eth1g_II_hdr_dat_copi,
+ reg_eth1g_II_hdr_dat_cipo => reg_eth1g_II_hdr_dat_cipo,
+ reg_eth1g_II_bsn_monitor_v2_tx_copi => reg_eth1g_II_bsn_monitor_v2_tx_copi,
+ reg_eth1g_II_bsn_monitor_v2_tx_cipo => reg_eth1g_II_bsn_monitor_v2_tx_cipo,
+ reg_eth1g_II_strobe_total_count_tx_copi => reg_eth1g_II_strobe_total_count_tx_copi,
+ reg_eth1g_II_strobe_total_count_tx_cipo => reg_eth1g_II_strobe_total_count_tx_cipo,
+
+ reg_eth1g_II_bsn_monitor_v2_rx_copi => reg_eth1g_II_bsn_monitor_v2_rx_copi,
+ reg_eth1g_II_bsn_monitor_v2_rx_cipo => reg_eth1g_II_bsn_monitor_v2_rx_cipo,
+ reg_eth1g_II_strobe_total_count_rx_copi => reg_eth1g_II_strobe_total_count_rx_copi,
+ reg_eth1g_II_strobe_total_count_rx_cipo => reg_eth1g_II_strobe_total_count_rx_cipo,
+
-- EPCS read
reg_dpmm_data_mosi => reg_dpmm_data_mosi,
reg_dpmm_data_miso => reg_dpmm_data_miso,
@@ -663,13 +721,6 @@ BEGIN
reg_heater_miso => reg_heater_miso,
-- block gen
- ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
- reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
- reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
-
ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
@@ -678,19 +729,10 @@ BEGIN
reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-- bsn
- reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-- databuffer
- ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
-
ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
@@ -761,89 +803,65 @@ BEGIN
ram_scrap_miso => ram_scrap_miso
);
- -- TODO: Add support for second 1GbE port
+
gen_udp_stream_1GbE : IF c_use_1GbE_I_UDP = TRUE GENERATE
- u_udp_stream_1GbE : ENTITY work.udp_stream
+ gn_eth_src_mac_I <= c_base_mac & func_eth_tester_gn_index_to_mac_15_0(gn_index, 0);
+ gn_ip_src_addr_I <= c_base_ip & func_eth_tester_gn_index_to_ip_15_0(gn_index, 0);
+ gn_udp_src_port_I <= c_base_udp & func_eth_tester_gn_index_to_udp_7_0(gn_index, 0);
+
+ u_eth_tester_I : ENTITY eth_lib.eth_tester
GENERIC MAP (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_1GbE_UDP,
- g_data_w => c_data_w_32,
- g_bg_block_size => c_def_1GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_1GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_1GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => TRUE
+ g_nof_streams => c_nof_udp_streams_1GbE_I,
+ g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
+ g_remove_crc => TRUE -- use TRUE when using TSE link interface
)
PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+ st_pps => dp_pps,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ -- UDP transmit interface
+ eth_src_mac => gn_eth_src_mac_I,
+ ip_src_addr => gn_ip_src_addr_I,
+ udp_src_port => gn_udp_src_port_I,
- ID => ID,
+ tx_fifo_rd_emp_arr => OPEN,
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
-
- -- dp_offload_tx
--- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
-
- -- dp_offload_rx
--- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
-
- -- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
-
- -- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ tx_udp_sosi_arr => eth1g_I_udp_tx_sosi_arr,
+ tx_udp_siso_arr => eth1g_I_udp_tx_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => eth1g_I_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ -- . Tx
+ reg_bg_ctrl_copi => reg_eth1g_I_bg_ctrl_copi,
+ reg_bg_ctrl_cipo => reg_eth1g_I_bg_ctrl_cipo,
+ reg_hdr_dat_copi => reg_eth1g_I_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_eth1g_I_hdr_dat_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_eth1g_I_bsn_monitor_v2_tx_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_eth1g_I_bsn_monitor_v2_tx_cipo,
+ reg_strobe_total_count_tx_copi => reg_eth1g_I_strobe_total_count_tx_copi,
+ reg_strobe_total_count_tx_cipo => reg_eth1g_I_strobe_total_count_tx_cipo,
+ -- . Rx
+ reg_bsn_monitor_v2_rx_copi => reg_eth1g_I_bsn_monitor_v2_rx_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_eth1g_I_bsn_monitor_v2_rx_cipo,
+ reg_strobe_total_count_rx_copi => reg_eth1g_I_strobe_total_count_rx_copi,
+ reg_strobe_total_count_rx_cipo => reg_eth1g_I_strobe_total_count_rx_cipo
);
END GENERATE;
- -----------------------------------------------------------------------------
- -- Interface : 1GbE
- -----------------------------------------------------------------------------
- -- TODO: Add support for second 1GbE port
- gen_wires_1GbE : IF c_use_1GbE_I_UDP=TRUE GENERATE
- gen_1GbE_wires : FOR i IN 0 TO c_nof_streams_1GbE_UDP-1 GENERATE
- eth1g_udp_tx_sosi_arr(i) <= dp_offload_tx_1GbE_src_out_arr(i);
- dp_offload_tx_1GbE_src_in_arr(i) <= eth1g_udp_tx_siso_arr(i);
- dp_offload_rx_1GbE_snk_in_arr(i) <= eth1g_udp_rx_sosi_arr(i);
- eth1g_udp_rx_siso_arr(i) <= dp_offload_rx_1GbE_snk_out_arr(i);
-
- END GENERATE;
- END GENERATE;
-
- -- Instantiate a second 1G Eth to check pinning
- gen_eth_II: IF c_use_1GbE_II=TRUE GENERATE
- --gen_eth_II: IF FALSE GENERATE
+ -- Instantiate a second 1GbE to check pinning
+ gen_eth_II: IF c_use_1GbE_II = TRUE GENERATE
u_eth : ENTITY eth_lib.eth
GENERIC MAP (
g_technology => g_technology,
- g_init_ip_address => C_base_ip_II & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_init_ip_address => c_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
g_cross_clock_domain => TRUE,
g_frm_discard_en => TRUE
)
@@ -879,6 +897,56 @@ BEGIN
-- LED interface
tse_led => open
);
+
+ -- TODO: Add control and connect for second 1GbE
+
+ gn_eth_src_mac_II <= c_base_mac & func_eth_tester_gn_index_to_mac_15_0(gn_index, 1);
+ gn_ip_src_addr_II <= c_base_ip & func_eth_tester_gn_index_to_ip_15_0(gn_index, 1);
+ gn_udp_src_port_II <= c_base_udp & func_eth_tester_gn_index_to_udp_7_0(gn_index, 1);
+
+ u_eth_tester_II : ENTITY eth_lib.eth_tester
+ GENERIC MAP (
+ g_nof_streams => c_nof_udp_streams_1GbE_II,
+ g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
+ g_remove_crc => TRUE -- use TRUE when using TSE link interface
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+ st_pps => dp_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => gn_eth_src_mac_II,
+ ip_src_addr => gn_ip_src_addr_II,
+ udp_src_port => gn_udp_src_port_II,
+
+ tx_fifo_rd_emp_arr => OPEN,
+
+ tx_udp_sosi_arr => eth1g_II_udp_tx_sosi_arr,
+ tx_udp_siso_arr => eth1g_II_udp_tx_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => eth1g_II_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ -- . Tx
+ reg_bg_ctrl_copi => reg_eth1g_II_bg_ctrl_copi,
+ reg_bg_ctrl_cipo => reg_eth1g_II_bg_ctrl_cipo,
+ reg_hdr_dat_copi => reg_eth1g_II_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_eth1g_II_hdr_dat_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_eth1g_II_bsn_monitor_v2_tx_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_eth1g_II_bsn_monitor_v2_tx_cipo,
+ reg_strobe_total_count_tx_copi => reg_eth1g_II_strobe_total_count_tx_copi,
+ reg_strobe_total_count_tx_cipo => reg_eth1g_II_strobe_total_count_tx_cipo,
+ -- . Rx
+ reg_bsn_monitor_v2_rx_copi => reg_eth1g_II_bsn_monitor_v2_rx_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_eth1g_II_bsn_monitor_v2_rx_cipo,
+ reg_strobe_total_count_rx_copi => reg_eth1g_II_strobe_total_count_rx_copi,
+ reg_strobe_total_count_rx_cipo => reg_eth1g_II_strobe_total_count_rx_cipo
+ );
END GENERATE;
@@ -1031,7 +1099,6 @@ BEGIN
QSFP_5_TX <= i_QSFP_TX(5);
-
u_front_io : ENTITY unb2c_board_lib.unb2c_board_front_io
GENERIC MAP (
g_nof_qsfp_bus => c_nof_qsfp_bus
@@ -1103,7 +1170,6 @@ BEGIN
END GENERATE;
-
gen_back_wiring : IF c_use_10GbE_back0 = TRUE GENERATE
gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
@@ -1389,6 +1455,4 @@ BEGIN
);
END GENERATE;
-
END str;
-
diff --git a/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
index 79b64ba28ede58c2fa569e3cccf8831cbfcb77e6..5471d440f416572fd6f1e8f5cd7d58582a9f217e 100644
--- a/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
@@ -132,7 +132,6 @@ ARCHITECTURE tb OF tb_unb2c_test IS
SIGNAL si_lpbk_8 : STD_LOGIC_VECTOR(c_unb2c_board_tr_back.bus_w-1 DOWNTO 0);
-
BEGIN
----------------------------------------------------------------------------
@@ -147,7 +146,6 @@ BEGIN
mb_I_ref_clk <= NOT mb_I_ref_clk AFTER c_mb_I_ref_clk_period/2; -- MB I reference clock (25 MHz)
mb_II_ref_clk <= NOT mb_II_ref_clk AFTER c_mb_II_ref_clk_period/2; -- MB II reference clock (25 MHz)
-
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
@@ -160,11 +158,8 @@ BEGIN
-- 1GbE Loopback model
------------------------------------------------------------------------------
eth_rxp(0) <= TRANSPORT eth_txp(0) AFTER c_cable_delay;
+ eth_rxp(1) <= TRANSPORT eth_txp(1) AFTER c_cable_delay;
- eth_rxp(1) <= '0';
-
- eth_txp(1) <= '0';
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
@@ -202,11 +197,10 @@ BEGIN
-- DDR reference clocks
MB_I_REF_CLK => mb_I_ref_clk,
MB_II_REF_CLK => mb_II_ref_clk,
-
-- Serial I/O
- -- QSFP_0_TX => si_lpbk_0,
- -- QSFP_0_RX => si_lpbk_0,
+-- QSFP_0_TX => si_lpbk_0,
+-- QSFP_0_RX => si_lpbk_0,
-- QSFP_1_TX => si_lpbk_1,
-- QSFP_1_RX => si_lpbk_1,
-- QSFP_2_TX => si_lpbk_2,
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
index 4bcc9cc53122eb7816fff45a50dca160633afba1..3ece313f75f7f3a4529721e4d1da7d2d8cd3df15 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
@@ -57,7 +57,7 @@ ARCHITECTURE str OF unb2c_board_system_info IS
SIGNAL hw_version_reg : STD_LOGIC_VECTOR(hw_version'RANGE);
SIGNAL id_reg : STD_LOGIC_VECTOR(id'RANGE);
- SIGNAL nxt_info : STD_LOGIC_VECTOR(info'RANGE);
+ SIGNAL nxt_info : STD_LOGIC_VECTOR(info'RANGE) := (OTHERS=>'0');
SIGNAL nxt_bck_id : STD_LOGIC_VECTOR(bck_id'RANGE);
SIGNAL nxt_chip_id : STD_LOGIC_VECTOR(chip_id'RANGE);
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index 45c015e10507b4d1780a3490763a7bf333f082b4..429197e7d13e277f1e30b4d0081f425d09625b9e 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -105,6 +105,31 @@ during tb simulation load --> fixed by "sudo chmod a+w -R modelsim_altera_libs/1
> run_quartus unb1 &
+# Modify QSYS
+> quartus_config unb2c
+> run_quartus unb2c &
+ - Open project
+ - Tools/Platform Designer
+ . Platform designer system choose qsys from build
+ - In system view:
+ . remove components
+ . add components from Uniboard library (double click avs_common_mm or use green +)
+ use qsys_unb2c_test_ prefix in component name ip file, but rename component without prefix
+ . System/assign base addresses
+ System/assign interrupt numbers
+ if needed do: Sync system infos button
+ . copy component from Generate/Show instance template --> qsys_unb2c_test_pkg.vhd
+ . no need to generate HDL
+ - File save.
+> Copy qsys and ip files to the quartus dir of the mother design.
+ . cp build/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/*.ip boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/
+ . cp build/unb2c/quartus/unb2c_test_1GbE_I/qsys_unb2c_test.qsys boards/uniboard2c/designs/unb2c_test/quartus
+> The hdllib.cfg of each revision design will copy the qsys and ip files to each
+ revision build quartus dir, so all revisions use the same qsys.
+
+
+
+
# Run command line synthesis for dts
quartus_config unb2c
run_qsys_pro unb2c lofar2_unb2c_sdp_station_full;
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 55bf1da32ec2cac8f6a1c035ea219a7c4ade3a75..103999daa8626e028136728eb91b0bfe1bb365e2 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -51,6 +51,7 @@ PACKAGE common_pkg IS
CONSTANT c_64 : NATURAL := 64;
CONSTANT c_128 : NATURAL := 128;
CONSTANT c_256 : NATURAL := 256;
+ CONSTANT c_natural_high : NATURAL := 2147483647; -- = 2**31 - 1 = NATURAL'HIGH;
-- widths and sizes
CONSTANT c_halfword_sz : NATURAL := 2;
diff --git a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
index 2a08ade6252bd31a5064cfbbe7c6f557f7c565e7..5f05e64a48373ba8ad06ca1a1573faf837685ca5 100644
--- a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
+++ b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
@@ -113,15 +113,17 @@ ARCHITECTURE rtl OF dp_strobe_total_count IS
TYPE t_cnt_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_count_w-1 DOWNTO 0);
-- Registers in dp_clk domain
- SIGNAL ref_sync_reg : STD_LOGIC := '0';
- SIGNAL in_strobe_reg_arr : STD_LOGIC_VECTOR(g_nof_counts-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL rd_reg : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL mm_cnt_clr : STD_LOGIC;
- SIGNAL cnt_clr : STD_LOGIC;
- SIGNAL cnt_en : STD_LOGIC := '0';
- SIGNAL cnt_en_arr : STD_LOGIC_VECTOR(g_nof_counts-1 DOWNTO 0);
- SIGNAL cnt_arr : t_cnt_arr(g_nof_counts-1 DOWNTO 0);
- SIGNAL hold_cnt_arr : t_cnt_arr(g_nof_counts-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+ SIGNAL ref_sync_reg : STD_LOGIC := '0';
+ SIGNAL ref_sync_reg2 : STD_LOGIC := '0';
+ SIGNAL in_strobe_reg_arr : STD_LOGIC_VECTOR(g_nof_counts-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_strobe_reg2_arr : STD_LOGIC_VECTOR(g_nof_counts-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL rd_reg : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL mm_cnt_clr : STD_LOGIC;
+ SIGNAL cnt_clr : STD_LOGIC;
+ SIGNAL cnt_en : STD_LOGIC := '0';
+ SIGNAL cnt_en_arr : STD_LOGIC_VECTOR(g_nof_counts-1 DOWNTO 0);
+ SIGNAL cnt_arr : t_cnt_arr(g_nof_counts-1 DOWNTO 0);
+ SIGNAL hold_cnt_arr : t_cnt_arr(g_nof_counts-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
BEGIN
@@ -140,16 +142,34 @@ BEGIN
out_pulse => cnt_clr
);
+ -- Register inputs to ease timing closure
-- . register ref_sync to ease timing closure for ref_sync fanout
- ref_sync_reg <= ref_sync WHEN rising_edge(dp_clk);
-
-- . register in_strobe_arr to preserve alignment with ref_sync
+ ref_sync_reg <= ref_sync WHEN rising_edge(dp_clk);
in_strobe_reg_arr <= in_strobe_arr WHEN rising_edge(dp_clk);
+ -- Register inputs again to be able to align registered cnt_en and
+ -- pipelined ref_sync pulse
+ ref_sync_reg2 <= ref_sync_reg WHEN rising_edge(dp_clk);
+ in_strobe_reg2_arr <= in_strobe_reg_arr WHEN rising_edge(dp_clk);
+
-- . clear strobe counters immediately at cnt_clr
- -- . start strobe counters after ref_sync, e.g. to align strobe counters in different nodes in
- -- case the input was (already) active during the cnt_clr
- cnt_en <= '0' WHEN cnt_clr = '1' ELSE '1' WHEN ref_sync_reg = '1' ELSE cnt_en;
+ -- . start strobe counters after ref_sync, e.g. to align strobe counters
+ -- in different nodes in case the input was (already) active during
+ -- the cnt_clr
+ p_cnt_en : PROCESS(dp_rst, dp_clk)
+ BEGIN
+ IF dp_rst = '1' THEN
+ cnt_en <= '0';
+ ELSIF rising_edge(dp_clk) THEN
+ IF cnt_clr = '1' THEN
+ cnt_en <= '0';
+ ELSIF ref_sync_reg = '1' THEN
+ -- use ref_sync_reg have cnt_en high aligned with ref_sync_reg2
+ cnt_en <= '1';
+ END IF;
+ END IF;
+ END PROCESS;
-- strobe counters
gen_counters : FOR I IN 0 TO g_nof_counts-1 GENERATE
@@ -170,13 +190,14 @@ BEGIN
);
END GENERATE;
- -- Hold counter values at ref_sync_reg to have stable values for MM read for comparision between nodes
+ -- Hold counter values at ref_sync_reg2 to have stable values for MM read
+ -- for comparision between nodes
p_hold_counters : PROCESS(dp_clk)
BEGIN
IF rising_edge(dp_clk) THEN
IF cnt_clr = '1' THEN
hold_cnt_arr <= (OTHERS=>(OTHERS=>'0'));
- ELSIF ref_sync_reg = '1' THEN
+ ELSIF ref_sync_reg2 = '1' THEN
hold_cnt_arr <= cnt_arr;
END IF;
END IF;
diff --git a/libraries/io/eth/src/vhdl/eth_tester.vhd b/libraries/io/eth/src/vhdl/eth_tester.vhd
index 9ff3d07b8fae0fb274410b2b1076e17ac906403b..e6253bb87bd4c786fa8ed39d676775e9d17cb485 100644
--- a/libraries/io/eth/src/vhdl/eth_tester.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester.vhd
@@ -38,7 +38,7 @@ USE work.eth_tester_pkg.ALL;
ENTITY eth_tester IS
GENERIC (
g_nof_streams : NATURAL := 1;
- g_bg_sync_timeout : NATURAL := 220*10**6; -- 10% margin for nominal 1 s with st_clk at 200MHz
+ g_bg_sync_timeout : NATURAL := c_eth_tester_sync_timeout;
g_remove_crc : BOOLEAN := TRUE -- use TRUE when using sim_tse and tech_tse link interface,
-- use FALSE when streaming link interface
);
diff --git a/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd b/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
index a60dc6c2e381120c811770d11e5100a14d1ac4be..207728be0545d8f11f45451d303960e31546ab05 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
@@ -35,6 +35,11 @@ PACKAGE eth_tester_pkg is
CONSTANT c_eth_tester_rx_block_len_max : NATURAL := c_network_eth_payload_jumbo_max + c_network_eth_crc_len; -- 9004 octets
CONSTANT c_eth_tester_eth_packet_len_max : NATURAL := c_network_eth_word_align_len + c_network_eth_frame_jumbo_max; -- 9020 octets = 2 word align + 14 header + 9000 + 4 crc
+ -- Support maximum (2**31-1)/200e6 = 10.7 s BG sync interval for sync timeout
+ -- in BSN monitors, assuming st_clk at 200 MHz and with maximum NATURAL value
+ -- of c_natural_high = 2**31 - 1.
+ CONSTANT c_eth_tester_sync_timeout : NATURAL := c_natural_high;
+
-- hdr_field_sel bit selects where the hdr_field value is set:
-- . 0 = data path controlled, value is set in data path, so field_default()
-- is not used.
@@ -92,7 +97,7 @@ PACKAGE eth_tester_pkg is
CONSTANT c_eth_tester_app_hdr_len : NATURAL := 12; -- octets
- -- Destinations:
+ -- Source ETH MAC/IP/UDP:
-- . MAC address 00:22:86:08:pp:qq = UNB_ETH_SRC_MAC_BASE in
-- libraries/unb_osy/unbos_eth.h, pp = backplane ID, qq = node ID
-- . IP address 10.99.xx.yy = g_base_ip in ctrl_unb2#_board.vhd used in
@@ -116,6 +121,15 @@ PACKAGE eth_tester_pkg is
app : t_eth_tester_app_header;
END RECORD;
+ -- Map global node index on UniBoard2 to node src MAC, IP and UDP port
+ FUNCTION func_eth_tester_gn_index_to_mac_15_0(gn_index : NATURAL; eth_port_index : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_eth_tester_gn_index_to_mac_15_0(gn_index : NATURAL) RETURN STD_LOGIC_VECTOR; -- default use 1GbE port I
+ FUNCTION func_eth_tester_gn_index_to_ip_15_0(gn_index : NATURAL; eth_port_index : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_eth_tester_gn_index_to_ip_15_0(gn_index : NATURAL) RETURN STD_LOGIC_VECTOR; -- default use 1GbE port I
+ FUNCTION func_eth_tester_gn_index_to_udp_7_0(gn_index : NATURAL; eth_port_index : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_eth_tester_gn_index_to_udp_7_0(gn_index : NATURAL) RETURN STD_LOGIC_VECTOR; -- default use 1GbE port I
+
+ -- Map packet header fields to t_eth_tester_header record
FUNCTION func_eth_tester_map_header(hdr_fields_raw : STD_LOGIC_VECTOR) RETURN t_eth_tester_header;
END eth_tester_pkg;
@@ -123,6 +137,58 @@ END eth_tester_pkg;
PACKAGE BODY eth_tester_pkg IS
+ FUNCTION func_eth_tester_gn_index_to_mac_15_0(gn_index : NATURAL; eth_port_index : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ -- Assume gn_index < 256.
+ -- Use default address for 1GbE II (eth_port_index = 0) and
+ -- an address offset for 1GbE II (eth_port_index = 1)
+ CONSTANT c_unb_nr : NATURAL := gn_index / c_4; -- 4 PN per Uniboard2
+ CONSTANT c_node_nr : NATURAL := gn_index MOD c_4;
+ CONSTANT c_offset : NATURAL := eth_port_index * c_4;
+ CONSTANT c_mac_15_0 : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr + c_offset, 8);
+ BEGIN
+ RETURN c_mac_15_0;
+ END func_eth_tester_gn_index_to_mac_15_0;
+
+ FUNCTION func_eth_tester_gn_index_to_mac_15_0(gn_index : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_eth_tester_gn_index_to_mac_15_0(gn_index, 0); -- default use 1GbE port I
+ END func_eth_tester_gn_index_to_mac_15_0;
+
+
+ FUNCTION func_eth_tester_gn_index_to_ip_15_0(gn_index : NATURAL; eth_port_index : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ -- Assume gn_index < 256.
+ -- Use default address for 1GbE II (eth_port_index = 0) and
+ -- an address offset for 1GbE II (eth_port_index = 1)
+ CONSTANT c_unb_nr : NATURAL := gn_index / c_4; -- 4 PN per Uniboard2
+ CONSTANT c_node_nr : NATURAL := gn_index MOD c_4;
+ CONSTANT c_offset : NATURAL := eth_port_index * c_4;
+ CONSTANT c_ip_15_0 : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr + 1 + c_offset, 8); -- +1 to avoid IP = *.*.*.0
+ BEGIN
+ RETURN c_ip_15_0;
+ END func_eth_tester_gn_index_to_ip_15_0;
+
+ FUNCTION func_eth_tester_gn_index_to_ip_15_0(gn_index : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_eth_tester_gn_index_to_ip_15_0(gn_index, 0); -- default use 1GbE port I
+ END func_eth_tester_gn_index_to_ip_15_0;
+
+
+ FUNCTION func_eth_tester_gn_index_to_udp_7_0(gn_index : NATURAL; eth_port_index : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ -- Assume gn_index < 128.
+ -- Use default udp port for 1GbE I (eth_port_index = 0) and
+ -- an increment udp port for 1GbE II (eth_port_index = 1)
+ CONSTANT c_offset : NATURAL := eth_port_index * c_128; -- MSbit 7
+ CONSTANT c_udp_7_0 : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(gn_index + c_offset, 8);
+ BEGIN
+ RETURN c_udp_7_0;
+ END func_eth_tester_gn_index_to_udp_7_0;
+
+ FUNCTION func_eth_tester_gn_index_to_udp_7_0(gn_index : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_eth_tester_gn_index_to_udp_7_0(gn_index, 0); -- default use 1GbE port I
+ END func_eth_tester_gn_index_to_udp_7_0;
+
+
FUNCTION func_eth_tester_map_header(hdr_fields_raw : STD_LOGIC_VECTOR) RETURN t_eth_tester_header IS
VARIABLE v : t_eth_tester_header;
BEGIN
diff --git a/libraries/io/eth/src/vhdl/eth_tester_tx.vhd b/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
index b4d2201a231e12ae4d740cac6cdc5561904ec466..d1051404ea32694f5633b233db53fafb86f8e364 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
@@ -79,8 +79,9 @@ ARCHITECTURE str OF eth_tester_tx IS
-- level flow control via bg_siso.xon. The input eop will release blocks
-- for FIFO output already before the FIFO is fill level is reached.
-- Choose FIFO size to fit one more packet on top of FIFO fill level.
- CONSTANT c_fifo_fill : NATURAL := c_eth_tester_bg_block_len_max * 11 / c_word_sz / 10;
- CONSTANT c_fifo_size : NATURAL := true_log_pow2(c_fifo_fill + c_eth_tester_bg_block_len_max); -- = 8192
+ CONSTANT c_packet_sz_max : NATURAL := ceil_div(c_eth_tester_bg_block_len_max, c_word_sz);
+ CONSTANT c_fifo_fill : NATURAL := c_packet_sz_max * 11 / 10;
+ CONSTANT c_fifo_size : NATURAL := true_log_pow2(c_fifo_fill + c_packet_sz_max); -- = 8192
CONSTANT c_nof_total_counts : NATURAL := 1; -- one to count Tx packets
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
index f0f0574905364b3ac22679e2f80e0799a633fc9c..8ca739e98fcfacc242c044c470a00d290ef17097 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
@@ -540,6 +540,7 @@ BEGIN
dut : ENTITY work.eth_tester
GENERIC MAP (
g_nof_streams => g_nof_streams,
+ g_bg_sync_timeout => c_eth_tester_sync_timeout,
g_remove_crc => g_loopback_eth -- remove CRC inserted by TSE (sim or tech)
)
PORT MAP (
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
index e0fd29ce23adf74df9ea0ccd9ef1bad4eb36e924..4705b6f018f3b1f657ee08fd7ee846a909855ef8 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
@@ -39,10 +39,6 @@ PACKAGE tb_eth_tester_pkg is
CONSTANT c_eth_tester_ip_dst_addr : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"0A6300FE"; -- 0A6300FE = '10.99.0.254' = DOP36-enp2s0
CONSTANT c_eth_tester_udp_dst_port : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(6001, 16); -- 0x1771 = 6001
- -- Map global node index on UniBoard2 to node MAC address and node IP address
- FUNCTION func_eth_tester_gn_index_to_mac_15_0(gn_index : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_eth_tester_gn_index_to_ip_15_0(gn_index : NATURAL) RETURN STD_LOGIC_VECTOR;
-
-- Ethernet packet length in octets inclduing eth header and CRC
FUNCTION func_eth_tester_eth_packet_length(block_len : NATURAL) RETURN NATURAL;
@@ -54,22 +50,6 @@ END tb_eth_tester_pkg;
PACKAGE BODY tb_eth_tester_pkg IS
- FUNCTION func_eth_tester_gn_index_to_mac_15_0(gn_index : NATURAL) RETURN STD_LOGIC_VECTOR IS
- CONSTANT c_unb_nr : NATURAL := gn_index / 4; -- 4 PN per Uniboard2
- CONSTANT c_node_nr : NATURAL := gn_index MOD 4;
- CONSTANT c_mac_15_0 : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr, 8);
- BEGIN
- RETURN c_mac_15_0;
- END func_eth_tester_gn_index_to_mac_15_0;
-
- FUNCTION func_eth_tester_gn_index_to_ip_15_0(gn_index : NATURAL) RETURN STD_LOGIC_VECTOR IS
- CONSTANT c_unb_nr : NATURAL := gn_index / 4; -- 4 PN per Uniboard2
- CONSTANT c_node_nr : NATURAL := gn_index MOD 4;
- CONSTANT c_ip_15_0 : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr+1, 8); -- +1 to avoid IP = *.*.*.0
- BEGIN
- RETURN c_ip_15_0;
- END func_eth_tester_gn_index_to_ip_15_0;
-
FUNCTION func_eth_tester_eth_packet_length(block_len : NATURAL) RETURN NATURAL IS
CONSTANT c_app_len : NATURAL := c_eth_tester_app_hdr_len + block_len;
CONSTANT c_udp_len : NATURAL := c_network_udp_header_len + c_app_len;