diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd index e76dfb98390db9e18c87c9b6d25abf0be5078650..0c3b1c322af3c6b2ebf90ec02d177b351981b69d 100644 --- a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd +++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd @@ -80,11 +80,11 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_filterbank_sst_offload IS CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps -- . 1GbE output - CONSTANT c_eth_check_nof_packets : NATURAL := 12; -- FXME + CONSTANT c_eth_check_nof_packets : NATURAL := 1024; -- FXME CONSTANT c_eth_header_size : NATURAL := 40; -- FIXME (pad(2) + eth(14) + ip(20) + udp(8) + app(16+24))/4 = 84 / 4 CONSTANT c_udp_payload_size : NATURAL := 4104; -- FIXME CONSTANT c_eth_packet_size : NATURAL := c_eth_header_size + c_udp_payload_size; - CONSTANT c_eth_runtime_timeout : TIME := 5 ms; -- factor 2 margin + CONSTANT c_eth_runtime_timeout : TIME := 500 ms; -- factor 2 margin -- MM CONSTANT c_mm_file_reg_bsn_source : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE"; @@ -208,7 +208,7 @@ BEGIN ------------------------------------------------------------------------------ -- MM slave accesses via file IO ------------------------------------------------------------------------------ - tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock + tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock p_mm_stimuli : PROCESS CONSTANT c_mm_file_reg_stat_enable : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE"; @@ -238,26 +238,26 @@ BEGIN -- 1 : phase[15:0] -- 2 : freq[30:0] -- 3 : ampl[16:0] - --mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc - --mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees - --mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER((c_subband_sp_0+c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq - --mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, INTEGER(REAL(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl - - ---- Read current BSN - --mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk); - --mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk); - --proc_common_wait_some_cycles(tb_clk, 1); + mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc + mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees + mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER((c_subband_sp_0+c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq + mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, INTEGER(REAL(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl + + -- Read current BSN + mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk); + mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk); + proc_common_wait_some_cycles(tb_clk, 1); - ---- Write scheduler BSN to trigger start of WG at next block - --v_bsn := TO_UINT(current_bsn_wg) + 2; - --ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR; - --v_bsn := c_bsn_start_wg; - --mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part - --mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1 + -- Write scheduler BSN to trigger start of WG at next block + v_bsn := TO_UINT(current_bsn_wg) + 2; + ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR; + v_bsn := c_bsn_start_wg; + mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part + mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1 - ---- Wait for ADUH monitor to have filled with WG data - --WAIT FOR c_sdp_T_sub*c_sdp_N_taps; - --WAIT FOR c_sdp_T_sub*2; + -- Wait for ADUH monitor to have filled with WG data + WAIT FOR c_sdp_T_sub*c_sdp_N_taps; + WAIT FOR c_sdp_T_sub*2; -- Offload enable @@ -282,7 +282,7 @@ BEGIN g_check_nof_valid_ref => c_eth_check_nof_packets*c_eth_packet_size ) PORT MAP ( - eth_serial_in => eth_txp(1), + eth_serial_in => eth_txp(0), tb_end => eth_done );