diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
index 88a30c35c09518cbccbc6d16183e980fec49fdce..c266c6948d49833f5a6415bd081f6cf9b7e7f828 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
@@ -19,18 +19,18 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, unb_common_lib;
+LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-USE unb_common_lib.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
-ENTITY unb_back_io IS
+ENTITY unb1_board_back_io IS
GENERIC (
g_bus_w : NATURAL := 4
);
PORT (
- tx_serial_2arr : IN t_unb_back_sl_2arr := (OTHERS=>(OTHERS=>'0'));
- rx_serial_2arr : OUT t_unb_back_sl_2arr;
+ tx_serial_2arr : IN t_unb1_board_back_sl_2arr := (OTHERS=>(OTHERS=>'0'));
+ rx_serial_2arr : OUT t_unb1_board_back_sl_2arr;
-- Serial I/O
-- . hard IP transceivers busses
@@ -44,10 +44,10 @@ ENTITY unb_back_io IS
BN_BI_3_TX : OUT STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0);
BN_BI_3_RX : IN STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0) := (OTHERS=>'0')
);
-END unb_back_io;
+END unb1_board_back_io;
-ARCHITECTURE str OF unb_back_io IS
+ARCHITECTURE str OF unb1_board_back_io IS
BEGIN
-- Map the serial streams to the back
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
index 5337bb0edb18d37519ff50b31f4c6cfd5ddf17f0..a6df6400d0e2ec7c6288281eb9d397538dd2625c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
@@ -30,8 +30,8 @@
-- The usr bus index can be 3:0, so including this UniBoard itself that is
-- indicated by usr bus index bck_id. The other 3 usr busses each connect to
-- the corresponding Uniboard.
--- The unb_back_reorder has to map the usr index 3:0 (excluding its own index
--- bck_id) on to the phy index 2:0. The logical mapping is:
+-- The unb1_board_back_reorder has to map the usr index 3:0 (excluding its
+-- own index bck_id) on to the phy index 2:0. The logical mapping is:
--
-- UniBoard bck_id=3 connects to UniBoards 2,1,0 via phy busses 2,1,0
-- 2 3,1,0 2,1,0
@@ -46,42 +46,43 @@
-- 1 3,2,0 0,1,2
-- 0 3,2,1 0,2,1
--
--- The mapping is the same for all BN on the UniBoard. The unb_back_reorder
--- maps for the Apertif beamformer backplane with 4 UniBoards.
+-- The mapping is the same for all BN on the UniBoard. The
+-- unb1_board_back_reorder maps for the Apertif beamformer backplane with
+-- 4 UniBoards.
-- Remark:
--- . See unb_back_model_sl.vhd for the Apertif backplane model
+-- . See unb1_board_back_model_sl.vhd for the Apertif backplane model
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE work.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
-ENTITY unb_back_reorder IS
+ENTITY unb1_board_back_reorder IS
PORT (
- bck_id : IN STD_LOGIC_VECTOR(c_unb_nof_uniboard_w-1 DOWNTO 0);
+ bck_id : IN STD_LOGIC_VECTOR(c_unb1_board_nof_uniboard_w-1 DOWNTO 0);
clk : IN STD_LOGIC;
-- usr side interface
- tx_usr_sosi_2arr : IN t_unb_back_sosi_2arr;
- tx_usr_siso_2arr : OUT t_unb_back_siso_2arr;
+ tx_usr_sosi_2arr : IN t_unb1_board_back_sosi_2arr;
+ tx_usr_siso_2arr : OUT t_unb1_board_back_siso_2arr;
- rx_usr_sosi_2arr : OUT t_unb_back_sosi_2arr;
- rx_usr_siso_2arr : IN t_unb_back_siso_2arr;
+ rx_usr_sosi_2arr : OUT t_unb1_board_back_sosi_2arr;
+ rx_usr_siso_2arr : IN t_unb1_board_back_siso_2arr;
-- phy side interface
- tx_phy_sosi_2arr : OUT t_unb_back_sosi_2arr;
- tx_phy_siso_2arr : IN t_unb_back_siso_2arr;
+ tx_phy_sosi_2arr : OUT t_unb1_board_back_sosi_2arr;
+ tx_phy_siso_2arr : IN t_unb1_board_back_siso_2arr;
- rx_phy_sosi_2arr : IN t_unb_back_sosi_2arr;
- rx_phy_siso_2arr : OUT t_unb_back_siso_2arr
+ rx_phy_sosi_2arr : IN t_unb1_board_back_sosi_2arr;
+ rx_phy_siso_2arr : OUT t_unb1_board_back_siso_2arr
);
-END unb_back_reorder;
+END unb1_board_back_reorder;
-ARCHITECTURE rtl OF unb_back_reorder IS
+ARCHITECTURE rtl OF unb1_board_back_reorder IS
BEGIN
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
index a4e9268415367352e2d8c079d16d1ae907342bb6..38fbf987131caa782d8f7eef82819ab47ea12cab 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
@@ -40,31 +40,31 @@ USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE work.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
-ENTITY unb_back_select IS
+ENTITY unb1_board_back_select IS
PORT (
- bck_id : IN STD_LOGIC_VECTOR(c_unb_nof_uniboard_w-1 DOWNTO 0);
+ bck_id : IN STD_LOGIC_VECTOR(c_unb1_board_nof_uniboard_w-1 DOWNTO 0);
clk : IN STD_LOGIC;
-- usr side interface
- tx_usr_sosi_2arr : IN t_unb_back_sosi_2arr;
- tx_usr_siso_2arr : OUT t_unb_back_siso_2arr;
+ tx_usr_sosi_2arr : IN t_unb1_board_back_sosi_2arr;
+ tx_usr_siso_2arr : OUT t_unb1_board_back_siso_2arr;
- rx_usr_sosi_2arr : OUT t_unb_back_sosi_2arr;
- rx_usr_siso_2arr : IN t_unb_back_siso_2arr;
+ rx_usr_sosi_2arr : OUT t_unb1_board_back_sosi_2arr;
+ rx_usr_siso_2arr : IN t_unb1_board_back_siso_2arr;
-- phy side interface
- tx_phy_sosi_2arr : OUT t_unb_back_sosi_2arr;
- tx_phy_siso_2arr : IN t_unb_back_siso_2arr;
+ tx_phy_sosi_2arr : OUT t_unb1_board_back_sosi_2arr;
+ tx_phy_siso_2arr : IN t_unb1_board_back_siso_2arr;
- rx_phy_sosi_2arr : IN t_unb_back_sosi_2arr;
- rx_phy_siso_2arr : OUT t_unb_back_siso_2arr
+ rx_phy_sosi_2arr : IN t_unb1_board_back_sosi_2arr;
+ rx_phy_siso_2arr : OUT t_unb1_board_back_siso_2arr
);
-END unb_back_select;
+END unb1_board_back_select;
-ARCHITECTURE rtl OF unb_back_select IS
+ARCHITECTURE rtl OF unb1_board_back_select IS
BEGIN
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
index eeceb6ca3420a3828083a706b2f1ff0ad7e786b0..54da98acc643de3f3f9840ea7ec4b1467f3c33ab 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
@@ -22,8 +22,8 @@
-- Purpose: Instantiate uthernet TX and/or RX terminals for UniBoard back
-- Description:
--- Remark: This file is identical to unb_mesh_terminals.vhd except for the
--- SOSI entity I/O types and the monitor outputs.
+-- Remark: This file is identical to unb1_board_mesh_uth_terminals_bidir.vhd
+-- except for the SOSI entity I/O types and the monitor outputs.
LIBRARY IEEE, common_lib, dp_lib, uth_lib;
USE IEEE.std_logic_1164.ALL;
@@ -31,10 +31,10 @@ USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.dp_packet_pkg.ALL;
-USE work.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
USE uth_lib.uth_pkg.ALL;
-ENTITY unb_back_terminals IS
+ENTITY unb1_board_back_terminals IS
GENERIC (
-- User
g_usr_nof_streams : NATURAL := 4; -- number of user streams per bus
@@ -62,30 +62,30 @@ ENTITY unb_back_terminals IS
dp_clk : IN STD_LOGIC;
-- User
- tx_dp_sosi_2arr : IN t_unb_back_sosi_2arr;
- tx_dp_siso_2arr : OUT t_unb_back_siso_2arr;
+ tx_dp_sosi_2arr : IN t_unb1_board_back_sosi_2arr;
+ tx_dp_siso_2arr : OUT t_unb1_board_back_siso_2arr;
- rx_dp_sosi_2arr : OUT t_unb_back_sosi_2arr;
- rx_dp_siso_2arr : IN t_unb_back_siso_2arr;
+ rx_dp_sosi_2arr : OUT t_unb1_board_back_sosi_2arr;
+ rx_dp_siso_2arr : IN t_unb1_board_back_siso_2arr;
-- Phy
- tx_uth_sosi_2arr : OUT t_unb_back_sosi_2arr;
- tx_uth_siso_2arr : IN t_unb_back_siso_2arr;
+ tx_uth_sosi_2arr : OUT t_unb1_board_back_sosi_2arr;
+ tx_uth_siso_2arr : IN t_unb1_board_back_siso_2arr;
- rx_uth_sosi_2arr : IN t_unb_back_sosi_2arr;
- rx_uth_siso_2arr : OUT t_unb_back_siso_2arr
+ rx_uth_sosi_2arr : IN t_unb1_board_back_sosi_2arr;
+ rx_uth_siso_2arr : OUT t_unb1_board_back_siso_2arr
);
-END unb_back_terminals;
+END unb1_board_back_terminals;
-ARCHITECTURE str OF unb_back_terminals IS
+ARCHITECTURE str OF unb1_board_back_terminals IS
CONSTANT c_tx_mux_mode : NATURAL := 1; -- can use 0 for non-blocking tx mux in dp_distribute or use 1 to preserve input order for tx
CONSTANT c_rx_mux_mode : NATURAL := 0; -- must use 0 for non-blocking rx mux in dp_distribute (can not use 1 to preserve input order for rx, because some rx frames may go lost)
BEGIN
- gen_bus : FOR I IN 0 TO c_unb_tr_back.nof_bus-1 GENERATE
+ gen_bus : FOR I IN 0 TO c_unb1_board_tr_back.nof_bus-1 GENERATE
u_uth_terminal_bidir : ENTITY uth_lib.uth_terminal_bidir
GENERIC MAP (
-- User
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
index 518ec38c548da1a7d71c2c4e73046a1605a0a82c..23bbdbb46ebc7791d318961ab6aa3bb706b5f44e 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
@@ -19,18 +19,18 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, unb_common_lib, common_lib;
+LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
-USE unb_common_lib.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
-ENTITY unb_front_io IS
+ENTITY unb1_board_front_io IS
GENERIC (
g_nof_xaui : NATURAL
);
PORT (
- xaui_tx_arr : IN t_unb_xaui_sl_2arr(g_nof_xaui-1 DOWNTO 0);
- xaui_rx_arr : OUT t_unb_xaui_sl_2arr(g_nof_xaui-1 DOWNTO 0);
+ xaui_tx_arr : IN t_unb1_board_xaui_sl_2arr(g_nof_xaui-1 DOWNTO 0);
+ xaui_rx_arr : OUT t_unb1_board_xaui_sl_2arr(g_nof_xaui-1 DOWNTO 0);
mdio_mdc_arr : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
mdio_mdat_in_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
@@ -38,28 +38,28 @@ ENTITY unb_front_io IS
-- Serial I/O
-- . hard IP transceivers busses
- SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0);
- SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0);
- SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0);
- SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_xaui.bus_w-1 DOWNTO 0);
+ SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_xaui.bus_w-1 DOWNTO 0);
+ SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_xaui.bus_w-1 DOWNTO 0);
+ SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-- . soft IP transceivers bus (typically not used on UniBoard)
- SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0);
- SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_xaui.bus_w-1 DOWNTO 0);
+ SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0);
- SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0);
- SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0);
- SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0)
+ SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0)
);
-END unb_front_io;
+END unb1_board_front_io;
-ARCHITECTURE str OF unb_front_io IS
+ARCHITECTURE str OF unb1_board_front_io IS
-- help signals so we can iterate through buses
- SIGNAL si_fn_tx_arr : t_unb_xaui_sl_2arr(c_unb_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
- SIGNAL si_fn_rx_arr : t_unb_xaui_sl_2arr(c_unb_tr_xaui.bus_w-1 DOWNTO 0);
+ SIGNAL si_fn_tx_arr : t_unb1_board_xaui_sl_2arr(c_unb1_board_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+ SIGNAL si_fn_rx_arr : t_unb1_board_xaui_sl_2arr(c_unb1_board_tr_xaui.bus_w-1 DOWNTO 0);
BEGIN
@@ -83,49 +83,49 @@ BEGIN
gen_iobuf_0 : IF g_nof_xaui>0 GENERATE
u_iobuf_0 : ENTITY common_lib.common_inout
PORT MAP (
- dat_inout => SI_FN_0_CNTRL(c_unb_ci.tr.cntrl_mdio_id),
+ dat_inout => SI_FN_0_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
dat_in_from_line => mdio_mdat_in_arr(0),
dat_out_to_line => '0',
dat_out_en => mdio_mdat_oen_arr(0)
);
- SI_FN_0_CNTRL(c_unb_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(0);
+ SI_FN_0_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(0);
END GENERATE;
gen_iobuf_1 : IF g_nof_xaui>1 GENERATE
u_iobuf_1 : ENTITY common_lib.common_inout
PORT MAP (
- dat_inout => SI_FN_1_CNTRL(c_unb_ci.tr.cntrl_mdio_id),
+ dat_inout => SI_FN_1_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
dat_in_from_line => mdio_mdat_in_arr(1),
dat_out_to_line => '0',
dat_out_en => mdio_mdat_oen_arr(1)
);
- SI_FN_1_CNTRL(c_unb_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(1);
+ SI_FN_1_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(1);
END GENERATE;
gen_iobuf_2 : IF g_nof_xaui>2 GENERATE
u_iobuf_2 : ENTITY common_lib.common_inout
PORT MAP (
- dat_inout => SI_FN_2_CNTRL(c_unb_ci.tr.cntrl_mdio_id),
+ dat_inout => SI_FN_2_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
dat_in_from_line => mdio_mdat_in_arr(2),
dat_out_to_line => '0',
dat_out_en => mdio_mdat_oen_arr(2)
);
- SI_FN_2_CNTRL(c_unb_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(2);
+ SI_FN_2_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(2);
END GENERATE;
gen_iobuf_3 : IF g_nof_xaui>3 GENERATE
u_iobuf_3 : ENTITY common_lib.common_inout
PORT MAP (
- dat_inout => SI_FN_3_CNTRL(c_unb_ci.tr.cntrl_mdio_id),
+ dat_inout => SI_FN_3_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
dat_in_from_line => mdio_mdat_in_arr(3),
dat_out_to_line => '0',
dat_out_en => mdio_mdat_oen_arr(3)
);
- SI_FN_3_CNTRL(c_unb_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(3);
+ SI_FN_3_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(3);
END GENERATE;
END;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
index 896961461126c4341fba05f3a0a34ea4109dddc5..d50283090f1c60c5f6d67ef14743a4833381e534 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
@@ -21,16 +21,16 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-USE work.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
-ENTITY unb_mesh_io IS
+ENTITY unb1_board_mesh_io IS
GENERIC (
g_bus_w : NATURAL := 3 -- use 4 to include the CMU transceives at port (3) else use 3 to only use the HW transceivers on port (2:0)
);
PORT (
- tx_serial_2arr : IN t_unb_mesh_sl_2arr := (OTHERS=>(OTHERS=>'0'));
- rx_serial_2arr : OUT t_unb_mesh_sl_2arr;
+ tx_serial_2arr : IN t_unb1_board_mesh_sl_2arr := (OTHERS=>(OTHERS=>'0'));
+ rx_serial_2arr : OUT t_unb1_board_mesh_sl_2arr;
-- Serial I/O
FN_BN_0_TX : OUT STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0);
@@ -42,10 +42,10 @@ ENTITY unb_mesh_io IS
FN_BN_3_TX : OUT STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0);
FN_BN_3_RX : IN STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0) := (OTHERS=>'0')
);
-END unb_mesh_io;
+END unb1_board_mesh_io;
-ARCHITECTURE str OF unb_mesh_io IS
+ARCHITECTURE str OF unb1_board_mesh_io IS
BEGIN
-- Map the serial streams to the mesh
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
index 946257f12ab8c96efab15adad9024f2827815625..97a852608dd4c05e2e6a54c297280a60d626d82c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
@@ -23,9 +23,9 @@
-- Purpose: Compensate for the mesh reorder between FN and BN on UniBoard
-- Description:
--
--- 0) The unb_mesh_reorder_* reorders combinatorially to preserve the RL.
--- 1) The unb_mesh_reorder_tx maps the usr bus index for each node chip_id on
--- the phy bus, so:
+-- 0) The unb1_board_mesh_reorder_* reorders combinatorially to preserve the RL.
+-- 1) The unb1_board_mesh_reorder_tx maps the usr bus index for each node
+-- chip_id on the phy bus, so:
--
-- usr phy phy usr phy phy
-- FN bus bus mesh bus BN BN bus bus mesh bus FN
@@ -49,8 +49,8 @@
-- 3 2 2 -----> 0 2 3 2 2 -----> 3 2
-- 3 3 3 -----> 0 3 3 3 0 -----> 3 3
--
--- 2) The unb_mesh_reorder_rx maps the phy bus index for each node chip_id on
--- the usr bus, so:
+-- 2) The unb1_board_mesh_reorder_rx maps the phy bus index for each node
+-- chip_id on the usr bus, so:
--
-- phy usr phy phy usr phy
-- FN bus bus mesh bus BN BN bus bus mesh bus FN
@@ -86,8 +86,8 @@
-- BN2 2,3,1,0 3,2,0,1 -- ! different for Tx and Rx
-- BN3 1,0,2,3 3,0,2,1 -- ! different for Tx and Rx
--
--- 4) The UniBoard mesh is modelled by unb_mesh_model. In summary the UniBoard
--- mesh is wired as:
+-- 4) The UniBoard mesh is modelled by unb1_board_mesh_model. In summary the
+-- UniBoard mesh is wired as:
--
-- phy phy phy phy
-- FN bus mesh bus BN BN bus mesh bus FN
@@ -112,61 +112,63 @@
-- 3 3 ------ 0 3 3 3 ------ 2 1
--
-- Remark:
--- . The indexing of the t_unb_mesh_*_2arr is (node id 0,1,2,3)(tr lane 3,2,1,0)
--- . Use fixed c_unb_tr.nof_bus=4, because the nodes connect always to 4 other
--- nodes accross the UniBoard mesh.
--- . Use fixed c_unb_tr.bus_w=4 transceivers per node-to-node bus, because the
--- UniBoard mesh does have 4 transceiver lanes per bus. It is possible to
--- use less then 4 transceivers per bus in the mesh. Typically use <= 3 via
--- index 2,1,0 to only use the 12 full-featured transceivers (so without the
--- 4 less-featured CMU ones).
+-- . The indexing of the t_unb1_board_mesh_*_2arr is (node id 0,1,2,3)(tr lane
+-- 3,2,1,0)
+-- . Use fixed c_unb1_board_tr.nof_bus=4, because the nodes connect always to
+-- 4 other nodes accross the UniBoard mesh.
+-- . Use fixed c_unb1_board_tr.bus_w=4 transceivers per node-to-node bus,
+-- because the UniBoard mesh does have 4 transceiver lanes per bus. It is
+-- possible to use less then 4 transceivers per bus in the mesh. Typically
+-- use <= 3 via index 2,1,0 to only use the 12 full-featured transceivers
+-- (so without the 4 less-featured CMU ones).
-- . Both the SOSI and SISO signals are supported, because the transceiver PHY
-- (e.g. tr_nonbonded) does support SISO.
-- . For the SOSI and SISO interfaces there is also a corresponding UniBoard
--- mesh model (unb_mesh_model_sosi and unb_mesh_model_siso). Therefor there
--- is no need for an unb_mesh_reorder_bidir at serial std_logic level.
--- The serial std_logic level can be simulated, but that requires using the
--- TR PHY module (e.g. tr_nonbonded) to convert between SOSI/SISO and serial.
--- Hence for simulating the UniBoard mesh at serial TR PHY level there is
--- the serial UniBoard mesh model unb_mesh_model_sl.
+-- mesh model (unb1_board_mesh_model_sosi and unb1_board_mesh_model_siso).
+-- Therefor there is no need for an unb1_board_mesh_reorder_bidir at serial
+-- std_logic level. The serial std_logic level can be simulated, but that
+-- requires using the TR PHY module (e.g. tr_nonbonded) to convert between
+-- SOSI/SISO and serial. Hence for simulating the UniBoard mesh at serial
+-- TR PHY level there is the serial UniBoard mesh model
+-- unb1_board_mesh_model_sl.
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE work.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
-ENTITY unb_mesh_reorder_bidir IS
+ENTITY unb1_board_mesh_reorder_bidir IS
GENERIC (
- g_node_type : t_e_unb_node := e_any; -- or e_fn, or e_bn
+ g_node_type : t_e_unb1_board_node := e_any; -- or e_fn, or e_bn
g_reorder : BOOLEAN := TRUE
);
PORT (
- chip_id : IN STD_LOGIC_VECTOR(c_unb_aux.chip_id_w-1 DOWNTO 0); -- [2:0]
+ chip_id : IN STD_LOGIC_VECTOR(c_unb1_board_aux.chip_id_w-1 DOWNTO 0); -- [2:0]
-- Transmit clock domain --> output data to node across the mesh
tx_clk : IN STD_LOGIC;
- tx_usr_sosi_2arr : IN t_unb_mesh_sosi_2arr; -- user side
- tx_usr_siso_2arr : OUT t_unb_mesh_siso_2arr;
- tx_phy_sosi_2arr : OUT t_unb_mesh_sosi_2arr; -- phy side
- tx_phy_siso_2arr : IN t_unb_mesh_siso_2arr := c_unb_mesh_siso_2arr_rst;
+ tx_usr_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr; -- user side
+ tx_usr_siso_2arr : OUT t_unb1_board_mesh_siso_2arr;
+ tx_phy_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr; -- phy side
+ tx_phy_siso_2arr : IN t_unb1_board_mesh_siso_2arr := c_unb1_board_mesh_siso_2arr_rst;
-- Receive clock domain --> input data from node across the mesh
rx_clk : IN STD_LOGIC;
- rx_phy_sosi_2arr : IN t_unb_mesh_sosi_2arr; -- phy side
- rx_phy_siso_2arr : OUT t_unb_mesh_siso_2arr;
- rx_usr_sosi_2arr : OUT t_unb_mesh_sosi_2arr; -- user side
- rx_usr_siso_2arr : IN t_unb_mesh_siso_2arr := c_unb_mesh_siso_2arr_rst
+ rx_phy_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr; -- phy side
+ rx_phy_siso_2arr : OUT t_unb1_board_mesh_siso_2arr;
+ rx_usr_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr; -- user side
+ rx_usr_siso_2arr : IN t_unb1_board_mesh_siso_2arr := c_unb1_board_mesh_siso_2arr_rst
);
-END unb_mesh_reorder_bidir;
+END unb1_board_mesh_reorder_bidir;
-ARCHITECTURE str OF unb_mesh_reorder_bidir IS
+ARCHITECTURE str OF unb1_board_mesh_reorder_bidir IS
BEGIN
- u_tx : ENTITY work.unb_mesh_reorder_tx
+ u_tx : ENTITY work.unb1_board_mesh_reorder_tx
GENERIC MAP (
g_node_type => g_node_type,
g_reorder => g_reorder
@@ -180,7 +182,7 @@ BEGIN
rx_phy_siso_2arr => rx_phy_siso_2arr
);
- u_rx : ENTITY work.unb_mesh_reorder_rx
+ u_rx : ENTITY work.unb1_board_mesh_reorder_rx
GENERIC MAP (
g_node_type => g_node_type,
g_reorder => g_reorder
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
index bea2c182d94f8acae30cbe8f5000b8a205859f4b..4e7e7c322d87e376c0c4bff5d5cb7c8c645d824d 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
-- Purpose: Compensate for the mesh reorder between FN and BN on UniBoard
--- Description: See unb_mesh_reorder_bidir.vhd
--- This unb_mesh_reorder_rx performs mesh reordering for user receive, so
--- for the rx_usr_sosi and the tx_usr_siso. Note that these belong to
+-- Description: See unb1_board_mesh_reorder_bidir.vhd
+-- This unb1_board_mesh_reorder_rx performs mesh reordering for user receive,
+-- so for the rx_usr_sosi and the tx_usr_siso. Note that these belong to
-- different streams. The rx_usr_sosi carries the user Rx data input stream
-- and the tx_usr_siso belongs to the user Tx data stream and carries the
-- input flow control for the Tx data stream.
@@ -35,33 +35,33 @@ USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE work.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
-ENTITY unb_mesh_reorder_rx IS
+ENTITY unb1_board_mesh_reorder_rx IS
GENERIC (
- g_node_type : t_e_unb_node := e_any;
+ g_node_type : t_e_unb1_board_node := e_any;
g_reorder : BOOLEAN := TRUE
);
PORT (
- chip_id : IN STD_LOGIC_VECTOR(c_unb_aux.chip_id_w-1 DOWNTO 0); -- [2:0]
+ chip_id : IN STD_LOGIC_VECTOR(c_unb1_board_aux.chip_id_w-1 DOWNTO 0); -- [2:0]
clk : IN STD_LOGIC;
- rx_phy_sosi_2arr : IN t_unb_mesh_sosi_2arr; -- _2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
- tx_phy_siso_2arr : IN t_unb_mesh_siso_2arr := c_unb_mesh_siso_2arr_rst;
- rx_usr_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
- tx_usr_siso_2arr : OUT t_unb_mesh_siso_2arr
+ rx_phy_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr; -- _2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
+ tx_phy_siso_2arr : IN t_unb1_board_mesh_siso_2arr := c_unb1_board_mesh_siso_2arr_rst;
+ rx_usr_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr;
+ tx_usr_siso_2arr : OUT t_unb1_board_mesh_siso_2arr
);
-END unb_mesh_reorder_rx;
+END unb1_board_mesh_reorder_rx;
-ARCHITECTURE rtl OF unb_mesh_reorder_rx IS
+ARCHITECTURE rtl OF unb1_board_mesh_reorder_rx IS
SIGNAL chip_id_i : STD_LOGIC_VECTOR(chip_id'RANGE);
BEGIN
-- force chip_id(2) to '0' or '1' to reduce the case options in p_comb if the design will run only on a FN or only on a BN
- chip_id_i <= func_unb_chip_id(chip_id, g_node_type);
+ chip_id_i <= func_unb1_board_chip_id(chip_id, g_node_type);
p_comb : PROCESS(chip_id_i, rx_phy_sosi_2arr, tx_phy_siso_2arr)
BEGIN
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
index 3a5cd19c4fd4a9387794931e1149f6067f321502..b6754d9d7f871bf94099ef64582418ea1d082e84 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
-- Purpose: Compensate for the mesh reorder between FN and BN on UniBoard
--- Description: See unb_mesh_reorder_bidir.vhd
--- This unb_mesh_reorder_tx performs mesh reordering for user transmit, so
--- for the tx_usr_sosi and the rx_usr_siso. Note that these belong to
+-- Description: See unb1_board_mesh_reorder_bidir.vhd
+-- This unb1_board_mesh_reorder_tx performs mesh reordering for user transmit,
+-- so for the tx_usr_sosi and the rx_usr_siso. Note that these belong to
-- different streams. The tx_usr_sosi carries the user Tx data output stream
-- and the rx_usr_siso belongs to the user Rx data stream and carries the
-- output flow control for the Rx data stream.
@@ -35,26 +35,26 @@ USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE work.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
-ENTITY unb_mesh_reorder_tx IS
+ENTITY unb1_board_mesh_reorder_tx IS
GENERIC (
- g_node_type : t_e_unb_node := e_any;
+ g_node_type : t_e_unb1_board_node := e_any;
g_reorder : BOOLEAN := TRUE
);
PORT (
- chip_id : IN STD_LOGIC_VECTOR(c_unb_aux.chip_id_w-1 DOWNTO 0); -- [2:0]
+ chip_id : IN STD_LOGIC_VECTOR(c_unb1_board_aux.chip_id_w-1 DOWNTO 0); -- [2:0]
clk : IN STD_LOGIC;
- tx_usr_sosi_2arr : IN t_unb_mesh_sosi_2arr; -- _2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
- rx_usr_siso_2arr : IN t_unb_mesh_siso_2arr := c_unb_mesh_siso_2arr_rst;
- tx_phy_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
- rx_phy_siso_2arr : OUT t_unb_mesh_siso_2arr
+ tx_usr_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr; -- _2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
+ rx_usr_siso_2arr : IN t_unb1_board_mesh_siso_2arr := c_unb1_board_mesh_siso_2arr_rst;
+ tx_phy_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr;
+ rx_phy_siso_2arr : OUT t_unb1_board_mesh_siso_2arr
);
-END unb_mesh_reorder_tx;
+END unb1_board_mesh_reorder_tx;
-ARCHITECTURE rtl OF unb_mesh_reorder_tx IS
+ARCHITECTURE rtl OF unb1_board_mesh_reorder_tx IS
SIGNAL chip_id_reg : STD_LOGIC_VECTOR(chip_id'RANGE);
SIGNAL chip_id_i : STD_LOGIC_VECTOR(chip_id'RANGE);
@@ -79,7 +79,7 @@ BEGIN
);
-- force chip_id(2) to '0' or '1' to reduce the case options in p_comb if the design will run only on a FN or only on a BN
- chip_id_i <= func_unb_chip_id(chip_id_reg, g_node_type);
+ chip_id_i <= func_unb1_board_chip_id(chip_id_reg, g_node_type);
p_comb : PROCESS(chip_id_i, tx_usr_sosi_2arr, rx_usr_siso_2arr)
BEGIN
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
index b94a59fb1f41d111f2aa42c5c5bf7d73fbf05109..5640edfd7752ceda9312a3579f705cea54f29102 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
@@ -22,8 +22,8 @@
-- Purpose: Instantiate uthernet TX and/or RX terminals for UniBoard mesh
-- Description:
--- Remark: This file is identical to unb_back_terminals.vhd except for the
--- SOSI entity I/O types and the monitor outputs.
+-- Remark: This file is identical to unb1_board_back_terminals.vhd except for
+-- the SOSI entity I/O types and the monitor outputs.
LIBRARY IEEE, common_lib, dp_lib, uth_lib;
USE IEEE.std_logic_1164.ALL;
@@ -31,10 +31,10 @@ USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.dp_packet_pkg.ALL;
-USE work.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
USE uth_lib.uth_pkg.ALL;
-ENTITY unb_mesh_terminals IS
+ENTITY unb1_board_mesh_terminals IS
GENERIC (
-- User
g_usr_nof_streams : NATURAL := 4; -- number of user streams per bus
@@ -65,34 +65,34 @@ ENTITY unb_mesh_terminals IS
dp_clk : IN STD_LOGIC;
-- User
- tx_dp_sosi_2arr : IN t_unb_mesh_sosi_2arr;
- tx_dp_siso_2arr : OUT t_unb_mesh_siso_2arr;
+ tx_dp_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr;
+ tx_dp_siso_2arr : OUT t_unb1_board_mesh_siso_2arr;
- rx_dp_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
- rx_dp_siso_2arr : IN t_unb_mesh_siso_2arr;
+ rx_dp_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr;
+ rx_dp_siso_2arr : IN t_unb1_board_mesh_siso_2arr;
-- Phy
- tx_uth_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
- tx_uth_siso_2arr : IN t_unb_mesh_siso_2arr;
+ tx_uth_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr;
+ tx_uth_siso_2arr : IN t_unb1_board_mesh_siso_2arr;
- rx_uth_sosi_2arr : IN t_unb_mesh_sosi_2arr;
- rx_uth_siso_2arr : OUT t_unb_mesh_siso_2arr;
+ rx_uth_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr;
+ rx_uth_siso_2arr : OUT t_unb1_board_mesh_siso_2arr;
-- Monitoring
- rx_mon_pkt_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
- rx_mon_dist_sosi_2arr : OUT t_unb_mesh_sosi_2arr
+ rx_mon_pkt_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr;
+ rx_mon_dist_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr
);
-END unb_mesh_terminals;
+END unb1_board_mesh_terminals;
-ARCHITECTURE str OF unb_mesh_terminals IS
+ARCHITECTURE str OF unb1_board_mesh_terminals IS
CONSTANT c_tx_mux_mode : NATURAL := 0; -- can use 0 for non-blocking tx mux in dp_distribute or use 1 to preserve input order for tx
CONSTANT c_rx_mux_mode : NATURAL := 0; -- must use 0 for non-blocking rx mux in dp_distribute (can not use 1 to preserve input order for rx, because some rx frames may go lost)
BEGIN
- gen_uth_terminal_bidir : FOR I IN 0 TO c_unb_tr_mesh.nof_bus-1 GENERATE
+ gen_uth_terminal_bidir : FOR I IN 0 TO c_unb1_board_tr_mesh.nof_bus-1 GENERATE
u_uth_terminal_bidir : ENTITY uth_lib.uth_terminal_bidir
GENERIC MAP (
-- User
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
index 57f445fcd91768090277d0bec313bb8c9a87ef24..7edbdb480b2ef1fa3b0582ddb4c08b712b528a0d 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
@@ -27,9 +27,9 @@
-- As one of the global UniBoard numbers will be itself, the streams with that
-- particaular array index will be looped back (user TX to user RX).
-- Remark:
--- Main differences with unb_mesh_terminals:
+-- Main differences with unb1_board_terminals_mesh:
-- - UniBoard-indexing instead of node indexing;
--- - One array index (mathcin board ID) is sourced by hosting node.
+-- - One array index (matching board ID) is sourced by hosting node.
-- - Always use the GX in both directions between the BN, so no need for
-- g_use_tx and g_use_rx because they are both TRUE.
@@ -38,19 +38,19 @@ USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE work.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.dp_packet_pkg.ALL;
USE uth_lib.uth_pkg.ALL;
USE tr_nonbonded_lib.tr_nonbonded_pkg.ALL;
-ENTITY unb_terminals_back IS
+ENTITY unb1_board_terminals_back IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 0;
-- System
- g_nof_bus : NATURAL := c_unb_nof_uniboard; -- = 4 Uniboard in subrack, this UniBoard and 3 other UniBoards, so each UniBoard can be indexed by logical index 3:0
+ g_nof_bus : NATURAL := c_unb1_board_nof_uniboard; -- = 4 Uniboard in subrack, this UniBoard and 3 other UniBoards, so each UniBoard can be indexed by logical index 3:0
-- User
g_usr_use_complex : BOOLEAN := FALSE; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
g_usr_data_w : NATURAL := 32;
@@ -71,7 +71,7 @@ ENTITY unb_terminals_back IS
g_rx_timeout_w : NATURAL := 0 -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
);
PORT (
- bck_id : IN STD_LOGIC_VECTOR(c_unb_nof_uniboard_w-1 DOWNTO 0); -- [7:3]; only [1:0] required to index boards 3:0 in a subrack
+ bck_id : IN STD_LOGIC_VECTOR(c_unb1_board_nof_uniboard_w-1 DOWNTO 0); -- [7:3]; only [1:0] required to index boards 3:0 in a subrack
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
@@ -81,14 +81,14 @@ ENTITY unb_terminals_back IS
cal_clk : IN STD_LOGIC;
-- User interface
- tx_usr_siso_2arr : OUT t_unb_back_siso_2arr;
- tx_usr_sosi_2arr : IN t_unb_back_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
- rx_usr_siso_2arr : IN t_unb_back_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rdy));
- rx_usr_sosi_2arr : OUT t_unb_back_sosi_2arr;
+ tx_usr_siso_2arr : OUT t_unb1_board_back_siso_2arr;
+ tx_usr_sosi_2arr : IN t_unb1_board_back_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+ rx_usr_siso_2arr : IN t_unb1_board_back_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rdy));
+ rx_usr_sosi_2arr : OUT t_unb1_board_back_sosi_2arr;
-- Serial (tr_nonbonded)
- tx_serial_2arr : OUT t_unb_back_sl_2arr;
- rx_serial_2arr : IN t_unb_back_sl_2arr := (OTHERS=>(OTHERS=>'0'));
+ tx_serial_2arr : OUT t_unb1_board_back_sl_2arr;
+ rx_serial_2arr : IN t_unb1_board_back_sl_2arr := (OTHERS=>(OTHERS=>'0'));
-- MM Control
-- . tr_nonbonded
@@ -98,10 +98,10 @@ ENTITY unb_terminals_back IS
reg_diagnostics_miso : OUT t_mem_miso
);
-END unb_terminals_back;
+END unb1_board_terminals_back;
-ARCHITECTURE str OF unb_terminals_back IS
+ARCHITECTURE str OF unb1_board_terminals_back IS
-- DP/UTH packet
CONSTANT c_packet_data_w : NATURAL := g_usr_data_w; -- = 32, packet data width for DP packet and for UTH packet, must be >= g_usr_data_w
@@ -110,25 +110,25 @@ ARCHITECTURE str OF unb_terminals_back IS
CONSTANT c_nof_bus_serial : NATURAL := g_nof_bus-1; -- Indexing 2:0, only the 'other' UniBoards can be indexed
CONSTANT c_nof_gx : NATURAL := c_nof_bus_serial*g_phy_nof_serial;
- -- unb_back_select
- SIGNAL tx_sel_siso_2arr : t_unb_back_siso_2arr;
- SIGNAL tx_sel_sosi_2arr : t_unb_back_sosi_2arr;
+ -- unb1_board_back_select
+ SIGNAL tx_sel_siso_2arr : t_unb1_board_back_siso_2arr;
+ SIGNAL tx_sel_sosi_2arr : t_unb1_board_back_sosi_2arr;
- SIGNAL rx_sel_siso_2arr : t_unb_back_siso_2arr;
- SIGNAL rx_sel_sosi_2arr : t_unb_back_sosi_2arr;
+ SIGNAL rx_sel_siso_2arr : t_unb1_board_back_siso_2arr;
+ SIGNAL rx_sel_sosi_2arr : t_unb1_board_back_sosi_2arr;
- -- unb_back_reorder
- SIGNAL tx_term_siso_2arr : t_unb_back_siso_2arr;
- SIGNAL tx_term_sosi_2arr : t_unb_back_sosi_2arr;
+ -- unb1_board_back_reorder
+ SIGNAL tx_term_siso_2arr : t_unb1_board_back_siso_2arr;
+ SIGNAL tx_term_sosi_2arr : t_unb1_board_back_sosi_2arr;
- SIGNAL rx_term_siso_2arr : t_unb_back_siso_2arr;
- SIGNAL rx_term_sosi_2arr : t_unb_back_sosi_2arr;
+ SIGNAL rx_term_siso_2arr : t_unb1_board_back_siso_2arr;
+ SIGNAL rx_term_sosi_2arr : t_unb1_board_back_sosi_2arr;
- -- unb_back_terminals
- SIGNAL tx_phy_siso_2arr : t_unb_back_siso_2arr;
- SIGNAL tx_phy_sosi_2arr : t_unb_back_sosi_2arr;
- SIGNAL rx_phy_siso_2arr : t_unb_back_siso_2arr;
- SIGNAL rx_phy_sosi_2arr : t_unb_back_sosi_2arr;
+ -- unb1_board_back_terminals
+ SIGNAL tx_phy_siso_2arr : t_unb1_board_back_siso_2arr;
+ SIGNAL tx_phy_sosi_2arr : t_unb1_board_back_sosi_2arr;
+ SIGNAL rx_phy_siso_2arr : t_unb1_board_back_siso_2arr;
+ SIGNAL rx_phy_sosi_2arr : t_unb1_board_back_sosi_2arr;
-- mms_tr_nonbonded
SIGNAL tx_phy_siso_arr : t_dp_siso_arr(c_nof_gx-1 DOWNTO 0);
@@ -141,7 +141,7 @@ ARCHITECTURE str OF unb_terminals_back IS
BEGIN
- u_back_select: ENTITY work.unb_back_select
+ u_unb1_board_back_select: ENTITY work.unb1_board_back_select
PORT MAP (
bck_id => bck_id,
clk => dp_clk,
@@ -161,7 +161,7 @@ BEGIN
rx_phy_siso_2arr => rx_sel_siso_2arr
);
- u_back_reorder : ENTITY work.unb_back_reorder
+ u_unb1_board_back_reorder : ENTITY work.unb1_board_back_reorder
PORT MAP (
bck_id => bck_id,
clk => dp_clk,
@@ -181,7 +181,7 @@ BEGIN
rx_phy_siso_2arr => rx_term_siso_2arr
);
- u_back_terminals : ENTITY work.unb_back_terminals
+ u_unb1_board_back_uth_terminals_bidir : ENTITY work.unb1_board_back_uth_terminals_bidir
GENERIC MAP (
-- User
g_usr_nof_streams => g_usr_nof_streams,
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
index 0bca78d269a534c7d46dbec47a6117afbd3eeb91..61ef25d28f5c64a7efb6ff8c061b5a83a1231f02 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
@@ -26,7 +26,7 @@
-- Data flow:
-- * g_use_tx=TRUE
-- tx_usr_sosi_2arr--> uth_terminal_tx
--- tx_term_sosi_2arr--> unb_mesh_reorder_tx
+-- tx_term_sosi_2arr--> unb1_board_mesh_reorder_tx
-- tx_phy_sosi_2arr--> map(I)(J) to (I*g_phy_nof_serial + J)
-- tx_phy_sosi_arr--> mms_tr_nonbonded
-- tx_serial_arr--> map(I*g_phy_nof_serial + J) to (I)(J)
@@ -35,18 +35,18 @@
-- rx_serial_2arr--> map(I)(J) to (I*g_phy_nof_serial + J)
-- rx_serial_arr--> mms_tr_nonbonded
-- rx_phy_sosi_arr--> map(I*g_phy_nof_serial + J) to (I)(J)
--- rx_phy_sosi_2arr--> unb_mesh_reorder_rx
+-- rx_phy_sosi_2arr--> unb1_board_mesh_reorder_rx
-- rx_term_sosi_2arr--> uth_terminal_rx
-- -->rx_usr_sosi_2arr
--
-- Remark:
-- . The number of user input streams is defined by the width of the mesh bus,
--- so g_usr_nof_streams = c_unb_tr.bus_w = 4 to be able to use
--- t_unb_mesh_sosi_2arr.
+-- so g_usr_nof_streams = c_unb1_board_tr.bus_w = 4 to be able to use
+-- t_unb1_board_mesh_sosi_2arr.
-- . The mesh reorder logic is always instantiated, but when g_phy_ena_reorder
-- = FALSE then no reodering is done. In simulation the g_phy_ena_reorder
--- must match the g_reorder setting for unb_mesh_model_*.vhd. On hardware
--- use the default g_phy_ena_reorder = TRUE.
+-- must match the g_reorder setting for unb1_board_mesh_model_*.vhd. On
+-- hardware use the default g_phy_ena_reorder = TRUE.
LIBRARY IEEE, common_lib, dp_lib, uth_lib, tr_nonbonded_lib, diag_lib;
@@ -54,19 +54,19 @@ USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE work.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.dp_packet_pkg.ALL;
USE uth_lib.uth_pkg.ALL;
USE tr_nonbonded_lib.tr_nonbonded_pkg.ALL;
-ENTITY unb_terminals_mesh IS
+ENTITY unb1_board_terminals_mesh IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 0;
-- System
- g_node_type : t_e_unb_node := e_any; -- or e_fn, or e_bn
+ g_node_type : t_e_unb1_board_node := e_any; -- or e_fn, or e_bn
g_nof_bus : NATURAL := 4; -- one bus to each of the 4 nodes on the other side of the mesh
-- User
g_usr_use_complex : BOOLEAN := FALSE; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
@@ -104,7 +104,7 @@ ENTITY unb_terminals_mesh IS
g_uth_typ_ofs : NATURAL := 256 -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
);
PORT (
- chip_id : IN STD_LOGIC_VECTOR(c_unb_aux.chip_id_w-1 DOWNTO 0) := (OTHERS=>'0'); -- [2:0]
+ chip_id : IN STD_LOGIC_VECTOR(c_unb1_board_aux.chip_id_w-1 DOWNTO 0) := (OTHERS=>'0'); -- [2:0]
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
@@ -115,14 +115,14 @@ ENTITY unb_terminals_mesh IS
cal_clk : IN STD_LOGIC;
-- User interface (4 nodes)(4 input streams)
- tx_usr_siso_2arr : OUT t_unb_mesh_siso_2arr;
- tx_usr_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst)); -- Tx
- rx_usr_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rdy));
- rx_usr_sosi_2arr : OUT t_unb_mesh_sosi_2arr; -- Rx
+ tx_usr_siso_2arr : OUT t_unb1_board_mesh_siso_2arr;
+ tx_usr_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst)); -- Tx
+ rx_usr_siso_2arr : IN t_unb1_board_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rdy));
+ rx_usr_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr; -- Rx
-- Serial (tr_nonbonded)
- tx_serial_2arr : OUT t_unb_mesh_sl_2arr; -- Tx
- rx_serial_2arr : IN t_unb_mesh_sl_2arr := (OTHERS=>(OTHERS=>'0')); -- Rx
+ tx_serial_2arr : OUT t_unb1_board_mesh_sl_2arr; -- Tx
+ rx_serial_2arr : IN t_unb1_board_mesh_sl_2arr := (OTHERS=>(OTHERS=>'0')); -- Rx
-- MM Control
-- . tr_nonbonded
@@ -135,10 +135,10 @@ ENTITY unb_terminals_mesh IS
ram_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_diag_data_buf_miso : OUT t_mem_miso
);
-END unb_terminals_mesh;
+END unb1_board_terminals_mesh;
-ARCHITECTURE str OF unb_terminals_mesh IS
+ARCHITECTURE str OF unb1_board_terminals_mesh IS
-- DP/UTH packet
CONSTANT c_packet_data_w : NATURAL := 32; -- fixed 32, packet data width for DP packet and for UTH packet, must be >= g_usr_data_w to avoid need for data packing
@@ -165,21 +165,21 @@ ARCHITECTURE str OF unb_terminals_mesh IS
c_packet_data_w);
-- uth terminals
- SIGNAL tx_term_siso_2arr : t_unb_mesh_siso_2arr;
- SIGNAL tx_term_sosi_2arr : t_unb_mesh_sosi_2arr; -- Tx
- SIGNAL rx_term_siso_2arr : t_unb_mesh_siso_2arr;
- SIGNAL rx_term_sosi_2arr : t_unb_mesh_sosi_2arr; -- Rx
+ SIGNAL tx_term_siso_2arr : t_unb1_board_mesh_siso_2arr;
+ SIGNAL tx_term_sosi_2arr : t_unb1_board_mesh_sosi_2arr; -- Tx
+ SIGNAL rx_term_siso_2arr : t_unb1_board_mesh_siso_2arr;
+ SIGNAL rx_term_sosi_2arr : t_unb1_board_mesh_sosi_2arr; -- Rx
-- g_mon_select
SIGNAL mon_sosi_arr : t_dp_sosi_arr(c_mon_nof_streams-1 DOWNTO 0); -- selected sosi for the SOSI data monitor
- SIGNAL mon_rx_term_pkt_sosi_2arr : t_unb_mesh_sosi_2arr;
- SIGNAL mon_rx_term_dist_sosi_2arr : t_unb_mesh_sosi_2arr;
+ SIGNAL mon_rx_term_pkt_sosi_2arr : t_unb1_board_mesh_sosi_2arr;
+ SIGNAL mon_rx_term_dist_sosi_2arr : t_unb1_board_mesh_sosi_2arr;
-- g_phy_ena_reorder
- SIGNAL tx_phy_siso_2arr : t_unb_mesh_siso_2arr;
- SIGNAL tx_phy_sosi_2arr : t_unb_mesh_sosi_2arr; -- Tx
- SIGNAL rx_phy_siso_2arr : t_unb_mesh_siso_2arr;
- SIGNAL rx_phy_sosi_2arr : t_unb_mesh_sosi_2arr; -- Rx
+ SIGNAL tx_phy_siso_2arr : t_unb1_board_mesh_siso_2arr;
+ SIGNAL tx_phy_sosi_2arr : t_unb1_board_mesh_sosi_2arr; -- Tx
+ SIGNAL rx_phy_siso_2arr : t_unb1_board_mesh_siso_2arr;
+ SIGNAL rx_phy_sosi_2arr : t_unb1_board_mesh_sosi_2arr; -- Rx
-- tr_nonbonded
SIGNAL tx_phy_siso_arr : t_dp_siso_arr(c_phy_nof_gx-1 DOWNTO 0);
@@ -197,42 +197,42 @@ BEGIN
------------------------------------------------------------------------------
mon_rx_mesh : IF g_mon_select=1 GENERATE
- gen_i : FOR I IN 0 TO c_unb_tr.nof_bus-1 GENERATE
+ gen_i : FOR I IN 0 TO c_unb1_board_tr.nof_bus-1 GENERATE
gen_j : FOR J IN 0 TO g_phy_nof_serial-1 GENERATE
mon_sosi_arr(I*g_phy_nof_serial+J) <= rx_phy_sosi_2arr(I)(J);
END GENERATE;
END GENERATE;
END GENERATE;
mon_rx_term_uth : IF g_mon_select=2 GENERATE
- gen_i : FOR I IN 0 TO c_unb_tr.nof_bus-1 GENERATE
+ gen_i : FOR I IN 0 TO c_unb1_board_tr.nof_bus-1 GENERATE
gen_j : FOR J IN 0 TO g_phy_nof_serial-1 GENERATE
mon_sosi_arr(I*g_phy_nof_serial+J) <= rx_term_sosi_2arr(I)(J);
END GENERATE;
END GENERATE;
END GENERATE;
mon_rx_term_pkt : IF g_mon_select=3 GENERATE
- gen_i : FOR I IN 0 TO c_unb_tr.nof_bus-1 GENERATE
+ gen_i : FOR I IN 0 TO c_unb1_board_tr.nof_bus-1 GENERATE
gen_j : FOR J IN 0 TO g_phy_nof_serial-1 GENERATE
mon_sosi_arr(I*g_phy_nof_serial+J) <= mon_rx_term_pkt_sosi_2arr(I)(J);
END GENERATE;
END GENERATE;
END GENERATE;
mon_rx_term_dist : IF g_mon_select=4 GENERATE
- gen_i : FOR I IN 0 TO c_unb_tr.nof_bus-1 GENERATE
+ gen_i : FOR I IN 0 TO c_unb1_board_tr.nof_bus-1 GENERATE
gen_j : FOR J IN 0 TO g_usr_nof_streams-1 GENERATE
mon_sosi_arr(I*g_usr_nof_streams+J) <= mon_rx_term_dist_sosi_2arr(I)(J);
END GENERATE;
END GENERATE;
END GENERATE;
mon_tx_mesh : IF g_mon_select=5 GENERATE
- gen_i : FOR I IN 0 TO c_unb_tr.nof_bus-1 GENERATE
+ gen_i : FOR I IN 0 TO c_unb1_board_tr.nof_bus-1 GENERATE
gen_j : FOR J IN 0 TO g_phy_nof_serial-1 GENERATE
mon_sosi_arr(I*g_phy_nof_serial+J) <= tx_phy_sosi_2arr(I)(J);
END GENERATE;
END GENERATE;
END GENERATE;
mon_tx_term_uth : IF g_mon_select=6 GENERATE
- gen_i : FOR I IN 0 TO c_unb_tr.nof_bus-1 GENERATE
+ gen_i : FOR I IN 0 TO c_unb1_board_tr.nof_bus-1 GENERATE
gen_j : FOR J IN 0 TO g_phy_nof_serial-1 GENERATE
mon_sosi_arr(I*g_phy_nof_serial+J) <= tx_term_sosi_2arr(I)(J);
END GENERATE;
@@ -270,7 +270,7 @@ BEGIN
-- Terminals
------------------------------------------------------------------------------
- u_mesh_terminals : ENTITY work.unb_mesh_terminals
+ u_unb1_board_mesh_uth_terminals_bidir : ENTITY work.unb1_board_mesh_uth_terminals_bidir
GENERIC MAP (
-- User
g_usr_nof_streams => g_usr_nof_streams,
@@ -323,7 +323,7 @@ BEGIN
-- Compensate for mesh reorder (g_phy_ena_reorder)
------------------------------------------------------------------------------
- u_tx : ENTITY work.unb_mesh_reorder_tx
+ u_tx : ENTITY work.unb1_board_mesh_reorder_tx
GENERIC MAP (
g_node_type => g_node_type,
g_reorder => g_phy_ena_reorder
@@ -337,7 +337,7 @@ BEGIN
rx_phy_siso_2arr => rx_phy_siso_2arr
);
- u_rx : ENTITY work.unb_mesh_reorder_rx
+ u_rx : ENTITY work.unb1_board_mesh_reorder_rx
GENERIC MAP (
g_node_type => g_node_type,
g_reorder => g_phy_ena_reorder
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
index 5b1d2a6795ae9165cd36830d417e87fc0b875b9a..d3515ad40ebce96a3b69ca7b1bba94405de5b572 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
--- Purpose: Test bench for mms_unb_sens
+-- Purpose: Test bench for mms_unb1_board_sens
--
-- Features:
-- . Verify that the UniBoard sensors are read.
@@ -28,8 +28,8 @@
-- . > as 10
-- . > run -all
-ENTITY tb_mms_unb_sens IS
-END tb_mms_unb_sens;
+ENTITY tb_mms_unb1_board_sens IS
+END tb_mms_unb1_board_sens;
LIBRARY IEEE, common_lib, i2c_lib;
USE IEEE.std_logic_1164.ALL;
@@ -39,7 +39,7 @@ USE common_lib.tb_common_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
-ARCHITECTURE tb OF tb_mms_unb_sens IS
+ARCHITECTURE tb OF tb_mms_unb1_board_sens IS
CONSTANT c_sim : BOOLEAN := TRUE; --FALSE;
CONSTANT c_repeat : NATURAL := 2;
@@ -61,7 +61,7 @@ ARCHITECTURE tb OF tb_mms_unb_sens IS
CONSTANT c_uniboard_adin : REAL := -1.0; -- = NC on UniBoard
CONSTANT c_sens_nof_result : NATURAL := 4 + 1;
- CONSTANT c_sens_expected : t_natural_arr(0 TO c_sens_nof_result-1) := (60, 40, 167, 120, 0); -- 4 bytes as read by c_SEQ in unb_sens_ctrl + sens_err
+ CONSTANT c_sens_expected : t_natural_arr(0 TO c_sens_nof_result-1) := (60, 40, 167, 120, 0); -- 4 bytes as read by c_SEQ in unb1_board_sens_ctrl + sens_err
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '0';
@@ -152,7 +152,7 @@ BEGIN
-- I2C sensors master
- u_mms_unb_sens : ENTITY work.mms_unb_sens
+ u_mms_unb1_board_sens : ENTITY work.mms_unb1_board_sens
GENERIC MAP (
g_sim => c_sim,
g_clk_freq => c_clk_freq,
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
index 1c985b7a597b2f0663f65181672f598bc3ad832c..5f0eddc3be8ff9d3b7544f22dc037aee649973ae 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
@@ -32,11 +32,11 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
-ENTITY tb_unb_clk200_pll IS
-END tb_unb_clk200_pll;
+ENTITY tb_unb1_board_clk200_pll IS
+END tb_unb1_board_clk200_pll;
-ARCHITECTURE tb OF tb_unb_clk200_pll IS
+ARCHITECTURE tb OF tb_unb1_board_clk200_pll IS
CONSTANT c_ext_clk_period : TIME := 5 ns; -- 200 MHz
CONSTANT c_clk_vec_w : NATURAL := 6;
@@ -75,7 +75,7 @@ BEGIN
ext_clk <= NOT ext_clk OR tb_end AFTER c_ext_clk_period/2;
ext_rst <= '1', '0' AFTER c_ext_clk_period*7;
- dut_0 : ENTITY work.unb_clk200_pll
+ dut_0 : ENTITY work.unb1_board_clk200_pll
GENERIC MAP (
g_sel => 0, -- g_sel=0 for clk200_pll.vhd
-- g_sel=0 for clk200_pll.vhd
@@ -93,7 +93,7 @@ BEGIN
st_rst400 => st_rst400
);
- dut_45 : ENTITY work.unb_clk200_pll
+ dut_45 : ENTITY work.unb1_board_clk200_pll
GENERIC MAP (
g_sel => 0, -- g_sel=0 for clk200_pll.vhd
-- g_sel=0 for clk200_pll.vhd
@@ -111,7 +111,7 @@ BEGIN
st_rst400 => OPEN
);
- dut_p6 : ENTITY work.unb_clk200_pll
+ dut_p6 : ENTITY work.unb1_board_clk200_pll
GENERIC MAP (
g_sel => 1, -- g_sel=0 for clk200_pll.vhd
-- g_sel=1 for clk200_pll_p6.vhd
@@ -142,7 +142,7 @@ BEGIN
st_clk_vec => st_clk_vec
);
- dut_pq : ENTITY work.unb_clk200_pll
+ dut_pq : ENTITY work.unb1_board_clk200_pll
GENERIC MAP (
g_sel => 2, -- g_sel=0 for clk200_pll.vhd
-- g_sel=1 for clk200_pll_p6.vhd
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
index a6f128f6a221a49953a238c6312a11092a56ed9b..2aa8c95e9644a88a6da867aed9ddee16b62d3e16 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
@@ -22,20 +22,20 @@
-- Purpose:
--- 1) Verify unb_mesh_reorder_bidir for SOSI using the unb_mesh_model_sosi
--- 2) Verify unb_mesh_reorder_bidir for SISO using the unb_mesh_model_siso
--- 3) Verify the serial unb_mesh_model_sl
+-- 1) Verify unb1_board_mesh_reorder_bidir for SOSI using the unb1_board_mesh_model_sosi
+-- 2) Verify unb1_board_mesh_reorder_bidir for SISO using the unb1_board_mesh_model_siso
+-- 3) Verify the serial unb1_board_mesh_model_sl
-- Usage:
--- > do wave_unb_mesh_reorder_bidir.do
+-- > do wave_unb1_board_mesh_reorder_bidir.do
-- > run -all
-- 1) Self check SOSI should report no bn_rx_valid[] or fn_rx_valid[] error
-- 2) Self check SISO should report no bn_tx_ready[] or fn_tx_ready[] error
--- 3) Self check unb_mesh_model_sl operates at PHY level using the SOSI.valid
--- as stimuli and the SOSI.valid result as reference and should report no
--- error.
+-- 3) Self check unb1_board_mesh_model_sl operates at PHY level using the
+-- SOSI.valid as stimuli and the SOSI.valid result as reference and should
+-- report no error.
-- . Manually observe that bn_rx_valid and fn_rx_valid show a series of pulses
-- Description:
--- . See unb_mesh_reorder_bidir.vhd
+-- . See unb1_board_mesh_reorder_bidir.vhd
-- . Use c_reorder=FALSE for a default FN to BN and BN to BN transpose without
-- reordering on the PCB. Default use c_reorder=TRUE to also model the
-- transceiver bus reorderings on UniBoard PCB.
@@ -46,22 +46,22 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE work.unb_common_pkg.ALL;
-USE work.tb_unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
+USE work.tb_unb1_board_pkg.ALL;
-ENTITY tb_unb_mesh_reorder_bidir IS
-END tb_unb_mesh_reorder_bidir;
+ENTITY tb_unb1_board_mesh_reorder_bidir IS
+END tb_unb1_board_mesh_reorder_bidir;
-ARCHITECTURE tb OF tb_unb_mesh_reorder_bidir IS
+ARCHITECTURE tb OF tb_unb1_board_mesh_reorder_bidir IS
CONSTANT c_reorder : BOOLEAN := TRUE;
- CONSTANT c_chip_id_w : NATURAL := c_unb_aux.chip_id_w; -- = 3 to fit 8 fpgas in [2:0]
- CONSTANT c_nof_node : NATURAL := c_unb_nof_node; -- = 4
- CONSTANT c_nof_bus : NATURAL := c_unb_tr.nof_bus; -- = 4
- CONSTANT c_bus_w : NATURAL := c_unb_tr.bus_w; -- = 4
+ CONSTANT c_chip_id_w : NATURAL := c_unb1_board_aux.chip_id_w; -- = 3 to fit 8 fpgas in [2:0]
+ CONSTANT c_nof_node : NATURAL := c_unb1_board_nof_node; -- = 4
+ CONSTANT c_nof_bus : NATURAL := c_unb1_board_tr.nof_bus; -- = 4
+ CONSTANT c_bus_w : NATURAL := c_unb1_board_tr.bus_w; -- = 4
CONSTANT c_repeat : NATURAL := 3;
CONSTANT c_clk_period : TIME := 10 ns;
@@ -73,14 +73,14 @@ ARCHITECTURE tb OF tb_unb_mesh_reorder_bidir IS
-- SL
------------------------------------------------------------------------------
-- . PHY signals to mesh
- SIGNAL fn_tx_phy_sl_3arr : t_unb_mesh_sl_3arr;
- SIGNAL bn_tx_phy_sl_3arr : t_unb_mesh_sl_3arr;
+ SIGNAL fn_tx_phy_sl_3arr : t_unb1_board_mesh_sl_3arr;
+ SIGNAL bn_tx_phy_sl_3arr : t_unb1_board_mesh_sl_3arr;
-- . PHY signals from mesh
- SIGNAL fn_rx_phy_sl_3arr : t_unb_mesh_sl_3arr;
+ SIGNAL fn_rx_phy_sl_3arr : t_unb1_board_mesh_sl_3arr;
SIGNAL fn_rx_phy_sl : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
SIGNAL fn_rx_phy_valid : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
- SIGNAL bn_rx_phy_sl_3arr : t_unb_mesh_sl_3arr;
+ SIGNAL bn_rx_phy_sl_3arr : t_unb1_board_mesh_sl_3arr;
SIGNAL bn_rx_phy_sl : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
SIGNAL bn_rx_phy_valid : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
@@ -94,20 +94,20 @@ ARCHITECTURE tb OF tb_unb_mesh_reorder_bidir IS
SIGNAL bn_rx_valid : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
-- . User domain driving stimuli signals
- SIGNAL fn_tx_usr_sosi_3arr : t_unb_mesh_sosi_3arr := (OTHERS=>(OTHERS=>(OTHERS=>c_dp_sosi_rst)));
- SIGNAL bn_tx_usr_sosi_3arr : t_unb_mesh_sosi_3arr := (OTHERS=>(OTHERS=>(OTHERS=>c_dp_sosi_rst)));
+ SIGNAL fn_tx_usr_sosi_3arr : t_unb1_board_mesh_sosi_3arr := (OTHERS=>(OTHERS=>(OTHERS=>c_dp_sosi_rst)));
+ SIGNAL bn_tx_usr_sosi_3arr : t_unb1_board_mesh_sosi_3arr := (OTHERS=>(OTHERS=>(OTHERS=>c_dp_sosi_rst)));
-- . PHY signals to mesh
- SIGNAL fn_tx_phy_sosi_3arr : t_unb_mesh_sosi_3arr;
- SIGNAL bn_tx_phy_sosi_3arr : t_unb_mesh_sosi_3arr;
+ SIGNAL fn_tx_phy_sosi_3arr : t_unb1_board_mesh_sosi_3arr;
+ SIGNAL bn_tx_phy_sosi_3arr : t_unb1_board_mesh_sosi_3arr;
-- . PHY signals from mesh
- SIGNAL fn_rx_phy_sosi_3arr : t_unb_mesh_sosi_3arr;
- SIGNAL bn_rx_phy_sosi_3arr : t_unb_mesh_sosi_3arr;
+ SIGNAL fn_rx_phy_sosi_3arr : t_unb1_board_mesh_sosi_3arr;
+ SIGNAL bn_rx_phy_sosi_3arr : t_unb1_board_mesh_sosi_3arr;
-- . User domain result signals
- SIGNAL fn_rx_usr_sosi_3arr : t_unb_mesh_sosi_3arr;
- SIGNAL bn_rx_usr_sosi_3arr : t_unb_mesh_sosi_3arr;
+ SIGNAL fn_rx_usr_sosi_3arr : t_unb1_board_mesh_sosi_3arr;
+ SIGNAL bn_rx_usr_sosi_3arr : t_unb1_board_mesh_sosi_3arr;
------------------------------------------------------------------------------
-- SISO
@@ -119,20 +119,20 @@ ARCHITECTURE tb OF tb_unb_mesh_reorder_bidir IS
SIGNAL bn_tx_ready : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
-- . User domain result signals
- SIGNAL fn_tx_usr_siso_3arr : t_unb_mesh_siso_3arr;
- SIGNAL bn_tx_usr_siso_3arr : t_unb_mesh_siso_3arr;
+ SIGNAL fn_tx_usr_siso_3arr : t_unb1_board_mesh_siso_3arr;
+ SIGNAL bn_tx_usr_siso_3arr : t_unb1_board_mesh_siso_3arr;
-- . PHY signals from mesh
- SIGNAL fn_tx_phy_siso_3arr : t_unb_mesh_siso_3arr;
- SIGNAL bn_tx_phy_siso_3arr : t_unb_mesh_siso_3arr;
+ SIGNAL fn_tx_phy_siso_3arr : t_unb1_board_mesh_siso_3arr;
+ SIGNAL bn_tx_phy_siso_3arr : t_unb1_board_mesh_siso_3arr;
-- . PHY signals to mesh
- SIGNAL fn_rx_phy_siso_3arr : t_unb_mesh_siso_3arr;
- SIGNAL bn_rx_phy_siso_3arr : t_unb_mesh_siso_3arr;
+ SIGNAL fn_rx_phy_siso_3arr : t_unb1_board_mesh_siso_3arr;
+ SIGNAL bn_rx_phy_siso_3arr : t_unb1_board_mesh_siso_3arr;
-- . User domain driving stimuli signals
- SIGNAL fn_rx_usr_siso_3arr : t_unb_mesh_siso_3arr := (OTHERS=>(OTHERS=>(OTHERS=>c_dp_siso_rst)));
- SIGNAL bn_rx_usr_siso_3arr : t_unb_mesh_siso_3arr := (OTHERS=>(OTHERS=>(OTHERS=>c_dp_siso_rst)));
+ SIGNAL fn_rx_usr_siso_3arr : t_unb1_board_mesh_siso_3arr := (OTHERS=>(OTHERS=>(OTHERS=>c_dp_siso_rst)));
+ SIGNAL bn_rx_usr_siso_3arr : t_unb1_board_mesh_siso_3arr := (OTHERS=>(OTHERS=>(OTHERS=>c_dp_siso_rst)));
BEGIN
@@ -229,7 +229,7 @@ BEGIN
------------------------------------------------------------------------------
gen_fn : FOR I IN 0 TO c_nof_node-1 GENERATE
- u_order : ENTITY work.unb_mesh_reorder_bidir
+ u_order : ENTITY work.unb1_board_mesh_reorder_bidir
GENERIC MAP (
g_node_type => e_fn,
g_reorder => c_reorder
@@ -258,9 +258,9 @@ BEGIN
-- Mesh between FN0,1,2,3 and BN0,1,2,3 as it is wired on the UniBoard PCB
------------------------------------------------------------------------------
- -- >>> unb_mesh_model_sl
+ -- >>> unb1_board_mesh_model_sl
- -- Use tx_phy SOSI.valid stimuli for input to unb_mesh_model_sl
+ -- Use tx_phy SOSI.valid stimuli for input to unb1_board_mesh_model_sl
gen_tx_serial : FOR I IN 0 TO c_nof_node-1 GENERATE
gen_bus : FOR J IN 0 TO c_nof_bus-1 GENERATE
gen_lanes : FOR K IN c_bus_w-1 DOWNTO 0 GENERATE
@@ -270,7 +270,7 @@ BEGIN
END GENERATE;
END GENERATE;
- u_pcb_mesh_serial : ENTITY work.unb_mesh_model_sl
+ u_pcb_mesh_serial : ENTITY work.unb1_board_mesh_model_sl
GENERIC MAP (
g_reorder => c_reorder
)
@@ -284,7 +284,7 @@ BEGIN
fn_rx_sl_3arr => fn_rx_phy_sl_3arr
);
- -- Use rx_phy SOSI.valid as reference output to verify output of unb_mesh_model_sl
+ -- Use rx_phy SOSI.valid as reference output to verify output of unb1_board_mesh_model_sl
mon_rx_serial : FOR I IN 0 TO c_nof_node-1 GENERATE
gen_bus : FOR J IN 0 TO c_nof_bus-1 GENERATE
gen_lanes : FOR K IN c_bus_w-1 DOWNTO 0 GENERATE
@@ -301,15 +301,15 @@ BEGIN
p_verify_serial : PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
- ASSERT bn_rx_phy_sl=bn_rx_phy_valid REPORT "unb_mesh_model_sl FN->BN error" SEVERITY ERROR;
- ASSERT fn_rx_phy_sl=fn_rx_phy_valid REPORT "unb_mesh_model_sl BN->FN error" SEVERITY ERROR;
+ ASSERT bn_rx_phy_sl=bn_rx_phy_valid REPORT "unb1_board_mesh_model_sl FN->BN error" SEVERITY ERROR;
+ ASSERT fn_rx_phy_sl=fn_rx_phy_valid REPORT "unb1_board_mesh_model_sl BN->FN error" SEVERITY ERROR;
END IF;
END PROCESS;
- -- >>> unb_mesh_model_sosi
+ -- >>> unb1_board_mesh_model_sosi
- u_pcb_mesh_sosi : ENTITY work.unb_mesh_model_sosi
+ u_pcb_mesh_sosi : ENTITY work.unb1_board_mesh_model_sosi
GENERIC MAP (
g_reorder => c_reorder
)
@@ -338,9 +338,9 @@ BEGIN
);
- -- >>> unb_mesh_model_siso
+ -- >>> unb1_board_mesh_model_siso
- u_pcb_mesh_siso : ENTITY work.unb_mesh_model_siso
+ u_pcb_mesh_siso : ENTITY work.unb1_board_mesh_model_siso
GENERIC MAP (
g_reorder => c_reorder
)
@@ -374,7 +374,7 @@ BEGIN
------------------------------------------------------------------------------
gen_bn : FOR I IN 0 TO c_nof_node-1 GENERATE
- u_order : ENTITY work.unb_mesh_reorder_bidir
+ u_order : ENTITY work.unb1_board_mesh_reorder_bidir
GENERIC MAP (
g_node_type => e_bn,
g_reorder => c_reorder
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
index 2ef100eeb43d7b8160444ac310ff4564e3e39678..642d51b167d4368d0d5317d0cf9781d3628b2f18 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
@@ -25,11 +25,11 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
-ENTITY tb_unb_node_ctrl IS
-END tb_unb_node_ctrl;
+ENTITY tb_unb1_board_node_ctrl IS
+END tb_unb1_board_node_ctrl;
-ARCHITECTURE tb OF tb_unb_node_ctrl IS
+ARCHITECTURE tb OF tb_unb1_board_node_ctrl IS
CONSTANT c_scale : NATURAL := 100; -- scale to speed up simulation
@@ -80,7 +80,7 @@ BEGIN
wdi_in <= wdi AND sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
- dut : ENTITY work.unb_node_ctrl
+ dut : ENTITY work.unb1_board_node_ctrl
GENERIC MAP (
g_pulse_us => c_pulse_us,
g_pulse_ms => c_pulse_ms,
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
index 6c0e9cf01a1bc520b449fac7568b2743d6684c73..228b257a8918b474333a4e3594d91284c731206f 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
@@ -25,36 +25,35 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE work.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
-PACKAGE tb_unb_common_pkg IS
+PACKAGE tb_unb1_board_pkg IS
-- Aggregate types to contain all TR for all nodes on one side of the mesh or backplane interface
-- UniBoard TR mesh IO for 4 to 4 nodes : [node][bus][lane]
- TYPE t_unb_mesh_sosi_3arr IS ARRAY (c_unb_nof_node-1 DOWNTO 0) OF t_unb_mesh_sosi_2arr;
- TYPE t_unb_mesh_siso_3arr IS ARRAY (c_unb_nof_node-1 DOWNTO 0) OF t_unb_mesh_siso_2arr;
- TYPE t_unb_mesh_sl_3arr IS ARRAY (c_unb_nof_node-1 DOWNTO 0) OF t_unb_mesh_sl_2arr;
+ TYPE t_unb1_board_mesh_sosi_3arr IS ARRAY (c_unb1_board_nof_node-1 DOWNTO 0) OF t_unb1_board_mesh_sosi_2arr;
+ TYPE t_unb1_board_mesh_siso_3arr IS ARRAY (c_unb1_board_nof_node-1 DOWNTO 0) OF t_unb1_board_mesh_siso_2arr;
+ TYPE t_unb1_board_mesh_sl_3arr IS ARRAY (c_unb1_board_nof_node-1 DOWNTO 0) OF t_unb1_board_mesh_sl_2arr;
-- Subrack with mesh IO for 4 UniBoards, each with TR mesh for 4 to 4 nodes : [unb][node][bus][lane]
- TYPE t_unb_mesh_sosi_4arr IS ARRAY (c_unb_nof_uniboard-1 DOWNTO 0) OF t_unb_mesh_sosi_3arr;
- TYPE t_unb_mesh_siso_4arr IS ARRAY (c_unb_nof_uniboard-1 DOWNTO 0) OF t_unb_mesh_siso_3arr;
- TYPE t_unb_mesh_sl_4arr IS ARRAY (c_unb_nof_uniboard-1 DOWNTO 0) OF t_unb_mesh_sl_3arr;
+ TYPE t_unb1_board_mesh_sosi_4arr IS ARRAY (c_unb1_board_nof_uniboard-1 DOWNTO 0) OF t_unb1_board_mesh_sosi_3arr;
+ TYPE t_unb1_board_mesh_siso_4arr IS ARRAY (c_unb1_board_nof_uniboard-1 DOWNTO 0) OF t_unb1_board_mesh_siso_3arr;
+ TYPE t_unb1_board_mesh_sl_4arr IS ARRAY (c_unb1_board_nof_uniboard-1 DOWNTO 0) OF t_unb1_board_mesh_sl_3arr;
-- UniBoard TR backplane IO for 4 BN, each BN with TR to 3 BN each on the 3 other UniBoards [bn][bus][lane]
- TYPE t_unb_back_sosi_3arr IS ARRAY (c_unb_nof_node-1 DOWNTO 0) OF t_unb_back_sosi_2arr;
- TYPE t_unb_back_siso_3arr IS ARRAY (c_unb_nof_node-1 DOWNTO 0) OF t_unb_back_siso_2arr;
- TYPE t_unb_back_sl_3arr IS ARRAY (c_unb_nof_node-1 DOWNTO 0) OF t_unb_back_sl_2arr;
+ TYPE t_unb1_board_back_sosi_3arr IS ARRAY (c_unb1_board_nof_node-1 DOWNTO 0) OF t_unb1_board_back_sosi_2arr;
+ TYPE t_unb1_board_back_siso_3arr IS ARRAY (c_unb1_board_nof_node-1 DOWNTO 0) OF t_unb1_board_back_siso_2arr;
+ TYPE t_unb1_board_back_sl_3arr IS ARRAY (c_unb1_board_nof_node-1 DOWNTO 0) OF t_unb1_board_back_sl_2arr;
-- UniBoard TR backplane IO for 4 UniBoards * 3 buses to other uniboards : [unb][bn][bus][lane]
- TYPE t_unb_back_sosi_4arr IS ARRAY (c_unb_nof_uniboard-1 DOWNTO 0) OF t_unb_back_sosi_3arr;
- TYPE t_unb_back_siso_4arr IS ARRAY (c_unb_nof_uniboard-1 DOWNTO 0) OF t_unb_back_siso_3arr;
- TYPE t_unb_back_sl_4arr IS ARRAY (c_unb_nof_uniboard-1 DOWNTO 0) OF t_unb_back_sl_3arr;
+ TYPE t_unb1_board_back_sosi_4arr IS ARRAY (c_unb1_board_nof_uniboard-1 DOWNTO 0) OF t_unb1_board_back_sosi_3arr;
+ TYPE t_unb1_board_back_siso_4arr IS ARRAY (c_unb1_board_nof_uniboard-1 DOWNTO 0) OF t_unb1_board_back_siso_3arr;
+ TYPE t_unb1_board_back_sl_4arr IS ARRAY (c_unb1_board_nof_uniboard-1 DOWNTO 0) OF t_unb1_board_back_sl_3arr;
- TYPE t_unb_id_arr IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(c_unb_aux.id_w-1 DOWNTO 0);
-END tb_unb_common_pkg;
+ TYPE t_unb1_board_id_arr IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+END tb_unb1_board_pkg;
-PACKAGE BODY tb_unb_common_pkg IS
-
-END tb_unb_common_pkg;
+PACKAGE BODY tb_unb1_board_common_pkg IS
+END tb_unb1_board_pkg;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
index 55606000d8de6bdfa132812cc356c49834d81872..2847dd89d034d3dc5d6281df76c6915ef92dd0d7 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
@@ -34,26 +34,26 @@
-- Remark:
-- . Phy bus 3 is not used and left not connected on the backplane.
-LIBRARY IEEE, common_lib, unb_common_lib, dp_lib;
+LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_pkg.ALL;
-USE work.unb_common_pkg.ALL;
-USE work.tb_unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
+USE work.tb_unb1_board_pkg.ALL;
-ENTITY unb_back_model_sl IS
+ENTITY unb1_board_back_model_sl IS
PORT (
- backplane_in_serial_4arr : IN t_unb_back_sl_4arr; -- _4arr = (UNB 3,2,1,0)(BN 3,2,1,0)(phy bus 2,1,0)(tr lane 3,2,1,0)
- backplane_out_serial_4arr : OUT t_unb_back_sl_4arr
+ backplane_in_serial_4arr : IN t_unb1_board_back_sl_4arr; -- _4arr = (UNB 3,2,1,0)(BN 3,2,1,0)(phy bus 2,1,0)(tr lane 3,2,1,0)
+ backplane_out_serial_4arr : OUT t_unb1_board_back_sl_4arr
);
-END unb_back_model_sl;
+END unb1_board_back_model_sl;
-ARCHITECTURE beh OF unb_back_model_sl IS
+ARCHITECTURE beh OF unb1_board_back_model_sl IS
BEGIN
- gen_bn : FOR BN IN 0 TO c_unb_nof_bn-1 GENERATE
+ gen_bn : FOR BN IN 0 TO c_unb1_board_nof_bn-1 GENERATE
----------------------------------------------------------------------------
-- Interconnect BN --> BN streaming with actual backplane routing
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
index 21361766c8b9699ab9a561d548e028d28611ba28..352c7f4c8c3408ee6f51f2314e0109f724493b88 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
@@ -22,29 +22,29 @@
-- Purpose: Model the UniBoard backplane of the Apertif beamformer
-- Description:
--- Model the backplane at sosi level. See unb_back_model_sl for more details.
+-- Model the backplane at sosi level. See unb1_board_back_model_sl for more details.
-LIBRARY IEEE, common_lib, unb_common_lib, dp_lib;
+LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_pkg.ALL;
-USE work.unb_common_pkg.ALL;
-USE work.tb_unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
+USE work.tb_unb1_board_pkg.ALL;
-ENTITY unb_back_model_sosi IS
+ENTITY unb1_board_back_model_sosi IS
PORT (
- backplane_in_sosi_4arr : IN t_unb_back_sosi_4arr; -- _4arr = (UNB 3,2,1,0)(BN 3,2,1,0)(phy bus 2,1,0)(tr lane 3,2,1,0)
- backplane_out_sosi_4arr : OUT t_unb_back_sosi_4arr
+ backplane_in_sosi_4arr : IN t_unb1_board_back_sosi_4arr; -- _4arr = (UNB 3,2,1,0)(BN 3,2,1,0)(phy bus 2,1,0)(tr lane 3,2,1,0)
+ backplane_out_sosi_4arr : OUT t_unb1_board_back_sosi_4arr
);
-END unb_back_model_sosi;
+END unb1_board_back_model_sosi;
-ARCHITECTURE beh OF unb_back_model_sosi IS
+ARCHITECTURE beh OF unb1_board_back_model_sosi IS
BEGIN
- gen_bn : FOR BN IN 0 TO c_unb_nof_bn-1 GENERATE
+ gen_bn : FOR BN IN 0 TO c_unb1_board_nof_bn-1 GENERATE
----------------------------------------------------------------------------
-- Interconnect BN --> BN streaming with actual backplane routing
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
index c088fd12fb1dfbc7d87b809531ab083b0ee75b1a..c6db812004fc9a9697d62732725db07e685cd9d8 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
@@ -21,47 +21,47 @@
-------------------------------------------------------------------------------
-- Purpose: Model the links between the FN and BN in the UniBoard TR mesh
--- Description: See unb_mesh_reorder_bidir.vhd
+-- Description: See unb1_board_mesh_reorder_bidir.vhd
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE work.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
-ENTITY unb_mesh_model_siso IS
+ENTITY unb1_board_mesh_model_siso IS
GENERIC (
g_reorder : BOOLEAN := TRUE
);
PORT (
-- FN to BN
- fn0_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst)); -- _2arr = (node id 3,2,1,0)(tr lane 3,2,1,0)
- fn1_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
- fn2_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
- fn3_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
+ fn0_rx_siso_2arr : IN t_unb1_board_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst)); -- _2arr = (node id 3,2,1,0)(tr lane 3,2,1,0)
+ fn1_rx_siso_2arr : IN t_unb1_board_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
+ fn2_rx_siso_2arr : IN t_unb1_board_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
+ fn3_rx_siso_2arr : IN t_unb1_board_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
- bn0_tx_siso_2arr : OUT t_unb_mesh_siso_2arr;
- bn1_tx_siso_2arr : OUT t_unb_mesh_siso_2arr;
- bn2_tx_siso_2arr : OUT t_unb_mesh_siso_2arr;
- bn3_tx_siso_2arr : OUT t_unb_mesh_siso_2arr;
+ bn0_tx_siso_2arr : OUT t_unb1_board_mesh_siso_2arr;
+ bn1_tx_siso_2arr : OUT t_unb1_board_mesh_siso_2arr;
+ bn2_tx_siso_2arr : OUT t_unb1_board_mesh_siso_2arr;
+ bn3_tx_siso_2arr : OUT t_unb1_board_mesh_siso_2arr;
-- BN to FN
- bn0_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
- bn1_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
- bn2_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
- bn3_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
-
- fn0_tx_siso_2arr : OUT t_unb_mesh_siso_2arr;
- fn1_tx_siso_2arr : OUT t_unb_mesh_siso_2arr;
- fn2_tx_siso_2arr : OUT t_unb_mesh_siso_2arr;
- fn3_tx_siso_2arr : OUT t_unb_mesh_siso_2arr
+ bn0_rx_siso_2arr : IN t_unb1_board_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
+ bn1_rx_siso_2arr : IN t_unb1_board_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
+ bn2_rx_siso_2arr : IN t_unb1_board_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
+ bn3_rx_siso_2arr : IN t_unb1_board_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
+
+ fn0_tx_siso_2arr : OUT t_unb1_board_mesh_siso_2arr;
+ fn1_tx_siso_2arr : OUT t_unb1_board_mesh_siso_2arr;
+ fn2_tx_siso_2arr : OUT t_unb1_board_mesh_siso_2arr;
+ fn3_tx_siso_2arr : OUT t_unb1_board_mesh_siso_2arr
);
-END unb_mesh_model_siso;
+END unb1_board_mesh_model_siso;
-ARCHITECTURE beh OF unb_mesh_model_siso IS
+ARCHITECTURE beh OF unb1_board_mesh_model_siso IS
BEGIN
-- Functional mesh connect for transpose
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
index 71351c3a439dcc6e61251707e908bdd9ba7227e9..aad50401764329a47f4cb0e560445c7126b7abeb 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
@@ -22,34 +22,34 @@
-- Purpose: Model the links between the FN and BN in the UniBoard TR mesh at
-- serial transceiver STD_LOGIC level.
--- Description: See unb_mesh_reorder_bidir.vhd
+-- Description: See unb1_board_mesh_reorder_bidir.vhd
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE work.unb_common_pkg.ALL;
-USE work.tb_unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
+USE work.tb_unb1_board_pkg.ALL;
-ENTITY unb_mesh_model_sl IS
+ENTITY unb1_board_mesh_model_sl IS
GENERIC (
g_reorder : BOOLEAN := TRUE
);
PORT (
-- FN to BN
- fn_tx_sl_3arr : IN t_unb_mesh_sl_3arr := (OTHERS=>(OTHERS=>(OTHERS=>'0'))); -- _3arr = (node id 3,2,1,0)(bus id 3,2,1,0)(tr lane 3,2,1,0)
- bn_rx_sl_3arr : OUT t_unb_mesh_sl_3arr;
+ fn_tx_sl_3arr : IN t_unb1_board_mesh_sl_3arr := (OTHERS=>(OTHERS=>(OTHERS=>'0'))); -- _3arr = (node id 3,2,1,0)(bus id 3,2,1,0)(tr lane 3,2,1,0)
+ bn_rx_sl_3arr : OUT t_unb1_board_mesh_sl_3arr;
-- BN to FN
- bn_tx_sl_3arr : IN t_unb_mesh_sl_3arr := (OTHERS=>(OTHERS=>(OTHERS=>'0')));
- fn_rx_sl_3arr : OUT t_unb_mesh_sl_3arr
+ bn_tx_sl_3arr : IN t_unb1_board_mesh_sl_3arr := (OTHERS=>(OTHERS=>(OTHERS=>'0')));
+ fn_rx_sl_3arr : OUT t_unb1_board_mesh_sl_3arr
);
-END unb_mesh_model_sl;
+END unb1_board_mesh_model_sl;
-ARCHITECTURE beh OF unb_mesh_model_sl IS
+ARCHITECTURE beh OF unb1_board_mesh_model_sl IS
BEGIN
-- Functional mesh connect for transpose
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
index bb72f50a2ff8cebb0222f2a4ca5418b11f93f279..daf3225a05e277564b72ce66e0501f1ca4c35868 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
@@ -21,47 +21,47 @@
-------------------------------------------------------------------------------
-- Purpose: Model the links between the FN and BN in the UniBoard TR mesh
--- Description: See unb_mesh_reorder_bidir.vhd
+-- Description: See unb1_board_mesh_reorder_bidir.vhd
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE work.unb_common_pkg.ALL;
+USE work.unb1_board_pkg.ALL;
-ENTITY unb_mesh_model_sosi IS
+ENTITY unb1_board_mesh_model_sosi IS
GENERIC (
g_reorder : BOOLEAN := TRUE
);
PORT (
-- FN to BN
- fn0_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst)); -- _2arr = (node id 3,2,1,0)(tr lane 3,2,1,0)
- fn1_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
- fn2_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
- fn3_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+ fn0_tx_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst)); -- _2arr = (node id 3,2,1,0)(tr lane 3,2,1,0)
+ fn1_tx_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+ fn2_tx_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+ fn3_tx_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
- bn0_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
- bn1_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
- bn2_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
- bn3_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
+ bn0_rx_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr;
+ bn1_rx_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr;
+ bn2_rx_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr;
+ bn3_rx_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr;
-- BN to FN
- bn0_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
- bn1_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
- bn2_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
- bn3_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
-
- fn0_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
- fn1_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
- fn2_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
- fn3_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr
+ bn0_tx_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+ bn1_tx_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+ bn2_tx_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+ bn3_tx_sosi_2arr : IN t_unb1_board_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+
+ fn0_rx_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr;
+ fn1_rx_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr;
+ fn2_rx_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr;
+ fn3_rx_sosi_2arr : OUT t_unb1_board_mesh_sosi_2arr
);
-END unb_mesh_model_sosi;
+END unb1_board_mesh_model_sosi;
-ARCHITECTURE beh OF unb_mesh_model_sosi IS
+ARCHITECTURE beh OF unb1_board_mesh_model_sosi IS
BEGIN
-- Functional mesh connect for transpose