Corrected use of cnt. Added g_pipeline.

libraries/base/dp/src/vhdl/dp_block_select.vhd

@@ -53,6 +53,7 @@ USE work.dp_stream_pkg.ALL;
 
 ENTITY dp_block_select IS
   GENERIC (
+    g_pipeline             : NATURAL := 1;
     g_nof_blocks_per_sync  : NATURAL;
     g_index_lo             : NATURAL := 0;
     g_index_hi             : NATURAL
@@ -81,8 +82,8 @@ ARCHITECTURE rtl OF dp_block_select IS
 
   SIGNAL cnt_reg       : NATURAL RANGE 0 TO true_log_pow2(g_nof_blocks_per_sync);
   SIGNAL cnt           : NATURAL;
-  SIGNAL sync_sosi_reg : t_dp_sosi;
-  SIGNAL sync_sosi     : t_dp_sosi;
+  SIGNAL sync_sosi_reg : t_dp_sosi;  -- hold snk_in.bsn
+  SIGNAL sync_sosi     : t_dp_sosi;  -- hold snk_in.bsn
   SIGNAL block_sosi    : t_dp_sosi;
   
 BEGIN
@@ -101,19 +102,19 @@ BEGIN
   -- Preserve snk_in @ sync
   sync_sosi <= snk_in WHEN snk_in.sync='1' ELSE sync_sosi_reg;
   
-  -- Count eop per sync interval
+  -- Count blocks at sop per sync interval and restart count at sync
   p_cnt : PROCESS(snk_in, cnt_reg)
   BEGIN
     cnt <= cnt_reg;
     IF snk_in.sync='1' THEN
       cnt <= 0;
-    ELSIF snk_in.eop='1' THEN
+    ELSIF snk_in.sop='1' THEN
       cnt <= cnt_reg + 1;
     END IF;
   END PROCESS;
 
   -- Resize snk_in combinatorially into block_sosi, so no impact on ready latency (RL)
-  p_block_sosi : PROCESS(snk_in, cnt_reg, index_lo, index_hi, sync_sosi)
+  p_block_sosi : PROCESS(snk_in, cnt, index_lo, index_hi, sync_sosi)
   BEGIN
     -- Default keep snk_in info and data fields
     block_sosi <= snk_in;
@@ -126,14 +127,14 @@ BEGIN
     ELSE    
       IF snk_in.valid='1' THEN
         -- Drop blocks outside selected range
-        IF cnt_reg < index_lo OR cnt_reg > index_hi THEN
+        IF cnt < index_lo OR cnt > index_hi THEN
           block_sosi.sync  <= '0';
           block_sosi.sop   <= '0';
           block_sosi.eop   <= '0';
           block_sosi.valid <= '0';
         END IF;
         -- Move input sync and bsn to first output block
-        IF cnt_reg=index_lo THEN
+        IF cnt=index_lo THEN
           block_sosi.sync <= snk_in.sop;
           block_sosi.bsn  <= sync_sosi.bsn;   -- bsn is valid at sop
         END IF;
@@ -144,7 +145,7 @@ BEGIN
   -- Register block_sosi to easy timing closure
   u_pipeline : ENTITY work.dp_pipeline
   GENERIC MAP (
-    g_pipeline   => 1  -- 0 for wires, > 0 for registers, 
+    g_pipeline   => g_pipeline  -- 0 for wires, > 0 for registers, 
   )
   PORT MAP (
     rst          => rst,