From 18cf247d22838ccb1ff9cf2d81fc35550a107409 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Fri, 12 Mar 2021 07:51:20 +0100
Subject: [PATCH] Added fpga.yaml for BF and first peripheral for reorder
library.
---
.../lofar2_unb2b_beamformer.fpga.yaml | 182 ++++++++++++++++++
.../base/reorder/reorder.peripheral.yaml | 33 ++++
2 files changed, 215 insertions(+)
create mode 100644 applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
create mode 100644 libraries/base/reorder/reorder.peripheral.yaml
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
new file mode 100644
index 0000000000..e57cc831f2
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
@@ -0,0 +1,182 @@
+schema_name : args
+schema_version: 1.0
+schema_type : fpga
+
+hdl_library_name: lofar2_unb2b_beamformer
+fpga_name : lofar2_unb2b_beamformer
+fpga_description: "FPGA design lofar2_unb2b_beamformer"
+
+peripherals:
+ #############################################################################
+ # Factory / minimal (see ctrl_unb2b_board.vhd)
+ #############################################################################
+ - peripheral_name: unb2b_board/system_info
+ slave_port_names:
+ - ROM_SYSTEM_INFO
+ - PIO_SYSTEM_INFO
+ lock_base_address: 0x10000
+
+ - peripheral_name: unb2b_board/wdi
+ slave_port_names:
+ - PIO_WDI
+
+ - peripheral_name: unb2b_board/unb2_fpga_sens
+ slave_port_names:
+ - REG_FPGA_TEMP_SENS
+ - REG_FPGA_VOLTAGE_SENS
+
+ - peripheral_name: unb2b_board/ram_scrap
+ slave_port_names:
+ - RAM_SCRAP
+
+ - peripheral_name: eth/eth
+ slave_port_names:
+ - AVS_ETH_0_TSE
+ - AVS_ETH_0_REG
+ - AVS_ETH_0_RAM
+
+ - peripheral_name: ppsh/ppsh
+ slave_port_names:
+ - PIO_PPS
+
+ - peripheral_name: epcs/epcs
+ slave_port_names:
+ - REG_EPCS
+
+ - peripheral_name: dp/dpmm
+ slave_port_names:
+ - REG_DPMM_CTRL
+ - REG_DPMM_DATA
+
+ - peripheral_name: dp/mmdp
+ slave_port_names:
+ - REG_MMDP_CTRL
+ - REG_MMDP_DATA
+
+ - peripheral_name: remu/remu
+ slave_port_names:
+ - REG_REMU
+
+ #############################################################################
+ # AIT = ADC Input and Timing (see node_adc_input_and_timing.vhd)
+ #############################################################################
+
+ - peripheral_name: tech_jesd204b/jesd_ctrl
+ slave_port_names:
+ - PIO_JESD_CTRL
+
+ - peripheral_name: tech_jesd204b/jesd204b_arria10
+ slave_port_names:
+ - JESD204B
+
+ - peripheral_name: dp/dp_shiftram
+ parameter_overrides:
+ - { name: g_nof_streams, value: 12 } # = S_pn
+ - { name: g_nof_words, value: 4096 }
+ - { name: g_data_w, value: 16 }
+ slave_port_names:
+ - REG_DP_SHIFTRAM
+
+ - peripheral_name: dp/dp_bsn_source
+ parameter_overrides:
+ - { name: g_nof_block_per_sync, value: 195313 } # 390625 = 2 * 195312, to have integer number of blocks in 2 s sync interval
+ slave_port_names:
+ - REG_BSN_SOURCE
+
+ # TODO: Use REG_BSN_SOURCE_V2 instead of REG_BSN_SOURCE
+ #peripheral_name: dp/dp_bsn_source_v2
+ #parameter_overrides:
+ # - { name: g_nof_clk_per_sync, value: 200000000 } # = f_adc
+ # - { name: g_block_size, value: 1024 } # = N_fft
+ # - { name: g_bsn_time_offset_w, value: 10 } # note: g_bsn_time_offset_w = ceil_log2(g_block_size)
+ #slave_port_names:
+ # - REG_BSN_SOURCE_V2
+
+ - peripheral_name: dp/dp_bsn_scheduler
+ slave_port_names:
+ - REG_BSN_SCHEDULER
+
+ - peripheral_name: dp/dp_bsn_monitor
+ peripheral_group: input
+ slave_port_names:
+ - REG_BSN_MONITOR_INPUT
+
+ - peripheral_name: diag/diag_wg_wideband
+ parameter_overrides:
+ - { name: g_nof_streams, value: 12 } # = S_pn
+ slave_port_names:
+ - REG_DIAG_WG
+ - RAM_DIAG_WG
+
+ - peripheral_name: aduh/aduh_mon_dc_power
+ parameter_overrides:
+ - { name: g_nof_streams, value: 12 } # = S_pn
+ slave_port_names:
+ - REG_ADUH_MON
+
+ # Commented RAM_ADUH_MON, because use RAM_DIAG_DATA_BUF_BSN instead
+ #- peripheral_name: aduh/aduh_mon_data_buffer
+ # parameter_overrides:
+ # - { name: g_nof_streams, value: 12 } # = S_pn
+ # - { name: g_symbol_w, value: 16 }
+ # - { name: g_nof_symbols_per_data, value: 1 }
+ # - { name: g_buffer_nof_symbols, value: 512 }
+ # - { name: g_buffer_use_sync, value: true }
+ # slave_port_names:
+ # - RAM_ADUH_MON
+
+ - peripheral_name: diag/diag_data_buffer
+ peripheral_group: bsn
+ parameter_overrides:
+ - { name: g_nof_streams, value: 12 } # = S_pn
+ - { name: g_data_w, value: 16 }
+ - { name: g_nof_data, value: 1024 }
+ slave_port_names:
+ - REG_DIAG_DATA_BUF_BSN
+ - RAM_DIAG_DATA_BUF_BSN
+
+ #############################################################################
+ # Fsub = Subband Filterbank (from node_sdp_filterbank.vhd)
+ #############################################################################
+
+ - peripheral_name: si/si
+ slave_port_names:
+ - REG_SI
+
+ - peripheral_name: filter/fil_ppf_w
+ parameter_overrides:
+ - { name: g_wb_factor, value: 1 }
+ - { name: g_nof_taps, value: 16 } # = N_taps
+ - { name: g_nof_bands, value: 1024 } # = N_fft
+ - { name: g_coef_dat_w, value: 16 } # = W_fir_coef
+ slave_port_names:
+ - RAM_FIL_COEFS
+
+ - peripheral_name: sdp/sdp_subband_equalizer
+ slave_port_names:
+ - RAM_EQUALIZER_GAINS
+
+ - peripheral_name: dp/dp_selector
+ slave_port_names:
+ - REG_DP_SELECTOR # input_select = 0 for weighted subbands, input_select = 1 for raw subbands
+
+ - peripheral_name: st/st_sst_for_sdp
+ slave_port_names:
+ - RAM_ST_SST
+
+
+ #############################################################################
+ # BF = Beamformer (from node_sdp_beamformer.vhd)
+ #############################################################################
+
+ - peripheral_name: sdp/sdp_info
+ slave_port_names:
+ - REG_SDP_INFO
+
+ - peripheral_name: reorder/reorder_col_wide
+ parameter_overrides:
+ - { name: g_wb_factor, value: 12 } # N_beamsets * P_pfb
+ - { name: g_nof_ch_in, value: 1024 } # = N_sub * Q_fft
+ - { name: g_nof_ch_sel, value: 976 } # = S_sub_bf * Q_fft
+ slave_port_names:
+ - RAM_SS_SS_WIDE
diff --git a/libraries/base/reorder/reorder.peripheral.yaml b/libraries/base/reorder/reorder.peripheral.yaml
new file mode 100644
index 0000000000..5281f2590d
--- /dev/null
+++ b/libraries/base/reorder/reorder.peripheral.yaml
@@ -0,0 +1,33 @@
+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: reorder
+hdl_library_description: "Reorder data within and between data streams."
+
+peripherals:
+ - peripheral_name: reorder_col_wide # pi_ss_ss_wide.py
+ peripheral_description: |
+ "Reorder the data serially per stream.
+ Each block of g_nof_ch_in input data gets stored, and then a block of g_nof_ch_sel
+ selected data is passed on. The index fields specify the order and the index of
+ the input data that is passed on.
+ There are g_wb_factor parallel data streams. All data streams can be reordered
+ independently."
+ parameters:
+ # Parameters of reorder_col_wide.vhd / reorder_col.vhd
+ - { name: g_wb_factor, value: 1 }
+ - { name: g_nof_ch_in, value: 256 }
+ - { name: g_nof_ch_sel, value: 192 } # g_nof_ch_sel < g_nof_ch_in
+ slave_ports:
+ # MM port for reorder_col_wide.vhd / reorder_col.vhd
+ - slave_name: RAM_SS_SS_WIDE
+ slave_description: ""
+ slave_type: RAM
+ number_of_slaves: g_wb_factor
+ fields:
+ - - field_name: index
+ field_description: ""
+ width: ceil_log2(g_nof_ch_in)
+ address_offset: 0x0
+ number_of_fields: g_nof_ch_sel
--
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