From 189148fe57ea116d413b1a3cc2c88186a689b301 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Mon, 2 Mar 2020 16:30:53 +0100
Subject: [PATCH] Added g_use_dual_clock; removed fill level checks
---
.../base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd | 42 ++++++++-----------
1 file changed, 18 insertions(+), 24 deletions(-)
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
index b13ef2a3a5..27a32a0af3 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
@@ -47,6 +47,7 @@ USE work.tb_dp_pkg.ALL;
ENTITY tb_dp_fifo_fill_eop IS
GENERIC (
-- Try FIFO settings
+ g_dut_use_dual_clock : BOOLEAN := TRUE;
g_dut_use_bsn : BOOLEAN := FALSE;
g_dut_use_empty : BOOLEAN := FALSE;
g_dut_use_channel : BOOLEAN := FALSE;
@@ -54,7 +55,7 @@ ENTITY tb_dp_fifo_fill_eop IS
g_dut_fifo_rl : NATURAL := 1; -- internal RL, use 0 for look ahead FIFO, default 1 for normal FIFO
g_dut_fifo_size : NATURAL := 128;
g_dut_fifo_fill : NATURAL := 100; -- selectable >= 0 for dp_fifo_fill
- g_dut_use_rd_fill_32b : BOOLEAN := False
+ g_dut_use_rd_fill_32b : BOOLEAN := FALSE
);
END tb_dp_fifo_fill_eop;
@@ -204,22 +205,14 @@ BEGIN
proc_dp_verify_value(e_at_least, clk, verify_done, exp_data, out_data);
-- Verify fill level
- p_verify_fifo_fill : PROCESS
+ p_tb_end : PROCESS
BEGIN
IF g_dut_fifo_fill>0 THEN
-- Use rd_fill_32b /= g_dut_fifo_fill to verify dynamic control
IF g_dut_use_rd_fill_32b=TRUE THEN
rd_fill_32b <= TO_UVEC(g_dut_fifo_size/5, c_word_w);
END IF;
-
- -- Check fill level at first output
- proc_common_wait_until_high(clk, out_val);
- ASSERT UNSIGNED(rd_usedw)=UNSIGNED(rd_fill_32b) REPORT "Usedw is not equal to fill level at start" SEVERITY ERROR;
-
- -- Check fill level after last output (account for block length given by c_tx_period_sop)
- proc_common_wait_until_high(clk, verify_done);
- proc_common_wait_some_cycles(clk, g_dut_fifo_size);
- ASSERT UNSIGNED(rd_usedw)>=UNSIGNED(rd_fill_32b)-c_tx_period_sop REPORT "Usedw does not match fill level at end" SEVERITY ERROR;
+
END IF;
proc_common_wait_until_high(clk, tb_done);
@@ -255,19 +248,20 @@ BEGIN
dut : ENTITY work.dp_fifo_fill_eop
GENERIC MAP (
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => FALSE,
- g_use_sync => g_dut_use_sync,
- g_fifo_fill => g_dut_fifo_fill,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_rl => g_dut_fifo_rl
+ g_use_dual_clock => g_dut_use_dual_clock,
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => FALSE,
+ g_use_sync => g_dut_use_sync,
+ g_fifo_fill => g_dut_fifo_fill,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_rl => g_dut_fifo_rl
)
PORT MAP (
rd_rst => rst,
--
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