diff --git a/libraries/readme_libraries.txt b/libraries/readme_libraries.txt
index 90c1c1deb9ffd1dac50ed0d775f91780cba3f6ab..cc71e8e54e2b5bfe3391812b9a44c695fee9e1c6 100644
--- a/libraries/readme_libraries.txt
+++ b/libraries/readme_libraries.txt
@@ -13,15 +13,17 @@ The libraries directory contains the HDL libraries that are reused by the HDL de
 The technology directory provides the FPGA specific IP as technology independent IP.
 
   technology/-- FPGA chip vendor IP
-             altera/
-                    altera_mf       -- general Altera FPGA IP
-                    stratixiv       -- Stratix IV specific IP
-                    stratixiv_hssi  -- Stratix IV High Speed Serial Interface transceiver IP
-             xilinx/
+             ip_<device_name>/
+             ip_stratixiv/
+                       .            -- simple FPGA IP
+                       <ip_name>/   -- composite FPGA IP
+             ip_arria10/
+             ip_virtex4/
+             ip_virtex7/
              
              -- Technology packages
-             base/technology_pkg.vhd         -- technology identifiers and some low level functions
-                  technology_select_pkg.vhd  -- constant for default device selection 
+             technology_pkg.vhd         -- technology identifiers and some low level functions
+             technology_select_pkg.vhd  -- constant for default device selection 
              
              -- Technology independent IP
              fifo/         -- FIFOs
@@ -30,25 +32,28 @@ The technology directory provides the FPGA specific IP as technology independent
              memory/       -- internal FPGA RAM and ROM components
              transceiver/  -- non bonded gigabit transceivers
 
-All files in the altera/ and xilinx/ IP directories start with prefix 'ip_' followed by the vendor library name and then a component name.
-All files in the technology independent IP directories start with prefix 'tech_' followed by the technology directory name and then a component name.
+The device dependend IP is organised per device in the ip_<device_name>/ directories. All files in the IP directories start with prefix
+'ip_<device_name>' followed by a component name.
+
+The technology indenpendent components are organised per component type in the <component_type>/ directories (like fifo/ iobuf/ etc). All
+files in the technology independent IP directories start with prefix 'tech_<component_type>' followed by a component name.
 
 The technology naming convention nicely clarifies the level of the component. The 'ip_' prefix indicates vendor specific IP and garantuees a name
 that will be different from any name that the vendor may use for its components. The 'tech_' prefix indicates the that the component is a wrapper
 component that acts as a portal between the technology independent application and the technology dependent IP.
 
-The default technology can be selected via the c_tech_select_default constant in technology_select_pkg.vhd or it can be passed on through the
-hierarchy via the g_technology generic.
+The supported IP technologies are given an indentifier number in the technology_pkg.vhd. The default technology can be selected via the
+c_tech_select_default constant in technology_select_pkg.vhd or it can be passed on through the hierarchy via the g_technology generic.
 
 The vendor IP components are typically pregenerated by the MegaWizard in case of Altera and Coregen in case of Xilinx. For each variation of
 parameters it may be necessary to pregenerate an IP component. Alternatively for many Altera IP components it is allowed to add generics to
 the IP sources to make some parameters configurable without having to run the MegaWizard for each variation.
 
-Each technology independent component directory contains a tech_<dir_name>_component.pkg that lists the IP components from the vendor IP directories.
-The tech_<dir_name>_component.pkg makes all vendor IP known to the synthesis tool, while allowing the synthesis tool to ignore all foreign vendor IP. 
-Only the vendor IP libraries that are realy needed for the selected technology need to be made available for synthesis. Similar for simulation only
-the actually used vendor IP libraries need to be avaiable. However in simulation it is also allowed to make all vendor IP libraries available. The
-'tech_<directory_name><component name>.vhd' technology independent component files have a IP library clause that declares the IP libraries to ensure
-default binding in simulation. The IP library clause is ignored by synthesis. E.g. LIBRARY ip_altera_mf_lib, LIBRARY ip_stratixiv_hssi_lib.
+Each technology independent component directory contains a tech_<component_type>_component.pkg that lists the IP components from the vendor IP directories.
+The tech_<component_type>_component.pkg makes all vendor IP known to the synthesis tool, while allowing the synthesis tool to ignore all foreign vendor IP. 
+Only the vendor device IP libraries that are realy needed for the selected technology need to be made available for synthesis. Similar for simulation only
+the actually used vendor device IP libraries need to be avaiable. However in simulation it is also allowed to make all vendor device IP libraries available.
+The 'tech_<component_type><component name>.vhd' technology independent component files have an IP library clause that declares the IP libraries to ensure
+default binding in simulation. The IP library clause is ignored by synthesis. E.g. LIBRARY ip_stratixiv_lib, LIBRARY ip_virtex4_lib.
 The default component to entity binding works because there is only one entity-architecture implementation for each component, because thanks
-to the IP naming convention with prefix 'ip_<vendor_library_name><component_name>.vhd' all IP components will have a unique name.
+to the IP naming convention with prefix 'ip_<device_name><component_name>.vhd' all vendor device IP components will have a unique name.