From 17ede42824cc879c1251ebdb06d7ff7d9f7bb67a Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 8 Apr 2015 14:29:36 +0000
Subject: [PATCH] Removed internal DDR memory model (now needs to be
instantiated in tb). Use dedicated records for DDR3 and DDR4 phy interfaces,
instead of the combined record.
---
libraries/io/ddr/src/vhdl/io_ddr.vhd | 38 ++++++++++++++------------
libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd | 38 ++++++++++++++++++--------
2 files changed, 47 insertions(+), 29 deletions(-)
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 26f21af7ba..adcbec171f 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -49,10 +49,6 @@
-- bursts already be pending. Therefore the g_rd_fifo_af_margin needs to be
-- large enough to fit a number of read bursts.
--- In simulation use g_use_ddr_memory_model=TRUE to also include the DDR
--- memory model that is internally available within tech_ddr. This avoids
--- having to connect a DDR memory model at top level in the test bench.
---
-- Usage:
-- . The dvr interface could be connected to a MM register. The DDR memory
-- may then be used to capture (large) blocks of streaming data that can
@@ -160,7 +156,6 @@ ENTITY io_ddr IS
GENERIC(
g_technology : NATURAL := c_tech_select_default;
g_tech_ddr : t_c_tech_ddr;
- g_use_ddr_memory_model : BOOLEAN := FALSE; -- when TRUE use internal DDR memory model, else connect DDR memory model in top level tb
g_cross_domain_dvr_ctlr : BOOLEAN := TRUE;
g_cross_domain_delay_len : NATURAL := c_meta_delay_len;
g_wr_data_w : NATURAL := 32;
@@ -216,13 +211,18 @@ ENTITY io_ddr IS
rd_sosi : OUT t_dp_sosi;
rd_siso : IN t_dp_siso;
- term_ctrl_out : OUT t_tech_ddr_phy_terminationcontrol;
- term_ctrl_in : IN t_tech_ddr_phy_terminationcontrol := c_tech_ddr_phy_terminationcontrol_rst;
+ term_ctrl_out : OUT t_tech_ddr3_phy_terminationcontrol;
+ term_ctrl_in : IN t_tech_ddr3_phy_terminationcontrol := c_tech_ddr3_phy_terminationcontrol_rst;
+
+ -- DDR3 PHY external interface
+ phy3_in : IN t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
+ phy3_io : INOUT t_tech_ddr3_phy_io;
+ phy3_ou : OUT t_tech_ddr3_phy_ou;
- -- DDR PHY external interface
- phy_in : IN t_tech_ddr_phy_in := c_tech_ddr_phy_in_x;
- phy_io : INOUT t_tech_ddr_phy_io;
- phy_ou : OUT t_tech_ddr_phy_ou
+ -- DDR4 PHY external interface
+ phy4_in : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
+ phy4_io : INOUT t_tech_ddr4_phy_io;
+ phy4_ou : OUT t_tech_ddr4_phy_ou
);
END io_ddr;
@@ -438,8 +438,7 @@ BEGIN
u_tech_ddr : ENTITY tech_ddr_lib.tech_ddr
GENERIC MAP (
g_technology => g_technology,
- g_tech_ddr => g_tech_ddr,
- g_use_ddr_memory_model => g_use_ddr_memory_model
+ g_tech_ddr => g_tech_ddr
)
PORT MAP (
-- PLL reference clock
@@ -458,10 +457,15 @@ BEGIN
term_ctrl_out => term_ctrl_out,
term_ctrl_in => term_ctrl_in,
- -- PHY interface
- phy_in => phy_in,
- phy_io => phy_io,
- phy_ou => phy_ou
+ -- DDR3 PHY interface
+ phy3_in => phy3_in,
+ phy3_io => phy3_io,
+ phy3_ou => phy3_ou,
+
+ -- DDR4 PHY interface
+ phy4_in => phy4_in,
+ phy4_io => phy4_io,
+ phy4_ou => phy4_ou
);
ctlr_rst_out <= ctlr_rst_out_i;
diff --git a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
index 3c25f729db..2f052b81c0 100644
--- a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
@@ -216,10 +216,15 @@ ARCHITECTURE str of tb_io_ddr IS
SIGNAL snk_val_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL expected_cnt : NATURAL;
- -- PHY interface
- SIGNAL phy_in : t_tech_ddr_phy_in;
- SIGNAL phy_io : t_tech_ddr_phy_io;
- SIGNAL phy_ou : t_tech_ddr_phy_ou;
+ -- DDR3 PHY interface
+ SIGNAL phy3_in : t_tech_ddr3_phy_in;
+ SIGNAL phy3_io : t_tech_ddr3_phy_io;
+ SIGNAL phy3_ou : t_tech_ddr3_phy_ou;
+
+ -- DDR4 PHY interface
+ SIGNAL phy4_in : t_tech_ddr4_phy_in;
+ SIGNAL phy4_io : t_tech_ddr4_phy_io;
+ SIGNAL phy4_ou : t_tech_ddr4_phy_ou;
BEGIN
@@ -453,22 +458,31 @@ BEGIN
rd_sosi => diag_rd_snk_in,
rd_siso => diag_rd_snk_out,
- -- DDR PHY external interface
- phy_ou => phy_ou,
- phy_io => phy_io,
- phy_in => phy_in
+ -- DDR3 PHY external interface
+ phy3_ou => phy3_ou,
+ phy3_io => phy3_io,
+ phy3_in => phy3_in,
+
+ -- DDR4 PHY external interface
+ phy4_ou => phy4_ou,
+ phy4_io => phy4_io,
+ phy4_in => phy4_in
);
u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
GENERIC MAP (
- g_sim => TRUE,
g_tech_ddr => c_tech_ddr
)
PORT MAP (
- mem_in => phy_ou,
- mem_io => phy_io
+ -- DDR3 PHY interface
+ mem3_in => phy3_ou,
+ mem3_io => phy3_io,
+
+ -- DDR4 PHY interface
+ mem4_in => phy4_ou,
+ mem4_io => phy4_io
);
-
+
END ARCHITECTURE str;
--
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