diff --git a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
index 68f2c79285e5ec40b12eebd38e078a5669d3892a..52996799caa8294a2c24069d4a5945cf67148b7a 100644
--- a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
+++ b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "65536";
+ value = "5242880";
type = "String";
}
}
@@ -266,7 +266,7 @@
{
datum baseAddress
{
- value = "5308416";
+ value = "5767168";
type = "String";
}
}
@@ -282,7 +282,7 @@
{
datum baseAddress
{
- value = "5242880";
+ value = "65536";
type = "String";
}
}
@@ -742,7 +742,7 @@
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="unb2_test_ddr.qpf" />
+ <parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
@@ -2120,7 +2120,7 @@
<parameter name="dataAddrWidth" value="23" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x80' end='0x100' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x180' /><slave name='reg_diag_data_buffer_ddr.mem' start='0x180' end='0x200' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x200' end='0x280' /><slave name='avs_eth_1.mms_reg' start='0x280' end='0x2C0' /><slave name='avs_eth_0.mms_reg' start='0x2C0' end='0x300' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x300' end='0x340' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x340' end='0x380' /><slave name='timer_0.s1' start='0x380' end='0x3A0' /><slave name='reg_diag_rx_seq_ddr.mem' start='0x3A0' end='0x3C0' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x3C0' end='0x3E0' /><slave name='reg_diag_bg_10gbe.mem' start='0x3E0' end='0x400' /><slave name='reg_diag_bg_1gbe.mem' start='0x400' end='0x420' /><slave name='reg_epcs.mem' start='0x420' end='0x440' /><slave name='reg_remu.mem' start='0x440' end='0x460' /><slave name='reg_unb_sens.mem' start='0x460' end='0x480' /><slave name='pio_wdi.s1' start='0x480' end='0x490' /><slave name='reg_diag_tx_seq_ddr.mem' start='0x490' end='0x4A0' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x4A0' end='0x4B0' /><slave name='reg_mmdp_data.mem' start='0x4B0' end='0x4B8' /><slave name='reg_mmdp_ctrl.mem' start='0x4B8' end='0x4C0' /><slave name='reg_dpmm_data.mem' start='0x4C0' end='0x4C8' /><slave name='reg_dpmm_ctrl.mem' start='0x4C8' end='0x4D0' /><slave name='pio_pps.mem' start='0x4D0' end='0x4D8' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x4D8' end='0x4E0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_tse' start='0x6000' end='0x7000' /><slave name='avs_eth_1.mms_ram' start='0x7000' end='0x8000' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' /><slave name='ram_diag_bg_1gbe.mem' start='0x9000' end='0xA000' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_io_ddr.mem' start='0x40000' end='0x80000' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /><slave name='ram_diag_data_buffer_ddr.mem' start='0x500000' end='0x510000' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0x510000' end='0x520000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x80' end='0x100' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x180' /><slave name='reg_diag_data_buffer_ddr.mem' start='0x180' end='0x200' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x200' end='0x280' /><slave name='avs_eth_1.mms_reg' start='0x280' end='0x2C0' /><slave name='avs_eth_0.mms_reg' start='0x2C0' end='0x300' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x300' end='0x340' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x340' end='0x380' /><slave name='timer_0.s1' start='0x380' end='0x3A0' /><slave name='reg_diag_rx_seq_ddr.mem' start='0x3A0' end='0x3C0' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x3C0' end='0x3E0' /><slave name='reg_diag_bg_10gbe.mem' start='0x3E0' end='0x400' /><slave name='reg_diag_bg_1gbe.mem' start='0x400' end='0x420' /><slave name='reg_epcs.mem' start='0x420' end='0x440' /><slave name='reg_remu.mem' start='0x440' end='0x460' /><slave name='reg_unb_sens.mem' start='0x460' end='0x480' /><slave name='pio_wdi.s1' start='0x480' end='0x490' /><slave name='reg_diag_tx_seq_ddr.mem' start='0x490' end='0x4A0' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x4A0' end='0x4B0' /><slave name='reg_mmdp_data.mem' start='0x4B0' end='0x4B8' /><slave name='reg_mmdp_ctrl.mem' start='0x4B8' end='0x4C0' /><slave name='reg_dpmm_data.mem' start='0x4C0' end='0x4C8' /><slave name='reg_dpmm_ctrl.mem' start='0x4C8' end='0x4D0' /><slave name='pio_pps.mem' start='0x4D0' end='0x4D8' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x4D8' end='0x4E0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_tse' start='0x6000' end='0x7000' /><slave name='avs_eth_1.mms_ram' start='0x7000' end='0x8000' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' /><slave name='ram_diag_bg_1gbe.mem' start='0x9000' end='0xA000' /><slave name='ram_diag_data_buffer_ddr.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_io_ddr.mem' start='0x40000' end='0x80000' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0x580000' end='0x590000' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
@@ -2372,7 +2372,7 @@
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <parameter name="g_adr_w" value="14" />
+ <parameter name="g_adr_w" value="17" />
<parameter name="g_dat_w" value="32" />
</module>
<module
@@ -2749,7 +2749,7 @@
start="cpu_0.data_master"
end="ram_diag_data_buffer_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00510000" />
+ <parameter name="baseAddress" value="0x00580000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -2803,7 +2803,7 @@
start="cpu_0.data_master"
end="ram_diag_data_buffer_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00500000" />
+ <parameter name="baseAddress" value="0x00010000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -2839,7 +2839,7 @@
start="cpu_0.data_master"
end="ram_diag_data_buffer_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00010000" />
+ <parameter name="baseAddress" value="0x00500000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index 47c9200c011234173ee844b2064f41d9271cde31..b7c27b666796426a7f1d317fa19f9972f0a2e40a 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -202,6 +202,9 @@ ARCHITECTURE str OF mmm_unb2_test IS
-- Block generator
CONSTANT c_ram_diag_bg_1GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(ceil_log2(g_bg_block_size)));
CONSTANT c_ram_diag_bg_10GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(ceil_log2(g_bg_block_size)));
+ CONSTANT c_ram_diag_databuffer_10GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(ceil_log2(g_bg_block_size)));
+ CONSTANT c_ram_diag_databuffer_1GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(ceil_log2(g_bg_block_size)));
+ CONSTANT c_ram_diag_databuffer_ddr_addr_w : NATURAL := ceil_log2(1 * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
-- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
@@ -617,7 +620,7 @@ BEGIN
ram_diag_data_buffer_1gbe_clk_export => OPEN,
ram_diag_data_buffer_1gbe_reset_export => OPEN,
- ram_diag_data_buffer_1gbe_address_export => ram_diag_data_buf_1gbe_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_1gbe_address_export => ram_diag_data_buf_1gbe_mosi.address(c_ram_diag_databuffer_1GbE_addr_w-1 DOWNTO 0),
ram_diag_data_buffer_1gbe_write_export => ram_diag_data_buf_1gbe_mosi.wr,
ram_diag_data_buffer_1gbe_writedata_export => ram_diag_data_buf_1gbe_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_1gbe_read_export => ram_diag_data_buf_1gbe_mosi.rd,
@@ -625,7 +628,7 @@ BEGIN
ram_diag_data_buffer_10gbe_clk_export => OPEN,
ram_diag_data_buffer_10gbe_reset_export => OPEN,
- ram_diag_data_buffer_10gbe_address_export => ram_diag_data_buf_10gbe_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_10gbe_address_export => ram_diag_data_buf_10gbe_mosi.address(c_ram_diag_databuffer_10GbE_addr_w-1 DOWNTO 0),
ram_diag_data_buffer_10gbe_write_export => ram_diag_data_buf_10gbe_mosi.wr,
ram_diag_data_buffer_10gbe_writedata_export => ram_diag_data_buf_10gbe_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_10gbe_read_export => ram_diag_data_buf_10gbe_mosi.rd,
@@ -689,7 +692,7 @@ BEGIN
ram_diag_data_buffer_ddr_clk_export => OPEN,
ram_diag_data_buffer_ddr_reset_export => OPEN,
- ram_diag_data_buffer_ddr_address_export => ram_diag_data_buf_ddr_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_ddr_address_export => ram_diag_data_buf_ddr_mosi.address(c_ram_diag_databuffer_ddr_addr_w-1 DOWNTO 0),
ram_diag_data_buffer_ddr_write_export => ram_diag_data_buf_ddr_mosi.wr,
ram_diag_data_buffer_ddr_writedata_export => ram_diag_data_buf_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_ddr_read_export => ram_diag_data_buf_ddr_mosi.rd,
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 3a99358aaf8b429aa5d941627d79d0af1575b747..7e4e34e954d1d01f037410138d7d8ca0eabf96be 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -27,286 +27,287 @@ PACKAGE qsys_unb2_test_pkg IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v15 QSYS builder
-----------------------------------------------------------------------------
-
+
component qsys_unb2_test is
- port (
- avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
- avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
- avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
- avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
- avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
- avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
- avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
- avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
- avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
- avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
- avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
- avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
- avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
- avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
- avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
- avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
- avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
- avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
- avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
- avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
- clk_clk : in std_logic := '0'; -- clk.clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
- pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
- pio_pps_read_export : out std_logic; -- pio_pps_read.export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
- pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
- pio_pps_write_export : out std_logic; -- pio_pps_write.export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
- pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
- pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
- pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
- pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
- pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
- ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
- ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0); -- ram_diag_bg_1gbe_address.export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
- ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
- ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(13 downto 0); -- ram_diag_data_buffer_10gbe_address.export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0); -- ram_diag_data_buffer_1gbe_address.export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
- ram_diag_data_buffer_ddr_address_export : out std_logic_vector(13 downto 0); -- ram_diag_data_buffer_ddr_address.export
- ram_diag_data_buffer_ddr_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_clk.export
- ram_diag_data_buffer_ddr_read_export : out std_logic; -- ram_diag_data_buffer_ddr_read.export
- ram_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_readdata.export
- ram_diag_data_buffer_ddr_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_reset.export
- ram_diag_data_buffer_ddr_write_export : out std_logic; -- ram_diag_data_buffer_ddr_write.export
- ram_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_writedata.export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- reg_bsn_monitor_1gbe_address.export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
- reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
- reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
- reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
- reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_10gbe_address.export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
- reg_diag_data_buffer_ddr_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_address.export
- reg_diag_data_buffer_ddr_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_clk.export
- reg_diag_data_buffer_ddr_read_export : out std_logic; -- reg_diag_data_buffer_ddr_read.export
- reg_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_readdata.export
- reg_diag_data_buffer_ddr_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_reset.export
- reg_diag_data_buffer_ddr_write_export : out std_logic; -- reg_diag_data_buffer_ddr_write.export
- reg_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_writedata.export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
- reg_diag_rx_seq_ddr_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_address.export
- reg_diag_rx_seq_ddr_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_clk.export
- reg_diag_rx_seq_ddr_read_export : out std_logic; -- reg_diag_rx_seq_ddr_read.export
- reg_diag_rx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_readdata.export
- reg_diag_rx_seq_ddr_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_reset.export
- reg_diag_rx_seq_ddr_write_export : out std_logic; -- reg_diag_rx_seq_ddr_write.export
- reg_diag_rx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_writedata.export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
- reg_diag_tx_seq_ddr_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_address.export
- reg_diag_tx_seq_ddr_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_clk.export
- reg_diag_tx_seq_ddr_read_export : out std_logic; -- reg_diag_tx_seq_ddr_read.export
- reg_diag_tx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_readdata.export
- reg_diag_tx_seq_ddr_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_reset.export
- reg_diag_tx_seq_ddr_write_export : out std_logic; -- reg_diag_tx_seq_ddr_write.export
- reg_diag_tx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_writedata.export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
- reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
- reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
- reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
- reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
- reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
- reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
- reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
- reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
- reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
- reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
- reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
- reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
- reg_io_ddr_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_address.export
- reg_io_ddr_clk_export : out std_logic; -- reg_io_ddr_clk.export
- reg_io_ddr_read_export : out std_logic; -- reg_io_ddr_read.export
- reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_readdata.export
- reg_io_ddr_reset_export : out std_logic; -- reg_io_ddr_reset.export
- reg_io_ddr_write_export : out std_logic; -- reg_io_ddr_write.export
- reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_writedata.export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
- reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
- reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
- reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
- reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
- reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
- reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
- reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
- reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
- reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
- reg_remu_read_export : out std_logic; -- reg_remu_read.export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
- reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
- reg_remu_write_export : out std_logic; -- reg_remu_write.export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
- reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
- reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
- reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
- reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
- reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- reg_unb_sens_address.export
- reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
- reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
- reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
- reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
- reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
- reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
- reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
- reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
- reset_reset_n : in std_logic := '0'; -- reset.reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
- rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
- rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
- rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
- rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
- );
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := '0'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_clk_export : out std_logic; -- export
+ avs_eth_1_irq_export : in std_logic := '0'; -- export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_ram_read_export : out std_logic; -- export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ avs_eth_1_ram_write_export : out std_logic; -- export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_1_reg_read_export : out std_logic; -- export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ avs_eth_1_reg_write_export : out std_logic; -- export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reset_export : out std_logic; -- export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_tse_read_export : out std_logic; -- export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- export
+ avs_eth_1_tse_write_export : out std_logic; -- export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := '0'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0); -- export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_ddr_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ ram_diag_data_buffer_ddr_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_diag_data_buffer_ddr_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_diag_rx_seq_ddr_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_diag_tx_seq_ddr_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_clk_export : out std_logic; -- export
+ reg_io_ddr_read_export : out std_logic; -- export
+ reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_io_ddr_reset_export : out std_logic; -- export
+ reg_io_ddr_write_export : out std_logic; -- export
+ reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := '0'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
end component qsys_unb2_test;
+
END qsys_unb2_test_pkg;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 9e54fb2ebdfe99f2a4b95fc0a390bc2a627dbefb..8308431ca7dc85521bdc9d2abf56677a790faa10 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -144,7 +144,7 @@ ARCHITECTURE str OF unb2_test IS
CONSTANT c_use_10GbE_ring : BOOLEAN := c_use_10GbE;
CONSTANT c_use_10GbE_back0 : BOOLEAN := FALSE;
CONSTANT c_use_10GbE_back1 : BOOLEAN := FALSE;
- CONSTANT c_use_ddr : BOOLEAN := g_design_name="unb2_test_ddr" OR g_design_name="unb2_test_all";
+ CONSTANT c_use_ddr : BOOLEAN := g_design_name="unb2_test_ddr" OR g_design_name="unb2_test_all";
CONSTANT c_use_MB_I : BOOLEAN := c_use_ddr; -- FIXME: g_design_name="unb2_test_MB_I" OR g_design_name="unb2_test_all";
CONSTANT c_use_MB_II : BOOLEAN := FALSE; -- FIXME: g_design_name="unb2_test_MB_II" OR g_design_name="unb2_test_all";
CONSTANT c_use_MB_both : BOOLEAN := FALSE; -- FIXME: c_use_MB_I OR c_use_MB_II;