From 16d93410a5a7cff625162279f120f6ece0ae02ab Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 21 Jan 2015 07:23:18 +0000
Subject: [PATCH] Added DDR4 simulation model for 4GByte and 8Byte. See
README.txt for description.
---
.../ip_arria10/ddr4_mem_model_141/README.txt | 114 ++
.../ddr4_mem_model_141/compile_ip.tcl | 61 +
.../ddr4_mem_model_141/diff_mem_model.sh | 65 +
.../ddr4_mem_model_141/generate_mem_model.sh | 59 +
.../ip_arria10/ddr4_mem_model_141/hdllib.cfg | 14 +
..._sim_altera_emif_mem_model_141_z3tvrmq.vhd | 328 ++++
..._sim_altera_emif_mem_model_141_oes36qy.vhd | 328 ++++
.../ddr4_core/altera_emif_ddr4_crc_tree.sv | 72 +
.../altera_emif_ddr4_model_rcd_chip.sv | 129 ++
.../sim/ddr4_core/altera_emif_ddrx_model.sv | 265 +++
.../altera_emif_ddrx_model_bidir_delay.sv | 53 +
.../altera_emif_ddrx_model_per_device.sv | 362 ++++
.../altera_emif_ddrx_model_per_ping_pong.sv | 186 ++
.../ddr4_core/altera_emif_ddrx_model_rank.sv | 1597 +++++++++++++++++
.../mentor/altera_emif_ddr4_crc_tree.sv | 125 ++
.../mentor/altera_emif_ddr4_model_rcd_chip.sv | 137 ++
.../mentor/altera_emif_ddrx_model.sv | 384 ++++
.../altera_emif_ddrx_model_bidir_delay.sv | 76 +
.../altera_emif_ddrx_model_per_device.sv | 397 ++++
.../altera_emif_ddrx_model_per_ping_pong.sv | 291 +++
.../mentor/altera_emif_ddrx_model_rank.sv | 1423 +++++++++++++++
21 files changed, 6466 insertions(+)
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
create mode 100755 libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
create mode 100755 libraries/technology/ip_arria10/ddr4_mem_model_141/generate_mem_model.sh
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_8g_2400/ed_sim_altera_emif_mem_model_141_oes36qy.vhd
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddr4_crc_tree.sv
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddr4_model_rcd_chip.sv
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model.sv
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_bidir_delay.sv
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_per_device.sv
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_per_ping_pong.sv
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_rank.sv
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddr4_crc_tree.sv
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddr4_model_rcd_chip.sv
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model.sv
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_bidir_delay.sv
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_per_device.sv
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_per_ping_pong.sv
create mode 100644 libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_rank.sv
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt b/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
new file mode 100644
index 0000000000..59bbb65023
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
@@ -0,0 +1,114 @@
+README.txt for $RADIOHDL/libraries/technology/ip_arria10/ddr4_mem_model
+
+1) DDR4 memory simulation model
+2) Automated scripts and one time manual actions
+3) Usage
+3) Remarks
+
+
+1) DDR4 memory simulation model
+
+The DDR memory model is obtained from the example design that can be generated with Qsys when a DDR IP component is defined.
+The first DDR4 component that was created is available via:
+
+ $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys
+
+Unfortunately the example design needs to be created via the GUI by pressing the 'Example Design...' button, because the qsys-generate command
+that is used in ddr4_4g_1600/generate_ip.sh to create the component does not have an option to also create the example design. After that the
+ddr4_mem_model/generate_mem_model.sh needs to be ran to roll out the directories and files of the example design.
+The manual intervenion via the GUI is stands in the way of an automated flow. Therefore the files in the example design that describe the DDR
+memory model have been copied to a fixed location in SVN. In this way it is no longer necessary to create the example design.
+
+In the example design for ddr4_4g_1600 the generic core files of the DDR model are located at:
+
+ $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_core_ddr4_141
+
+The size specific entity of the DDR model is created in:
+
+ $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
+
+The generic core files of the DDR memory model are the same for every DDR size. These files only depend on the Quartus tool version as indicated by 141
+(Quartus 14.1) in their name. Therefore the generic core files have been copied to:
+
+ $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core
+
+The size specific DDR component file is copied to:
+
+ $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
+
+and other size DDR component files can be store there as well.
+
+The ddr4_mem_model_141/sim is kept in SVN. Hence for each new size of DDR memory the example design needs to be created only once. The size specific
+entity of that example design is then copied and kept at ddr4_mem_model_141/sim in SVN. The generic core files of the DDR model are already in SVN,
+but it is good to manually check with Linux 'diff' as in diff_mem_model.sh that they are indeed the same as for a newly generated example design.
+
+ ddr4_mem_model_141/sim/ddr4_core # DDR core model files
+ ddr4_mem_model_141/sim/ddr4_4g_1600 # specific DDR4 size model file
+ ddr4_mem_model_141/sim/ddr4_8g_2400 # specific DDR4 size model file
+
+
+2) Automated scripts and one time manual actions
+
+Relative to $RADIOHDL/libraries/technology/ip_arria10/:
+
+- ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys : Qsys definition file for size and speed specific DDR4 controller
+- ddr4_4g_1600/generate_ip.sh : Use qsys-generate to create the size and speed specific DDR4 controller
+
+- GUI --> open ip_arria10_ddr4_4g_1600.qsys --> press the 'Example Design...' button --> run ddr4_mem_model/generate_mem_model.sh:
+ . ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_core_ddr4_141/*
+ . ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
+
+- Copied these DDR memory model files to ddr4_mem_model_141/sim and commited them to SVN
+
+- ddr4_mem_model/compile_ip.tcl : Modelsim compile HDL script
+
+The ddr4_mem_model/compile_ip.tcl script compiles the HDL files of the DDR4 memory model in the ddr4_mem_model Modelsim project. Therefore
+the ddr4_mem_model/compile_ip.tcl is listed at the modelsim_compile_ip_files key in the ddr4_mem_model/hdllib.cfg
+
+The DDR model ed_sim_altera_emif_mem_model_core_ddr4_141.vhd file assumes that the generic core files are from a VHDL library called
+ed_sim_altera_emif_mem_model_core_ddr4_141. Therefore this name is used as hdl_library_clause_name in the ddr4_mem_model/hdllib.cfg.
+
+Using a dedicated ddr4_mem_model_<version> directory for the DDR memory model is necessary because then it can have a hdllib.cfg and a
+hdl_library_clause_name. Furthermore it is necessary to have a directrory per version, because each version will have another VHDL library
+name and per hdllib.cfg there can only be one hdl_library_clause_name.
+
+
+3) Usage
+
+a) Existing DDR4 memory models
+ Since the DDR4 memory models are in SVN they do not need tobe generated.
+
+b) New DDR4 memory models
+
+ The following procedure shows how the models in SVN can be recreated or how a new device specific DDR4 model can be created.
+ With the DDR4 memory models for the core files and the specific devices ddr4_4g_1600 and ddr4_8g_2400 the following yield no diff.
+
+ > cd ddr4_4g_1600/
+ > ./generate_ip.sh
+ > run_quartus unb2 & # manually open ip_arria10_ddr4_4g_1600.qsys and press the 'Example Design...' button
+ >
+ > cd ../ddr4_8g_2400/
+ > ./generate_ip.sh
+ > run_quartus unb2 & # manually open ip_arria10_ddr4_84g_2400.qsys and press the 'Example Design...' button
+ >
+ > cd ../ddr4_mem_model_141/
+ > ./generate_mem_model.sh ../ddr4_4g_1600/emif_0_example_design
+ > ./generate_mem_model.sh ../ddr4_8g_2400/ddr4_inst_example_design
+
+
+
+4) Remarks
+
+a) If the example design for a specific size DDR could have been created automatically, then probably it would have been preferred to not keep the
+ DDR4 memory model files in SVN.
+
+b) If a new version of Quartus is used then it may be necessary to recreate all the example design model files in a new directory
+ ddr4_mem_model_<version>. However the DDR memory model is plain HDL so strictly speaking it does not depend FPGA device or
+ Quartus version, therefore it should be possible to keep on using the ddr4_mem_model_141. Still a newer version of Quartus
+ may provide a better and faster model.
+
+c) The Quartus 14.1 DDR4 IP and memory model simulate much slower than the DDR3 IP and memory model of Quartus 11.1 that are used for UniBoard1.
+ In simulation it is the memory storage and the access rate that are important, DDR3 and DDR4 are quite similar from that point of view.
+ A work around to speed up simulation in applications could therefore be to use the io_ddr with DDR3 IP to model DDR4. For the DDR4 controller
+ test bench it is of course still necessary to use the DDR4 IP and DDR4 memory model, because that test bench verifies the DDR4 functionality
+ in simulation and shows that it will also work on hardware.
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
new file mode 100644
index 0000000000..ff31689fcc
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
@@ -0,0 +1,61 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on Qsys-generated file $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/mentor/msim_setup.tcl.
+#
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_mem_model_141"
+
+# Assume library work already exists
+vmap ed_sim_altera_emif_mem_model_core_ddr4_141 ./work/
+
+# Compile the design files in correct order and map them all to library work
+
+#------------------------------------------------------------------------------
+# generic DDR memory model core files
+#------------------------------------------------------------------------------
+# . Readable files
+vlog -sv "$IP_DIR/sim/ddr4_core/altera_emif_ddrx_model.sv" -work work
+vlog -sv "$IP_DIR/sim/ddr4_core/altera_emif_ddrx_model_per_ping_pong.sv" -work work
+vlog -sv "$IP_DIR/sim/ddr4_core/altera_emif_ddrx_model_per_device.sv" -work work
+vlog -sv "$IP_DIR/sim/ddr4_core/altera_emif_ddr4_crc_tree.sv" -work work
+vlog -sv "$IP_DIR/sim/ddr4_core/altera_emif_ddrx_model_rank.sv" -work work
+vlog -sv "$IP_DIR/sim/ddr4_core/altera_emif_ddr4_model_rcd_chip.sv" -work work
+vlog -sv "$IP_DIR/sim/ddr4_core/altera_emif_ddrx_model_bidir_delay.sv" -work work
+# . Binary files
+#vlog -sv "$IP_DIR/sim/ddr4_core/mentor/altera_emif_ddrx_model.sv" -work work
+#vlog -sv "$IP_DIR/sim/ddr4_core/mentor/altera_emif_ddrx_model_per_ping_pong.sv" -work work
+#vlog -sv "$IP_DIR/sim/ddr4_core/mentor/altera_emif_ddrx_model_per_device.sv" -work work
+#vlog -sv "$IP_DIR/sim/ddr4_core/mentor/altera_emif_ddr4_crc_tree.sv" -work work
+#vlog -sv "$IP_DIR/sim/ddr4_core/mentor/altera_emif_ddrx_model_rank.sv" -work work
+#vlog -sv "$IP_DIR/sim/ddr4_core/mentor/altera_emif_ddr4_model_rcd_chip.sv" -work work
+#vlog -sv "$IP_DIR/sim/ddr4_core/mentor/altera_emif_ddrx_model_bidir_delay.sv" -work work
+
+
+#------------------------------------------------------------------------------
+# Size specific DDR component files
+#------------------------------------------------------------------------------
+
+# . ddr4_4g_1600
+vcom "$IP_DIR/sim/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd" -work work
+
+# . ddr4_8g_2400
+vcom "$IP_DIR/sim/ddr4_8g_2400/ed_sim_altera_emif_mem_model_141_oes36qy.vhd" -work work
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh b/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
new file mode 100755
index 0000000000..32f282b561
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
@@ -0,0 +1,65 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Compare DDR4 memory model core files with Qsys example design core files
+# Description:
+# The DDR4 memory model core files do not depend on the size and speed of the specific DDR4 example design.
+# Therefore there shouldbe no diffs.
+# Usage:
+#
+# ./diff_mem_model.sh <path to specific DDR4 example design>
+#
+# eg:
+#
+# ./diff_mem_model.sh $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design
+#
+
+EXAMPLE_DESIGN_DIR=${1}
+
+CORE_DIR="${EXAMPLE_DESIGN_DIR}/sim/altera_emif_mem_model_core_ddr4_141/sim"
+
+SIM_DIR="${RADIOHDL}/libraries/technology/ip_arria10/ddr4_mem_model_141/sim"
+
+# DDR4 memory model core files
+diff ${SIM_DIR}/ddr4_core/altera_emif_ddr4_crc_tree.sv ${CORE_DIR}/altera_emif_ddr4_crc_tree.sv
+diff ${SIM_DIR}/ddr4_core/altera_emif_ddr4_model_rcd_chip.sv ${CORE_DIR}/altera_emif_ddr4_model_rcd_chip.sv
+diff ${SIM_DIR}/ddr4_core/altera_emif_ddrx_model_bidir_delay.sv ${CORE_DIR}/altera_emif_ddrx_model_bidir_delay.sv
+diff ${SIM_DIR}/ddr4_core/altera_emif_ddrx_model_per_device.sv ${CORE_DIR}/altera_emif_ddrx_model_per_device.sv
+diff ${SIM_DIR}/ddr4_core/altera_emif_ddrx_model_per_ping_pong.sv ${CORE_DIR}/altera_emif_ddrx_model_per_ping_pong.sv
+diff ${SIM_DIR}/ddr4_core/altera_emif_ddrx_model_rank.sv ${CORE_DIR}/altera_emif_ddrx_model_rank.sv
+diff ${SIM_DIR}/ddr4_core/altera_emif_ddrx_model.sv ${CORE_DIR}/altera_emif_ddrx_model.sv
+
+diff ${SIM_DIR}/ddr4_core/mentor/altera_emif_ddr4_crc_tree.sv ${CORE_DIR}/mentor/altera_emif_ddr4_crc_tree.sv
+diff ${SIM_DIR}/ddr4_core/mentor/altera_emif_ddr4_model_rcd_chip.sv ${CORE_DIR}/mentor/altera_emif_ddr4_model_rcd_chip.sv
+diff ${SIM_DIR}/ddr4_core/mentor/altera_emif_ddrx_model_bidir_delay.sv ${CORE_DIR}/mentor/altera_emif_ddrx_model_bidir_delay.sv
+diff ${SIM_DIR}/ddr4_core/mentor/altera_emif_ddrx_model_per_device.sv ${CORE_DIR}/mentor/altera_emif_ddrx_model_per_device.sv
+diff ${SIM_DIR}/ddr4_core/mentor/altera_emif_ddrx_model_per_ping_pong.sv ${CORE_DIR}/mentor/altera_emif_ddrx_model_per_ping_pong.sv
+diff ${SIM_DIR}/ddr4_core/mentor/altera_emif_ddrx_model_rank.sv ${CORE_DIR}/mentor/altera_emif_ddrx_model_rank.sv
+diff ${SIM_DIR}/ddr4_core/mentor/altera_emif_ddrx_model.sv ${CORE_DIR}/mentor/altera_emif_ddrx_model.sv
+
+# DDR4 memory model device specific files
+DEVICE_DIR="${EXAMPLE_DESIGN_DIR}/sim/altera_emif_mem_model_141/sim"
+
+# Uncomment the line below to check that a recreated device specific DDR4 model is the same asthat in SVN
+#diff ${SIM_DIR}/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd ${DEVICE_DIR}/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
+#diff ${SIM_DIR}/ddr4_8g_2400/ed_sim_altera_emif_mem_model_141_oes36qy.vhd ${DEVICE_DIR}/ed_sim_altera_emif_mem_model_141_oes36qy.vhd
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/generate_mem_model.sh b/libraries/technology/ip_arria10/ddr4_mem_model_141/generate_mem_model.sh
new file mode 100755
index 0000000000..d001ff86d3
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/generate_mem_model.sh
@@ -0,0 +1,59 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate DDR4 memory model with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# Unfortunately the example design with the memory model cannot be created from the qsys-generate command line, because
+# there is no option to invoke this.
+# Therefore first open ip_arria10_ddr4_4g_1600.qsys in the Quartus QUI and then click the 'Example Design...' button.
+# This will then created the emif_0_example_design/ directory that contains the TCL scripts to create the example design.
+#
+# ./generate_mem_model.sh <path to example design directory>
+#
+# eg. for ddr4_4g_1600:
+#
+# ./generate_mem_model.sh ../ddr4_4g_1600/emif_0_example_design
+#
+# eg. for ddr4_8g_2400:
+#
+# ./generate_mem_model.sh ../ddr4_8g_2400/ddr4_inst_example_design
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+EXAMPLE_DESIGN_DIR=${1}
+MODEL_DIR=${RADIOHDL}/libraries/technology/ip_arria10/ddr4_mem_model_141
+
+cd ${EXAMPLE_DESIGN_DIR}
+quartus_sh -t make_sim_design.tcl VHDL
+
+cd ${MODEL_DIR}
+echo "pwd = ${PWD}"
+echo "Run diff_mem_model.sh"
+. diff_mem_model.sh ${EXAMPLE_DESIGN_DIR}
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
new file mode 100644
index 0000000000..a952090c1b
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
@@ -0,0 +1,14 @@
+hdl_lib_name = ip_arria10_ddr4_mem_model_141
+hdl_library_clause_name = ed_sim_altera_emif_mem_model_core_ddr4_141
+hdl_lib_uses =
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
+
+synth_files =
+
+test_bench_files =
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
new file mode 100644
index 0000000000..5d895d529f
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
@@ -0,0 +1,328 @@
+-- ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
+
+-- This file was auto-generated from altera_emif_mem_model_hw.tcl. If you edit it your changes
+-- will probably be lost.
+--
+-- Generated using ACDS version 14.1 186 at 2015.01.12.14:47:37
+
+library IEEE;
+library ed_sim_altera_emif_mem_model_core_ddr4_141;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ed_sim_altera_emif_mem_model_141_z3tvrmq is
+ port (
+ mem_ck : in std_logic_vector(0 downto 0) := (others => '0'); -- mem_conduit_end.mem_ck
+ mem_ck_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_ck_n
+ mem_a : in std_logic_vector(16 downto 0) := (others => '0'); -- .mem_a
+ mem_act_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_act_n
+ mem_ba : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_ba
+ mem_bg : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_bg
+ mem_cke : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_cke
+ mem_cs_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_cs_n
+ mem_odt : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_odt
+ mem_reset_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_reset_n
+ mem_par : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_par
+ mem_alert_n : out std_logic_vector(0 downto 0); -- .mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0') -- .mem_dbi_n
+ );
+end entity ed_sim_altera_emif_mem_model_141_z3tvrmq;
+
+architecture rtl of ed_sim_altera_emif_mem_model_141_z3tvrmq is
+ component altera_emif_ddrx_model is
+ generic (
+ PROTOCOL_ENUM : string := "PROTOCOL_DDR3";
+ PHY_PING_PONG_EN : boolean := false;
+ MEM_FORMAT_ENUM : string := "";
+ PORT_MEM_CK_WIDTH : integer := 1;
+ PORT_MEM_CK_N_WIDTH : integer := 1;
+ PORT_MEM_DK_WIDTH : integer := 1;
+ PORT_MEM_DK_N_WIDTH : integer := 1;
+ PORT_MEM_DKA_WIDTH : integer := 1;
+ PORT_MEM_DKA_N_WIDTH : integer := 1;
+ PORT_MEM_DKB_WIDTH : integer := 1;
+ PORT_MEM_DKB_N_WIDTH : integer := 1;
+ PORT_MEM_K_WIDTH : integer := 1;
+ PORT_MEM_K_N_WIDTH : integer := 1;
+ PORT_MEM_A_WIDTH : integer := 1;
+ PORT_MEM_BA_WIDTH : integer := 1;
+ PORT_MEM_BG_WIDTH : integer := 1;
+ PORT_MEM_C_WIDTH : integer := 1;
+ PORT_MEM_CKE_WIDTH : integer := 1;
+ PORT_MEM_CS_N_WIDTH : integer := 1;
+ PORT_MEM_RM_WIDTH : integer := 1;
+ PORT_MEM_ODT_WIDTH : integer := 1;
+ PORT_MEM_RAS_N_WIDTH : integer := 1;
+ PORT_MEM_CAS_N_WIDTH : integer := 1;
+ PORT_MEM_WE_N_WIDTH : integer := 1;
+ PORT_MEM_RESET_N_WIDTH : integer := 1;
+ PORT_MEM_ACT_N_WIDTH : integer := 1;
+ PORT_MEM_PAR_WIDTH : integer := 1;
+ PORT_MEM_CA_WIDTH : integer := 1;
+ PORT_MEM_REF_N_WIDTH : integer := 1;
+ PORT_MEM_WPS_N_WIDTH : integer := 1;
+ PORT_MEM_RPS_N_WIDTH : integer := 1;
+ PORT_MEM_DOFF_N_WIDTH : integer := 1;
+ PORT_MEM_LDA_N_WIDTH : integer := 1;
+ PORT_MEM_LDB_N_WIDTH : integer := 1;
+ PORT_MEM_RWA_N_WIDTH : integer := 1;
+ PORT_MEM_RWB_N_WIDTH : integer := 1;
+ PORT_MEM_LBK0_N_WIDTH : integer := 1;
+ PORT_MEM_LBK1_N_WIDTH : integer := 1;
+ PORT_MEM_CFG_N_WIDTH : integer := 1;
+ PORT_MEM_AP_WIDTH : integer := 1;
+ PORT_MEM_AINV_WIDTH : integer := 1;
+ PORT_MEM_DM_WIDTH : integer := 1;
+ PORT_MEM_BWS_N_WIDTH : integer := 1;
+ PORT_MEM_D_WIDTH : integer := 1;
+ PORT_MEM_DQ_WIDTH : integer := 1;
+ PORT_MEM_DBI_N_WIDTH : integer := 1;
+ PORT_MEM_DQA_WIDTH : integer := 1;
+ PORT_MEM_DQB_WIDTH : integer := 1;
+ PORT_MEM_DINVA_WIDTH : integer := 1;
+ PORT_MEM_DINVB_WIDTH : integer := 1;
+ PORT_MEM_Q_WIDTH : integer := 1;
+ PORT_MEM_DQS_WIDTH : integer := 1;
+ PORT_MEM_DQS_N_WIDTH : integer := 1;
+ PORT_MEM_QK_WIDTH : integer := 1;
+ PORT_MEM_QK_N_WIDTH : integer := 1;
+ PORT_MEM_QKA_WIDTH : integer := 1;
+ PORT_MEM_QKA_N_WIDTH : integer := 1;
+ PORT_MEM_QKB_WIDTH : integer := 1;
+ PORT_MEM_QKB_N_WIDTH : integer := 1;
+ PORT_MEM_CQ_WIDTH : integer := 1;
+ PORT_MEM_CQ_N_WIDTH : integer := 1;
+ PORT_MEM_ALERT_N_WIDTH : integer := 1;
+ PORT_MEM_PE_N_WIDTH : integer := 1;
+ MEM_DISCRETE_CS_WIDTH : integer := 1;
+ MEM_ROW_ADDR_WIDTH : integer := 15;
+ MEM_COL_ADDR_WIDTH : integer := 10;
+ MEM_TRTP : integer := 8;
+ MEM_TRCD : integer := 8;
+ MEM_RANKS_PER_DIMM : integer := 1;
+ MEM_NUM_OF_DIMMS : integer := 0;
+ MEM_DM_EN : boolean := false;
+ MEM_MIRROR_ADDRESSING_EN : boolean := false;
+ MEM_INIT_MRS0 : integer := 0;
+ MEM_INIT_MRS1 : integer := 0;
+ MEM_INIT_MRS2 : integer := 0;
+ MEM_INIT_MRS3 : integer := 0;
+ MEM_CFG_GEN_SBE : boolean := false;
+ MEM_CFG_GEN_DBE : boolean := false
+ );
+ port (
+ mem_ck : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ck
+ mem_ck_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ck_n
+ mem_a : in std_logic_vector(16 downto 0) := (others => 'X'); -- mem_a
+ mem_act_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_act_n
+ mem_ba : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_ba
+ mem_bg : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_bg
+ mem_cke : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_cke
+ mem_cs_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_cs_n
+ mem_odt : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_odt
+ mem_reset_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_reset_n
+ mem_par : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_par
+ mem_alert_n : out std_logic_vector(0 downto 0); -- mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
+ mem_c : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_c
+ mem_rm : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_rm
+ mem_dk : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dk
+ mem_dk_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dk_n
+ mem_dka : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dka
+ mem_dka_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dka_n
+ mem_dkb : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dkb
+ mem_dkb_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dkb_n
+ mem_k : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_k
+ mem_k_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_k_n
+ mem_ras_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ras_n
+ mem_cas_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_cas_n
+ mem_we_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_we_n
+ mem_ca : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ca
+ mem_ref_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ref_n
+ mem_wps_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_wps_n
+ mem_rps_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_rps_n
+ mem_doff_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_doff_n
+ mem_lda_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_lda_n
+ mem_ldb_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ldb_n
+ mem_rwa_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_rwa_n
+ mem_rwb_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_rwb_n
+ mem_lbk0_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_lbk0_n
+ mem_lbk1_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_lbk1_n
+ mem_cfg_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_cfg_n
+ mem_ap : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ap
+ mem_ainv : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ainv
+ mem_dm : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dm
+ mem_bws_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_bws_n
+ mem_d : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_d
+ mem_dqa : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dqa
+ mem_dqb : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dqb
+ mem_dinva : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dinva
+ mem_dinvb : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dinvb
+ mem_q : out std_logic_vector(0 downto 0); -- mem_q
+ mem_qk : out std_logic_vector(0 downto 0); -- mem_qk
+ mem_qk_n : out std_logic_vector(0 downto 0); -- mem_qk_n
+ mem_qka : out std_logic_vector(0 downto 0); -- mem_qka
+ mem_qka_n : out std_logic_vector(0 downto 0); -- mem_qka_n
+ mem_qkb : out std_logic_vector(0 downto 0); -- mem_qkb
+ mem_qkb_n : out std_logic_vector(0 downto 0); -- mem_qkb_n
+ mem_cq : out std_logic_vector(0 downto 0); -- mem_cq
+ mem_cq_n : out std_logic_vector(0 downto 0); -- mem_cq_n
+ mem_pe_n : out std_logic_vector(0 downto 0) -- mem_pe_n
+ );
+ end component altera_emif_ddrx_model;
+
+ for core : altera_emif_ddrx_model
+ use entity ed_sim_altera_emif_mem_model_core_ddr4_141.altera_emif_ddrx_model;
+begin
+
+ core : component altera_emif_ddrx_model
+ generic map (
+ PROTOCOL_ENUM => "PROTOCOL_DDR4",
+ PHY_PING_PONG_EN => false,
+ MEM_FORMAT_ENUM => "MEM_FORMAT_SODIMM",
+ PORT_MEM_CK_WIDTH => 1,
+ PORT_MEM_CK_N_WIDTH => 1,
+ PORT_MEM_DK_WIDTH => 1,
+ PORT_MEM_DK_N_WIDTH => 1,
+ PORT_MEM_DKA_WIDTH => 1,
+ PORT_MEM_DKA_N_WIDTH => 1,
+ PORT_MEM_DKB_WIDTH => 1,
+ PORT_MEM_DKB_N_WIDTH => 1,
+ PORT_MEM_K_WIDTH => 1,
+ PORT_MEM_K_N_WIDTH => 1,
+ PORT_MEM_A_WIDTH => 17,
+ PORT_MEM_BA_WIDTH => 2,
+ PORT_MEM_BG_WIDTH => 2,
+ PORT_MEM_C_WIDTH => 1,
+ PORT_MEM_CKE_WIDTH => 1,
+ PORT_MEM_CS_N_WIDTH => 1,
+ PORT_MEM_RM_WIDTH => 1,
+ PORT_MEM_ODT_WIDTH => 1,
+ PORT_MEM_RAS_N_WIDTH => 1,
+ PORT_MEM_CAS_N_WIDTH => 1,
+ PORT_MEM_WE_N_WIDTH => 1,
+ PORT_MEM_RESET_N_WIDTH => 1,
+ PORT_MEM_ACT_N_WIDTH => 1,
+ PORT_MEM_PAR_WIDTH => 1,
+ PORT_MEM_CA_WIDTH => 1,
+ PORT_MEM_REF_N_WIDTH => 1,
+ PORT_MEM_WPS_N_WIDTH => 1,
+ PORT_MEM_RPS_N_WIDTH => 1,
+ PORT_MEM_DOFF_N_WIDTH => 1,
+ PORT_MEM_LDA_N_WIDTH => 1,
+ PORT_MEM_LDB_N_WIDTH => 1,
+ PORT_MEM_RWA_N_WIDTH => 1,
+ PORT_MEM_RWB_N_WIDTH => 1,
+ PORT_MEM_LBK0_N_WIDTH => 1,
+ PORT_MEM_LBK1_N_WIDTH => 1,
+ PORT_MEM_CFG_N_WIDTH => 1,
+ PORT_MEM_AP_WIDTH => 1,
+ PORT_MEM_AINV_WIDTH => 1,
+ PORT_MEM_DM_WIDTH => 1,
+ PORT_MEM_BWS_N_WIDTH => 1,
+ PORT_MEM_D_WIDTH => 1,
+ PORT_MEM_DQ_WIDTH => 72,
+ PORT_MEM_DBI_N_WIDTH => 9,
+ PORT_MEM_DQA_WIDTH => 1,
+ PORT_MEM_DQB_WIDTH => 1,
+ PORT_MEM_DINVA_WIDTH => 1,
+ PORT_MEM_DINVB_WIDTH => 1,
+ PORT_MEM_Q_WIDTH => 1,
+ PORT_MEM_DQS_WIDTH => 9,
+ PORT_MEM_DQS_N_WIDTH => 9,
+ PORT_MEM_QK_WIDTH => 1,
+ PORT_MEM_QK_N_WIDTH => 1,
+ PORT_MEM_QKA_WIDTH => 1,
+ PORT_MEM_QKA_N_WIDTH => 1,
+ PORT_MEM_QKB_WIDTH => 1,
+ PORT_MEM_QKB_N_WIDTH => 1,
+ PORT_MEM_CQ_WIDTH => 1,
+ PORT_MEM_CQ_N_WIDTH => 1,
+ PORT_MEM_ALERT_N_WIDTH => 1,
+ PORT_MEM_PE_N_WIDTH => 1,
+ MEM_DISCRETE_CS_WIDTH => 1,
+ MEM_ROW_ADDR_WIDTH => 15,
+ MEM_COL_ADDR_WIDTH => 10,
+ MEM_TRTP => 6,
+ MEM_TRCD => 12,
+ MEM_RANKS_PER_DIMM => 1,
+ MEM_NUM_OF_DIMMS => 1,
+ MEM_DM_EN => true,
+ MEM_MIRROR_ADDRESSING_EN => false,
+ MEM_INIT_MRS0 => 0,
+ MEM_INIT_MRS1 => 0,
+ MEM_INIT_MRS2 => 0,
+ MEM_INIT_MRS3 => 0,
+ MEM_CFG_GEN_SBE => false,
+ MEM_CFG_GEN_DBE => false
+ )
+ port map (
+ mem_ck => mem_ck, -- mem_conduit_end.mem_ck
+ mem_ck_n => mem_ck_n, -- .mem_ck_n
+ mem_a => mem_a, -- .mem_a
+ mem_act_n => mem_act_n, -- .mem_act_n
+ mem_ba => mem_ba, -- .mem_ba
+ mem_bg => mem_bg, -- .mem_bg
+ mem_cke => mem_cke, -- .mem_cke
+ mem_cs_n => mem_cs_n, -- .mem_cs_n
+ mem_odt => mem_odt, -- .mem_odt
+ mem_reset_n => mem_reset_n, -- .mem_reset_n
+ mem_par => mem_par, -- .mem_par
+ mem_alert_n => mem_alert_n, -- .mem_alert_n
+ mem_dqs => mem_dqs, -- .mem_dqs
+ mem_dqs_n => mem_dqs_n, -- .mem_dqs_n
+ mem_dq => mem_dq, -- .mem_dq
+ mem_dbi_n => mem_dbi_n, -- .mem_dbi_n
+ mem_c => "0", -- (terminated)
+ mem_rm => "0", -- (terminated)
+ mem_dk => "0", -- (terminated)
+ mem_dk_n => "0", -- (terminated)
+ mem_dka => "0", -- (terminated)
+ mem_dka_n => "0", -- (terminated)
+ mem_dkb => "0", -- (terminated)
+ mem_dkb_n => "0", -- (terminated)
+ mem_k => "0", -- (terminated)
+ mem_k_n => "0", -- (terminated)
+ mem_ras_n => "0", -- (terminated)
+ mem_cas_n => "0", -- (terminated)
+ mem_we_n => "0", -- (terminated)
+ mem_ca => "0", -- (terminated)
+ mem_ref_n => "0", -- (terminated)
+ mem_wps_n => "0", -- (terminated)
+ mem_rps_n => "0", -- (terminated)
+ mem_doff_n => "0", -- (terminated)
+ mem_lda_n => "0", -- (terminated)
+ mem_ldb_n => "0", -- (terminated)
+ mem_rwa_n => "0", -- (terminated)
+ mem_rwb_n => "0", -- (terminated)
+ mem_lbk0_n => "0", -- (terminated)
+ mem_lbk1_n => "0", -- (terminated)
+ mem_cfg_n => "0", -- (terminated)
+ mem_ap => "0", -- (terminated)
+ mem_ainv => "0", -- (terminated)
+ mem_dm => "0", -- (terminated)
+ mem_bws_n => "0", -- (terminated)
+ mem_d => "0", -- (terminated)
+ mem_dqa => open, -- (terminated)
+ mem_dqb => open, -- (terminated)
+ mem_dinva => open, -- (terminated)
+ mem_dinvb => open, -- (terminated)
+ mem_q => open, -- (terminated)
+ mem_qk => open, -- (terminated)
+ mem_qk_n => open, -- (terminated)
+ mem_qka => open, -- (terminated)
+ mem_qka_n => open, -- (terminated)
+ mem_qkb => open, -- (terminated)
+ mem_qkb_n => open, -- (terminated)
+ mem_cq => open, -- (terminated)
+ mem_cq_n => open, -- (terminated)
+ mem_pe_n => open -- (terminated)
+ );
+
+end architecture rtl; -- of ed_sim_altera_emif_mem_model_141_z3tvrmq
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_8g_2400/ed_sim_altera_emif_mem_model_141_oes36qy.vhd b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_8g_2400/ed_sim_altera_emif_mem_model_141_oes36qy.vhd
new file mode 100644
index 0000000000..ec70888a21
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_8g_2400/ed_sim_altera_emif_mem_model_141_oes36qy.vhd
@@ -0,0 +1,328 @@
+-- ed_sim_altera_emif_mem_model_141_oes36qy.vhd
+
+-- This file was auto-generated from altera_emif_mem_model_hw.tcl. If you edit it your changes
+-- will probably be lost.
+--
+-- Generated using ACDS version 14.1 186 at 2015.01.14.11:33:05
+
+library IEEE;
+library ed_sim_altera_emif_mem_model_core_ddr4_141;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ed_sim_altera_emif_mem_model_141_oes36qy is
+ port (
+ mem_ck : in std_logic_vector(1 downto 0) := (others => '0'); -- mem_conduit_end.mem_ck
+ mem_ck_n : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_ck_n
+ mem_a : in std_logic_vector(16 downto 0) := (others => '0'); -- .mem_a
+ mem_act_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_act_n
+ mem_ba : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_ba
+ mem_bg : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_bg
+ mem_cke : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_cke
+ mem_cs_n : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_cs_n
+ mem_odt : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_odt
+ mem_reset_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_reset_n
+ mem_par : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_par
+ mem_alert_n : out std_logic_vector(0 downto 0); -- .mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0') -- .mem_dbi_n
+ );
+end entity ed_sim_altera_emif_mem_model_141_oes36qy;
+
+architecture rtl of ed_sim_altera_emif_mem_model_141_oes36qy is
+ component altera_emif_ddrx_model is
+ generic (
+ PROTOCOL_ENUM : string := "PROTOCOL_DDR3";
+ PHY_PING_PONG_EN : boolean := false;
+ MEM_FORMAT_ENUM : string := "";
+ PORT_MEM_CK_WIDTH : integer := 1;
+ PORT_MEM_CK_N_WIDTH : integer := 1;
+ PORT_MEM_DK_WIDTH : integer := 1;
+ PORT_MEM_DK_N_WIDTH : integer := 1;
+ PORT_MEM_DKA_WIDTH : integer := 1;
+ PORT_MEM_DKA_N_WIDTH : integer := 1;
+ PORT_MEM_DKB_WIDTH : integer := 1;
+ PORT_MEM_DKB_N_WIDTH : integer := 1;
+ PORT_MEM_K_WIDTH : integer := 1;
+ PORT_MEM_K_N_WIDTH : integer := 1;
+ PORT_MEM_A_WIDTH : integer := 1;
+ PORT_MEM_BA_WIDTH : integer := 1;
+ PORT_MEM_BG_WIDTH : integer := 1;
+ PORT_MEM_C_WIDTH : integer := 1;
+ PORT_MEM_CKE_WIDTH : integer := 1;
+ PORT_MEM_CS_N_WIDTH : integer := 1;
+ PORT_MEM_RM_WIDTH : integer := 1;
+ PORT_MEM_ODT_WIDTH : integer := 1;
+ PORT_MEM_RAS_N_WIDTH : integer := 1;
+ PORT_MEM_CAS_N_WIDTH : integer := 1;
+ PORT_MEM_WE_N_WIDTH : integer := 1;
+ PORT_MEM_RESET_N_WIDTH : integer := 1;
+ PORT_MEM_ACT_N_WIDTH : integer := 1;
+ PORT_MEM_PAR_WIDTH : integer := 1;
+ PORT_MEM_CA_WIDTH : integer := 1;
+ PORT_MEM_REF_N_WIDTH : integer := 1;
+ PORT_MEM_WPS_N_WIDTH : integer := 1;
+ PORT_MEM_RPS_N_WIDTH : integer := 1;
+ PORT_MEM_DOFF_N_WIDTH : integer := 1;
+ PORT_MEM_LDA_N_WIDTH : integer := 1;
+ PORT_MEM_LDB_N_WIDTH : integer := 1;
+ PORT_MEM_RWA_N_WIDTH : integer := 1;
+ PORT_MEM_RWB_N_WIDTH : integer := 1;
+ PORT_MEM_LBK0_N_WIDTH : integer := 1;
+ PORT_MEM_LBK1_N_WIDTH : integer := 1;
+ PORT_MEM_CFG_N_WIDTH : integer := 1;
+ PORT_MEM_AP_WIDTH : integer := 1;
+ PORT_MEM_AINV_WIDTH : integer := 1;
+ PORT_MEM_DM_WIDTH : integer := 1;
+ PORT_MEM_BWS_N_WIDTH : integer := 1;
+ PORT_MEM_D_WIDTH : integer := 1;
+ PORT_MEM_DQ_WIDTH : integer := 1;
+ PORT_MEM_DBI_N_WIDTH : integer := 1;
+ PORT_MEM_DQA_WIDTH : integer := 1;
+ PORT_MEM_DQB_WIDTH : integer := 1;
+ PORT_MEM_DINVA_WIDTH : integer := 1;
+ PORT_MEM_DINVB_WIDTH : integer := 1;
+ PORT_MEM_Q_WIDTH : integer := 1;
+ PORT_MEM_DQS_WIDTH : integer := 1;
+ PORT_MEM_DQS_N_WIDTH : integer := 1;
+ PORT_MEM_QK_WIDTH : integer := 1;
+ PORT_MEM_QK_N_WIDTH : integer := 1;
+ PORT_MEM_QKA_WIDTH : integer := 1;
+ PORT_MEM_QKA_N_WIDTH : integer := 1;
+ PORT_MEM_QKB_WIDTH : integer := 1;
+ PORT_MEM_QKB_N_WIDTH : integer := 1;
+ PORT_MEM_CQ_WIDTH : integer := 1;
+ PORT_MEM_CQ_N_WIDTH : integer := 1;
+ PORT_MEM_ALERT_N_WIDTH : integer := 1;
+ PORT_MEM_PE_N_WIDTH : integer := 1;
+ MEM_DISCRETE_CS_WIDTH : integer := 1;
+ MEM_ROW_ADDR_WIDTH : integer := 15;
+ MEM_COL_ADDR_WIDTH : integer := 10;
+ MEM_TRTP : integer := 8;
+ MEM_TRCD : integer := 8;
+ MEM_RANKS_PER_DIMM : integer := 1;
+ MEM_NUM_OF_DIMMS : integer := 0;
+ MEM_DM_EN : boolean := false;
+ MEM_MIRROR_ADDRESSING_EN : boolean := false;
+ MEM_INIT_MRS0 : integer := 0;
+ MEM_INIT_MRS1 : integer := 0;
+ MEM_INIT_MRS2 : integer := 0;
+ MEM_INIT_MRS3 : integer := 0;
+ MEM_CFG_GEN_SBE : boolean := false;
+ MEM_CFG_GEN_DBE : boolean := false
+ );
+ port (
+ mem_ck : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_ck
+ mem_ck_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_ck_n
+ mem_a : in std_logic_vector(16 downto 0) := (others => 'X'); -- mem_a
+ mem_act_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_act_n
+ mem_ba : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_ba
+ mem_bg : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_bg
+ mem_cke : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_cke
+ mem_cs_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_cs_n
+ mem_odt : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_odt
+ mem_reset_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_reset_n
+ mem_par : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_par
+ mem_alert_n : out std_logic_vector(0 downto 0); -- mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
+ mem_c : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_c
+ mem_rm : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_rm
+ mem_dk : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dk
+ mem_dk_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dk_n
+ mem_dka : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dka
+ mem_dka_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dka_n
+ mem_dkb : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dkb
+ mem_dkb_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dkb_n
+ mem_k : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_k
+ mem_k_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_k_n
+ mem_ras_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ras_n
+ mem_cas_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_cas_n
+ mem_we_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_we_n
+ mem_ca : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ca
+ mem_ref_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ref_n
+ mem_wps_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_wps_n
+ mem_rps_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_rps_n
+ mem_doff_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_doff_n
+ mem_lda_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_lda_n
+ mem_ldb_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ldb_n
+ mem_rwa_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_rwa_n
+ mem_rwb_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_rwb_n
+ mem_lbk0_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_lbk0_n
+ mem_lbk1_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_lbk1_n
+ mem_cfg_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_cfg_n
+ mem_ap : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ap
+ mem_ainv : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ainv
+ mem_dm : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dm
+ mem_bws_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_bws_n
+ mem_d : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_d
+ mem_dqa : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dqa
+ mem_dqb : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dqb
+ mem_dinva : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dinva
+ mem_dinvb : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dinvb
+ mem_q : out std_logic_vector(0 downto 0); -- mem_q
+ mem_qk : out std_logic_vector(0 downto 0); -- mem_qk
+ mem_qk_n : out std_logic_vector(0 downto 0); -- mem_qk_n
+ mem_qka : out std_logic_vector(0 downto 0); -- mem_qka
+ mem_qka_n : out std_logic_vector(0 downto 0); -- mem_qka_n
+ mem_qkb : out std_logic_vector(0 downto 0); -- mem_qkb
+ mem_qkb_n : out std_logic_vector(0 downto 0); -- mem_qkb_n
+ mem_cq : out std_logic_vector(0 downto 0); -- mem_cq
+ mem_cq_n : out std_logic_vector(0 downto 0); -- mem_cq_n
+ mem_pe_n : out std_logic_vector(0 downto 0) -- mem_pe_n
+ );
+ end component altera_emif_ddrx_model;
+
+ for core : altera_emif_ddrx_model
+ use entity ed_sim_altera_emif_mem_model_core_ddr4_141.altera_emif_ddrx_model;
+begin
+
+ core : component altera_emif_ddrx_model
+ generic map (
+ PROTOCOL_ENUM => "PROTOCOL_DDR4",
+ PHY_PING_PONG_EN => false,
+ MEM_FORMAT_ENUM => "MEM_FORMAT_SODIMM",
+ PORT_MEM_CK_WIDTH => 2,
+ PORT_MEM_CK_N_WIDTH => 2,
+ PORT_MEM_DK_WIDTH => 1,
+ PORT_MEM_DK_N_WIDTH => 1,
+ PORT_MEM_DKA_WIDTH => 1,
+ PORT_MEM_DKA_N_WIDTH => 1,
+ PORT_MEM_DKB_WIDTH => 1,
+ PORT_MEM_DKB_N_WIDTH => 1,
+ PORT_MEM_K_WIDTH => 1,
+ PORT_MEM_K_N_WIDTH => 1,
+ PORT_MEM_A_WIDTH => 17,
+ PORT_MEM_BA_WIDTH => 2,
+ PORT_MEM_BG_WIDTH => 2,
+ PORT_MEM_C_WIDTH => 1,
+ PORT_MEM_CKE_WIDTH => 2,
+ PORT_MEM_CS_N_WIDTH => 2,
+ PORT_MEM_RM_WIDTH => 1,
+ PORT_MEM_ODT_WIDTH => 2,
+ PORT_MEM_RAS_N_WIDTH => 1,
+ PORT_MEM_CAS_N_WIDTH => 1,
+ PORT_MEM_WE_N_WIDTH => 1,
+ PORT_MEM_RESET_N_WIDTH => 1,
+ PORT_MEM_ACT_N_WIDTH => 1,
+ PORT_MEM_PAR_WIDTH => 1,
+ PORT_MEM_CA_WIDTH => 1,
+ PORT_MEM_REF_N_WIDTH => 1,
+ PORT_MEM_WPS_N_WIDTH => 1,
+ PORT_MEM_RPS_N_WIDTH => 1,
+ PORT_MEM_DOFF_N_WIDTH => 1,
+ PORT_MEM_LDA_N_WIDTH => 1,
+ PORT_MEM_LDB_N_WIDTH => 1,
+ PORT_MEM_RWA_N_WIDTH => 1,
+ PORT_MEM_RWB_N_WIDTH => 1,
+ PORT_MEM_LBK0_N_WIDTH => 1,
+ PORT_MEM_LBK1_N_WIDTH => 1,
+ PORT_MEM_CFG_N_WIDTH => 1,
+ PORT_MEM_AP_WIDTH => 1,
+ PORT_MEM_AINV_WIDTH => 1,
+ PORT_MEM_DM_WIDTH => 1,
+ PORT_MEM_BWS_N_WIDTH => 1,
+ PORT_MEM_D_WIDTH => 1,
+ PORT_MEM_DQ_WIDTH => 72,
+ PORT_MEM_DBI_N_WIDTH => 9,
+ PORT_MEM_DQA_WIDTH => 1,
+ PORT_MEM_DQB_WIDTH => 1,
+ PORT_MEM_DINVA_WIDTH => 1,
+ PORT_MEM_DINVB_WIDTH => 1,
+ PORT_MEM_Q_WIDTH => 1,
+ PORT_MEM_DQS_WIDTH => 9,
+ PORT_MEM_DQS_N_WIDTH => 9,
+ PORT_MEM_QK_WIDTH => 1,
+ PORT_MEM_QK_N_WIDTH => 1,
+ PORT_MEM_QKA_WIDTH => 1,
+ PORT_MEM_QKA_N_WIDTH => 1,
+ PORT_MEM_QKB_WIDTH => 1,
+ PORT_MEM_QKB_N_WIDTH => 1,
+ PORT_MEM_CQ_WIDTH => 1,
+ PORT_MEM_CQ_N_WIDTH => 1,
+ PORT_MEM_ALERT_N_WIDTH => 1,
+ PORT_MEM_PE_N_WIDTH => 1,
+ MEM_DISCRETE_CS_WIDTH => 1,
+ MEM_ROW_ADDR_WIDTH => 15,
+ MEM_COL_ADDR_WIDTH => 10,
+ MEM_TRTP => 9,
+ MEM_TRCD => 17,
+ MEM_RANKS_PER_DIMM => 2,
+ MEM_NUM_OF_DIMMS => 1,
+ MEM_DM_EN => true,
+ MEM_MIRROR_ADDRESSING_EN => false,
+ MEM_INIT_MRS0 => 0,
+ MEM_INIT_MRS1 => 0,
+ MEM_INIT_MRS2 => 0,
+ MEM_INIT_MRS3 => 0,
+ MEM_CFG_GEN_SBE => false,
+ MEM_CFG_GEN_DBE => false
+ )
+ port map (
+ mem_ck => mem_ck, -- mem_conduit_end.mem_ck
+ mem_ck_n => mem_ck_n, -- .mem_ck_n
+ mem_a => mem_a, -- .mem_a
+ mem_act_n => mem_act_n, -- .mem_act_n
+ mem_ba => mem_ba, -- .mem_ba
+ mem_bg => mem_bg, -- .mem_bg
+ mem_cke => mem_cke, -- .mem_cke
+ mem_cs_n => mem_cs_n, -- .mem_cs_n
+ mem_odt => mem_odt, -- .mem_odt
+ mem_reset_n => mem_reset_n, -- .mem_reset_n
+ mem_par => mem_par, -- .mem_par
+ mem_alert_n => mem_alert_n, -- .mem_alert_n
+ mem_dqs => mem_dqs, -- .mem_dqs
+ mem_dqs_n => mem_dqs_n, -- .mem_dqs_n
+ mem_dq => mem_dq, -- .mem_dq
+ mem_dbi_n => mem_dbi_n, -- .mem_dbi_n
+ mem_c => "0", -- (terminated)
+ mem_rm => "0", -- (terminated)
+ mem_dk => "0", -- (terminated)
+ mem_dk_n => "0", -- (terminated)
+ mem_dka => "0", -- (terminated)
+ mem_dka_n => "0", -- (terminated)
+ mem_dkb => "0", -- (terminated)
+ mem_dkb_n => "0", -- (terminated)
+ mem_k => "0", -- (terminated)
+ mem_k_n => "0", -- (terminated)
+ mem_ras_n => "0", -- (terminated)
+ mem_cas_n => "0", -- (terminated)
+ mem_we_n => "0", -- (terminated)
+ mem_ca => "0", -- (terminated)
+ mem_ref_n => "0", -- (terminated)
+ mem_wps_n => "0", -- (terminated)
+ mem_rps_n => "0", -- (terminated)
+ mem_doff_n => "0", -- (terminated)
+ mem_lda_n => "0", -- (terminated)
+ mem_ldb_n => "0", -- (terminated)
+ mem_rwa_n => "0", -- (terminated)
+ mem_rwb_n => "0", -- (terminated)
+ mem_lbk0_n => "0", -- (terminated)
+ mem_lbk1_n => "0", -- (terminated)
+ mem_cfg_n => "0", -- (terminated)
+ mem_ap => "0", -- (terminated)
+ mem_ainv => "0", -- (terminated)
+ mem_dm => "0", -- (terminated)
+ mem_bws_n => "0", -- (terminated)
+ mem_d => "0", -- (terminated)
+ mem_dqa => open, -- (terminated)
+ mem_dqb => open, -- (terminated)
+ mem_dinva => open, -- (terminated)
+ mem_dinvb => open, -- (terminated)
+ mem_q => open, -- (terminated)
+ mem_qk => open, -- (terminated)
+ mem_qk_n => open, -- (terminated)
+ mem_qka => open, -- (terminated)
+ mem_qka_n => open, -- (terminated)
+ mem_qkb => open, -- (terminated)
+ mem_qkb_n => open, -- (terminated)
+ mem_cq => open, -- (terminated)
+ mem_cq_n => open, -- (terminated)
+ mem_pe_n => open -- (terminated)
+ );
+
+end architecture rtl; -- of ed_sim_altera_emif_mem_model_141_oes36qy
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddr4_crc_tree.sv b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddr4_crc_tree.sv
new file mode 100644
index 0000000000..bfbaed8bd6
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddr4_crc_tree.sv
@@ -0,0 +1,72 @@
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+module altera_emif_ddr4_crc_tree (
+ d,
+ newcrc
+
+);
+timeunit 1ps;
+timeprecision 1ps;
+
+input [71:0] d;
+output [7:0] newcrc;
+
+assign newcrc[0] = d[69] ^ d[68] ^ d[67] ^ d[66] ^ d[64] ^ d[63] ^ d[60] ^
+ d[56] ^ d[54] ^ d[53] ^ d[52] ^ d[50] ^ d[49] ^ d[48] ^
+ d[45] ^ d[43] ^ d[40] ^ d[39] ^ d[35] ^ d[34] ^ d[31] ^
+ d[30] ^ d[28] ^ d[23] ^ d[21] ^ d[19] ^ d[18] ^ d[16] ^
+ d[14] ^ d[12] ^ d[8] ^ d[7] ^ d[6] ^ d[0] ;
+assign newcrc[1] = d[70] ^ d[66] ^ d[65] ^ d[63] ^ d[61] ^ d[60] ^ d[57] ^
+ d[56] ^ d[55] ^ d[52] ^ d[51] ^ d[48] ^ d[46] ^ d[45] ^
+ d[44] ^ d[43] ^ d[41] ^ d[39] ^ d[36] ^ d[34] ^ d[32] ^
+ d[30] ^ d[29] ^ d[28] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^
+ d[20] ^ d[18] ^ d[17] ^ d[16] ^ d[15] ^ d[14] ^ d[13] ^
+ d[12] ^ d[9] ^ d[6] ^ d[1] ^ d[0];
+assign newcrc[2] = d[71] ^ d[69] ^ d[68] ^ d[63] ^ d[62] ^ d[61] ^ d[60] ^
+ d[58] ^ d[57] ^ d[54] ^ d[50] ^ d[48] ^ d[47] ^ d[46] ^
+ d[44] ^ d[43] ^ d[42] ^ d[39] ^ d[37] ^ d[34] ^ d[33] ^
+ d[29] ^ d[28] ^ d[25] ^ d[24] ^ d[22] ^ d[17] ^ d[15] ^
+ d[13] ^ d[12] ^ d[10] ^ d[8] ^ d[6] ^ d[2] ^ d[1] ^ d[0];
+assign newcrc[3] = d[70] ^ d[69] ^ d[64] ^ d[63] ^ d[62] ^ d[61] ^ d[59] ^
+ d[58] ^ d[55] ^ d[51] ^ d[49] ^ d[48] ^ d[47] ^ d[45] ^
+ d[44] ^ d[43] ^ d[40] ^ d[38] ^ d[35] ^ d[34] ^ d[30] ^
+ d[29] ^ d[26] ^ d[25] ^ d[23] ^ d[18] ^ d[16] ^ d[14] ^
+ d[13] ^ d[11] ^ d[9] ^ d[7] ^ d[3] ^ d[2] ^ d[1];
+assign newcrc[4] = d[71] ^ d[70] ^ d[65] ^ d[64] ^ d[63] ^ d[62] ^ d[60] ^
+ d[59] ^ d[56] ^ d[52] ^ d[50] ^ d[49] ^ d[48] ^ d[46] ^
+ d[45] ^ d[44] ^ d[41] ^ d[39] ^ d[36] ^ d[35] ^ d[31] ^
+ d[30] ^ d[27] ^ d[26] ^ d[24] ^ d[19] ^ d[17] ^ d[15] ^
+ d[14] ^ d[12] ^ d[10] ^ d[8] ^ d[4] ^ d[3] ^ d[2];
+assign newcrc[5] = d[71] ^ d[66] ^ d[65] ^ d[64] ^ d[63] ^ d[61] ^ d[60] ^
+ d[57] ^ d[53] ^ d[51] ^ d[50] ^ d[49] ^ d[47] ^ d[46] ^
+ d[45] ^ d[42] ^ d[40] ^ d[37] ^ d[36] ^ d[32] ^ d[31] ^
+ d[28] ^ d[27] ^ d[25] ^ d[20] ^ d[18] ^ d[16] ^ d[15] ^
+ d[13] ^ d[11] ^ d[9] ^ d[5] ^ d[4] ^ d[3];
+assign newcrc[6] = d[67] ^ d[66] ^ d[65] ^ d[64] ^ d[62] ^ d[61] ^ d[58] ^
+ d[54] ^ d[52] ^ d[51] ^ d[50] ^ d[48] ^ d[47] ^ d[46] ^
+ d[43] ^ d[41] ^ d[38] ^ d[37] ^ d[33] ^ d[32] ^ d[29] ^
+ d[28] ^ d[26] ^ d[21] ^ d[19] ^ d[17] ^ d[16] ^ d[14] ^
+ d[12] ^ d[10] ^ d[6] ^ d[5] ^ d[4];
+assign newcrc[7] = d[68] ^ d[67] ^ d[66] ^ d[65] ^ d[63] ^ d[62] ^ d[59] ^
+ d[55] ^ d[53] ^ d[52] ^ d[51] ^ d[49] ^ d[48] ^ d[47] ^
+ d[44] ^ d[42] ^ d[39] ^ d[38] ^ d[34] ^ d[33] ^ d[30] ^
+ d[29] ^ d[27] ^ d[22] ^ d[20] ^ d[18] ^ d[17] ^ d[15] ^
+ d[13] ^ d[11] ^ d[7] ^ d[6] ^ d[5];
+
+
+
+endmodule
+
+
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddr4_model_rcd_chip.sv b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddr4_model_rcd_chip.sv
new file mode 100644
index 0000000000..94d78bcf91
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddr4_model_rcd_chip.sv
@@ -0,0 +1,129 @@
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Basic simulation model of DDR4 Registering Clock Driver used by RDIMM and LRDIMM
+//
+///////////////////////////////////////////////////////////////////////////////
+module altera_emif_ddr4_model_rcd_chip # (
+ parameter ADDRESS_MIRRORING = 1
+) (
+ input [1:0] DCKE,
+ input [1:0] DODT,
+ input [3:0] DCS_n,
+ input [2:0] DC,
+
+ input [17:0] DA,
+ input [1:0] DBA,
+ input [1:0] DBG,
+ input DACT_n,
+
+ input CK_t,
+ input CK_c,
+
+ input DRST_n,
+
+ input DPAR,
+
+ input ERROR_IN_n,
+
+ output BODT,
+ output BCKE,
+ output [3:0] BCOM,
+ output BCK_t,
+ output BCK_c,
+ output BVrefCA,
+
+ output logic [1:0] QACKE,
+ output logic [1:0] QBCKE,
+ output logic [1:0] QAODT,
+ output logic [1:0] QBODT,
+ output logic [3:0] QACS_n,
+ output logic [3:0] QBCS_n,
+ output logic [1:0] QAC,
+ output logic [1:0] QBC,
+
+ output logic [17:0] QAA,
+ output logic [17:0] QBA,
+ output logic [1:0] QABA,
+ output logic [1:0] QABG,
+ output logic [1:0] QBBA,
+ output logic [1:0] QBBG,
+ output logic QAACT_n,
+ output logic QBACT_n,
+
+ output [3:0] Y_c,
+ output [3:0] Y_t,
+
+ output logic QRST_n,
+
+ output logic QAPAR,
+ output logic QBPAR,
+
+ output logic ALERT_n,
+
+ inout SDA,
+ input [2:0] SA,
+ input SCL,
+ input BFUNC,
+ input VDDSPD,
+
+ input VDD,
+ input VSS,
+ input AVDD,
+ input PVDD,
+ input PVSS
+);
+
+ timeunit 1ps;
+ timeprecision 1ps;
+
+ assign Y_t = {4{CK_t}};
+ assign Y_c = {4{CK_c}};
+
+ assign QRST_n = DRST_n;
+
+ reg [1:0] DCKE_1;
+ reg [1:0] DCKE_2;
+
+ assign QACKE = DCKE_1 || DCKE_2;
+ assign QBCKE = DCKE_1 || DCKE_2;
+
+ assign ALERT_n = ERROR_IN_n;
+
+ always @ (*)
+ begin
+ QAA <= repeat(2) @(negedge CK_t) DA;
+ QBA <= repeat(2) @(negedge CK_t) ((ADDRESS_MIRRORING) ? ({~DA[17], DA[16:14], ~DA[11], DA[12], ~DA[13], DA[10], ~DA[9], ~DA[7], ~DA[8], ~DA[5], ~DA[6], ~DA[3], ~DA[4], DA[2:0]}) : ({~DA[17], DA[16:14], ~DA[13], DA[12], ~DA[11], DA[10], ~DA[9:3], DA[2:0]}));
+ QABA <= repeat(2) @(negedge CK_t) DBA;
+ QBBA <= repeat(2) @(negedge CK_t) ((ADDRESS_MIRRORING) ? ({~DBA[0], ~DBA[1]}) : (~DBA));
+ QABG <= repeat(2) @(negedge CK_t) DBG;
+ QBBG <= repeat(2) @(negedge CK_t) ((ADDRESS_MIRRORING) ? ({~DBG[0], ~DBG[1]}) : (~DBG));
+ QAACT_n <= repeat(2) @(negedge CK_t) DACT_n;
+ QBACT_n <= repeat(2) @(negedge CK_t) DACT_n;
+ QACS_n <= repeat(2) @(negedge CK_t) DCS_n;
+ QBCS_n <= repeat(2) @(negedge CK_t) DCS_n;
+ QAC <= repeat(2) @(negedge CK_t) DC;
+ QBC <= repeat(2) @(negedge CK_t) DC;
+ QAODT <= repeat(2) @(negedge CK_t) DODT;
+ QBODT <= repeat(2) @(negedge CK_t) DODT;
+
+ DCKE_2 <= repeat(2) @(negedge CK_t) DCKE;
+ DCKE_1 <= repeat(1) @(negedge CK_t) DCKE;
+
+ QAPAR <= repeat(1) @(negedge CK_t) DPAR;
+ QBPAR <= repeat(1) @(negedge CK_t) ~DPAR;
+ end
+
+endmodule
+
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model.sv b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model.sv
new file mode 100644
index 0000000000..b9087aba31
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model.sv
@@ -0,0 +1,265 @@
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Top-level wrapper of memory model
+//
+///////////////////////////////////////////////////////////////////////////////
+module altera_emif_ddrx_model # (
+ parameter PROTOCOL_ENUM = "",
+ parameter MEM_FORMAT_ENUM = "",
+ parameter PHY_PING_PONG_EN = 0,
+ parameter MEM_RANKS_PER_DIMM = 0,
+ parameter MEM_NUM_OF_DIMMS = 0,
+ parameter MEM_DM_EN = 0,
+ parameter MEM_AC_PAR_EN = 0,
+
+ parameter MEM_DISCRETE_CS_WIDTH = 1,
+ parameter MEM_ROW_ADDR_WIDTH = 1,
+ parameter MEM_COL_ADDR_WIDTH = 1,
+
+ parameter MEM_TRTP = 0,
+ parameter MEM_TRCD = 0,
+ parameter MEM_MIRROR_ADDRESSING_EN = 0,
+ parameter MEM_INIT_MRS0 = 0,
+ parameter MEM_INIT_MRS1 = 0,
+ parameter MEM_INIT_MRS2 = 0,
+ parameter MEM_INIT_MRS3 = 0,
+ parameter MEM_CFG_GEN_SBE = 0,
+ parameter MEM_CFG_GEN_DBE = 0,
+
+ // Definition of port widths for "mem" interface
+ parameter PORT_MEM_CK_WIDTH = 1,
+ parameter PORT_MEM_CK_N_WIDTH = 1,
+ parameter PORT_MEM_DK_WIDTH = 1,
+ parameter PORT_MEM_DK_N_WIDTH = 1,
+ parameter PORT_MEM_DKA_WIDTH = 1,
+ parameter PORT_MEM_DKA_N_WIDTH = 1,
+ parameter PORT_MEM_DKB_WIDTH = 1,
+ parameter PORT_MEM_DKB_N_WIDTH = 1,
+ parameter PORT_MEM_K_WIDTH = 1,
+ parameter PORT_MEM_K_N_WIDTH = 1,
+ parameter PORT_MEM_A_WIDTH = 1,
+ parameter PORT_MEM_BA_WIDTH = 1,
+ parameter PORT_MEM_BG_WIDTH = 1,
+ parameter PORT_MEM_C_WIDTH = 1,
+ parameter PORT_MEM_CKE_WIDTH = 1,
+ parameter PORT_MEM_CS_N_WIDTH = 1,
+ parameter PORT_MEM_RM_WIDTH = 1,
+ parameter PORT_MEM_ODT_WIDTH = 1,
+ parameter PORT_MEM_RAS_N_WIDTH = 1,
+ parameter PORT_MEM_CAS_N_WIDTH = 1,
+ parameter PORT_MEM_WE_N_WIDTH = 1,
+ parameter PORT_MEM_RESET_N_WIDTH = 1,
+ parameter PORT_MEM_ACT_N_WIDTH = 1,
+ parameter PORT_MEM_PAR_WIDTH = 1,
+ parameter PORT_MEM_CA_WIDTH = 1,
+ parameter PORT_MEM_REF_N_WIDTH = 1,
+ parameter PORT_MEM_WPS_N_WIDTH = 1,
+ parameter PORT_MEM_RPS_N_WIDTH = 1,
+ parameter PORT_MEM_DOFF_N_WIDTH = 1,
+ parameter PORT_MEM_LDA_N_WIDTH = 1,
+ parameter PORT_MEM_LDB_N_WIDTH = 1,
+ parameter PORT_MEM_RWA_N_WIDTH = 1,
+ parameter PORT_MEM_RWB_N_WIDTH = 1,
+ parameter PORT_MEM_LBK0_N_WIDTH = 1,
+ parameter PORT_MEM_LBK1_N_WIDTH = 1,
+ parameter PORT_MEM_CFG_N_WIDTH = 1,
+ parameter PORT_MEM_AP_WIDTH = 1,
+ parameter PORT_MEM_PE_N_WIDTH = 1,
+ parameter PORT_MEM_AINV_WIDTH = 1,
+ parameter PORT_MEM_DM_WIDTH = 1,
+ parameter PORT_MEM_BWS_N_WIDTH = 1,
+ parameter PORT_MEM_D_WIDTH = 1,
+ parameter PORT_MEM_DQ_WIDTH = 1,
+ parameter PORT_MEM_DBI_N_WIDTH = 1,
+ parameter PORT_MEM_DQA_WIDTH = 1,
+ parameter PORT_MEM_DQB_WIDTH = 1,
+ parameter PORT_MEM_DINVA_WIDTH = 1,
+ parameter PORT_MEM_DINVB_WIDTH = 1,
+ parameter PORT_MEM_Q_WIDTH = 1,
+ parameter PORT_MEM_ALERT_N_WIDTH = 1,
+ parameter PORT_MEM_DQS_WIDTH = 1,
+ parameter PORT_MEM_DQS_N_WIDTH = 1,
+ parameter PORT_MEM_QK_WIDTH = 1,
+ parameter PORT_MEM_QK_N_WIDTH = 1,
+ parameter PORT_MEM_QKA_WIDTH = 1,
+ parameter PORT_MEM_QKA_N_WIDTH = 1,
+ parameter PORT_MEM_QKB_WIDTH = 1,
+ parameter PORT_MEM_QKB_N_WIDTH = 1,
+ parameter PORT_MEM_CQ_WIDTH = 1,
+ parameter PORT_MEM_CQ_N_WIDTH = 1
+) (
+ // Ports for "mem" interface
+ input logic [PORT_MEM_CK_WIDTH-1:0] mem_ck,
+ input logic [PORT_MEM_CK_N_WIDTH-1:0] mem_ck_n,
+ input logic [PORT_MEM_DK_WIDTH-1:0] mem_dk,
+ input logic [PORT_MEM_DK_N_WIDTH-1:0] mem_dk_n,
+ input logic [PORT_MEM_DKA_WIDTH-1:0] mem_dka,
+ input logic [PORT_MEM_DKA_N_WIDTH-1:0] mem_dka_n,
+ input logic [PORT_MEM_DKB_WIDTH-1:0] mem_dkb,
+ input logic [PORT_MEM_DKB_N_WIDTH-1:0] mem_dkb_n,
+ input logic [PORT_MEM_K_WIDTH-1:0] mem_k,
+ input logic [PORT_MEM_K_N_WIDTH-1:0] mem_k_n,
+ input logic [PORT_MEM_A_WIDTH-1:0] mem_a,
+ input logic [PORT_MEM_BA_WIDTH-1:0] mem_ba,
+ input logic [PORT_MEM_BG_WIDTH-1:0] mem_bg,
+ input logic [PORT_MEM_C_WIDTH-1:0] mem_c,
+ input logic [PORT_MEM_CKE_WIDTH-1:0] mem_cke,
+ input logic [PORT_MEM_CS_N_WIDTH-1:0] mem_cs_n,
+ input logic [PORT_MEM_RM_WIDTH-1:0] mem_rm,
+ input logic [PORT_MEM_ODT_WIDTH-1:0] mem_odt,
+ input logic [PORT_MEM_RAS_N_WIDTH-1:0] mem_ras_n,
+ input logic [PORT_MEM_CAS_N_WIDTH-1:0] mem_cas_n,
+ input logic [PORT_MEM_WE_N_WIDTH-1:0] mem_we_n,
+ input logic [PORT_MEM_RESET_N_WIDTH-1:0] mem_reset_n,
+ input logic [PORT_MEM_ACT_N_WIDTH-1:0] mem_act_n,
+ input logic [PORT_MEM_PAR_WIDTH-1:0] mem_par,
+ input logic [PORT_MEM_CA_WIDTH-1:0] mem_ca,
+ input logic [PORT_MEM_REF_N_WIDTH-1:0] mem_ref_n,
+ input logic [PORT_MEM_WPS_N_WIDTH-1:0] mem_wps_n,
+ input logic [PORT_MEM_RPS_N_WIDTH-1:0] mem_rps_n,
+ input logic [PORT_MEM_DOFF_N_WIDTH-1:0] mem_doff_n,
+ input logic [PORT_MEM_LDA_N_WIDTH-1:0] mem_lda_n,
+ input logic [PORT_MEM_LDB_N_WIDTH-1:0] mem_ldb_n,
+ input logic [PORT_MEM_RWA_N_WIDTH-1:0] mem_rwa_n,
+ input logic [PORT_MEM_RWB_N_WIDTH-1:0] mem_rwb_n,
+ input logic [PORT_MEM_LBK0_N_WIDTH-1:0] mem_lbk0_n,
+ input logic [PORT_MEM_LBK1_N_WIDTH-1:0] mem_lbk1_n,
+ input logic [PORT_MEM_CFG_N_WIDTH-1:0] mem_cfg_n,
+ input logic [PORT_MEM_AP_WIDTH-1:0] mem_ap,
+ output logic [PORT_MEM_PE_N_WIDTH-1:0] mem_pe_n,
+ input logic [PORT_MEM_AINV_WIDTH-1:0] mem_ainv,
+ input logic [PORT_MEM_DM_WIDTH-1:0] mem_dm,
+ input logic [PORT_MEM_BWS_N_WIDTH-1:0] mem_bws_n,
+ input logic [PORT_MEM_D_WIDTH-1:0] mem_d,
+ inout tri [PORT_MEM_DQ_WIDTH-1:0] mem_dq,
+ inout tri [PORT_MEM_DBI_N_WIDTH-1:0] mem_dbi_n,
+ inout tri [PORT_MEM_DQA_WIDTH-1:0] mem_dqa,
+ inout tri [PORT_MEM_DQB_WIDTH-1:0] mem_dqb,
+ inout tri [PORT_MEM_DINVA_WIDTH-1:0] mem_dinva,
+ inout tri [PORT_MEM_DINVB_WIDTH-1:0] mem_dinvb,
+ output logic [PORT_MEM_Q_WIDTH-1:0] mem_q,
+ output logic [PORT_MEM_ALERT_N_WIDTH-1:0] mem_alert_n,
+ inout tri [PORT_MEM_DQS_WIDTH-1:0] mem_dqs,
+ inout tri [PORT_MEM_DQS_N_WIDTH-1:0] mem_dqs_n,
+ output logic [PORT_MEM_QK_WIDTH-1:0] mem_qk,
+ output logic [PORT_MEM_QK_N_WIDTH-1:0] mem_qk_n,
+ output logic [PORT_MEM_QKA_WIDTH-1:0] mem_qka,
+ output logic [PORT_MEM_QKA_N_WIDTH-1:0] mem_qka_n,
+ output logic [PORT_MEM_QKB_WIDTH-1:0] mem_qkb,
+ output logic [PORT_MEM_QKB_N_WIDTH-1:0] mem_qkb_n,
+ output logic [PORT_MEM_CQ_WIDTH-1:0] mem_cq,
+ output logic [PORT_MEM_CQ_N_WIDTH-1:0] mem_cq_n
+);
+ timeunit 1ps;
+ timeprecision 1ps;
+
+ // The first level of the memory model (i.e. this module) acts as a bus
+ // "splitter" for ping-pong PHY configuration. In ping-pong mode, the
+ // memory bus consists of signals for two logically-independent
+ // interfaces. The two interfaces however share the same physical
+ // address/command bus through time-multiplexing. Certain signals, including
+ // CS#/ODT/CKE/CK/CK# and the data signals, are not shared by the two
+ // interfaces. This module is responsible for instantiating two underlying
+ // memory models corresponding to the two logically-independent memory
+ // interfaces, feeding shared signals to both models, and splitting the
+ // non-shared signals before feeding them to each model.
+ //
+ // In non-ping-pong configuration, only one underlying model is
+ // instantiated and this module is a pass-through.
+ //(JCHOI)
+ localparam NUM_OF_IFS = (PHY_PING_PONG_EN ? 2 : 1);
+
+ // Calculate width of non-shared signals after splitting
+ localparam PORT_MEM_CKE_WIDTH_PER_IF = PORT_MEM_CKE_WIDTH / NUM_OF_IFS;
+ localparam PORT_MEM_CS_N_WIDTH_PER_IF = PORT_MEM_CS_N_WIDTH / NUM_OF_IFS;
+ localparam PORT_MEM_ODT_WIDTH_PER_IF = PORT_MEM_ODT_WIDTH / NUM_OF_IFS;
+ localparam PORT_MEM_CK_WIDTH_PER_IF = PORT_MEM_CK_WIDTH;
+ localparam PORT_MEM_CK_N_WIDTH_PER_IF = PORT_MEM_CK_N_WIDTH;
+ localparam PORT_MEM_DQ_WIDTH_PER_IF = PORT_MEM_DQ_WIDTH / NUM_OF_IFS;
+ localparam PORT_MEM_DQS_WIDTH_PER_IF = PORT_MEM_DQS_WIDTH / NUM_OF_IFS;
+ localparam PORT_MEM_DQS_N_WIDTH_PER_IF = PORT_MEM_DQS_N_WIDTH / NUM_OF_IFS;
+
+ // DBI#/DM are optional pins. If they're unused, we still generate a fake signal of width 1 to avoid
+ // index range issue when declaring/selecting signals. Note that mem_dm is a DDR3-only issue and
+ // mem_dbi_n is a DDR4-only signal.
+ localparam PORT_MEM_DM_WIDTH_PER_IF = (PORT_MEM_DM_WIDTH == 1 && NUM_OF_IFS == 2) ? 1 : (PORT_MEM_DM_WIDTH / NUM_OF_IFS);
+ localparam PORT_MEM_DBI_N_WIDTH_PER_IF = (PORT_MEM_DBI_N_WIDTH == 1 && NUM_OF_IFS == 2) ? 1 : (PORT_MEM_DBI_N_WIDTH / NUM_OF_IFS);
+
+ // Multiple alert# pins are meant to be daisy-chained on the board
+ // to obtain a single logically-AND'ed version of alert# before
+ // passing upward.
+ logic [NUM_OF_IFS-1:0] alert_n;
+ assign mem_alert_n = &alert_n;
+
+ generate
+ genvar inst_i;
+
+ for (inst_i = 0; inst_i < NUM_OF_IFS; ++inst_i)
+ begin : pp_gen
+ altera_emif_ddrx_model_per_ping_pong # (
+ .PROTOCOL_ENUM (PROTOCOL_ENUM),
+ .MEM_FORMAT_ENUM (MEM_FORMAT_ENUM),
+ .MEM_DISCRETE_CS_WIDTH (MEM_DISCRETE_CS_WIDTH),
+ .MEM_RANKS_PER_DIMM (MEM_RANKS_PER_DIMM),
+ .MEM_NUM_OF_DIMMS (MEM_NUM_OF_DIMMS),
+ .MEM_AC_PAR_EN (MEM_AC_PAR_EN),
+ .MEM_DM_EN (MEM_DM_EN),
+ .PORT_MEM_CKE_WIDTH (PORT_MEM_CKE_WIDTH_PER_IF),
+ .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH_PER_IF),
+ .PORT_MEM_CK_N_WIDTH (PORT_MEM_CK_N_WIDTH_PER_IF),
+ .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH),
+ .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH),
+ .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH),
+ .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH),
+ .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH_PER_IF),
+ .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH),
+ .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH),
+ .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH),
+ .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH),
+ .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH_PER_IF),
+ .PORT_MEM_DQS_N_WIDTH (PORT_MEM_DQS_N_WIDTH_PER_IF),
+ .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH_PER_IF),
+ .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH_PER_IF),
+ .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH_PER_IF),
+ .PORT_MEM_RESET_N_WIDTH (PORT_MEM_RESET_N_WIDTH),
+ .PORT_MEM_PAR_WIDTH (PORT_MEM_PAR_WIDTH),
+ .PORT_MEM_ALERT_N_WIDTH (1),
+ .PORT_MEM_ODT_WIDTH (PORT_MEM_ODT_WIDTH / NUM_OF_IFS),
+ .MEM_ROW_ADDR_WIDTH (MEM_ROW_ADDR_WIDTH),
+ .MEM_COL_ADDR_WIDTH (MEM_COL_ADDR_WIDTH),
+ .MEM_TRTP (MEM_TRTP),
+ .MEM_TRCD (MEM_TRCD),
+ .MEM_INIT_MRS0 (MEM_INIT_MRS0),
+ .MEM_INIT_MRS1 (MEM_INIT_MRS1),
+ .MEM_INIT_MRS2 (MEM_INIT_MRS2),
+ .MEM_INIT_MRS3 (MEM_INIT_MRS3),
+ .MEM_MIRROR_ADDRESSING_EN (MEM_MIRROR_ADDRESSING_EN),
+ .MEM_CFG_GEN_SBE (MEM_CFG_GEN_SBE),
+ .MEM_CFG_GEN_DBE (MEM_CFG_GEN_DBE)
+ ) inst (
+ .mem_cs_n (mem_cs_n [ (PORT_MEM_CS_N_WIDTH_PER_IF * inst_i) +: PORT_MEM_CS_N_WIDTH_PER_IF]),
+ .mem_cke (mem_cke [ (PORT_MEM_CKE_WIDTH_PER_IF * inst_i) +: PORT_MEM_CKE_WIDTH_PER_IF]),
+ .mem_odt (mem_odt [ (PORT_MEM_ODT_WIDTH_PER_IF * inst_i) +: PORT_MEM_ODT_WIDTH_PER_IF]),
+ .mem_dq (mem_dq [ (PORT_MEM_DQ_WIDTH_PER_IF * inst_i) +: PORT_MEM_DQ_WIDTH_PER_IF]),
+ .mem_dqs (mem_dqs [ (PORT_MEM_DQS_WIDTH_PER_IF * inst_i) +: PORT_MEM_DQS_WIDTH_PER_IF]),
+ .mem_dqs_n (mem_dqs_n[ (PORT_MEM_DQS_N_WIDTH_PER_IF * inst_i) +: PORT_MEM_DQS_N_WIDTH_PER_IF]),
+ .mem_dm (mem_dm [ (PORT_MEM_DM_WIDTH_PER_IF * ((PORT_MEM_DM_WIDTH == 1 && NUM_OF_IFS == 2) ? 0 : inst_i)) +: PORT_MEM_DM_WIDTH_PER_IF]),
+ .mem_dbi_n (mem_dbi_n[ (PORT_MEM_DBI_N_WIDTH_PER_IF * ((PORT_MEM_DBI_N_WIDTH == 1 && NUM_OF_IFS == 2) ? 0 : inst_i)) +: PORT_MEM_DBI_N_WIDTH_PER_IF]),
+ .mem_alert_n (alert_n [inst_i]),
+ .*
+ );
+ end
+ endgenerate
+endmodule
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_bidir_delay.sv b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_bidir_delay.sv
new file mode 100644
index 0000000000..a7315be92c
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_bidir_delay.sv
@@ -0,0 +1,53 @@
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+module altera_emif_ddrx_model_bidir_delay
+ #(
+
+ parameter DELAY = 2.0
+
+ ) (
+
+ inout porta,
+ inout portb
+
+ );
+ timeunit 1ps; timeprecision 1ps;
+ reg porta_dly;
+ reg portb_dly;
+
+ initial begin
+ porta_dly = 1'bz;
+ portb_dly = 1'bz;
+ end
+
+ always @(porta) begin
+
+ if (portb_dly === 1'bz || porta === 1'bz) begin
+ porta_dly <= #DELAY porta;
+ end
+
+ end
+
+ always @(portb) begin
+
+ if (porta_dly === 1'bz || portb === 1'bz) begin
+ portb_dly <= #DELAY portb;
+ end
+
+ end
+
+ assign porta = portb_dly;
+ assign portb = porta_dly;
+
+endmodule
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_per_device.sv b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_per_device.sv
new file mode 100644
index 0000000000..16c2d86eb4
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_per_device.sv
@@ -0,0 +1,362 @@
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+// memory model per device in a given depth expansion
+//
+///////////////////////////////////////////////////////////////////////////////
+module altera_emif_ddrx_model_per_device
+ # (
+
+ parameter PROTOCOL_ENUM = "",
+ parameter MEM_FORMAT_ENUM = "",
+ parameter MEM_RANKS_PER_DIMM = 0,
+ parameter MEM_NUM_OF_DIMMS = 0,
+ parameter MEM_AC_PAR_EN = 0,
+ parameter MEM_DM_EN = 0,
+
+ parameter PORT_MEM_CKE_WIDTH = 1,
+ parameter PORT_MEM_BA_WIDTH = 1,
+ parameter PORT_MEM_BG_WIDTH = 1,
+ parameter PORT_MEM_C_WIDTH = 1,
+ parameter PORT_MEM_A_WIDTH = 1,
+ parameter PORT_MEM_CS_N_WIDTH = 1,
+ parameter PORT_MEM_RAS_N_WIDTH = 1,
+ parameter PORT_MEM_CAS_N_WIDTH = 1,
+ parameter PORT_MEM_WE_N_WIDTH = 1,
+ parameter PORT_MEM_ACT_N_WIDTH = 1,
+ parameter PORT_MEM_DQS_WIDTH = 1,
+ parameter PORT_MEM_DQS_N_WIDTH = 1,
+ parameter PORT_MEM_DQ_WIDTH = 1,
+ parameter PORT_MEM_DM_WIDTH = 1,
+ parameter PORT_MEM_DBI_N_WIDTH = 1,
+ parameter PORT_MEM_RESET_N_WIDTH = 1,
+ parameter PORT_MEM_PAR_WIDTH = 1,
+ parameter PORT_MEM_ALERT_N_WIDTH = 1,
+
+ parameter MEM_ROW_ADDR_WIDTH = 1,
+ parameter MEM_COL_ADDR_WIDTH = 1,
+ parameter MEM_TRTP = 0,
+ parameter MEM_TRCD = 0,
+ parameter MEM_INIT_MRS0 = 0,
+ parameter MEM_INIT_MRS1 = 0,
+ parameter MEM_INIT_MRS2 = 0,
+ parameter MEM_INIT_MRS3 = 0,
+ parameter MEM_MIRROR_ADDRESSING_EN = 0,
+ parameter MEM_DEPTH_IDX = -1,
+ parameter MEM_CFG_GEN_SBE = 0,
+ parameter MEM_CFG_GEN_DBE = 0
+ ) (
+
+ input logic [PORT_MEM_A_WIDTH-1:0] mem_a,
+ input logic [PORT_MEM_BA_WIDTH-1:0] mem_ba,
+ input logic [PORT_MEM_BG_WIDTH-1:0] mem_bg,
+ input logic [PORT_MEM_C_WIDTH-1:0] mem_c,
+ input logic mem_ck,
+ input logic mem_ck_n,
+ input logic [PORT_MEM_CKE_WIDTH - 1:0] mem_cke,
+ input logic [PORT_MEM_CS_N_WIDTH - 1:0] mem_cs_n,
+ input logic [PORT_MEM_RAS_N_WIDTH - 1:0] mem_ras_n,
+ input logic [PORT_MEM_CAS_N_WIDTH - 1:0] mem_cas_n,
+ input logic [PORT_MEM_WE_N_WIDTH - 1:0] mem_we_n,
+ input logic [PORT_MEM_ACT_N_WIDTH - 1:0] mem_act_n,
+ input logic [PORT_MEM_RESET_N_WIDTH - 1:0] mem_reset_n,
+ input logic [PORT_MEM_DM_WIDTH - 1:0] mem_dm,
+ inout tri [PORT_MEM_DBI_N_WIDTH - 1:0] mem_dbi_n,
+ inout tri [PORT_MEM_DQ_WIDTH - 1:0] mem_dq,
+ inout tri [PORT_MEM_DQS_WIDTH - 1:0] mem_dqs,
+ inout tri [PORT_MEM_DQS_N_WIDTH - 1:0] mem_dqs_n,
+ output logic [PORT_MEM_ALERT_N_WIDTH-1:0] mem_alert_n,
+ input logic [PORT_MEM_PAR_WIDTH-1:0] mem_par,
+ input logic mem_odt
+
+ );
+ timeunit 1ps;
+ timeprecision 1ps;
+
+ localparam MEM_CS_PER_RANK = 1;
+ localparam MEM_NUMBER_OF_RANKS = ((MEM_RANKS_PER_DIMM == 0) ? (PORT_MEM_CS_N_WIDTH/MEM_CS_PER_RANK) : MEM_RANKS_PER_DIMM);
+
+ localparam MEM_PHYS_RANKS = MEM_NUMBER_OF_RANKS;
+ localparam PORT_MEM_DQ_A_WIDTH = (MEM_PHYS_RANKS == 8) ? 72 : 40;
+ localparam PORT_MEM_DQ_B_WIDTH = (MEM_PHYS_RANKS == 8) ? 72 : (PORT_MEM_DQ_WIDTH - PORT_MEM_DQ_A_WIDTH);
+ localparam PORT_MEM_DQS_A_WIDTH = (MEM_PHYS_RANKS == 8) ? PORT_MEM_DQS_WIDTH : ((PORT_MEM_DQS_WIDTH * PORT_MEM_DQ_A_WIDTH) / PORT_MEM_DQ_WIDTH);
+ localparam PORT_MEM_DQS_B_WIDTH = (MEM_PHYS_RANKS == 8) ? PORT_MEM_DQS_WIDTH : (PORT_MEM_DQS_WIDTH - PORT_MEM_DQS_A_WIDTH);
+
+ localparam MEM_DQ_A_U = PORT_MEM_DQ_A_WIDTH-1;
+ localparam MEM_DQ_A_L = 0;
+ localparam MEM_DQ_B_U = 71;
+ localparam MEM_DQ_B_L = (MEM_PHYS_RANKS == 8) ? 0 : PORT_MEM_DQ_A_WIDTH;
+ localparam MEM_DQS_A_U = PORT_MEM_DQS_A_WIDTH-1;
+ localparam MEM_DQS_A_L = 0;
+ localparam MEM_DQS_B_U = (PORT_MEM_DQS_WIDTH-1);
+ localparam MEM_DQS_B_L = (MEM_PHYS_RANKS == 8) ? 0 : PORT_MEM_DQS_A_WIDTH;
+
+
+ reg [PORT_MEM_A_WIDTH-1:0] a;
+ reg [PORT_MEM_BA_WIDTH-1:0] ba;
+ reg [PORT_MEM_BG_WIDTH-1:0] bg;
+ reg [PORT_MEM_C_WIDTH-1:0] c;
+ reg ck;
+ reg ck_n;
+ reg cke;
+ reg [MEM_NUMBER_OF_RANKS-1:0] cs_n;
+ reg [PORT_MEM_CS_N_WIDTH-1:0] cs_rdimm_n;
+ reg ras_n;
+ reg cas_n;
+ reg we_n;
+ reg act_n;
+ reg [PORT_MEM_RESET_N_WIDTH-1:0] reset_n;
+ reg odt;
+ reg [MEM_NUMBER_OF_RANKS-1:0] alert_n;
+ reg [PORT_MEM_PAR_WIDTH-1:0] par;
+ reg single_bit_alert_n;
+
+ reg [PORT_MEM_DM_WIDTH-1:0] dm;
+
+ generate
+
+ if (MEM_FORMAT_ENUM == "MEM_FORMAT_RDIMM") begin
+
+ always @(*) begin
+ ras_n <= a[16];
+ cas_n <= a[15];
+ we_n <= a[14];
+ end
+
+ end
+ else begin
+
+ always @(*) begin
+
+ a <= mem_a;
+ ba <= mem_ba;
+ bg <= mem_bg;
+ c <= mem_c;
+ ck <= mem_ck;
+ ck_n <= mem_ck_n;
+ cke <= mem_cke;
+ cs_n <= mem_cs_n;
+ ras_n <= mem_ras_n;
+ cas_n <= mem_cas_n;
+ we_n <= mem_we_n;
+ act_n <= mem_act_n;
+ reset_n <= mem_reset_n;
+ odt <= mem_odt;
+ par <= mem_par;
+ mem_alert_n <= single_bit_alert_n;
+
+ if (MEM_DM_EN != 0) begin
+ if ((PROTOCOL_ENUM != "PROTOCOL_DDR4") && (PORT_MEM_DM_WIDTH != PORT_MEM_DQS_WIDTH) ||
+ (PROTOCOL_ENUM == "PROTOCOL_DDR4") && (PORT_MEM_DBI_N_WIDTH != PORT_MEM_DQS_WIDTH)) begin
+ $display("Memory model DM width must equal DQS width.");
+ $finish;
+ end
+ end
+ else
+ begin
+ dm <= #10 {PORT_MEM_DM_WIDTH{1'b0}};
+ end
+
+ end
+
+ end
+
+ endgenerate
+
+ generate
+ reg my_parity;
+ reg [4:0] err_out_shiftreg = 5'b11111;
+ if (MEM_AC_PAR_EN) begin
+ always @(posedge mem_ck) begin
+ if (mem_cke) begin
+ my_parity <= ^{mem_a, mem_ba, mem_ras_n, mem_cas_n, mem_we_n};
+ err_out_shiftreg[4:1] <= err_out_shiftreg[3:0];
+ if (cs_n != {PORT_MEM_CS_N_WIDTH{1'b1}}) begin
+ err_out_shiftreg[1:0] <= {2{my_parity == mem_par}};
+ end else begin
+ err_out_shiftreg[0] <= 1'b1;
+ end
+ end
+ end
+ end
+ assign single_bit_alert_n = (PROTOCOL_ENUM == "PROTOCOL_DDR4" ? &alert_n : err_out_shiftreg[4]);
+ endgenerate
+
+
+ generate
+ if ((PROTOCOL_ENUM == "PROTOCOL_DDR4") && (MEM_FORMAT_ENUM == "MEM_FORMAT_RDIMM")) begin : gen_ddr4_rcd_chip
+
+ altera_emif_ddr4_model_rcd_chip ddr4_rcd_chip (
+ .DCKE (mem_cke),
+ .DODT (mem_odt),
+ .DCS_n (mem_cs_n),
+ .DC (mem_c),
+
+ .DA (mem_a),
+ .DBA (mem_ba),
+ .DBG (mem_bg),
+ .DACT_n (mem_act_n),
+
+ .CK_t (mem_ck),
+ .CK_c (mem_ck_n),
+
+ .DRST_n (mem_reset_n),
+
+ .DPAR (mem_par),
+
+ .ERROR_IN_n (single_bit_alert_n),
+
+ .BODT (),
+ .BCKE (),
+ .BCOM (),
+ .BCK_t (),
+ .BCK_c (),
+ .BVrefCA (),
+
+ .QACKE (cke),
+ .QBCKE (),
+ .QAODT (odt),
+ .QBODT (),
+ .QACS_n (cs_n),
+ .QBCS_n (),
+ .QAC (c),
+ .QBC (),
+
+ .QAA (a),
+ .QBA (),
+ .QABA (ba),
+ .QABG (bg),
+ .QBBA (),
+ .QBBG (),
+ .QAACT_n (act_n),
+ .QBACT_n (),
+
+ .Y_t (ck),
+ .Y_c (ck_n),
+
+ .QRST_n (reset_n),
+
+ .QAPAR (par),
+ .QBPAR (),
+
+ .ALERT_n (mem_alert_n),
+
+ .SDA (),
+ .SA (),
+ .SCL (),
+ .BFUNC (),
+ .VDDSPD (),
+
+ .VDD (1'b1),
+ .VSS (1'b0),
+ .AVDD (1'b1),
+ .PVDD (1'b1),
+ .PVSS (1'b0)
+ );
+ end
+
+ if ((PROTOCOL_ENUM == "PROTOCOL_DDR4") && (MEM_FORMAT_ENUM == "MEM_FORMAT_LRDIMM")) begin : gen_ddr4_db_chips
+ initial
+ begin
+ $display("Simulation of DDR4 LRDIMM is not supported in this version of Quartus.");
+ $finish;
+ end
+ end
+
+ if ((PROTOCOL_ENUM == "PROTOCOL_DDR3") && (MEM_FORMAT_ENUM == "MEM_FORMAT_RDIMM")) begin : gen_ddr3_rdimm_chip
+ initial
+ begin
+ $display("Simulation of DDR3 RDIMM is not supported in this version of Quartus.");
+ $finish;
+ end
+ end
+
+ if ((PROTOCOL_ENUM == "PROTOCOL_DDR3") && (MEM_FORMAT_ENUM == "MEM_FORMAT_LRDIMM")) begin : gen_ddr3_lrdimm_chip
+ initial
+ begin
+ $display("Simulation of DDR3 LRDIMM is not supported in this version of Quartus.");
+ $finish;
+ end
+ end
+
+ endgenerate
+
+
+ generate
+
+ if (MEM_FORMAT_ENUM == "MEM_FORMAT_LRDIMM") begin : gen_lrdimm_mem
+ // Simulation of LRDIMMs is not supported in this version of Quartus.
+ end
+ else begin : gen_mem_rank
+ genvar rank;
+ for (rank = 0; rank < MEM_NUMBER_OF_RANKS; rank = rank + 1) begin : rank_gen
+ altera_emif_ddrx_model_rank #(
+
+ .PROTOCOL_ENUM (PROTOCOL_ENUM),
+ .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH),
+ .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH),
+ .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH),
+ .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH),
+ .MEM_ROW_ADDR_WIDTH (MEM_ROW_ADDR_WIDTH),
+ .MEM_COL_ADDR_WIDTH (MEM_COL_ADDR_WIDTH),
+ .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH),
+ .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH),
+ .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH),
+ .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH),
+
+ .MEM_DM_EN (MEM_DM_EN),
+ .MEM_TRTP (MEM_TRTP),
+ .MEM_TRCD (MEM_TRCD),
+ .MEM_INIT_MRS0 (MEM_INIT_MRS0),
+ .MEM_INIT_MRS1 (MEM_INIT_MRS1),
+ .MEM_INIT_MRS2 (MEM_INIT_MRS2),
+ .MEM_INIT_MRS3 (MEM_INIT_MRS3),
+ .MEM_MIRROR_ADDRESSING (MEM_MIRROR_ADDRESSING_EN & (rank & 1'b1)),
+ .MEM_DEPTH_IDX (MEM_DEPTH_IDX),
+ .MEM_RANK_IDX (rank),
+ .MEM_CFG_GEN_SBE (MEM_CFG_GEN_SBE),
+ .MEM_CFG_GEN_DBE (MEM_CFG_GEN_DBE)
+
+ ) rank_inst (
+
+ .mem_a (a),
+ .mem_ba (ba),
+ .mem_bg (bg),
+ .mem_c (c),
+ .mem_ck (ck),
+ .mem_ck_n (ck_n),
+ .mem_cke (cke),
+ .mem_ras_n (ras_n),
+ .mem_cas_n (cas_n),
+ .mem_we_n (we_n),
+ .mem_act_n (act_n),
+ .mem_reset_n (reset_n),
+ .mem_dm (mem_dm),
+ .mem_dbi_n (mem_dbi_n),
+ .mem_dq (mem_dq),
+ .mem_dqs (mem_dqs),
+ .mem_dqs_n (mem_dqs_n),
+ .mem_odt (odt),
+ .mem_cs_n (cs_n[rank]),
+ .mem_alert_n (alert_n[rank]),
+ .mem_par (par)
+
+ );
+ end
+
+ end
+
+ endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_per_ping_pong.sv b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_per_ping_pong.sv
new file mode 100644
index 0000000000..eb5eb289d6
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_per_ping_pong.sv
@@ -0,0 +1,186 @@
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Memory model representing either the "ping" or the "pong" side of
+// the memory device for ping-pong topology. For non-ping-pong topology
+// this is simply the top-level wrapper of the memory model.
+//
+///////////////////////////////////////////////////////////////////////////////
+module altera_emif_ddrx_model_per_ping_pong #
+(
+ parameter PROTOCOL_ENUM = "",
+ parameter MEM_FORMAT_ENUM = "",
+ parameter MEM_DISCRETE_CS_WIDTH = 1,
+ parameter MEM_RANKS_PER_DIMM = 0,
+ parameter MEM_NUM_OF_DIMMS = 0,
+ parameter MEM_AC_PAR_EN = 0,
+ parameter MEM_DM_EN = 0,
+
+ parameter PORT_MEM_CKE_WIDTH = 1,
+ parameter PORT_MEM_CK_WIDTH = 1,
+ parameter PORT_MEM_CK_N_WIDTH = 1,
+ parameter PORT_MEM_BA_WIDTH = 1,
+ parameter PORT_MEM_BG_WIDTH = 1,
+ parameter PORT_MEM_C_WIDTH = 1,
+ parameter PORT_MEM_A_WIDTH = 1,
+ parameter PORT_MEM_CS_N_WIDTH = 1,
+ parameter PORT_MEM_RAS_N_WIDTH = 1,
+ parameter PORT_MEM_CAS_N_WIDTH = 1,
+ parameter PORT_MEM_WE_N_WIDTH = 1,
+ parameter PORT_MEM_ACT_N_WIDTH = 1,
+ parameter PORT_MEM_DQS_WIDTH = 1,
+ parameter PORT_MEM_DQS_N_WIDTH = 1,
+ parameter PORT_MEM_DQ_WIDTH = 1,
+ parameter PORT_MEM_DM_WIDTH = 1,
+ parameter PORT_MEM_DBI_N_WIDTH = 1,
+ parameter PORT_MEM_RESET_N_WIDTH = 1,
+ parameter PORT_MEM_PAR_WIDTH = 1,
+ parameter PORT_MEM_ALERT_N_WIDTH = 1,
+ parameter PORT_MEM_ODT_WIDTH = 1,
+
+ parameter MEM_ROW_ADDR_WIDTH = 1,
+ parameter MEM_COL_ADDR_WIDTH = 1,
+ parameter MEM_TRTP = 0,
+ parameter MEM_TRCD = 0,
+ parameter MEM_INIT_MRS0 = 0,
+ parameter MEM_INIT_MRS1 = 0,
+ parameter MEM_INIT_MRS2 = 0,
+ parameter MEM_INIT_MRS3 = 0,
+ parameter MEM_MIRROR_ADDRESSING_EN = 0,
+ parameter MEM_CFG_GEN_SBE = 0,
+ parameter MEM_CFG_GEN_DBE = 0
+) (
+ input logic [PORT_MEM_A_WIDTH-1:0] mem_a,
+ input logic [PORT_MEM_BA_WIDTH-1:0] mem_ba,
+ input logic [PORT_MEM_BG_WIDTH-1:0] mem_bg,
+ input logic [PORT_MEM_C_WIDTH-1:0] mem_c,
+ input logic [PORT_MEM_CK_WIDTH-1:0] mem_ck,
+ input logic [PORT_MEM_CK_N_WIDTH-1:0] mem_ck_n,
+ input logic [PORT_MEM_CKE_WIDTH - 1:0] mem_cke,
+ input logic [PORT_MEM_CS_N_WIDTH - 1:0] mem_cs_n,
+ input logic [PORT_MEM_RAS_N_WIDTH - 1:0] mem_ras_n,
+ input logic [PORT_MEM_CAS_N_WIDTH - 1:0] mem_cas_n,
+ input logic [PORT_MEM_WE_N_WIDTH - 1:0] mem_we_n,
+ input logic [PORT_MEM_ACT_N_WIDTH - 1:0] mem_act_n,
+ input logic [PORT_MEM_RESET_N_WIDTH - 1:0] mem_reset_n,
+ input logic [PORT_MEM_DM_WIDTH - 1:0] mem_dm,
+ inout tri [PORT_MEM_DBI_N_WIDTH - 1:0] mem_dbi_n,
+ inout tri [PORT_MEM_DQ_WIDTH - 1:0] mem_dq,
+ inout tri [PORT_MEM_DQS_WIDTH - 1:0] mem_dqs,
+ inout tri [PORT_MEM_DQS_N_WIDTH - 1:0] mem_dqs_n,
+ output logic [PORT_MEM_ALERT_N_WIDTH-1:0] mem_alert_n,
+ input logic [PORT_MEM_PAR_WIDTH-1:0] mem_par,
+ input logic [PORT_MEM_ODT_WIDTH-1:0] mem_odt
+);
+ timeunit 1ps;
+ timeprecision 1ps;
+
+ localparam MEM_MODEL_DEVICE_DEPTH = (MEM_FORMAT_ENUM == "MEM_FORMAT_RDIMM" || MEM_FORMAT_ENUM == "MEM_FORMAT_LRDIMM" || MEM_FORMAT_ENUM == "MEM_FORMAT_UDIMM" ) ? MEM_NUM_OF_DIMMS : MEM_DISCRETE_CS_WIDTH ;
+
+ wire logic [MEM_MODEL_DEVICE_DEPTH - 1:0] alert_n;
+ assign mem_alert_n = &alert_n;
+
+ /* DDR4 Shared Address/Command Bus: {RAS_n, CAS_n, WE_n} = A[16:14]
+ Interpret as RAS/CAS/WE when ACT_n = 1
+ Interpret as A[16:14] when ACT_n = 0
+ If DDR4, there should be no RAS/CAS/WE coming in. We copy A[16:14] to those signals here. */
+ logic [PORT_MEM_RAS_N_WIDTH-1:0] int_mem_ras_n;
+ logic [PORT_MEM_CAS_N_WIDTH-1:0] int_mem_cas_n;
+ logic [PORT_MEM_WE_N_WIDTH-1:0] int_mem_we_n;
+ initial begin
+ assert(!(PROTOCOL_ENUM == "PROTOCOL_DDR4" && PORT_MEM_A_WIDTH < 17)) else $error("mem_a width must be at least 17 for DDR4");
+ end
+
+ generate
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ always_comb begin
+ int_mem_ras_n <= {PORT_MEM_RAS_N_WIDTH{mem_a[16]}};
+ int_mem_cas_n <= {PORT_MEM_CAS_N_WIDTH{mem_a[15]}};
+ int_mem_we_n <= {PORT_MEM_WE_N_WIDTH{mem_a[14]}};
+ end
+ end else begin
+ always_comb begin
+ int_mem_ras_n <= mem_ras_n;
+ int_mem_cas_n <= mem_cas_n;
+ int_mem_we_n <= mem_we_n;
+ end
+ end
+ endgenerate
+
+ generate
+ genvar depth;
+ for (depth = 0; depth < MEM_MODEL_DEVICE_DEPTH; ++depth) begin : depth_gen
+
+ altera_emif_ddrx_model_per_device #(
+ .PROTOCOL_ENUM (PROTOCOL_ENUM),
+ .PORT_MEM_CKE_WIDTH (PORT_MEM_CKE_WIDTH),
+ .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH),
+ .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH),
+ .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH),
+ .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH),
+ .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH / MEM_MODEL_DEVICE_DEPTH),
+ .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH),
+ .PORT_MEM_DQS_N_WIDTH (PORT_MEM_DQS_N_WIDTH),
+ .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH),
+ .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH),
+ .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH),
+ .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH),
+ .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH),
+ .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH),
+ .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH),
+ .PORT_MEM_RESET_N_WIDTH (PORT_MEM_RESET_N_WIDTH),
+ .PORT_MEM_PAR_WIDTH (PORT_MEM_PAR_WIDTH),
+ .PORT_MEM_ALERT_N_WIDTH (1),
+ .MEM_ROW_ADDR_WIDTH (MEM_ROW_ADDR_WIDTH),
+ .MEM_COL_ADDR_WIDTH (MEM_COL_ADDR_WIDTH),
+ .MEM_TRTP (MEM_TRTP),
+ .MEM_TRCD (MEM_TRCD),
+ .MEM_INIT_MRS0 (MEM_INIT_MRS0),
+ .MEM_INIT_MRS1 (MEM_INIT_MRS1),
+ .MEM_INIT_MRS2 (MEM_INIT_MRS2),
+ .MEM_INIT_MRS3 (MEM_INIT_MRS3),
+ .MEM_DEPTH_IDX (depth),
+ .MEM_FORMAT_ENUM (MEM_FORMAT_ENUM),
+ .MEM_RANKS_PER_DIMM (MEM_RANKS_PER_DIMM),
+ .MEM_DM_EN (MEM_DM_EN),
+ .MEM_MIRROR_ADDRESSING_EN (MEM_MIRROR_ADDRESSING_EN),
+ .MEM_AC_PAR_EN (MEM_AC_PAR_EN),
+ .MEM_CFG_GEN_SBE (MEM_CFG_GEN_SBE),
+ .MEM_CFG_GEN_DBE (MEM_CFG_GEN_DBE)
+ ) mem_inst (
+ .mem_a (mem_a),
+ .mem_ba (mem_ba),
+ .mem_bg (mem_bg),
+ .mem_c (mem_c),
+ .mem_ck (mem_ck[0]),
+ .mem_ck_n (mem_ck_n[0]),
+ .mem_cke (mem_cke),
+ .mem_cs_n (mem_cs_n[PORT_MEM_CS_N_WIDTH/MEM_MODEL_DEVICE_DEPTH*(depth+1)-1:PORT_MEM_CS_N_WIDTH/MEM_MODEL_DEVICE_DEPTH*depth]),
+ .mem_ras_n (int_mem_ras_n),
+ .mem_cas_n (int_mem_cas_n),
+ .mem_we_n (int_mem_we_n),
+ .mem_act_n (mem_act_n),
+ .mem_reset_n (mem_reset_n),
+ .mem_dm (mem_dm),
+ .mem_dbi_n (mem_dbi_n),
+ .mem_dq (mem_dq),
+ .mem_dqs (mem_dqs),
+ .mem_dqs_n (mem_dqs_n),
+ .mem_par (mem_par),
+ .mem_alert_n (alert_n[depth]),
+ .mem_odt (mem_odt[0])
+ );
+ end
+ endgenerate
+endmodule
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_rank.sv b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_rank.sv
new file mode 100644
index 0000000000..47cbc56fa3
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/altera_emif_ddrx_model_rank.sv
@@ -0,0 +1,1597 @@
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+module altera_emif_ddrx_model_rank
+ # (
+ parameter PROTOCOL_ENUM = "",
+ parameter PORT_MEM_BA_WIDTH = 1,
+ parameter PORT_MEM_BG_WIDTH = 1,
+ parameter PORT_MEM_C_WIDTH = 1,
+ parameter PORT_MEM_A_WIDTH = 1,
+ parameter MEM_ROW_ADDR_WIDTH = 1,
+ parameter MEM_COL_ADDR_WIDTH = 1,
+ parameter PORT_MEM_DM_WIDTH = 1,
+ parameter PORT_MEM_DBI_N_WIDTH = 1,
+ parameter PORT_MEM_DQS_WIDTH = 1,
+ parameter PORT_MEM_DQ_WIDTH = 1,
+ parameter MEM_DM_EN = 0,
+ parameter MEM_PAR_ALERT_PW = 48,
+ parameter MEM_CRC_ALERT = 13,
+ parameter MEM_CRC_ALERT_PW = 6,
+ parameter MEM_TRTP = 0,
+ parameter MEM_TRCD = 0,
+ parameter MEM_DQS_TO_CLK_CAPTURE_DELAY = 100,
+ parameter MEM_CLK_TO_DQS_CAPTURE_DELAY = 100000,
+ parameter MEM_MIRROR_ADDRESSING = 0,
+ parameter MEM_DEPTH_IDX = -1,
+ parameter MEM_WIDTH_IDX = 0,
+ parameter MEM_RANK_IDX = -1,
+ parameter MEM_VERBOSE = 1,
+ parameter MEM_GUARANTEED_WRITE_INIT = 0,
+ parameter REFRESH_BURST_VALIDATION = 0,
+ parameter MEM_INIT_MRS0 = 0,
+ parameter MEM_INIT_MRS1 = 0,
+ parameter MEM_INIT_MRS2 = 0,
+ parameter MEM_INIT_MRS3 = 0,
+ parameter MEM_CFG_GEN_SBE = 0,
+ parameter MEM_CFG_GEN_DBE = 0
+ ) (
+
+ input logic [PORT_MEM_A_WIDTH-1:0] mem_a,
+ input logic [PORT_MEM_BA_WIDTH-1:0] mem_ba,
+ input logic [PORT_MEM_BG_WIDTH-1:0] mem_bg,
+ input logic [PORT_MEM_C_WIDTH-1:0] mem_c,
+ input logic mem_ck,
+ input logic mem_ck_n,
+ input logic mem_cke,
+ input logic mem_ras_n,
+ input logic mem_cas_n,
+ input logic mem_we_n,
+ input logic mem_act_n,
+ input logic mem_reset_n,
+ input logic [PORT_MEM_DM_WIDTH-1:0] mem_dm,
+ inout tri [PORT_MEM_DBI_N_WIDTH-1:0] mem_dbi_n,
+ inout tri [PORT_MEM_DQ_WIDTH-1:0] mem_dq,
+ inout tri [PORT_MEM_DQS_WIDTH-1:0] mem_dqs,
+ inout tri [PORT_MEM_DQS_WIDTH-1:0] mem_dqs_n,
+ input logic mem_odt,
+ input logic mem_cs_n,
+ output logic mem_alert_n,
+ input logic mem_par
+ );
+ timeunit 1ps;
+ timeprecision 1ps;
+
+
+ localparam NUM_BANKS_PER_GROUP = 2**PORT_MEM_BA_WIDTH;
+ localparam NUM_BANK_GROUPS = 2**PORT_MEM_BG_WIDTH;
+ localparam NUM_BANKS = NUM_BANKS_PER_GROUP * NUM_BANK_GROUPS;
+ localparam MEM_DQS_GROUP_SIZE = PORT_MEM_DQ_WIDTH / PORT_MEM_DQS_WIDTH;
+ localparam ALERT_N_PIPELINE_SIZE = 2 * (MEM_PAR_ALERT_PW+16) + 1;
+ localparam DISABLE_NOP_DISPLAY = 1;
+ localparam CHECK_VIOLATIONS = 1;
+ localparam REFRESH_INTERVAL_PS = 36000000;
+ localparam FULL_BURST_REFRESH_COUNT = 8192;
+ localparam STD_REFRESH_INTERVAL_PS = 7800000;
+ localparam MAX_LATENCY = 64;
+ localparam MAX_BURST = 8;
+ localparam OPCODE_WIDTH = 5;
+ localparam CRC_DQ_RATIO = 8;
+ localparam CRC_DBI_BITS = 1;
+ localparam CRC_TREE_BITS = 72;
+ localparam CRC_NUM_TREES = PORT_MEM_DQ_WIDTH / CRC_DQ_RATIO;
+ localparam CRC_BURST_LENGTH = 10;
+
+ wire [PORT_MEM_A_WIDTH - 1:0] mem_a_wire;
+ wire [PORT_MEM_BA_WIDTH - 1:0] mem_ba_wire;
+ wire [PORT_MEM_BG_WIDTH - 1:0] mem_bg_wire;
+
+ wire [PORT_MEM_DQS_WIDTH - 1:0] mem_dqs_shifted;
+ wire [PORT_MEM_DQS_WIDTH - 1:0] mem_dqs_n_shifted;
+
+ wire [PORT_MEM_DQS_WIDTH - 1:0] mem_dqs_n_shifted_2;
+ reg [PORT_MEM_DQS_WIDTH - 1:0] mem_dqs_n_shifted_2_prev = 'z;
+
+
+ typedef enum logic[OPCODE_WIDTH-1:0] {
+ OPCODE_PRECHARGE = 'b01010,
+ OPCODE_ACTIVATE = 'b01011,
+ OPCODE_DDR4_ACTIVATE = 'b00xxx,
+ OPCODE_WRITE = 'b01100,
+ OPCODE_READ = 'b01101,
+ OPCODE_MRS = 'b01000,
+ OPCODE_REFRESH = 'b01001,
+ OPCODE_DES = 'b1xxxx,
+ OPCODE_ZQC = 'b01110,
+ OPCODE_NOP = 'b01111
+
+ } OPCODE_TYPE;
+
+ typedef enum {
+
+ DDR_BURST_TYPE_BL16,
+ DDR_BURST_TYPE_BL8,
+ DDR_BURST_TYPE_OTF,
+ DDR_BURST_TYPE_BL4
+
+ } DDR_BURST_TYPE;
+
+ typedef enum {
+
+ DDR_AL_TYPE_ZERO,
+ DDR_AL_TYPE_CL_MINUS_1,
+ DDR_AL_TYPE_CL_MINUS_2
+
+ } DDR_AL_TYPE;
+
+ DDR_BURST_TYPE burst_type;
+ int cas_latency;
+ int cas_write_latency;
+ DDR_AL_TYPE al_type;
+ int parity_latency;
+ bit crc_en;
+ bit wlevel_en;
+ bit [1:0] lpasr;
+ bit geardown_mode;
+ bit [2:0] fine_granularity_refresh_mode;
+ bit max_power_saving_en;
+ bit temp_controlled_refresh_range;
+ bit temp_controlled_refresh_en;
+
+ int tRTP_cycles = MEM_TRTP;
+ int tRCD_cycles = MEM_TRCD;
+
+ int clock_cycle;
+
+ reg clock_stable;
+
+ time last_refresh_time;
+ bit refresh_burst_active;
+ int refresh_executed_count;
+ int refresh_debt;
+ time refresh_required_time;
+
+ typedef struct {
+
+ bit [MEM_ROW_ADDR_WIDTH - 1:0] opened_row;
+ time last_ref_time;
+ int last_ref_cycle;
+ int last_activate_cycle;
+ int last_precharge_cycle;
+ int last_write_cmd_cycle;
+ int last_write_access_cycle;
+ int last_read_cmd_cycle;
+ int last_read_access_cycle;
+
+ } bank_struct;
+
+ typedef struct {
+ bank_struct bank[NUM_BANKS_PER_GROUP-1:0];
+ } bg_struct;
+
+ bit [PORT_MEM_DQ_WIDTH - 1:0] mem_data[*];
+
+ bg_struct bg [NUM_BANK_GROUPS - 1:0];
+
+ bit [CRC_TREE_BITS-1:0] write_burst_data [0:CRC_NUM_TREES-1];
+ bit [CRC_DQ_RATIO-1:0] crc_received [0:CRC_NUM_TREES-1];
+ bit [PORT_MEM_DQ_WIDTH-1:0] crc_received_prev;
+ bit [PORT_MEM_DQ_WIDTH-1:0] crc_received_curr;
+ bit [CRC_DQ_RATIO-1:0] mem_crc [0:CRC_NUM_TREES-1];
+
+ typedef enum {
+
+ DDR_CMD_TYPE_PRECHARGE,
+ DDR_CMD_TYPE_ACTIVATE,
+ DDR_CMD_TYPE_WRITE,
+ DDR_CMD_TYPE_READ,
+ DDR_CMD_TYPE_REFRESH,
+ DDR_CMD_TYPE_NOP,
+ DDR_CMD_TYPE_MRS,
+ DDR_CMD_TYPE_DES,
+ DDR_CMD_TYPE_ZQC,
+ DDR_CMD_TYPE_ERROR
+
+ } DDR_CMD_TYPE;
+
+ typedef struct {
+ DDR_CMD_TYPE cmd_type;
+ int word_count;
+ int burst_length;
+ bit [PORT_MEM_BA_WIDTH - 1:0] bank;
+ bit [PORT_MEM_BG_WIDTH - 1:0] bank_group;
+ bit [PORT_MEM_A_WIDTH - 1:0] address;
+ bit [OPCODE_WIDTH-1:0] opcode;
+ } command_struct;
+
+
+
+ DDR_CMD_TYPE write_command_queue[$];
+ int write_word_count_queue[$];
+ int write_burst_length_queue[$];
+ bit [PORT_MEM_A_WIDTH - 1:0] write_address_queue[$];
+ bit [PORT_MEM_BA_WIDTH - 1:0] write_bank_queue[$];
+ bit [PORT_MEM_BG_WIDTH - 1:0] write_bank_group_queue[$];
+
+ DDR_CMD_TYPE read_command_queue[$];
+ int read_word_count_queue[$];
+ int read_burst_length_queue[$];
+ bit [PORT_MEM_A_WIDTH - 1:0] read_address_queue[$];
+ bit [PORT_MEM_BA_WIDTH - 1:0] read_bank_queue[$];
+ bit [PORT_MEM_BG_WIDTH - 1:0] read_bank_group_queue[$];
+
+ DDR_CMD_TYPE precharge_command_queue[$];
+ bit [PORT_MEM_BA_WIDTH - 1:0] precharge_bank_queue[$];
+ bit [PORT_MEM_BG_WIDTH - 1:0] precharge_bank_group_queue[$];
+
+ DDR_CMD_TYPE activate_command_queue[$];
+ bit [PORT_MEM_BA_WIDTH-1:0] activate_bank_queue[$];
+ bit [PORT_MEM_BG_WIDTH-1:0] activate_bank_group_queue[$];
+ bit [PORT_MEM_A_WIDTH-1:0] activate_row_queue[$];
+
+ command_struct parity_latency_queue[$];
+ bit [2 * MAX_LATENCY + 1:0] parity_latency_pipeline;
+ bit [ALERT_N_PIPELINE_SIZE:0] parity_alert_n_pipeline;
+ bit [ALERT_N_PIPELINE_SIZE:0] crc_alert_n_pipeline;
+
+ command_struct active_command;
+ command_struct new_command;
+ command_struct precharge_command;
+ command_struct activate_command;
+
+ bit [2 * MAX_LATENCY + 1:0] read_command_pipeline;
+ bit [2 * MAX_LATENCY + 1:0] write_command_pipeline;
+ bit [2 * MAX_LATENCY + 1:0] precharge_command_pipeline;
+ bit [2 * MAX_LATENCY + 1:0] activate_command_pipeline;
+
+ reg [PORT_MEM_DQ_WIDTH - 1:0] mem_dq_from_mem;
+ reg [PORT_MEM_DQ_WIDTH - 1:0] mem_dq_int;
+ reg [PORT_MEM_DQ_WIDTH - 1:0] mem_dq_captured;
+ reg [PORT_MEM_DQ_WIDTH - 1:0] mem_ck_sampled_by_dqs;
+ reg [PORT_MEM_DQS_WIDTH - 1:0] mem_dm_captured;
+ bit mem_dq_en;
+ bit mem_dqs_en;
+ bit mem_dqs_preamble;
+ wire [PORT_MEM_DQ_WIDTH - 1:0] full_mask;
+ logic [PORT_MEM_DQ_WIDTH - 1:0] full_dbi_n;
+ wire [PORT_MEM_DQ_WIDTH - 1:0] full_dbi_n_in;
+ reg [PORT_MEM_DQS_WIDTH - 1:0] dbi_n;
+
+ time mem_dqs_time[PORT_MEM_DQS_WIDTH];
+ time mem_ck_time;
+
+ bit wdbi_en;
+ bit rdbi_en;
+ bit dm_n_en;
+
+
+ function automatic string bank_str (input [PORT_MEM_BG_WIDTH-1:0] bank_group, input [PORT_MEM_BA_WIDTH-1:0] bank);
+ string result;
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ $sformat(result, "BANK_GROUP [ %0h ] - BANK [ %0h ]", bank_group, bank);
+ end else begin
+ $sformat(result, "BANK [ %0h ]", bank);
+ end
+ return result;
+ endfunction
+
+ task init_guaranteed_write (input integer option);
+
+ static int burst_length = 8;
+ static int other_bank = 3;
+ bit [32-1:0] five_s;
+ bit [32-1:0] a_s;
+
+ int i;
+ command_struct cmd;
+
+ $display("Pre-initializing memory for guaranteed write");
+
+ if (option == -1) begin
+ $display("option=%0d: distorting guaranteed write data", option);
+ five_s = 32'h55554;
+ a_s = 32'hAAAAB;
+ end else begin
+ five_s = 32'h55555;
+ a_s = 32'hAAAAA;
+ end
+
+ cmd.word_count = 0;
+ cmd.burst_length = burst_length;
+ cmd.address = 0;
+ cmd.bank = 0;
+ cmd.bank_group = 0;
+ cmd.opcode = OPCODE_WRITE;
+
+ cmd.address = burst_length;
+ cmd.bank = 0;
+ for (i = 0; i < burst_length; i++) begin
+ cmd.word_count = i;
+ write_memory(cmd, five_s, '0, '0);
+ end
+
+ cmd.address = 0;
+ cmd.bank = other_bank;
+ for (i = 0; i < burst_length; i++) begin
+ cmd.word_count = i;
+ write_memory(cmd, five_s, '0, '0);
+ end
+
+ cmd.address = burst_length;
+ cmd.bank = other_bank;
+ for (i = 0; i < burst_length; i++) begin
+ cmd.word_count = i;
+ write_memory(cmd, a_s, '0, '0);
+ end
+
+ cmd.address = 0;
+ cmd.bank = 0;
+ for (i = 0; i < burst_length; i++) begin
+ cmd.word_count = i;
+ write_memory(cmd, a_s, '0, '0);
+ end
+
+ endtask
+
+ function automatic int min;
+ input int a;
+ input int b;
+ int result = (a < b) ? a : b;
+ return result;
+ endfunction
+
+ task automatic initialize_db;
+ while (write_command_queue.size() > 0)
+ write_command_queue.delete(0);
+ while (write_word_count_queue.size() > 0)
+ write_word_count_queue.delete(0);
+ while (write_burst_length_queue.size() > 0)
+ write_burst_length_queue.delete(0);
+ while (write_address_queue.size() > 0)
+ write_address_queue.delete(0);
+ while (write_bank_queue.size() > 0)
+ write_bank_queue.delete(0);
+
+ while (read_command_queue.size() > 0)
+ read_command_queue.delete(0);
+ while (read_word_count_queue.size() > 0)
+ read_word_count_queue.delete(0);
+ while (read_burst_length_queue.size() > 0)
+ read_burst_length_queue.delete(0);
+ while (read_address_queue.size() > 0)
+ read_address_queue.delete(0);
+ while (read_bank_queue.size() > 0)
+ read_bank_queue.delete(0);
+
+ while (precharge_command_queue.size() > 0)
+ precharge_command_queue.delete(0);
+ while (precharge_bank_queue.size() > 0)
+ precharge_bank_queue.delete(0);
+
+ while (activate_command_queue.size() > 0)
+ activate_command_queue.delete(0);
+ while (activate_bank_queue.size() > 0)
+ activate_bank_queue.delete(0);
+ while (activate_row_queue.size() > 0)
+ activate_row_queue.delete(0);
+
+ mem_data.delete();
+ endtask
+
+ task automatic set_cas_latency (input bit [3:0] code);
+ if(PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ case(code)
+ 4'b0000 : cas_latency = 9;
+ 4'b0001 : cas_latency = 10;
+ 4'b0010 : cas_latency = 11;
+ 4'b0011 : cas_latency = 12;
+ 4'b0100 : cas_latency = 13;
+ 4'b0101 : cas_latency = 14;
+ 4'b0110 : cas_latency = 15;
+ 4'b0111 : cas_latency = 16;
+ 4'b1101 : cas_latency = 17;
+ 4'b1000 : cas_latency = 18;
+ 4'b1110 : cas_latency = 19;
+ 4'b1001 : cas_latency = 20;
+ 4'b1111 : cas_latency = 21;
+ 4'b1010 : cas_latency = 22;
+ 4'b1011 : cas_latency = 24;
+ default: begin
+ $display("Error: Use of reserved DDR4 CAS latency code : %b", code);
+ $stop(1);
+ end
+ endcase
+ end else begin
+ case(code)
+ 4'b0001 : cas_latency = 5;
+ 4'b0010 : cas_latency = 6;
+ 4'b0011 : cas_latency = 7;
+ 4'b0100 : cas_latency = 8;
+ 4'b0101 : cas_latency = 9;
+ 4'b0110 : cas_latency = 10;
+ 4'b0111 : cas_latency = 11;
+ 4'b1000 : cas_latency = 12;
+ 4'b1001 : cas_latency = 13;
+ 4'b1010 : cas_latency = 14;
+ default: begin
+ end
+ endcase
+ end
+
+ if (MEM_VERBOSE) begin
+ $display(" CAS LATENCY set to : %0d", cas_latency);
+ end
+
+ endtask
+
+ task automatic set_additive_latency (input bit [1:0] code);
+ case(code)
+ 3'b00 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting Additive CAS LATENCY to 0");
+ al_type = DDR_AL_TYPE_ZERO;
+ end
+ 3'b01 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting Additive CAS LATENCY to CL - 1");
+ al_type = DDR_AL_TYPE_CL_MINUS_1;
+ end
+ 3'b10 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting Additive CAS LATENCY to CL - 2");
+ al_type = DDR_AL_TYPE_CL_MINUS_2;
+ end
+ 3'b11 : begin
+ $display("Error: Use of reserved Additive CAS latency code : %b", code);
+ $stop(1);
+ end
+ endcase
+ endtask
+
+ task automatic set_write_leveling_mode (input bit code);
+ wlevel_en = code;
+ if (MEM_VERBOSE)
+ $display(" Setting write_leveling mode to %d", wlevel_en);
+ endtask
+
+ function automatic int get_additive_latency;
+ int additive_latency = 0;
+ case(al_type)
+ DDR_AL_TYPE_ZERO : begin
+ end
+ DDR_AL_TYPE_CL_MINUS_1 : begin
+ additive_latency = cas_latency - 1;
+ end
+ DDR_AL_TYPE_CL_MINUS_2 : begin
+ additive_latency = cas_latency - 2;
+ end
+ default : begin
+ $display("Error: Unknown additive latency type: %0d", al_type);
+ end
+ endcase
+ return additive_latency;
+ endfunction
+
+ task automatic set_parity_latency (input bit [2:0] code);
+
+ int i;
+
+ case(code)
+ 3'b000 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting A/C parity to DISABLED");
+ parity_latency = 0;
+ end
+ 3'b001 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting A/C parity to 4CK");
+ parity_latency = 4;
+ end
+ 3'b010 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting A/C parity to 5CK");
+ parity_latency = 5;
+ end
+ 3'b011 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting A/C parity to 6CK");
+ parity_latency = 6;
+ end
+ 3'b100 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting A/C parity to 8CK");
+ parity_latency = 8;
+ end
+ default : begin
+ $display("Error: Use of reserved A/C parity latency code : %b", code);
+ $stop(1);
+ end
+ endcase
+
+ while (parity_latency_queue.size() > 0)
+ parity_latency_queue.delete(0);
+
+ for (i = 0; i < 2 * MAX_LATENCY; i++) begin
+ parity_latency_pipeline[i] = 0;
+ end
+
+ endtask
+
+ function automatic int get_read_latency;
+ int read_latency = cas_latency + get_additive_latency();
+ return read_latency;
+ endfunction
+
+ function automatic int get_write_latency;
+ int write_latency = cas_write_latency + get_additive_latency();
+ return write_latency;
+ endfunction
+
+ function automatic int get_precharge_latency;
+ return tRTP_cycles + get_additive_latency();
+ endfunction
+
+ task automatic set_cas_write_latency (input bit [2:0] code);
+ if(PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ case(code)
+ 3'b000 : cas_write_latency = 9;
+ 3'b001 : cas_write_latency = 10;
+ 3'b010 : cas_write_latency = 11;
+ 3'b011 : cas_write_latency = 12;
+ 3'b100 : cas_write_latency = 14;
+ 3'b101 : cas_write_latency = 16;
+ 3'b110 : cas_write_latency = 18;
+ default : begin
+ $display("Error: Use of reserved DDR4 CAS WRITE latency code : %b", code);
+ $stop(1);
+ end
+ endcase
+ end else begin
+ case(code)
+ 3'b000 : cas_write_latency = 5;
+ 3'b001 : cas_write_latency = 6;
+ 3'b010 : cas_write_latency = 7;
+ 3'b011 : cas_write_latency = 8;
+ 3'b100 : cas_write_latency = 9;
+ 3'b101 : cas_write_latency = 10;
+ default : begin
+ $display("Error: Use of reserved CAS WRITE latency code : %b", code);
+ $stop(1);
+ end
+ endcase
+ end
+ if (MEM_VERBOSE)
+ $display(" CAS WRITE LATENCY set to : %0d", cas_write_latency);
+ endtask
+
+ task automatic reset_dll (input bit code);
+ if(code == 1'b1) begin
+ if (MEM_VERBOSE)
+ $display(" Resetting DLL");
+ end
+ endtask
+
+ task automatic set_burst_type (input bit [1:0] burst_mode);
+ case (burst_mode)
+ 2'b00 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting burst length Fixed BL8");
+ burst_type = DDR_BURST_TYPE_BL8;
+ end
+ 2'b01 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting burst length on-the-fly");
+ burst_type = DDR_BURST_TYPE_OTF;
+ end
+ 2'b10 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting burst length Fixed BL4");
+ burst_type = DDR_BURST_TYPE_BL4;
+ end
+ default : begin
+ $display("ERROR: Invalid burst type mode %0d specified!", burst_mode);
+ $finish(1);
+ end
+ endcase
+ endtask
+
+ task automatic set_crc (input bit crc);
+ crc_en = crc;
+ $display(" Setting CRC %s", crc_en ? "enabled" : "disabled");
+ endtask
+ task automatic set_lpasr (input bit [1:0] code);
+ if (code ^ lpasr) begin
+ case (code)
+ 2'b00 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting low power array self refresh mode: Manual, Normal temperature range");
+ end
+ 2'b01 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting low power array self refresh mode: Manual, Reduced temperature range");
+ end
+ 2'b10 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting low power array self refresh mode: Manual, Extended temperature range");
+ end
+ 2'b11 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting low power array self refresh mode: Auto self-refresh");
+ end
+ default : begin
+ $display("ERROR: Invalid low power array self refresh mode %0d specified!", code);
+ $finish(1);
+ end
+ endcase
+ lpasr = code;
+ $display(" Low power array self refresh mode behavior is not implemented in this memory model.");
+ end
+ endtask
+
+ task automatic set_geardown_mode (input bit code);
+ if (code ^ geardown_mode) begin
+ $display(" Setting geardown mode: %d", code);
+ if (code)
+ $display(" Geardown mode behavior is not implemented in this memory model.");
+ geardown_mode = code;
+ end
+ endtask
+ task automatic set_fine_granularity_refresh_mode (input bit [2:0] code);
+ if (code ^ fine_granularity_refresh_mode) begin
+ case (code)
+ 3'b000 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting fine granularity refresh mode: Fixed 1x");
+ end
+ 3'b001 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting fine granularity refresh mode: Fixed 2x");
+ end
+ 3'b010 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting fine granularity refresh mode: Fixed 4x");
+ end
+ 3'b101 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting fine granularity refresh mode: On-the-fly 2x");
+ end
+ 3'b110 : begin
+ if (MEM_VERBOSE)
+ $display(" Setting fine granularity refresh mode: On-the-fly 4x");
+ end
+ default : begin
+ $display("ERROR: Invalid fine granularity refresh mode %0d specified!", code);
+ $finish(1);
+ end
+ endcase
+ fine_granularity_refresh_mode = code;
+ $display(" Fine granularity refresh mode behavior is not implemented in this memory model.");
+ end
+ endtask
+
+ task automatic set_max_power_saving (input bit code);
+ if (code ^ max_power_saving_en) begin
+ $display(" Setting maximum power saving mode: %d", code);
+ if (code)
+ $display(" Maximum power saving mode behavior is not implemented in this memory model.");
+ max_power_saving_en = code;
+ end
+ endtask
+ task automatic set_temp_controlled_refresh_range(input bit code);
+ if (code ^ temp_controlled_refresh_range) begin
+ $display(" Setting temperature controlled refresh range: %d", code);
+ temp_controlled_refresh_range = code;
+ end
+ endtask
+ task automatic set_temp_controlled_refresh_enable(input bit code);
+ if (code ^ temp_controlled_refresh_en) begin
+ $display(" Setting temperature controlled refresh enable: %d", code);
+ if (code)
+ $display(" Temperature controlled refresh behavior is not implemented in this memory model.");
+ temp_controlled_refresh_en = code;
+ end
+ endtask
+
+ task automatic cmd_nop;
+ if (MEM_VERBOSE && !DISABLE_NOP_DISPLAY)
+ $display("[%0t] [DWR=%0d%0d%0d]: NOP Command", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX);
+ endtask
+
+ task automatic cmd_des;
+ if (MEM_VERBOSE && !DISABLE_NOP_DISPLAY)
+ $display("[%0t] [DWR=%0d%0d%0d]: DES Command", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX);
+ endtask
+
+ task automatic cmd_zqc;
+ if (MEM_VERBOSE)
+ $display("[%0t] [DWR=%0d%0d%0d]: ZQC Command", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX);
+ endtask
+
+
+ task automatic cmd_unknown;
+ if (MEM_VERBOSE)
+ $display("[%0t] [DWR=%0d%0d%0d]: WARNING: Unknown Command (OPCODE %b). Command ignored.", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, new_command.opcode);
+ endtask
+
+ task automatic cmd_set_activate;
+ int activate_latency = min(get_read_latency(), get_write_latency()) + 1;
+
+ if (MEM_VERBOSE)
+ $display("[%0t] [DWR=%0d%0d%0d]: ACTIVATE (queue) - %s - ROW [ %0h ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, bank_str(new_command.bank_group, new_command.bank), new_command.address);
+ activate_command_queue.push_back(DDR_CMD_TYPE_ACTIVATE);
+ activate_bank_queue.push_back(new_command.bank);
+ activate_bank_group_queue.push_back(new_command.bank_group);
+ activate_row_queue.push_back(new_command.address);
+ activate_command_pipeline[ 2 * activate_latency ] = 1;
+ bg[new_command.bank_group].bank[new_command.bank].last_activate_cycle = clock_cycle;
+ endtask
+
+ task automatic cmd_activate(bit [PORT_MEM_BG_WIDTH-1:0] bank_group, bit [PORT_MEM_BA_WIDTH-1:0] bank, bit [PORT_MEM_A_WIDTH-1:0] address);
+ if (MEM_VERBOSE)
+ $display("[%0t] [DWR=%0d%0d%0d]: ACTIVATE (execute) - %s - ROW [ %0h ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, bank_str(bank_group, bank), address);
+ bg[bank_group].bank[bank].opened_row = address;
+ endtask
+
+ task automatic cmd_precharge(bit [PORT_MEM_BG_WIDTH-1:0] bank_group, bit [PORT_MEM_BA_WIDTH-1:0] bank, bit all_banks);
+ if (MEM_VERBOSE)
+ if(all_banks)
+ $display("[%0t] [DWR=%0d%0d%0d]: PRECHARGE - ALL BANKS", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX);
+ else
+ $display("[%0t] [DWR=%0d%0d%0d]: PRECHARGE - %s", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, bank_str(bank_group, bank));
+ bg[bank_group].bank[bank].last_precharge_cycle = clock_cycle;
+ endtask
+
+ task automatic cmd_mrs;
+ int mrs_idx;
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4")
+ $display("MRS commands not fully supported for DDR4 at this time");
+
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4")
+ mrs_idx = {new_command.bank_group[0], new_command.bank[1:0]};
+ else
+ mrs_idx = new_command.bank;
+
+ if (MEM_VERBOSE)
+ $display("[%0t] [DWR=%0d%0d%0d]: MRS Command - MRS [ %0d ] -> %0h", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, mrs_idx, new_command.address);
+
+ case(mrs_idx)
+ 3'b000 : begin
+ if (MEM_VERBOSE)
+ $display(" MRS - 0");
+ set_burst_type(new_command.address[1:0]);
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ set_cas_latency({new_command.address[6:4], new_command.address[2:2] });
+ end else begin
+ set_cas_latency({new_command.address[2:2], new_command.address[6:4]});
+ end
+ reset_dll(new_command.address[8]);
+ end
+
+ 3'b001 : begin
+ if (MEM_VERBOSE)
+ $display(" MRS - 1");
+ set_additive_latency(new_command.address[4:3]);
+ set_write_leveling_mode(new_command.address[7]);
+ end
+
+ 3'b010 : begin
+ if (MEM_VERBOSE)
+ $display(" MRS - 2");
+ set_cas_write_latency(new_command.address[5:3]);
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ set_lpasr(new_command.address[7:6]);
+ set_crc(new_command.address[12]);
+ end
+ end
+
+ 3'b011 : begin
+ if (MEM_VERBOSE)
+ $display(" MRS - 3");
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ set_geardown_mode(new_command.address[3]);
+ set_fine_granularity_refresh_mode(new_command.address[8:6]);
+ end
+ end
+
+ 3'b100 : begin
+ if (MEM_VERBOSE)
+ $display(" MRS - 4");
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ set_max_power_saving(new_command.address[1]);
+ set_temp_controlled_refresh_range(new_command.address[2]);
+ set_temp_controlled_refresh_enable(new_command.address[3]);
+ end
+ end
+
+ 3'b101 : begin
+ if (MEM_VERBOSE)
+ $display(" MRS - 5");
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ set_parity_latency(new_command.address[2:0]);
+ dm_n_en = new_command.address[10];
+ wdbi_en = new_command.address[11];
+ rdbi_en = new_command.address[12];
+ end
+ end
+
+ 3'b110 : begin
+ if (MEM_VERBOSE)
+ $display(" MRS - 6: not supported");
+ end
+
+ 3'b111 : begin
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ if (MEM_VERBOSE) begin
+ $display(" Detected RCD/DB Control Word");
+ end
+ end else begin
+ $display("Error: MRS Invalid Bank Address: %0d", mrs_idx);
+ $stop(1);
+ end
+ end
+ endcase
+ endtask
+
+ task automatic cmd_refresh;
+ if (MEM_VERBOSE)
+ $display("[%0t] [DWR=%0d%0d%0d]: REFRESH Command", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX);
+
+ for (int g = 0; g < NUM_BANK_GROUPS; g++) begin
+ for (int b = 0; b < NUM_BANKS_PER_GROUP; b++) begin
+ refresh_bank(g, b);
+ end
+ end
+ endtask
+
+ task automatic cmd_read;
+ int read_latency = get_read_latency();
+ int precharge_latency = get_precharge_latency();
+
+ if (MEM_VERBOSE) begin
+ if(mem_a_wire[10])
+ $display("[%0t] [DWR=%0d%0d%0d]: READ with AP (BL%0d) - %s - COL [ %0h ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, new_command.burst_length, bank_str(new_command.bank_group, new_command.bank), new_command.address);
+ else
+ $display("[%0t] [DWR=%0d%0d%0d]: READ (BL%0d) - %s - COL [ %0h ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, new_command.burst_length, bank_str(new_command.bank_group, new_command.bank), new_command.address);
+ end
+
+ new_command.word_count = 0;
+ read_command_queue.push_back(new_command.cmd_type);
+ read_word_count_queue.push_back(new_command.word_count);
+ read_burst_length_queue.push_back(new_command.burst_length);
+ read_address_queue.push_back(new_command.address);
+ read_bank_queue.push_back(new_command.bank);
+ read_bank_group_queue.push_back(new_command.bank_group);
+ read_command_pipeline[ 2 * read_latency ] = 1;
+ bg[new_command.bank_group].bank[new_command.bank].last_read_cmd_cycle = clock_cycle;
+ refresh_bank(new_command.bank_group, new_command.bank);
+
+ if(mem_a_wire[10]) begin
+ precharge_command_queue.push_back(DDR_CMD_TYPE_PRECHARGE);
+ precharge_bank_group_queue.push_back(new_command.bank_group);
+ precharge_bank_queue.push_back(new_command.bank);
+ precharge_command_pipeline[ 2 * precharge_latency ] = 1;
+ end
+ endtask
+
+ task automatic cmd_write;
+ int write_latency = get_write_latency();
+
+ if (MEM_VERBOSE) begin
+ if(mem_a_wire[10])
+ $display("[%0t] [DWR=%0d%0d%0d]: WRITE with AP (BL%0d) - BANK [ %0d ] - COL [ %0h ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, new_command.burst_length, new_command.bank, new_command.address);
+ else
+ $display("[%0t] [DWR=%0d%0d%0d]: WRITE (BL%0d) - BANK [ %0d ] - COL [ %0h ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, new_command.burst_length, new_command.bank, new_command.address);
+ end
+
+ new_command.word_count = 0;
+ write_command_queue.push_back(new_command.cmd_type);
+ write_word_count_queue.push_back(new_command.word_count);
+ write_burst_length_queue.push_back(new_command.burst_length);
+ write_address_queue.push_back(new_command.address);
+ write_bank_queue.push_back(new_command.bank);
+ write_bank_group_queue.push_back(new_command.bank_group);
+ write_command_pipeline[2 * write_latency] = 1'b1;
+ bg[new_command.bank_group].bank[new_command.bank].last_write_cmd_cycle = clock_cycle;
+ endtask
+
+ task automatic refresh_bank(input int bank_group_num, input int bank_num);
+ if (MEM_VERBOSE)
+ $display("[%0t] [DWR=%0d%0d%0d]: Refreshing %s", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, bank_str(bank_group_num, bank_num));
+ bg[bank_group_num].bank[bank_num].last_ref_time = $time;
+ bg[bank_group_num].bank[bank_num].last_ref_cycle = clock_cycle;
+ endtask
+
+ task automatic init_banks;
+ int b,g;
+ for (g = 0; g < NUM_BANK_GROUPS; g++) begin
+ for (b = 0; b < NUM_BANKS_PER_GROUP; b++) begin
+ if (MEM_VERBOSE)
+ $display("[%0t] [DWR=%0d%0d%0d]: Initializing %s", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, bank_str(g,b));
+ bg[g].bank[b].opened_row = '0;
+ bg[g].bank[b].last_ref_time = 0;
+ bg[g].bank[b].last_ref_cycle = 0;
+ bg[g].bank[b].last_activate_cycle = 0;
+ bg[g].bank[b].last_precharge_cycle = 0;
+ bg[g].bank[b].last_read_cmd_cycle = 0;
+ bg[g].bank[b].last_read_access_cycle = 0;
+ bg[g].bank[b].last_write_cmd_cycle = 0;
+ bg[g].bank[b].last_write_access_cycle = 0;
+ end
+ end
+ endtask
+
+ task automatic check_violations;
+
+ /* **** *
+ * tRCD *
+ * **** */
+
+ if(new_command.cmd_type == DDR_CMD_TYPE_READ) begin
+ if(bg[new_command.bank_group].bank[new_command.bank].last_activate_cycle > bg[new_command.bank_group].bank[new_command.bank].last_read_cmd_cycle + get_additive_latency() - tRCD_cycles) begin
+ $display("[%0t] [DWR=%0d%0d%0d]: ERROR: tRCD violation (READ) on %s @ cycle %0d", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, bank_str(new_command.bank_group, new_command.bank), clock_cycle);
+ $display(" tRCD = %0d", tRCD_cycles);
+ $display(" Last ACTIVATE @ %0d", bg[new_command.bank_group].bank[new_command.bank].last_activate_cycle);
+ $display(" Last READ CMD @ %0d", bg[new_command.bank_group].bank[new_command.bank].last_read_cmd_cycle);
+ $finish(1);
+ end
+ end
+ if(new_command.cmd_type == DDR_CMD_TYPE_WRITE) begin
+ if(bg[new_command.bank_group].bank[new_command.bank].last_activate_cycle > bg[new_command.bank_group].bank[new_command.bank].last_write_cmd_cycle + get_additive_latency() - tRCD_cycles) begin
+ $display("[%0t] [DWR=%0d%0d%0d]: ERROR: tRCD violation (WRITE) on %s @ cycle %0d", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, bank_str(new_command.bank_group, new_command.bank), clock_cycle);
+ $display(" tRCD = %0d", tRCD_cycles);
+ $display(" Last ACTIVATE @ %0d", bg[new_command.bank_group].bank[new_command.bank].last_activate_cycle);
+ $display(" Last WRITE CMD @ %0d", bg[new_command.bank_group].bank[new_command.bank].last_write_cmd_cycle);
+ $finish(1);
+ end
+ end
+ endtask
+
+ task write_memory(
+ input command_struct write_command,
+ input [PORT_MEM_DQ_WIDTH - 1:0] write_data,
+ input [PORT_MEM_DQ_WIDTH - 1:0] data_mask,
+ input [PORT_MEM_DQ_WIDTH - 1:0] dbi_n);
+
+ bit [PORT_MEM_BA_WIDTH - 1:0] bank_address;
+ bit [PORT_MEM_BG_WIDTH - 1:0] bank_group;
+ bit [MEM_ROW_ADDR_WIDTH - 1:0] row_address;
+ bit [MEM_COL_ADDR_WIDTH - 1:0] col_address;
+ bit [PORT_MEM_BG_WIDTH + PORT_MEM_BA_WIDTH + MEM_ROW_ADDR_WIDTH + MEM_COL_ADDR_WIDTH - 1 : 0] address;
+ bit [PORT_MEM_DQ_WIDTH - 1:0] masked_data;
+
+ integer i;
+
+ bank_group = write_command.bank_group;
+ bank_address = write_command.bank;
+ row_address = bg[bank_group].bank[bank_address].opened_row;
+ col_address = write_command.address;
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ address = {bank_group, bank_address, row_address, col_address} + write_command.word_count;
+ end else begin
+ address = {bank_address, row_address, col_address} + write_command.word_count;
+ end
+
+ if (write_command.word_count == 0) begin
+ for (int i = 0; i < CRC_NUM_TREES; i = i + 1) begin
+ write_burst_data[i] = {CRC_TREE_BITS{1'b1}};
+ end
+ end
+
+ for(i = 0; i < PORT_MEM_DQ_WIDTH; i = i + 1) begin
+ if (data_mask[i] !== 0 && data_mask[i] !== 1)
+ masked_data[i] = 'x;
+ else if (wdbi_en) begin
+ masked_data[i] = dbi_n[i] ? write_data[i] : ~write_data[i];
+ end else if (PROTOCOL_ENUM == "PROTOCOL_DDR4" ? ~data_mask[i] : data_mask[i])
+ begin
+ if (mem_data.exists(address))
+ masked_data[i] = mem_data[address][i];
+ else
+ masked_data[i] = 'x;
+ end
+ else
+ masked_data[i] = write_data[i];
+
+ write_burst_data[i/CRC_DQ_RATIO][((i%CRC_DQ_RATIO) * CRC_DQ_RATIO) + write_command.word_count] = write_data[i];
+ end
+
+ if(wdbi_en || dm_n_en) begin
+ for(i = 0; i < PORT_MEM_DBI_N_WIDTH; i = i + 1) begin
+ write_burst_data[i][64 + write_command.word_count] = dbi_n[i*MEM_DQS_GROUP_SIZE];
+ end
+ end
+
+ if (MEM_VERBOSE)
+ $display("[%0t] [DWR=%0d%0d%0d]: Writing data %h (%h/%h) @ %0h (GBRC=%0h/%0h/%0h/%0h ) burst %0d",
+ $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, masked_data, write_data, PROTOCOL_ENUM == "PROTOCOL_DDR4" ? data_mask : ~data_mask, address, bank_group, bank_address, row_address, col_address, write_command.word_count);
+
+ mem_data[address] = masked_data;
+ bg[bank_group].bank[bank_address].last_write_access_cycle = clock_cycle;
+ endtask
+
+ task check_crc (
+ input command_struct write_command,
+ input [PORT_MEM_DQ_WIDTH - 1:0] dq_write,
+ input [PORT_MEM_DBI_N_WIDTH - 1:0] dbi_write);
+
+ crc_received_prev = crc_received_curr;
+ crc_received_curr = dq_write;
+
+ for (int i = 0; i < CRC_NUM_TREES; i = i + 1) begin
+ if (write_command.word_count == CRC_BURST_LENGTH - 1) begin
+ if (mem_crc[i] != crc_received[i]) begin
+ $display("Error: CRC tree %d expected %x but received %x", i, mem_crc[i], crc_received[i]);
+ for (i = 2*MEM_CRC_ALERT; i < 2*MEM_CRC_ALERT + 2*(MEM_CRC_ALERT + MEM_CRC_ALERT_PW); i = i + 1) begin
+ crc_alert_n_pipeline[i] = 1'b0;
+ end
+ $finish(1);
+ end else begin
+ end
+ end
+ end
+
+ endtask
+
+ generate
+ genvar i;
+ if(PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ for (i = 0; i < CRC_NUM_TREES; i = i + 1) begin
+ altera_emif_ddr4_crc_tree crc_tree(
+ .d(write_burst_data[i]),
+ .newcrc(mem_crc[i])
+ );
+ assign crc_received[i] = crc_received_prev[(i+1)*CRC_DQ_RATIO-1 : i*CRC_DQ_RATIO];
+ end
+ end
+ endgenerate
+
+ task read_memory(
+ input command_struct write_command,
+ output [PORT_MEM_DQ_WIDTH - 1:0] read_data,
+ output [PORT_MEM_DQS_WIDTH - 1:0] dbi_n);
+
+ bit [PORT_MEM_BA_WIDTH - 1:0] bank_address;
+ bit [PORT_MEM_BG_WIDTH - 1:0] bank_group;
+ bit [MEM_ROW_ADDR_WIDTH - 1:0] row_address;
+ bit [MEM_COL_ADDR_WIDTH - 1:0] col_address;
+ bit [PORT_MEM_BG_WIDTH + PORT_MEM_BA_WIDTH + MEM_ROW_ADDR_WIDTH + MEM_COL_ADDR_WIDTH - 1 : 0] address;
+ reg [1:0] int_error_inject;
+ integer bit_index;
+
+ bank_group = write_command.bank_group;
+ bank_address = write_command.bank;
+ row_address = bg[bank_group].bank[bank_address].opened_row;
+ col_address = write_command.address;
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ address = {bank_group, bank_address, row_address, col_address} + write_command.word_count;
+ end else begin
+ address = {bank_address, row_address, col_address} + write_command.word_count;
+ end
+
+ if (mem_data.exists(address)) begin
+ integer i, j;
+ if (rdbi_en) begin
+ for (i = 0; i < PORT_MEM_DQS_WIDTH; i = i + 1) begin
+ integer sum;
+ sum = 0;
+ for (j = 0; j < (MEM_DQS_GROUP_SIZE); j = j + 1) begin
+ sum = sum + mem_data[address][i*(MEM_DQS_GROUP_SIZE) + j];
+ end
+ dbi_n[i] = sum >= 4;
+ end
+ read_data = mem_data[address];
+ end else begin
+ dbi_n = 'z;
+ read_data = mem_data[address];
+ end
+ for (i = 0; i < PORT_MEM_DQ_WIDTH; i = i + 1) begin: dbi_n_in_mapping
+ full_dbi_n [i] = dbi_n[i / MEM_DQS_GROUP_SIZE];
+ end
+
+ if (MEM_CFG_GEN_SBE == 1) begin
+ int_error_inject = 2'b01;
+ end
+ else if (MEM_CFG_GEN_DBE == 1) begin
+ int_error_inject = 2'b11;
+ end
+ else begin
+ int_error_inject = 2'b00;
+ end
+ bit_index = {$random} % PORT_MEM_DQ_WIDTH;
+ read_data[bit_index] = read_data[bit_index] ^ int_error_inject[0];
+ if (bit_index < PORT_MEM_DQ_WIDTH-1) begin
+ read_data[bit_index+1] = read_data[bit_index+1] ^ int_error_inject[1];
+ end
+
+ if (MEM_VERBOSE)
+ $display("[%0t] [DWR=%0d%0d%0d]: Reading data %h @ %0h (GBRC=%0h/%0h/%0h/%0h ) burst %0d",
+ $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, read_data, address, bank_group, bank_address, row_address, col_address, write_command.word_count);
+ end
+ else begin
+ if (MEM_VERBOSE)
+ $display("[%0t] [DWR=%0d%0d%0d]: WARNING: Attempting to read from uninitialized location @ %0h (GBRC=%0h/%0h/%0h/%0h) burst %0d",
+ $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, address, bank_group, bank_address, row_address, col_address, write_command.word_count);
+ read_data = '0;
+ end
+
+ bg[bank_group].bank[bank_address].last_read_access_cycle = clock_cycle;
+ endtask
+
+ if(MEM_MIRROR_ADDRESSING) begin
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ if (PORT_MEM_A_WIDTH > 14) begin
+ assign mem_a_wire = {mem_a[PORT_MEM_A_WIDTH - 1:14], mem_a[11], mem_a[12], mem_a[13], mem_a[10:9], mem_a[7], mem_a[8], mem_a[5], mem_a[6], mem_a[3], mem_a[4], mem_a[2:0]};
+ end else begin
+ assign mem_a_wire = {mem_a[11], mem_a[12], mem_a[13], mem_a[10:9], mem_a[7], mem_a[8], mem_a[5], mem_a[6], mem_a[3], mem_a[4], mem_a[2:0]};
+ end
+
+ if(PORT_MEM_BA_WIDTH > 2) begin
+ assign mem_ba_wire = {mem_ba[PORT_MEM_BA_WIDTH - 1:2], mem_ba[0], mem_ba[1]};
+ end else begin
+ assign mem_ba_wire = {mem_ba[0], mem_ba[1]};
+ end
+
+ if(PORT_MEM_BG_WIDTH > 2) begin
+ assign mem_bg_wire = {mem_bg[PORT_MEM_BG_WIDTH - 1:2], mem_bg[0], mem_bg[1]};
+ end else begin
+ assign mem_bg_wire = {mem_bg[0], mem_bg[1]};
+ end
+
+ end else begin
+ assign mem_a_wire = {mem_a[PORT_MEM_A_WIDTH - 1:9], mem_a[7], mem_a[8], mem_a[5], mem_a[6], mem_a[3], mem_a[4], mem_a[2:0]};
+
+ if(PORT_MEM_BA_WIDTH > 2) begin
+ assign mem_ba_wire = {mem_ba[PORT_MEM_BA_WIDTH - 1:2], mem_ba[0], mem_ba[1]};
+ end else begin
+ assign mem_ba_wire = {mem_ba[0], mem_ba[1]};
+ end
+
+ assign mem_bg_wire = mem_bg;
+ end
+ end
+ else begin
+ assign mem_a_wire = mem_a;
+ assign mem_ba_wire = mem_ba;
+ assign mem_bg_wire = mem_bg;
+ end
+
+ logic mem_ck_diff;
+ always @(posedge mem_ck) begin
+ if (mem_cke == 1'b1) begin
+ #8 mem_ck_diff <= mem_ck;
+ end
+ end
+
+ always @(posedge mem_ck_n) begin
+ if (mem_cke == 1'b1) begin
+ #8 mem_ck_diff <= ~mem_ck_n;
+ end
+ end
+
+ initial begin
+ int i;
+
+ $display("Altera Generic DDRx Memory Model");
+ if (MEM_VERBOSE) begin
+ $display("[%0t] [DWR=%0d%0d%0d]: Max refresh interval of %0d ps", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, REFRESH_INTERVAL_PS);
+ end
+
+ if (PORT_MEM_C_WIDTH > 0) begin
+ $display("WARNING: Chip ID not supported in memory model");
+ end
+
+ clock_cycle = 0;
+ clock_stable = 1'b0;
+ initialize_db;
+ set_burst_type(2'b0);
+ init_banks();
+
+ mem_data.delete();
+
+ if (MEM_VERBOSE) begin
+ $display(" MRS - 0");
+ end
+
+ set_burst_type(MEM_INIT_MRS0[1:0]);
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ set_cas_latency({MEM_INIT_MRS0[6:4], MEM_INIT_MRS0[2]});
+ end else begin
+ set_cas_latency({MEM_INIT_MRS0[2], MEM_INIT_MRS0[6:4]});
+ end
+
+ if (MEM_VERBOSE) begin
+ $display(" MRS - 1");
+ end
+
+ set_additive_latency(MEM_INIT_MRS1[4:3]);
+
+ if (MEM_VERBOSE) begin
+ $display(" MRS - 2");
+ end
+
+ set_cas_write_latency(MEM_INIT_MRS2[5:3]);
+ set_crc(MEM_INIT_MRS2[12]);
+
+ if (MEM_VERBOSE) begin
+ $display(" MRS - 3: not supported");
+ end
+
+ parity_latency = 0;
+ wdbi_en = 0;
+ rdbi_en = 0;
+ max_power_saving_en = 0;
+ temp_controlled_refresh_range = 0;
+ temp_controlled_refresh_en = 0;
+
+ if (MEM_GUARANTEED_WRITE_INIT != 0) begin
+ init_guaranteed_write(MEM_GUARANTEED_WRITE_INIT);
+ end
+
+ active_command.cmd_type <= DDR_CMD_TYPE_NOP;
+
+ for (i = 0; i < 2 * MAX_LATENCY; i++) begin
+ read_command_pipeline[i] = 0;
+ write_command_pipeline[i] = 0;
+ parity_latency_pipeline[i] = 0;
+ end
+
+ for (i = 0; i <= ALERT_N_PIPELINE_SIZE; i++) begin
+ parity_alert_n_pipeline[i] = 1'b1;
+ crc_alert_n_pipeline[i] = 1'b1;
+ end
+
+ last_refresh_time = 0;
+ refresh_burst_active = 0;
+ refresh_executed_count = 0;
+ refresh_required_time = 0;
+ refresh_debt = 0;
+ mem_ck_sampled_by_dqs = '0;
+ end
+
+ always @ (posedge mem_ck) begin
+ clock_cycle <= clock_cycle + 1;
+ if (clock_cycle == 4) clock_stable <= 1'b1;
+ end
+
+ wire [MEM_COL_ADDR_WIDTH-1:0] col_addr;
+ generate
+ if(MEM_COL_ADDR_WIDTH <= 10) begin : col_addr_gen1
+ assign col_addr = mem_a_wire[9:0];
+ end
+ else if(MEM_COL_ADDR_WIDTH == 11) begin : col_addr_gen2
+ assign col_addr = {mem_a_wire[11],mem_a_wire[9:0]};
+ end
+ else begin : col_addr_gen3
+ assign col_addr = {mem_a_wire[MEM_COL_ADDR_WIDTH+1:13],mem_a_wire[11],mem_a_wire[9:0]};
+ end
+ endgenerate
+
+ always @ (posedge mem_ck_diff or negedge mem_ck_diff) begin
+ int i;
+
+ mem_ck_time = $time;
+ read_command_pipeline = read_command_pipeline >> 1;
+ write_command_pipeline = write_command_pipeline >> 1;
+ activate_command_pipeline = activate_command_pipeline >> 1;
+ parity_latency_pipeline = parity_latency_pipeline >> 1;
+ crc_alert_n_pipeline = crc_alert_n_pipeline >> 1;
+ parity_alert_n_pipeline = parity_alert_n_pipeline >> 1;
+
+ crc_alert_n_pipeline[ALERT_N_PIPELINE_SIZE] = 1'b1;
+ parity_alert_n_pipeline[ALERT_N_PIPELINE_SIZE] = 1'b1;
+
+ if(mem_ck_diff && clock_stable) begin
+ new_command.bank = mem_ba_wire;
+ new_command.bank_group = mem_bg_wire;
+ new_command.word_count = 0;
+ if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin
+ new_command.opcode = {mem_cs_n, mem_act_n, mem_ras_n, mem_cas_n, mem_we_n};
+ end else begin
+ new_command.opcode = {mem_cs_n, 1'b1, mem_ras_n, mem_cas_n, mem_we_n};
+ end
+
+ case (burst_type)
+ DDR_BURST_TYPE_BL8 : new_command.burst_length = 8;
+ DDR_BURST_TYPE_BL4 : new_command.burst_length = 4;
+ DDR_BURST_TYPE_OTF : new_command.burst_length = (mem_a_wire[12]) ? 8 : 4;
+ endcase
+
+ casex (new_command.opcode)
+ OPCODE_PRECHARGE : new_command.cmd_type = DDR_CMD_TYPE_PRECHARGE;
+ OPCODE_ACTIVATE : new_command.cmd_type = DDR_CMD_TYPE_ACTIVATE;
+ OPCODE_DDR4_ACTIVATE : new_command.cmd_type = DDR_CMD_TYPE_ACTIVATE;
+ OPCODE_WRITE : new_command.cmd_type = DDR_CMD_TYPE_WRITE;
+ OPCODE_READ : new_command.cmd_type = DDR_CMD_TYPE_READ;
+ OPCODE_MRS : new_command.cmd_type = DDR_CMD_TYPE_MRS;
+ OPCODE_REFRESH : new_command.cmd_type = DDR_CMD_TYPE_REFRESH;
+ OPCODE_NOP : new_command.cmd_type = DDR_CMD_TYPE_NOP;
+ OPCODE_DES : new_command.cmd_type = DDR_CMD_TYPE_DES;
+ OPCODE_ZQC : new_command.cmd_type = DDR_CMD_TYPE_ZQC;
+ default : new_command.cmd_type = DDR_CMD_TYPE_ERROR;
+ endcase
+
+ new_command.address = mem_a_wire;
+ if(new_command.cmd_type == DDR_CMD_TYPE_READ || new_command.cmd_type == DDR_CMD_TYPE_WRITE) begin
+ new_command.address = {'0,col_addr};
+ end
+
+ if (REFRESH_BURST_VALIDATION) begin
+ if (new_command.cmd_type == DDR_CMD_TYPE_REFRESH) begin
+ if (!refresh_burst_active) begin
+ refresh_burst_active = 1;
+ refresh_executed_count = 1;
+ refresh_required_time = mem_ck_time - last_refresh_time;
+ $display("[%0t] [DWR=%0d%0d%0d]: Time since last refresh %0t ps", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, refresh_required_time);
+ last_refresh_time = mem_ck_time;
+ end else begin
+ refresh_executed_count = refresh_executed_count + 1;
+ end
+ end else if (new_command.cmd_type == DDR_CMD_TYPE_NOP || new_command.cmd_type == DDR_CMD_TYPE_DES) begin
+ end else begin
+ if (refresh_burst_active) begin
+ refresh_burst_active = 0;
+ if (refresh_executed_count >= FULL_BURST_REFRESH_COUNT)
+ refresh_debt = -(STD_REFRESH_INTERVAL_PS * 9);
+ else
+ refresh_debt = refresh_debt + (refresh_required_time - (STD_REFRESH_INTERVAL_PS * refresh_executed_count));
+
+ if (refresh_debt > STD_REFRESH_INTERVAL_PS * 9) begin
+ $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: REFRESH interval has exceeded allowable buffer! %0d refreshes executed. Debt: %0t ps",
+ $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, refresh_executed_count, refresh_debt);
+ $finish(1);
+ end else begin
+ $display("[%0t] [DWR=%0d%0d%0d]: REFRESH burst complete! %0d refreshes executed. Buffer: %0d ps",
+ $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, refresh_executed_count, refresh_debt);
+ end
+ end
+ end
+ end
+
+ if (parity_latency > 0) begin
+
+ reg my_parity;
+ my_parity = ^{mem_a, mem_ba, mem_bg, mem_act_n};
+ if (mem_cs_n == 1'b0) begin
+ if (my_parity != mem_par) begin
+ for (i = 0; i < 2*parity_latency + 2*(parity_latency + MEM_PAR_ALERT_PW); i = i + 1) begin
+ if (i >= 2*parity_latency) begin
+ parity_alert_n_pipeline[i] = 1'b0;
+ end
+ end
+ end else begin
+ parity_latency_queue.push_back(new_command);
+ parity_latency_pipeline[2*parity_latency] = 1'b1;
+ end
+ end
+
+ if (parity_latency_pipeline[0]) begin
+ if (parity_latency_queue.size() == 0) begin
+ $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: Parity latency command queue empty but commands expected!", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX);
+ $stop(1);
+ end else begin
+ new_command = parity_latency_queue.pop_front();
+ end
+ end else begin
+ new_command.cmd_type = DDR_CMD_TYPE_DES;
+ end
+
+ if (parity_alert_n_pipeline[0] == 1'b0) begin
+ new_command.cmd_type = DDR_CMD_TYPE_ERROR;
+ end
+ end
+
+ case (new_command.cmd_type)
+ DDR_CMD_TYPE_NOP : cmd_nop();
+ DDR_CMD_TYPE_DES : cmd_des();
+ DDR_CMD_TYPE_ZQC : cmd_zqc();
+ DDR_CMD_TYPE_ERROR : cmd_unknown();
+ DDR_CMD_TYPE_ACTIVATE : cmd_set_activate();
+ DDR_CMD_TYPE_PRECHARGE : cmd_precharge(new_command.bank_group, new_command.bank, mem_a_wire[10]);
+ DDR_CMD_TYPE_WRITE : cmd_write();
+ DDR_CMD_TYPE_READ : cmd_read();
+ DDR_CMD_TYPE_MRS : cmd_mrs();
+ DDR_CMD_TYPE_REFRESH : cmd_refresh();
+ endcase
+
+ if(CHECK_VIOLATIONS)
+ check_violations();
+
+ end
+
+
+ if (read_command_pipeline[0]) begin
+ if (read_command_queue.size() == 0) begin
+ $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: READ command queue empty but READ commands expected!", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX);
+ $stop(1);
+ end
+ end
+
+ if (write_command_pipeline[0]) begin
+ if (write_command_queue.size() == 0) begin
+ $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: WRITE command queue empty but WRITE commands expected!", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX);
+ $stop(1);
+ end
+ end
+
+ if (active_command.cmd_type != DDR_CMD_TYPE_NOP) begin
+ if (active_command.cmd_type == DDR_CMD_TYPE_WRITE && crc_en) begin
+ if (active_command.word_count == CRC_BURST_LENGTH) begin
+ active_command.cmd_type = DDR_CMD_TYPE_NOP;
+ end
+ end else if (active_command.word_count == active_command.burst_length) begin
+ active_command.cmd_type = DDR_CMD_TYPE_NOP;
+ end
+ end
+
+
+ if (active_command.cmd_type == DDR_CMD_TYPE_NOP) begin
+
+ if (read_command_pipeline[0]) begin
+ active_command.cmd_type = read_command_queue.pop_front();
+ active_command.word_count = read_word_count_queue.pop_front();
+ active_command.burst_length = read_burst_length_queue.pop_front();
+ active_command.address = read_address_queue.pop_front();
+ active_command.bank = read_bank_queue.pop_front();
+ active_command.bank_group = read_bank_group_queue.pop_front();
+
+ if (active_command.cmd_type != DDR_CMD_TYPE_READ) begin
+ $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: Expected READ command not in queue!", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX);
+ $stop(1);
+ end
+
+ end
+ else if (write_command_pipeline[0]) begin
+ active_command.cmd_type = write_command_queue.pop_front();
+ active_command.word_count = write_word_count_queue.pop_front();
+ active_command.burst_length = write_burst_length_queue.pop_front();
+ active_command.address = write_address_queue.pop_front();
+ active_command.bank = write_bank_queue.pop_front();
+ active_command.bank_group = write_bank_group_queue.pop_front();
+
+ if (active_command.cmd_type != DDR_CMD_TYPE_WRITE) begin
+ $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: Expected WRITE command not in queue!", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX);
+ $stop(1);
+ end
+ end
+ else begin
+ if (read_command_pipeline[0] || write_command_pipeline[0]) begin
+ $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: Active command but read/write pipeline also active!", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX);
+ $stop(1);
+ end
+ end
+ end
+
+ if (precharge_command_pipeline[0]) begin
+ precharge_command.cmd_type = precharge_command_queue.pop_front();
+ precharge_command.bank = precharge_bank_queue.pop_front();
+ precharge_command.bank_group = precharge_bank_group_queue.pop_front();
+ cmd_precharge(precharge_command.bank_group, precharge_command.bank, 1'b0);
+ end
+
+ if (activate_command_pipeline[0]) begin
+ activate_command.cmd_type = activate_command_queue.pop_front();
+ activate_command.bank = activate_bank_queue.pop_front();
+ activate_command.bank_group = activate_bank_group_queue.pop_front();
+ activate_command.address = activate_row_queue.pop_front();
+ cmd_activate(activate_command.bank_group, activate_command.bank, activate_command.address);
+ end
+
+ mem_dq_en = 1'b0;
+ mem_dqs_en = 1'b0;
+ mem_dqs_preamble = 1'b0;
+ if (active_command.cmd_type == DDR_CMD_TYPE_WRITE) begin
+ integer mem_ck_dqs_diff;
+ integer dqs;
+ logic [PORT_MEM_DQ_WIDTH - 1:0] mem_dq_write;
+ #(MEM_DQS_TO_CLK_CAPTURE_DELAY);
+ mem_dq_write = '0;
+ for (dqs = 0; dqs < PORT_MEM_DQS_WIDTH; dqs = dqs + 1) begin
+
+ if (mem_ck_time > mem_dqs_time[dqs]) begin
+ mem_ck_dqs_diff = -(mem_ck_time - mem_dqs_time[dqs]);
+ end
+ else begin
+ mem_ck_dqs_diff = mem_dqs_time[dqs] - mem_ck_time;
+ end
+
+ if (mem_ck_dqs_diff >= -(MEM_CLK_TO_DQS_CAPTURE_DELAY)) begin
+ mem_dq_write = mem_dq_write | (mem_dq_captured & ({MEM_DQS_GROUP_SIZE{1'b1}} << (dqs*MEM_DQS_GROUP_SIZE)));
+ end
+ else begin
+ $display("[%0t] %s Write: mem_ck=%0t mem_dqs=%0t delta=%0d min=%0d",
+ $time, mem_ck_dqs_diff >= -(MEM_CLK_TO_DQS_CAPTURE_DELAY) ? "GOOD" : "BAD",
+ mem_ck_time, mem_dqs_time[dqs], mem_ck_dqs_diff, -(MEM_CLK_TO_DQS_CAPTURE_DELAY));
+ mem_dq_write = mem_dq_write | ({MEM_DQS_GROUP_SIZE{1'bx}} << (dqs*MEM_DQS_GROUP_SIZE));
+ end
+
+ end
+
+ if (active_command.word_count == CRC_BURST_LENGTH - 1 ||
+ active_command.word_count == CRC_BURST_LENGTH - 2) begin
+ check_crc(active_command, mem_dq_write, mem_dbi_n);
+ end else begin
+ write_memory(active_command, mem_dq_write, full_mask, full_dbi_n_in);
+ end
+ active_command.word_count = active_command.word_count+1;
+
+ end
+ else if (active_command.cmd_type == DDR_CMD_TYPE_READ) begin
+ if (rdbi_en) begin
+ read_memory(active_command, mem_dq_from_mem, dbi_n);
+ mem_dq_int = mem_dq_from_mem ^ ~full_dbi_n;
+ end else
+ read_memory(active_command, mem_dq_int, dbi_n);
+ mem_dq_en = 1'b1;
+ mem_dqs_en = 1'b1;
+ active_command.word_count = active_command.word_count+1;
+ end
+
+ if (!mem_dqs_en & (read_command_pipeline[2] | read_command_pipeline[1])) begin
+ mem_dqs_en = 1'b1;
+ mem_dqs_preamble = 1'b1;
+ end
+
+ end
+
+ generate
+ genvar dm_count;
+ for (dm_count = 0; dm_count < PORT_MEM_DQS_WIDTH; dm_count = dm_count + 1) begin: dm_mapping
+ assign full_mask [(dm_count + 1) * MEM_DQS_GROUP_SIZE - 1 : dm_count * MEM_DQS_GROUP_SIZE] = {MEM_DQS_GROUP_SIZE{mem_dm_captured[dm_count]}};
+ end
+ genvar dbi_n_count_in;
+ for (dbi_n_count_in = 0; dbi_n_count_in < PORT_MEM_DQS_WIDTH; dbi_n_count_in = dbi_n_count_in + 1) begin: dbi_n_mapping
+ assign full_dbi_n_in [(dbi_n_count_in + 1) * MEM_DQS_GROUP_SIZE - 1 : dbi_n_count_in * MEM_DQS_GROUP_SIZE] = {MEM_DQS_GROUP_SIZE{mem_dbi_n[dbi_n_count_in]}};
+ end
+ endgenerate
+
+ assign #1 mem_dqs_shifted = mem_dqs;
+ assign #1 mem_dqs_n_shifted = mem_dqs_n;
+ assign #2 mem_dqs_n_shifted_2 = mem_dqs_n;
+
+ generate
+
+ genvar dqs;
+ for (dqs = 0; dqs < PORT_MEM_DQS_WIDTH; dqs = dqs + 1) begin
+ always @(posedge mem_dqs_shifted[dqs] or posedge mem_dqs_n_shifted[dqs]) begin
+ if (mem_dqs_shifted[dqs] === 1'b1 || mem_dqs_n_shifted[dqs] === 1'b1) begin
+ mem_dqs_time[dqs] <= $time;
+ mem_dq_captured[((dqs+1)*MEM_DQS_GROUP_SIZE)-1:dqs*MEM_DQS_GROUP_SIZE] <= mem_dq[((dqs+1)*MEM_DQS_GROUP_SIZE)-1:dqs*MEM_DQS_GROUP_SIZE];
+ mem_dm_captured[dqs] <= (PROTOCOL_ENUM == "PROTOCOL_DDR4") ? ((wdbi_en || dm_n_en) ? mem_dbi_n[dqs] : 1'b1) : ((PORT_MEM_DM_WIDTH == PORT_MEM_DQS_WIDTH) ? mem_dm[dqs] : 1'b0);
+ if (mem_dqs_n_shifted_2[dqs] === 'z || mem_dqs_n_shifted_2_prev[dqs] === 'z) begin
+ mem_dq_captured[((dqs+1)*MEM_DQS_GROUP_SIZE)-1:dqs*MEM_DQS_GROUP_SIZE] <= 'z;
+ mem_dm_captured[dqs] <= 'z;
+ end
+ mem_dqs_n_shifted_2_prev[dqs] <= mem_dqs_n_shifted_2[dqs];
+ end else begin
+ mem_dq_captured[((dqs+1)*MEM_DQS_GROUP_SIZE)-1:dqs*MEM_DQS_GROUP_SIZE] <= 'x;
+ mem_dm_captured[dqs] <= 'x;
+ end
+ end
+ always @(posedge mem_dqs_shifted[dqs]) begin
+ mem_ck_sampled_by_dqs[((dqs+1)*MEM_DQS_GROUP_SIZE)-1:dqs*MEM_DQS_GROUP_SIZE] <= {MEM_DQS_GROUP_SIZE{mem_ck_diff}};
+ end
+ end
+
+ endgenerate
+
+ assign mem_dq = wlevel_en ? mem_ck_sampled_by_dqs : (mem_dq_en ? mem_dq_int : 'z);
+ assign mem_dbi_n = rdbi_en ? (mem_dq_en ? dbi_n : 'z) : 'z;
+ assign mem_dqs = (mem_dqs_en) ? (mem_dqs_preamble) ? '0 : {PORT_MEM_DQS_WIDTH{mem_ck_diff}} : 'z;
+
+ assign mem_dqs_n = (mem_dqs_en) ? (mem_dqs_preamble) ? '1 : {PORT_MEM_DQS_WIDTH{~mem_ck_diff}} : 'z;
+
+ assign mem_alert_n = (parity_alert_n_pipeline[0] & crc_alert_n_pipeline[0]);
+
+// synthesis translate_on
+
+endmodule
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddr4_crc_tree.sv b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddr4_crc_tree.sv
new file mode 100644
index 0000000000..dd964b09b3
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddr4_crc_tree.sv
@@ -0,0 +1,125 @@
+// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, the Altera Quartus II License Agreement, the Altera
+// MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your
+// use is for the sole purpose of simulating designs for use
+// exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 14.1
+// ALTERA_TIMESTAMP:Thu Dec 4 07:39:38 PST 2014
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV-6.6"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+O8E9LZyZkEc8SP1rl9oeRQSt9WQCCjiKTHWvJJU2NzFe1PBc5ZW01B1brJCB0Ilj
+MQjCV3w0fgmOttBVdiulv7uMOVSF6RMnQT6EHuNw0xKoPS9RZcJgEiMuk4doBHZM
+Pcwqrj/GO9LV2x/bBywb3hWIXcbcsJ7o/7XK2lMFV6c=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 4160)
+EyBgOqzM5WcM3uVBffBecVSM4uH7duIZopisQUton980DrrAEELj0YQLqJw/OpKs
+dcAACLpelZvD9VFXc5QlF+rnamVmJMDSi+touJy2Qs2rxknJXbgPMwLdKOfuYunW
+fJ+ocWmusunF0J85Hs4ytyO90Tk/Bh3Jd1Nq+Z+EKZgUji9/bgDrKlJSFwiKZK1I
+Ygb6KTYF89RxRAqjJWr2oa8LPTL+t2WTwP/Paz3BNEcAFxxZ6NIZY0nvhRgdYv8O
+S73NZANbaQj2lpCRiJieyD/0qk+jEqrtbe6tFHGLgGsySF0QSOY7CjM4jdcyYlIa
+muNtsn0iJDs/sod/xNXrxWBVFf11Yvzb4sMoQXXx67/WAJ8H6f63CEzrRX3HaHKX
+kawmLPR7Ycrk0L1jzNpJECkUXW+nz7jWte38OKW3tf2qist0BMxcdpeaGNGSxiqJ
+6b0nfk+SpZW9KUsBcVIUOG9/C3A/qcndjNQK7o9biHLsNGTGCyn4EcOxAP+t2/we
+i4knXArwYd4jwn4QFO1IIN97ljriSdIgBYubZEEAHEOLtyeOv9Lk9b/HoOu7ORA0
+om9VqOr1Wd6GdxIbWYPVvZyI3c0StF4smvsc/lWS/+nnqAW0qKFOGIsH1oTzeTmg
+pf4Evq4bW4cb4/8IoORfcgS8ApQMYGpR7u3cYLCFLvtegl1V2tYfyvHe8Ie1cM0X
+gVU1vfz2XLYA5w86Yg8PZeVCCsJqgCxlJnB3rDUL9sOu/y9GDrU/r+ZhuVhx9Isc
+M5yjdUbVKYdOo00oZWUQwAEQqljQED2KpVlaLthBIWCGbylA62fqX+VDmw1UbsFh
+/MGciLTCli7g43z2Ycd82VkQyBDO+QcuEqcEVA/HFi5Fr3ZRzlTkdQP6nvfJVbt9
+uJqTiyVLWTjqufph6N8aQzIDOnupet3z0ofEFVXhh+5AA1n7wAt2ajTtIWKsL5e/
+B7SQYf6Xm4D+kkllmee11w2RRpfQie5LZmfTYIVXQZ+Tq1fWrBVk0dhNpOUQcSO5
+c65OpXSKI7iQU14UfjCLAVod0G/wY8EC6U6Nq6oFpo2Xpj3pTrLBg2IZYrroT2zW
+dWQ2MpwCkMd/TORrCqmstyqCh8750u5poEPv7Re15dyI9TO6hQl30lNlfWfWWbDX
+mFZwsp89Pu/EDP5HUAGXgDr2CB7z2Dw6eBIsJpcE0gJBJKr2cOSbtvZD0Vj9Dll/
+zivCxmipNLUZQZtjWHgLQcgpgMwb4n9pyzQ5o1joH3YBdsJ56sbFIsD7bkQH/l7H
+XUWPYEXjSozNevGsCjErDPA6jiSArugTtrn4Up4It61xczyuUt/Vs2YgXCOSpC2C
+86nZDlsCVDQU3LIL96mDm3sKIpgzn8LIk3TCKovDLodj3cF+OMxZvQt2emza+19O
+pnC7oMa9Yfa5YgL9/MibkUvsZRNp88iUIGWpWebk62fOBm0vw+D9p1Pcge6Rh9FB
++gsFmH7PEAlqrTwiehsNA2oD4ptqMRnrcyK8ZuWacD19DMm6b84beAawRLhxe3hL
+Ycw320Rb6e+yiRDiwV64RIMyaFpBzm3TqL3/dXeGBZtLUEkaEEWUsaKMpeAMgdHL
+5vkK51wG1pzgNiV0vyt8arHKd4Uqh+qvLR3EPLhRlI3VnjZm+TOW9PIbIVkOhNJ4
+3Y1Md9aH0UAv6UAAN3NwsLLfsob49RuYf14vkShYMEZJmiC7WnvFHuJ1qy5PfU6M
+XV4f77RlPO/CjI3FH8ruXk0wzPtEImF3Z+8jvw0mzVN3Y2UfzvxdQPKR1zbNPyXi
+qhij6qUeuwMm97p1JdVUjDnhheHEzInAwhzWzfqprcgpLHUepqxVixHXjdYv3+r+
+4NALbPYm5JzBvkx172Lsx2RHNi7w1XlsNr2nk86lsU+i5ipK2tVczLcITSqOcCIg
+KXDwWgxIlnCvHSJt078m1kHY6XL7N959MdxdLkbTizYoqa3eg2ehj8GWLMuak8Us
+hUaenasOxD2OXFkAV9cz/M1iAz3rdsHdhjp8nh0Ttlya4ye1rl0iRlBe8YYT4s8Y
+je2f+Hp/5f3EcckROiwixbKeWqLGInU/GNG43MG/gmblzHi+x0nu1lh2xEvA3WTq
+aZpHE52EiNBk9n/DQarTqkxiN8f96JsqQf5ljsTzEvAFQLOQw82Pr34QWkEbOpvO
+G+iSvqOAEPkt1d/GzQLf0mKfuYHKnXyXM1U1AgAT/Go9NDlBOxBBlgseQ3db5cU1
+OS9nPADDYe7i0jaJYoV6bVAkruh9eyRmPBGPQytUap1kCvg29Bk6IYRHaxznJNst
+wfZ+OOJMN85e8l59UAuiUTf39bEudjTPI0ZBXWZCI3Jbco1B50ywXB995uWLLGkZ
+alAHJqdNItFJSjZJy3sqo9TIGcaH5hY4OIJc421cHIMvO0DoKloUt27IDmy7apV7
+WC4QM2Sr9oBwT9X+dNPrjyfrRRAKaBS5keIRK/Fkzd3IEfNnjgTFksoGv+GQta5K
+Z+aKd3zrTjObbIxfl7nqBo8FwYuxx9K8QKPgcN/xrLi0Md9inDqIqOyBEwV0RYmd
+bHTcwNvPhqL3bZxiuWT0p3Plyss4XGPXHMlpPrALAEKclxOOImRqlrulWoxC29d5
+r6P7SYBYZM+42RKY+RSq7N2B8PgBfvmAe4kdqzo2AMlOF3R+xYTwdYuohJACIRTH
+GMz1RsZCteVHDx2dVs8zVOYafAQWfAJknmlfhTIPGuAIkHJeyO8Wbvi/+wz6gklz
++Sw387yizzaQiAoiGXvepBk49HUbcKI12vW/tRrju3hKBpRohtj42n/11750uj0s
+R3pguSl9cgIGJzhDk9tXDJpLuTXABICKM7YrxcU3LabNh+HvATCS9sAQprJkaoYO
+WNiEJ7jv5B54L7hT/W+6RlcyyTYNTTEnRmoVzd8xcbbTZnc5NCA1TpPWJvJuZU9x
+Y77fPa6yi/F/2Mi9k2JWU84pJ5bK3TlJibRRl1opTkeSA/XqbTch1b40eIuzo+Pj
+UdINbwOPD2tIc3Nmd5ecmn2WLdwdp/DsqxBYaMQvZysaNG8wyjYKbWrOIKB2Utt1
+2IS0nz0oQiYverFatfu0uvWKY1fNOeeO5Si2JkZwniuI6ZHQwwgQZ1A+pKqMEiwh
+Ms+y2YKTPVyeVsFyQZ4vNO9iA8n4nwbW+AarP4178/JQhvEm7FRVrTTQtsAnv+Ts
+kJsMA29x5+JE7m9twiJMnG4xW7rXg5u+cAERtAVcdLHa+EkD0MF63rzaCc1ucB9R
+MNsP574mfCzJJKNNJOfDjfvcxK05XKV0KlltHEAzfJ/ng15QLhvrkhmxEagRWOfk
+9/cLdPvbImx2gVG2LTbd5yJt8bSAAIBzXddCsJ+UZ3u0C0gnVLUPPcvaKkH35bYJ
+SpBu6i6ZEfgn9YqQeTgcJrOm4qMPtnn3Jfo5Zq5XJ2L/Y4BcxMLDBW06tw9jI5R6
+Q914pjYoROQU8mLB6MrMp83rI+xnwDFHPZO0qHhPML/KHPizP0uB41c2/y2iU6SV
+/L7n4XkSdxgRSB/3eBtB+XB2VbDaxpgr7FL/G1JrNpgOWFnXPBM16BjF8xJJqNnP
+itIdbIeQFB1VRAP06X4qCholBJTZBikg8UrnIK1muPuYpToRnw+qvKg8u73cIUDd
+k72qQ3U/NWtM42PsV/6UpGVXXbBJJWI19gD7ZnT+RBqT0xweeaLgdylXsZlRiFdw
+nWrqeM0lNQQZzOkA3h5geGJJZNTR8Ee0WcAv+9CrlFHE/Tkb/VkhSe1rB6xLWskh
+xSpAs0P52V+gWooIjL+nG40sKAypT9eb+gBKMRWRf2sD511V58LoFAiEHL5I/ZgW
+Hh3zM1iy3TKAnEpUBPRrsZ1YerrEiqCqPZQL7/gRJ7owXM205o0FC9bVmHnhIvQ2
+SNBoMicfsdDiZhzS4sdOyf5gaZTBwtC97rwolS3jVbW+6bSoxwOkgSoXJASqJkhw
+kIa7V+Kl4V8HHN1wLRY7W/CM0wQmRkqmvsBDXQwk9TsLoJHzmYBD03ur+gSkPeDw
+Wv390kXse3Ds8J6leWJdcHB+27TlrYMJLdpcvq8IkPNtzWsMLKWMuwIIkcDxlh+F
+FjqqwxpAl2mrYa1RHOU0lVC/9V5bMlElR9znXJ9NmB9mxERqKbVlGq/9+VpZPgso
+5g4ClRN181229wTKCzUeVObVsGjvGkHFc3ySUsCGmhmqNu4uKl0n++qG3/9p4AW3
+LB65/pjEIExJ9DoOZ4WByhsgH8RSYjQ611m7MNVJ6y8B8LiFei5mKt9Zw+j0qwiD
+GC7QQcRLy9kS26Ck6XTiBX1gv6TNrn76YgI8Vl85c4Yydu2MW9x7BJx4+vXMKbvM
+1JpHnf0gjqrGrKFJII8SVoOzWAOzvyDhIMKPzXLct4fvonW7xmhKmMKeJi9QLTMj
+fSvc9zs6kYcGim7P77jQ1LAENqkxKbZrc3iRNA0D2omCisgjOR7Kd8bnDYFGvOmp
+9Wg32bWS5lqu9D8+3a5ffdN94Beu/hwETyDPZqmOJ0FPnCSAmF0GKjZM5H+lXN7C
+1+5FhJUCt0OdmN/ebIDgvpsEXPiCi7rzhJZwtXHZBDYkxr0R/lv0V0Si2DmzXmxC
+wWeq6KGLqhOXVkbiPExSmgXtFwd717af0z+ZUHen5GUE71pkBUhLzM7sVJeceFDY
+pDornEVRKJ/KJnrWywnuQBXQVqk4TMdvRBA4KpwZCyitS+hZaMwbFPAMiLu3J2dK
+pBzMkLG/nRReAFwJLVjg1iFUHiM3BBgWKKCQLZ52686DeM3VaOdcxbckYRF2ASKT
+w7TtsbzdUxMm5l7YdKnYcQHecA5r6GXb0JKNhvgmaVcNR3PyG8X4HRNLGlG/Qmrv
+FO20BC4kNy8PIYv/8e3ctwjaxMZs8nWFg7mrU/nKR7O7qEN+6+fgCAQdD0gin8VK
+/+NjuBzO19iWewlgbS2iTjtkv9pexJk/nGWWrnXtdk18buxiwU9fKdc7+uOumiWm
+c0aTAHCyiwv5sSoDvUhBn38KufJOeJJClcgQFxT7k+/LTQyW3Ss7qWgAAypZjTr6
+9tED0lZj8SvKW9TY6lnezYIaN7Vn5FTXca3ohJCl4R/QV/VviL2F2eWDD09y1DIj
+i89b93uxeeAHKsiev1OcCvkmepweKstO8NQaMlceFFq1L5A5IzhbuBKdyBeKdI5G
+OGI0P+pZ10ULq5R5n+/ScNWG4DqwUeXt3EGQCRUyOB+706JEtkS43RU8SEgts6eg
+j0yQGDhlG12Ygn/5DuJPEO7zAZFklihRp5LUDmXi2W9DktVCUASYn5cwSci8Sqzu
+k9+XpNU4n9EjekZ1/5TB3xgGiX9jOtZq3/2fi2BLya8BOUBstapjw/Ga4wONcTs+
+noEJ06OTxn60NZYkWPbtVnuVRdAMSjPbo2tn408zLpkJRqYqfL6STtr2aWaZhCDE
+HNi3BklH7ahjR8kYihGCzUMTQ1GFSeAelt2APx4Sfao6jfdmRp839kAJC4V4+8n6
+3+tOpLpXRuFNSZlb7xXIqD5BSj5fYdZiRBHmRXkyjSQ=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddr4_model_rcd_chip.sv b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddr4_model_rcd_chip.sv
new file mode 100644
index 0000000000..7069f204a4
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddr4_model_rcd_chip.sv
@@ -0,0 +1,137 @@
+// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, the Altera Quartus II License Agreement, the Altera
+// MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your
+// use is for the sole purpose of simulating designs for use
+// exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 14.1
+// ALTERA_TIMESTAMP:Thu Dec 4 07:39:38 PST 2014
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV-6.6"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+dklMCsgXf2xX+ZTkxffPzOgEyp2VwtvWmq7W9FQJjpwC7S+b5pCwpc6sJi+ioElp
+5yG+ZGGw8qhyJEKk9bQEJcye514v3MldGyq7i1aQC5K1tNvFOcvzCqeih+0WaSRn
+PoM5Y6rNGlhcAVgiqGUtdOQ2UC2Ax2BorDBn6T4MnzE=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 4752)
+nICPwWWhC4d6IsL420G0rCo95Yg4er3T4X5tH1XOjZCSLFQgcyW4SCvzssd6BYSi
+B7cFN0SPotKZoVW1ZPkJFodr39cTo8yVhNIW2sCmu9nd+X88pbWA2yxIrPrZT57x
+sUep7mt9pbYgSIvSs5qjQf/LA+4Katvf+VuRHRgL+i22NCBijFL04hVBhpf3ESpb
+GWzzYOmrAyi08F1VTN0IaR83KvqCmUdobQQkayaWWXR3w0riYa2Q2cN5RwuweM5M
+UvyiTK5g4zqkbLvQ9YabAxWsJqH7jgnJlYcuPN5sMc0ztm73t4gQXCGEzCQWJ9Te
+aFjYhYiTbwyp/vHaHIY/+nLmsYDmQVyBMaD4QBa+7mRXk7AZhp49LWJI7xcudeVN
+0DOgLeYF8Eamu5jqv9UcmWKL5WQ1lJHVXKvshOIPg+UuOO0SK3vsfS6TBbc9J5Ck
+15YnoKjtvLb+ba7F9/GhXGDO/ExXPD33o1aPhn3GbYrWDwIlr5idiY3hkLgyFPgK
++OEeVWMRpzUyAAoNlAjF7lCWszG1F634T8EWquH34XlQUhn0keb3yhlDplkfFV1k
+VZIFKGwLN+z3Mvp2/uH4ugeBfj+apQQpUEvhMmbZsK6lNjuFulCrF0sz34wT46kU
+1Jutk7HhzMHe5psKjmVYZRz2AY++nbhcIhxgWA/lkLmGG92WY1Wgwmn+B8Ag8tbE
+ODgt9gTCJyOEn6SdjZMxo6+4aM7lIVIJz09W2YGuhdOPxMcamv4ZyDfKMrSdLFKS
+iHQZn8neuKoktlShp1qXsh62PB9V1rsH6VWrx/Bznc7y57pd8mO3MSijfmgaZnxn
+e+En9j3nFVLpUReq6f/lm1SfEUEqvcm+viFS/CbyULTZZKmVEVFN/5pOPYVKbS7Q
+ZbFJ4GcIiWdenhDR1OZADz4FwQqJszXJtvl2T06JOa1yFycDuTCVmF7Yww+90XsX
+ernjGfuTo1cOSFF4NFzAHJNMOasXzXNjMDXWeaAQKtpM4h80dddptAa0lvxLBImD
++gUNU9xa1FOktDl9LTkTmXfno+JjeP/+OqFASRoe85b+kOSJi8PE1SmwwSjxWbuS
+BUgIVhQt+VkQRFxowUVF/ASEV2QPWbZevpowWAfGQj/Q04Qh21tOsTHNauGKCUGr
+APH30KSr6xzXurzpD2FnTUZI3bZtamyJZ8jGhSJwT0tpZNF30qa5WLrV7Xzgp+dr
+18DpSheHMPPEomLiKZLXHuuKWqMnoVbtVbMFDR06hrObiW+vNbP6n8R5qmkV+Fqn
+fCRHyG8LVhB3c14pIr5G98ckERymven/J29hn4g02d7CwkUxeqHXNau0IYR1+qqJ
+6rbnbgIyeaZIxu6Jx3tA6qJVz2NSu1TVDmt2xKIq5dvwbv8T/AWQqM0dN5SrDJ1z
+EvenbcO8RaKLTYUOYrnGjgbCii2ranYeP2M+c/0N/OMj4rCXSOX9zosWwWj8NgiL
+jbeH7sLtPWG3iRhtWBg004iqEv9BWExpcOmmpF8GvqUlbwn+vw1YccY1uXHyOaw/
+FT39CtWO+AMZjaZbu6u1+DhvwzE9849fsW6rvGqnoNgQX+4Toi9nZYuhaUvr/Aqh
+wVZ2d3ycF2GE7pkjuUixGGpWSj7e2aIsS4jO73QtMZPIwoMIgEmNKqyHrQUbG1PC
+4+2Q4oTZKzIvAejtB8XjlVH0pffVcQhKiuTvF1hsJakhVWNxoHgD4XPq+ZQ8Y7/A
+J7KB/C/Z/9/34RM+4+1Qiq5qPYV2wfvEUrzg4FtxORtEppB6hAspa2jRQ2D8dtV4
+vUsgrEiN8jaiWiVGoBt0siJP05SQD+L4JcvlfYd4H54zzYAd4qv021sJu8r7BNl/
+yN6n+kpJvxTbCulePFzpuDaILX+xg4Ur7LsdXq6dieqZltecyV5d4QIwSK8ZJCqf
+NDTES6qPSVwRaJI4zGRVexjQru8nJJ1FPxAAyj59shyRxmxvWJNi6AT3uDdHTJOg
+xvK1GzYHkHcKw/nSQhPkFEL35aV8gZ7M/o9yUQlmpkl31jZa5uGlXIIWJeuprp5o
+AHvviEfCJqkDCGN3/nUO29zQKVbcm52sfcIf+n7tKgpyNCEyYfPtN9sA1dSvRRv0
+0MrRAteqcJ3qVPjjgb18gaJOLFpz+8A5SRtyAwfPLVHjrB/Wnu2q8R8aVENF5G8T
+hzuygdQnK4ibdoOO9C5rXo11NToFyYDJbRb+r3G0o+P6PicJ7rNyF4Bil/ari0u1
+uJ9y9mqCMZjTyvvwjFG64ZBQdGKo/l9v29+JWtfO8m8OfSluL2OM94qW68xfaYCY
+u70GYsHVdcn5IgNv1P7nG2jeOu2Emt6LLOCx1OSS8PfB6TrHL3ocfwbdKCWPk8yu
+PEpcEfHgN5331NQ6aCmHQn7UctU+b+6q9aQ9jr1F201iTX4E1BC0E5L2v32XZTDg
+uDqg6TAPbYGtypNm+Wh3W9sAPN++ai6YWnNXH+7kRr6IaiKCtuMo5fxEth7k+5gJ
+Tjbhjo03bnPpzSuSCMq47WIG1DVII4dJf20SEvBt7l7fGalrD9aikmvuwVnFyS5o
+P1GDQUVPFz/BYpZolCZbvSqkj2yXsW09bvwAvWSZRGhSqBTqaka9vg/t/6brMuOe
+ku+dDHCjaIKwKuDk8p0bk+Elrjz3XoK+Njvw965jDyJ1CA1JaPQ3PD668JOSI6VI
+9Aorz2kU/K/s/kj42o8YzxXDSGOqO9/SeDk6d0KrxN2KuncQ/TV1J7lWTUvs4MuU
+A/rMnD5xpATA3b3y1RQ8b8iQ2zq4buuIzqQysGXm2J6Z5teW4js62C+TIEkaVOQt
+MGf8Dk6W5tdDqUWzniQ4iniZGRC1jGNaEljKY/84xxjEbV/FSnTdYwLbsBKf0doB
+9E2ljNkK0BbFyz1t9DTiHpdRiNHZsi3fOq+vGWeZVZ+B6V+a8i/ixiBZ+MnbWnkO
+CKHGMu+kDbATiXIGXOeE0NWwtXlGpVaOmHYmkWSZIsA8Vn8aAMHEY8i88ohRSrfx
+HoR/dgVes1hFRPE+eJCY/lYSUYwgpvn8D3FKHCp4Fvkc6pcqMiXZGlQUdGlJX/nA
+krjLYd8OMrWyj5Oybk/VC24teZRytX/SsvPyacmdf03FupXj3+fDU03b+0AR3HBI
+eJytB9Ui2kbJsla1X1gdKDyRN5YNibC3jvEuNn7gPsCuqjJh+SxKeA7D3KjT38Yo
+NslVBwRCMqONFEguXkFdlnofMW/xsqESqS6YjLvt+3E/rWFptTKXOlfOxLrY8RjM
+Nlgv3EGJl85Wvq01whUCBemCfQtKdUPcdXm/iLmEWSz9+yZ8d4jKq/KdWqY1wo8x
+F/aGCnCCAm7VKVaLqZMJ5LXD9pkRqgYlAXwbYMFpKDUIktzl3GXohDFOFe5Ozobi
+mc6W6vNiB4bk/KG+ZhJrz+yah071M/nihvyfoc9TaIpwd1GC7a4TaSwBc8mcoY6K
+o/Wr8oCBkzkVVTsHwDJVbekbxYICXlWUikg/Eb3qouulzPEHC/QZ0ezd1yDFI6CD
+QcZiYdhTQ5/21tDo99t2pW8LzeQch4bQ624mKE7U4A2ibnaXujLz29nEStEg+ZEr
+qZ8/XbYt2ee6TjVmgstSBflmUmsXdtvhWix/blFTcuaoLds6ErxeH/YoQ1YCBZOa
+UEqkRNK369l8kQY6iyF+mzU3ED0lawU3/vhjytZEZciJILeznn1liTgy6X3d/LZ6
+i8N3FyOYg2tdLoFHPx6D4mmN2FGQoak09zWd+vdwYt8v63FWKhDvzWrzUZhjpec+
+HGo0tDXiQOEtPNVuEUvNYBmX3QylNKjyHKPAexbdFAuIZnvx7iHMatxn6BThO+Cl
+meAt/rIBKAJSkIBQCiZ/WROIJoz26/ucre+YBGl7XKGRFPvzL73l4qLLZPFOz35k
+gEIFe1H3mflRDN+UxaHGfr4WFdwHPA9jiWQWXRyOswEqipOG6Ek0D2OQkdXKMUgi
+28oG/cPHv5oe1Ql8VkLOEsc9kRfpx7JoKx5VUgvliDPizV5l+8auo0c8EZxqcmW2
+vKMqIBTXA5s5tR8e+7Wmnf5LPbLnF2qVq5D10AJbRGAu5fCjkVlqBG3CQVJ18UzV
+Mp/sJe8TjDF/ZQai24r8J/vQzxqEF9qE94S0QqtlK/u07h8dSpwCsMUjtpOzKt7I
+IM3ZjBp2Ru65eKA5DwWsney+FCnLFwpBDiYxnFxDvDp9RpQRSnwNDxz/MpQYsh+o
+07fc+FBygcjJ32tGUCFC9Pm9JbpkStBckO8xfeX9HMKdj4DsYvM5xK4mtlFrxML1
+8xCRYJhKZKx2a+6yoGx2hwoFa26v4wm7H+vpVc8eb+f3amZlmLUaTovRhij9pLpQ
+ul8k/6ZZaYIH8DEsiBdczNLijXHUBUZNQRlbbNQYDEvOpx8uNkxNSddqD1k7648E
+Rt/njz3Cfu4l3M1uqewUjka4r+Eby+3uw5yUk16j0ey+ZtJ5gWtAuS5xn2tMP/bl
+KRidEvv/ZmzyOPbh9AOECBfKvIkV6Nfx84HQT7rx8yj8BAWqzzxTp4YpOIPyRqoS
+WyG8g7rPK02IlW26LbcHAIcrZHM0oTq7qwEIJvejaWz2xbwrlSQoA26R515ERT82
+Zs6mhKyaEhbc1c2x7TDFX3LYA2RTjao1cUSNm+eqgNMwk8PdtD03rGjtWI/aWszO
+YimHeRxlIbZhw3Ha4lzUUjgdZexKg1/9SLKNrAmSDmcZq88PdL6RM6WylhWTWRql
+EzfU35h9DYh9cQGjXqlHu3tlXEBV/qwXEp/Rr5EeulhPoKEWQ5LxXwHYtPaxCNuw
+XoTK9Z1iB8dEQn8O2f3n0b88Ae+DsmqGeCBLGdh8ntPubIvobai01e+t+t6ukIIe
+ayPbGh8Tc0pf0afb/J+RQkHQdMncLD7LCxE4yHJfZKZLbcCqiF19rkX+gVcolNaW
+n7W2Swi6IbCQhKDOA0xshHM1PzGrmf9tMN8PVl896g2mksT3jEdeFmBE+/AS4Y8d
+3EokapH9/yqg79kixIMDCQJT9/5F3dCoKFAXD1qHp+yq17dUyPa9RyuVhqMP5bTc
+arzc/b80PHiAIhDnMtN+TzNFZqsknbhjAODskaGvLOk34wwxNjHVFB7yjlYuCgVV
+BgjAqozyB7F0/el797+FTO0ab5+UZSIxML9OzpuTtkpVKkpO656l2SEjNYfruq6K
+Nbr2lrD4HtZDfatPEA92ymzLiW0fIUz3yytyBw/Dy/G57k43uYFNDKGbyl+XwfuU
+IlehT4JmQQaVYNz6oyoXz61Slk4vAOZbUfwipM6hXIur5F2Rz+N3H2FX6bQbAPvy
+B4nUHQ8kXNxQpjhM67NAKJqGnVUDmGJNWQW2S8AqIEiDZBaQ3feNt7p0u8EvohV3
+VTU9MMydwivKfOSAxWFvfIwXhDhDQ9kjvl0YCx7U0J1aOvnmr6MYK63sAw7FuQIM
+mP+SVWAjbx5gxwolAe7FhY5REKZIF2rtAyH9QfMNz0vIky5Ou+C70RpUxggUxoUy
+VVhK6u4pd48vvFPq7ymr2YC/VwqzI7NTJGDESdKV3na/wPqpgsriiKwNfyofQtlN
+RxU6mt/QgJtIMGn75WgnhBVZHwQSJmWDfTWk6fnBweNgFOVacbHmjvaMYJ/l/PGN
+vkiyX82GdzAGWBYsjCaOR5gU7yteorCC0nqaWIyrhePatKDL0LyYfj6OWrnmayfd
+8pF1E/j3BH8IDGmK5s/Wf4lU7duOK4bvNUza5GWoKCOZklVlpQ9OT8R8pEhaOFVA
+yb5fHbwWsxw2eUlyyGPdEPwaVS3WA/shhmK9B21+cr8QLpIaKF5LsikoIpsBG2Vj
+IJqCkp76CF2y/CnSSKyB5rmoPvTaGNxtH7CCb4mjhKr5pk4en5k1X9UQok0kR54R
+U7w4auwB7s+H7Gx1e1BZGkyUipmLUBYilryHPzDG1BqmMMIfsMu27V7qQ0FeOc35
+LrnHURndTS+/9k4g5KA2T/7nsjxN+TwghJAwN4lckCMdN1yiHzbBYvzb80GjhaU5
+Er0prC1ltjRrBOixjsxNBkrLhLLT1X/vPUJ2GWczpRzUMacX1OiPD8hfB7z7OwWa
+NvnQnQQAob2Wusz+nfeS47Ujs81vRrHLDwPvlw7TFyFfS7HUnR9Ec1TK1THf0CMT
+6FayDudgLuZfogDhfZ0wwJ9YyAnJ7gBBhnIw7lHyOsLNUYOUz/DCZ3xCF1dwGli9
+5HEyVd9zSYqb38tlqvYgy5MRIa/k7RfMIQO7Iwhw/vnM5YFKGhcyZhPnE3KXunUG
+ub4RmXkn0BSACN8Bam1G7VLBXAo/UYRuN0y167qbf5c5VQXFv89bQ3lkH7dIkCZ0
+`pragma protect end_protected
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model.sv b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model.sv
new file mode 100644
index 0000000000..3a46869ce1
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model.sv
@@ -0,0 +1,384 @@
+// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, the Altera Quartus II License Agreement, the Altera
+// MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your
+// use is for the sole purpose of simulating designs for use
+// exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 14.1
+// ALTERA_TIMESTAMP:Thu Dec 4 07:39:38 PST 2014
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV-6.6"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+TBf2vIRDNR14rq3gCIcYguxD9UGpf6Cm7GEB84JewV1I2isaTiPKOh2xOVqSFCR6
+rLLgDLEXa2eoUDcp/IEMD47Miw17nlFXfbwMBec4aXKN+3N2jHKAn2c7jjuC2v+8
+Ou/F+W/n3VaHSDgWnqgWi10+XC0L/GbfdeSq9jmQ9MU=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 16592)
+YVSnYoXlPTJJ3zt8JzJVjOQ9i/EciQ6jJ0tFGP+LmWaeKePsOqZkYZy8IrTwkS+C
+J8wZGE+XWAaxOssS38VXHBIqaADjxl+zKMpXM4Xbdg8UbxmLtbJ03kORNWsu/N1P
+VcSQivyOjczRM0PosJn6bsC9NLFy7Ye591rx/kG2oOknH9z8On7rA97XYoqZ8y7/
+TXjMdBat5mL1uC1tvdCoj9q8wc3YbAxbETQyqwJu+yXASlrt5HJcWDadVln85daR
+n6HFtygOl/mBsIHJTRmdx86td1N4b2zzTQVEfytDaFsoZEzhNB63plQwp5q1qS3J
+cJmNxOPs0llbAMzeCuo2a/WeaP+6+KOEoE5fnlaro3aI5JhlEwsFVW0JRtsav4xK
+Q9AuLJ2wdVnzj5h+15J8FTfEWHxO7ulbpnP0w2Of93zMsZDcSm/FsBiktg9YJVKj
+s/3vNKqHJ64+tpE9W7B1I41XU01SjsnRIXSZCwUkMW4KjHdzbaqgv0uaLzYfrViL
+aJQN/Nei9g8CMR9b+29620as2cTBW8+Fj4hG3dnZyUYYOudbJnQmJkGd1NaC7XCN
+R2ykKsP5dAV+UkntzdDSvGMd/dw5XCuL1QfImhUjc1/vf5mBW0GpDa0bgD3cx+ay
+86tE7AFIU9thfVpsr7oLISvoJ5TPEF+DlG66Yw94JTzf27pWI0Gkk8Ra8PtxH/a4
+YjvzAWwE8tvp18XRGv59Ldm2cTjeHVvl5zF1b2tkxCMh1A9CG7Dyp9edt9ArO1c7
+HoODnhB3ECCD3K2+P+DeZlRyo7hqxYVmc852nO79hGAJ2nncSpUurxGPAWkzxbx3
+VgDqja4aC41zpKfCaVMrcseMqpaL1UzP0+HBREyuP75Xvgo5agqhrgtpJov6TXkO
+72Rkr96PyRkCC0ZEpMX9GM5fyJ4u3TtJIwb07EWMojPENn47y8Ug9Z/XgwVn2Fvf
+JEjEkneZHRTh0B0yeXppCTNz3chzF5rHPxcSnkAF0GhgSeRjA8S/tOCfhGln85aO
++ouc29ptOYIwD+NvkX1Is+Hj/D0LlqkuOoe25ZQfv5WLMcbNxOotHnq467HhDD3J
+YCd3afTzTABbmWj8cqlMP54bUORHm/F7cAGkIVC4GSSLJCT+eU52ayY4GZCPFo80
+IPsfhYsIWQIG1JEvcSUUIMQJawSoL/uG76do+uvWn6M686yHt6FUA+X89y2qNouW
+Wq+KOc0itoxC+7FcpXdIOy145MHrmzmH4w0UTi9xDRG6AdF3Ce10+FQtaGmKr0AN
+mTj9SsPdiRFpNQuYZ+YQ5+FhX6AOBqwXWwBtGNsGUOpDapf4xlogwV/ayLEZzyZm
++5gk7WU9oNkYqVuVk963T9UD+t8Qjj22vlCxi1MgRgHIj0LMyiT7+7kQAME0MZxL
+257qtlARcvy4e6t6q/RP5Kfs2ps93aMm6F1buGLjLRMJcVe0K36dlNf0YPgosKgI
+xCX4qeo3vBiVqoFMy/+Vy9c0ynDHB5e5n0rNDjHhylGwaDFUH622q+HqEOkN1cWs
+9a7OEXOywdrYj7f3YjPibRoM4ePCUZslTv2Wqk8QODUgdWB0V1FFi9PUl4jBtuAD
+UBkiF6QqzXNtgM67fsRQphQVkkZ9W1MXo+4mee4Lu8JSr19Y7E0nKCiffOrb5CvM
+E02b/3Oo0fvpF2hiChCIxH3Zv5KVb135o8kP384+jPYDVCrBD45Q9ZU91x0b+9gy
+g/ubEY8AecdWSkRpPUqwH8SHEN4dG4W4a1KAXQKibUbf4R+MSwmt3tAyw8bCah7w
+Nm6ZRuhal0SUIDrz8zqt0ogTPooxrtAsKdeLxKWqT5ditAh7vF9AeLQNXBKFswAB
+fzsAla+ml8hWrpqLMvya25ss9To8Ro8McaXMPS9CjPFpedrJi6X7xzdXM9hQb05X
+IUbmFs7p0agZBvImzLvNya2H0FIvg/7N3AO5Rxdyhcn30qu79TxGbK2WPugC7hMb
+C5e/luxmRwO8t+qoPFvUWcWeks5QBvXvNFZjz7XHY5PBMYIaySzoXRSwC29xcklT
+mxEcjSdWuqEnbkiX4foX4PuLdtSHNiVFDskpSnRydnVAtvM/Q4tHua3EBXL8jgI1
+RzxH8QIudyzbMSDxcBMGFBHJw3fBSdP2IqwYn/aeRN3xIRj7T0va5MoI24SznAxi
+x/Zqd0aMSt71+8nq1Nrw+SOXT8OaDm0aw0M0mj7rcR+WlaaEdDyjSVImTQpasU1E
+TxpTxwP0l5SnHdUo6rPNmztrmvrXKnlWN3g+r03xAixwH2A61hNxqlbqIAfpKYsL
+cI/gzK/BFmfl+FkICYE2xnHnXcLSc68bL+yPg2jBdANWQl9/1Q3Pga1NilGo2ZYh
+mKyxzb4T3j24HIOxUFe+qZsZzfGIrFFIRGLl3/kx/oiGgQ3Nf+b14/kz3LOxt1Dn
+bkdheBjR73qabUz9mZs9tt6Q7EPiQ1WOfbT4h5dLjWd4SJxDtpEvImySag+WK5k5
+9RlpfM4TXi1RBR3D6kpPYiuEtcSi9ppsYZ+HWsUbuOtbFDeNo9p3C43d31Z91CFL
+019NUNzwIDInw8huaE4K2wb8+sVqhphvGBn46xFvbpmL5niXfFce98eZJDD4aVGQ
+4e7HffIn/ID2oA/uw8pKgCCmNGLjO8OtItUSr5aK1yAPvmsxKseB1zAX02DQonR2
+etDg/aQV/8vIYFbrId3eMvkH+FBEWPpKfoW6OUF1ofHrxsC6rW+pAKwlD6tjksqE
+AhV5QMMMYlWDSwwNrOQG43pKHOqTJ6usTD0GfjB09WFF8lED34zxltvd1CrMdSZu
+VUz3mre1tdVa4txVFsz0PAUOU8UmzvhF4jGzi6+qfoqHWFnlFL/ysSfKwqZE5lB3
+n2kAKQWICaylHEMJKKoqf8tLVQMS2VGBpcbaqb0s0gS/CbpBOM0aJ/bsyoTT4Zwt
+lwm6+xjMQlucK1t9TTqJRdyIaPg2urcYZIv23eVHfcSaCndPfRj7sB6BiT13JVP0
+IGmQ/oqnaqE5Zd3hgPFydCsLRfhgUKRUelCFpEdRYt51VWpLyN2q+A94x2Y692OW
+JhvwlKFhXi+Swc+oq1XrEIW6dCXMpa3nDUAnDfNRe0bSU5F6/EUX5ozGh0dYdWRE
+jxIJMxIRkwegQ6P6UjsYQpkTY9uINXKOGtJmF2BWI0Pe1JgZhJVOxb9fUmmMczZM
+PCqq3yNL3+gkysRkqnwYCQVfTiloXwAiTk5r8jKuYChsvieYT4rdT9otmVGI7qqX
+vdnJtgWmTIgAhYALxI8zIFBq6Sef2pxCTrs8Ts2BgNaQ8jGdd2/b478C2uGwbFJo
+/Li4Bp2K8J8xd2XlzUr8ccH+XASbYWsBWi5Ap603465v36PR1H/xjbqP/ufz0Mze
+B3IgPUy1SVwUhNfcmcgPSFI481nBk1mq02qHZ9EtvrPwkF9gio0NEKPBD3VCTO1l
+5/Do9AAZhfQlINPMUOtg2BnkoaB64mYqXLGCOlhw4X4DwWQ4vQdjFSQpJYdv5XSi
+BtbY5F8Tz2GwDzPW6Amb0pOAc1qS8epDEHWWntdVNwmdsR0U/+uAKBHsjc+Y6Zn7
+jsTuiEcn3O7EgQ3xAf6nwKFoEIEro3MSKdaAL3Ezp8sKhp7P5+5o3ppI9lj0+up5
+rnw1p56Ty1C9yhzNPHNnKDWy2JZ1gtQPRMhzB9mEQy1SH38AKVqraxsXRwI2x+Jg
+tpNyf61ENZmaEvW1X2MMqq+owMR3cTI7L9A57RGZnefod7GSQp2KdIHpIxS/8BXh
+kxWZoqhQNXwtpvH4QJ1hJKdCQxmQD+rIp8ELtWXqcnAo2UU9RXuLtvPNa6KnrSgV
+amezNYoh2N2DuOHpjRUyDopDUXv5ywMZaVWgfN0dv266VlnZLy6veCIms8t2IYCM
+DU/0vdaJWgU/ktzTE+7RmseNrJOFkzxtt8d7wOwyg0DDHxBFS3pjNIcWynN8E0pH
+J+kYzJeRv5LjQkOtsUEetDTKYUTZGPCbVNWqwb1fj7EVTkEiyy2qBqgRwZGxxHHe
+DDcM+Qndw7aZ8d1BibfLsKoArHhFe2DrJBCGDFYLPbhY+IR9xvNEl7E0yvhtDZxe
+vaZyNcOVBP1u5/Cpbkut/62IJfgE4rKZARtxJCUDFdSI7f20pc7cxcCeeTafp/tg
+UnUHrDg0KEmj309JbStEfkjRyh0wtj4J20zMpnIcCGwZ6wjkd/7ys266QnJLUZgx
+q3Gh+dHTdsBEtUQVJ8rBYhocOnz+VMqQwx2pkDrWqgYEyaj70NkcF/xFhjps1/LI
+fNrbJCzz+jR8Nd7r3A5lDH9rWhk5TGfK08tea+i9cIr3kVxFdD9/zNI6jvlLYDfF
+1zINb7xp6Vpw2KhtryY2IOa5LrXq0xylgG0laW0Z4yao6hUqdf4EYW0oRUfW6q4U
+X0MUQaGVY5Ww9uQj9YFzNABFuhjSlpmyanK3BWhEmsqmYX5Xf+MPFcHO21SicSft
+Wvn5V/9eE9UzzkJqS0yiCVIrR6Y8muRHvyRuJ1MhdmUFxN+wnTJ4Cnh4n8kTPyYP
+1a2sVvcgb8EiG5QLqwqpblnQ4nUmRlpaRG2C6WB1AmozHy1qw0OIvX9SlizRwn9O
+7P+6fE5tMMxiFFKG1e5koaOfIHEwoIN/xZctWL5ZxczC4Ot1qt5cLnrfYS7o80qh
+JvLp7fMv3uUPHIPSaJ18oGgeMB0OYhRBHVoaHh14JJQ3B0tdDZPgU7ABQUXJu8X5
+MJNU3dditoktRVPyVPCDRFVIgaNAWU7kwFdL4/WJz8k1iOPgbf8XjKiUT7pJD1Dz
+A+2sxXyo0f4Ggwe6RRV2wUCiyHdLMpmhKXBIzlbsW71NH6JwdZcWmnB4fdZFqE4b
+l4NE3XPPuUq/lUu/r8XW8wqTUfsf/3V1T5ipA4egPGS5r/UVCYr34fnuqCFNHQ7E
+fBGZtXf8GDppL0C4MrBRhwNwDZpr0Szu+SIuwWuQeRyPyqiAIA4TOlOXbGgdsuL3
+H57GUIvFb/2QvC6vuILndMXOn4d0n7bqRcQRxCfqdQacReYW4AcJLM12OIqzelzW
+CeqVBvJWKjfaVeHQVtuestk4VI0lOfozvTPbk9LHUezT6f+kMMAWnem7Pxhr5z8J
+7cfqNeufML5MzQfOJN/F226Mqv3N999SnqseiOoz7KufK10VG0O9oa4JJcR6b8Yo
+BfyqCKx4M4Kqmr/cfp+p39+GQVxe6/cxQ4mqgy4+c5moTnE8TG+F3y6gp7+9vX8i
+VEPm/4T9/wYhu6vp1TqGuZUBd2jIBtcI1nFQUbXXHuMu296wehUCaWtxbrgGHVtT
+UYjKyCwLfdT47c9pawW7Q1IKBjSQhSb354/yT4nPpdn05mJ47K0bPSmEZtTTT1p9
+xeDSJ4G1mzGgpNvUqmf8z4RelENiY5goaxCxvmpInVflCUSmJcUX+/1IKNUIjaS1
+B6nJQhcZqVHZki9fxGokc19kE0LbBCusNL00LbMq+1xb+pT0afiaGAktddKjtZqi
+6YmDk/k+MwrziC9zQIpUzCOAtM54Lt7DIafNcYWx3UtRnnImjcGM7TyHCJYP/xyC
+8ofU2zbQeVq0crgTi0VGSLu5oct9bbpU9+F++GOwGw2RZEIIOH6GRzmGHnEJhtcm
+DE9jhKAwt1btzUXp8+Hk/208RDjP/7PW72SKtlF39vKy957LcUw9GLkZDK/3hypG
+OkAXf7Dx5c3rXdvDJZHWCa3QhDc5MPmR4QXfu7NGf4kdMpfDGFQW1H52GHUhLnXG
+UWpfpBQKcR/M51/4DaTikjuQu74TMMgar2Fsu53+CtLdbpsQwxf5U32AypDoIdfT
+KFsf0d3B4ZFm+qtr8S/hJc0huFuCyNnYTA1HNst5PbT6YyqBbi5wAa7mNn8OFJoY
+Tg7Pg//P2NcYcN32DoJJWREi0rSraUm3tda4f8gBAjHijLD8TqyUPumptFWMkp32
+OjyGkz1oCSy0Rzd9oiOMEu6RXBsoAoS8HVA77mEp2Q0EPScc4Qop3VNBLBY1FRLG
+0Wcqw7lIZWkDcf57RrFvljR43IQgsq2HDpk+UmZFhTVXoQA+/F/BjThNt1U4Hcpv
+t+XNY//PgzJNdj4hye7bvqwSC0CjIsO98NE030mMCyv36hLfsKosVlK51GaIU2Yo
+oByfZvsW7ArawHAdFSxUOTVkxmv0WSOKw4AvE/R3m+f2Kmf4Tx71NMbVb7GULyoJ
+IxLVfjz6oW+GBLHPEssnIusQ/K2hycVUgIo7foxy2Jf2RuxcDigPq0cS6RvzQcLA
+AILDEeORvUIu58qghKWhzxSzc9bJVj942AenaJd2lIi/MyCMkfUAuKr0hyPzgaL8
+OkKCQYKdyt2VlBth3HUdIixDGoRTfJWAIlTgv8EmNMVuwspdm4miKON7NGm+j1hj
+9GyrraWQd2WaMV1erelR+RrPodyL8xLAWpW380rRroi+7JHKvFHdLz2hQ8SG3RjB
+piK6u2pBxvSeUInm0fhGhi4y1WdRD2eClRH0p0cnqCM6S65s63V0BKBM0Xjrw1zb
+468D8nr+45SgiMrPzlYj7tPySSg9bH2DrImU3gZOfUANrv3/Qo/dnt5wFKEghHjB
+K67TnIeN8I0cpwJ7BSd1reA3kZe3V4PJOqmh6NV8OWKzxFSQ5iJSicGY0lkeAwxQ
+r/l4vKlXtfQPNPLCFDkkxyNwplT7r9BNWhlrb5idd0L11fV2ByoVoW8BJhpo8zTe
+/fViZhURaNBqG5jdLHOanj0W8/quN9IpLbF2enFEduErsP25lLPFO0942Qnmhq8c
+b8sWw3v/otJWM+m7qPylCYQDezfvVG0tTIvL6VbYgUpIUnHO4HOXCTktWhVt4cAN
+AF4C0zkpvebGyUYDsgJ20hfaP1ERUqt5TijwpH5FYa6MNF3ZWoOKpQKz5OCYgwNw
+OUYBMd5ePZLgZYg1XaOKrm0dXW/4OAgBHj9fiHA/CKZAsBSdq3dAe+hikjMFUmRe
+dn6l57LSh1qylc1nhbQu/OHFfkhCTYAqlwWdGcO1w4XTOCjprUvEWUpLyfYdY2+d
+ZFStiFUPIHB0VkIJ6c35q3B4Ftbt+9JRvoSzFqMVei1Q9PqkXRkOPbJepGfWqpZ7
+wmCh9Uo3WXvgtXREKKUahssApjDOWNUPyH7fp1XWN1trZevCR+WNrc5GehfYWG5A
+Wjva4mXZ2xF8hkxcDSeOWVttKb3gASlvHiK4PLfZ8KcA7yS2WB7fIt2oXIwtMdRg
+9i/lUEBReXDJhS6V151BvGAauV0p+gFTN/ICXfzO/5nz4g6LlN8uB55zI6s/GHmg
+ZX2cg9CgNVlNnCA/kNURbuYmFw1HiDD6ZdqMRspjFzDpKjKu34x8ul0ZwfQ9SfDM
+M96SmJ6HNBp3p2g+NGqpud1ilbsoNqJ/hs08t2BfL8+d1CENn4E/is4TTyuP2q7p
+8f7D0waOVPe5YQyHDVDPxKrba9EtgXtfNhCeUbFRWFcdcAvZKGRXYc94Ey9Xczro
+nJ01qgUbWHDO8dUVfY8JMoL64kshQp11fORJJd8iHx3Hf728l1OQleIWbPxyDm7N
+xxKVM7zelFt0cC7oF765y3pU30UfGohiMzPkCGi98OUtpedG00SZ11DO21Zr302d
+QldIqXYhMl+kuCjZoclzmMDwD8Y10jFAV/aMd5JpV+X8HrDPVJexAoi0t+byJenS
+k14Tj65Xwq+j17nZsYgO2pnpIKStFS34cYoDFVOUHR5gzPawe+blqeBg6U14WMC8
+7yQ0DeH0Ifq8O8qFXdSO2ZcB15OgVcUR5AgsHK/L1I4h3BVq34jYNXMks3+Rluqz
+wcRh2FZseEyUFUCgr9qBpB0bKcxkR5XZualqIeTojNFF7s0YDMWclQfQ7NKkLPqz
+w5Eez30fJMw4SjgGwSwpFx/fufP8R19i+FjHKEE0pi6GxvOjv4ZLCvmVRZVEjwJN
+574jFe8ymrvSQNQvAREcvJt40BpjFAyyU6HxbfBJXOEDD4H+Sd86jlIAoILCCDir
+VCvpZw8tfKb+4A6AVhL4eCFhwctKQeLRglLxeH2BzBCHjtgR6qV0Gc8Anu7O8lTl
+4VMd8OlYnwfJicuTEYROZy3IMjFWiEi9Yk7m9xfsIvoBrJr0NdKeBobxAj9S9R2r
+Xxuk2ODeiE2GCl3iWSOkM9sYlg2hwDPRxOcH9V22NTcAxbSgAdXAjy1pHBkuoX5m
+eccXOZP2EvgW+5dvWMGZ1DBfxCNQm0XvLXdHaLyfKAw1x2P4IBBdPuznDsscCaHP
+qzO3YtBduw4rynLtCrld0w3RUOunH2Ffv9FIRCoXnck60U0ViY2ibXtGd2OzeosB
+gJGo5FYAzSCVAVvIHR3CC9jspLy30mwF450tm09EfjBxSG4QPkukqXcELDpnOSEI
+x4DVVw5E+HzgkDl4Yh1EgAfD6E/JezSg4NMS5pthssanbUq3T0E0AJE8fh+aXxGw
+5QWjBPVhhcSnOQdzT/h+HnBQuYaWMY3Xx/s5yxm7jFwa+/8EfXzrv2qYO9SsvPUr
+Em2JLhcsfpp66IxU2J9P3VRE9CDjQdAV9ij7/IRfuapq13UbwWKuHUu6I+Ezrb1M
+pVfjzerfyLmevOXY+Gmz0LdJRFCKbPC2yEpcnyfUAqmdcKZ98RvkWt5exaZSN9Vy
++HzhD5KRBzifggh766AXnWf1Rny7kp42P4kgbNzxoJVLKZSNDU38xkD1iCWzHqH7
+aeBzNwK3uWXIDwz+6eG1aSVkIwPoQEknCN4wVEdBxCRcdiRSk6DgIvbbBKxgega/
+4LLgRiCgF2kyvv6J3j3ZSNmOX7PDc+hmxk0RqKObBgBCn0tBcmg30M3v18Oqd5me
+dQWq4ugD+svac4RE1cSKGno+w6dIqRwwscTnfAynCksQ7EiNeRaG0/j7YF5SVU1o
+tbJzL/cgwqClGSbyhxbibuQJuG0N9G9atZb7MzxENHqpzqJDORPBWjoXbPAbLdwY
+jHiKKVtiF+JRsGP5wF2dgFFdYW7rkVm1YcyZLo7ciB6DtS4LNPTphS8J/WRpajPo
+bbgU4F5g2/zQYdOYIVYH8m+kDrH3jNcTVlaHrIE8dEIhM/dOfOtmW7EQzFdR1/pk
+PlF9MwTk0GzDR03Uf1yLhezmS/uLlzgWsFOwJ5kp+WZidhfFZplH2NindlBOfGwv
+qOSCOcdPh8Vzao9QpW7SThxHQdbRKXURm4qFfT0RhYrGXhOtVcNr27Oxrnn1IRrl
+dYK6VMPBQoq4JVNZTkViO0C4QBvhdjc5ttOS4bcELBv/rGY3L44JjZP5PMDVvll2
+0nvdDEVwoIFKVBq5mLY/9CxvPDy5mX7vPfzy9+H+yeN5JEW+BtkeGfXfpXxVCzYE
+wSEHIp5mJi1tCjaPpdPUKuLdmxapZt7NDrwU11ahwQzyL4MTHdbfOxAJBu8hgUuN
+yZ/eIxDiHqcnudhf3Rj2JwfEhAAIjtqnxf2kDAK1zh+V0+jQdtYMOEEBuBXNIBR2
+9UZHWCxmwakHPREN7CTZTX6GJv3FB8+MLW4jqWv8kWIC5jssiWsSqu9j56O5jOha
+46IE3wTIRM+/fWpmD+o+nt1wseC+r2gyPbDq9fqWt/n3GrFwqxXw3cKhOI9d24iw
+pS+5I3EwxBsp+jvKQU4N8lXGZn1gf+rjGQ5Wj9SHihDJSzmNwNDlpgfWoM/Yk6R/
+/KpqIXqfgMQTELPxdVoTfO5VU3Xx433Xvdkepe1WQ72RL4pYc+yh7XLRooWrkvcb
+2AOX2vNXo2eaINO6J1sKqlf2tf9ve97f6LSSPy/nSd1AdEfd2wHC4gSxKKpP+eZr
+6bvL3PWaPvag1OZcMIU74snvr1vdbg29xbaGwiKILLBjpDO8fcCxr0HeNdEsVdAI
+WTzwF6MFaQJ5RQXsOuSoy38plfK+KjzyTt1zIvBiLQevqcD5nACLxbjGt7zm22AY
+I+gEGm8kSt74JueMr/B+czrz13RpXH1bTXSDuUD7+C2LN6xn9HVm/HuRWEJEL+Sv
+NDSdMh9tasAjaw7LuIF1Og/0TQB56vWeman8mTBsQyKZjGP6F5tJnf58zNxVmz7L
+MrY12Frqa33CnRpZFQnuoOjTMEi2PBOhXEhYrzOg44StcpLN8sy3Qhk0DtLNE5SM
+5WVAvL94q+XpdXJKUXUGs60NVFS4XcOFHQyhheJDnMs0mOzR74vOufLZh5U812Fo
+QfiJ3YzsKp7iuaElyrFyEeRKwQAqdHQt6aEkSCTsbRFiC4ifOZtCE16ZjiFxj7o+
+EZDnZnU2Z4GBRfouNe2iLSk5TIWXt64qhPfIKdIe53g/xch21CPfe6L1D7IVl4lM
+JerqroqgZIt4/zdlskgjAEHC1K+1Q0URdZjjaAftUbWSS1NXMiVL1V3s8a8u7f1u
+phq1rgjZl9YiSmAyCxAgB4Fvx6oKmT6Yq2lqEYpBb8qz1Y5DwTfNJ15t3wybTsGT
+TN55m0KLnptmjKBbbFyE4RYaJhqdMXomsMcCTNK0rhm3a0TpwYJzRG066xEudR7/
+v51EAGT2xOnNRWDo5AQog1Sx3CEZ4eyFUAnA5q84ivZPHr1zoJmpSUOw1+mMJ+fm
+A040NinMbMzgPWfRVcQtfe7U6dkro/p8uDVfa7Wc+9MXpbTI4Ba2AAEkuuX2hdmK
+yyshfEXdNabnVNEm9TwAJc+jFRg8zieOvZx3iUz+F95vNgLG/iiJ+NohfULTeZiN
+Eemy+V5Kn5Q33EZaV6i5Pkvu0svdO52OvoTVyovYKPCk/x2XGx4PXNNB9ynbmG4S
+idcP736iRuFHFLq+fJ2F8UIW+jxex8NTvau14Gjih5ICdfvJ6/HH8wJoDS1UjBok
+gGl+7mGHeFLKTcGJ/0Z2RMBGwbkI7PUytJSYdVWVTMBxaNWa8t1tYpuY5Uy8ssuC
+1Rx65fM0XQse5Xo9sUWS1V56ENa1r6ba7+Pj177mG8DdQT3ojTnoqeCI2vMyvC1Z
+QrwPX053uSMysqqA+1ENUEH1UEYIEyOM1heajAR9AC00pWddBMl8kQ/B5zGMH3py
+W6Z2vGkGRXY6OtLP2IlES2esiPUEYE7/RYESyROF3iGU0+ouNVR7N21jSubKsJo1
+6FVtVlZidBTeCFHMZsB9aWqLxgWLvTXtJFx+uIVAh4W5VoBcncaSj3yVLd0xcDTq
+Z+StlR25L2891+4EWUTxVCb9MA7QxtkITq88CIquMq9zKNB1IkXjYWlVm7DiSeu9
+QCzH7dLcrTZorR7cqgKEhIV2H0mcKiWoMccv9W06IID2/O7iJybXeZ+M2gHp/Yfi
+0WrMNHd0wHqU2IPZuepC8MzQeMd66Sf6hkJ0IN5S/3kH8tGHOZ70kP+442pOp1ze
+eCuy6IFbbo95YvOZ+Vjj8k2n4a1QD/W48qMZzBSmsywEbzGBaNANcjwb1OWhiuzx
+GUcw4DnJ2m/0ps1EzqCrD9rUWjNZG48C7s0tbUT95gUT8rILL6OZpYjPeNqMTMKb
+x8TEX1p/2G3gWBG1HJVmtZlMVrVXR9/r9YVxcjSBEupo4ZrSmZSgZ8/7Ix+nXRaF
+noVplHcAeG7Lr3ajI1G8pngXBxLJhJh23ArUsHHhVc1HEDQzjgV8jdve8s+NQmC1
+3hU52YZY1y2gW7WIGg3fY2ymcXJzdNtv6B4kB/OjZKDKnpnAU9oi56JyGKwLlLFn
+bDmnT2QVSTIkmjCkk2kfLdoYRVg/KvYGib9UyTqfqeXGUAlOjLr0ieqaMrKbN3wz
+oh+YB7PxPOkylZe3dcz/9Gnce+XB1MOqRRMbbzP9I8JXt91hB0nI7UxCvmj4Ii0R
+P2DVZ6tCscP/3Iyuz0kK0xGs7J0rv2V/Pnfbj9OUW1BSm3RVoa0i0CWeQxlcglBJ
++29g2SLvPLyF1q4TXz2d3T5dNiD4YFXQZX/QzEx2x8dGHJMH7mHXJaTELll+R3J6
+I2M/WC00/PYeO4I/zUBi4Yw9edFr9FtuJTQm97jwMpRfowYK9T+uSjWAn7cV1Gf3
+qNiYVSmuO8Iz5/qscZOSGVYYK558tCYW772ML1iNhZR5XVadehxd/whCk9PCS/EM
+j6G/geFnJM0xHQzfPgYyM+qYVNEoToWaH2iSEHpt+TyngqqTI2fO2Te1UHtDIqKO
+Mhp23UiTUpnU7w3t3Hrs+uYVlx++v9TTBZIk3f8l5wPCaHucqUWdzK87ACh77eIv
+bFfCD706pTjYwLozO5Wv7oFgiyhN4ofWUcfn8/SeIi8BxWLzqQLggeqAzZnUrELr
+CZMSvBVomZAR6mcy/rBtPb1SvGId409gJrDEDRVkxMNPiR2FkqmbGtccoVaowPO7
+obswxAZ5pzhKS7FfbxHuBE++SKjpkVDnarlav3IE9HMu4AtTEaA+/rzmODm4EUSf
+I9YstBFA0VP5d3aW3Ul/9m9P7m7JsD65fcEaLHpVLxSnwlm2GRGuHU8J+N/dEYfm
+7MpT7jEo24pWXPX0PCq3wz4sP24n795u73C2auh+cakfyWHOU19o1fobVBkxG0SW
+gDIgOYPHzhQ2tw35L+XVd4cy+TT2O4ikIHS7Q7jvfnikvzydSsEFlin811ecBSwJ
+ZXgGp3VjMPI8AunX+6QKSJkc3mDz4XvcCViRvoL2rh6fcPB/DAAbjLpGlwZHptNs
+dWZSmy7fnVBAfKyRi0QR27CpwE6zAH+uf+tSqR5/2GXTJIjPqk/ULEyJUliglUvt
+ylw/XdVIOK7cvSkgqA6dICvZj88ap1PVXqil/3JU151G6kPGU5fC3GdKahkYBKDz
+wdZCZBrPITpZaHQaiLPsx77UvV550APsaI5GlC/mfUXB24vwgcsvj6AVvQGIz2Wf
+YxXgFMQXcIJIzQHd5o9SHsYqgKpFG4FFFUy6himjdP52VxKBve+jJw0Dga8fXvsV
+uZ9tIpwBX53njnlZ706PrcqSm8MuNpf5Y4xDYPKNxA7EEoGghlgcTjjs/7lFEdnK
+0NPm2iIgJo7pADC8t/mXWIoZ4U1gTTgZuCbyQ6a3e5Qxl7kFkpAMDsfvbZ1a4Wjv
+4KVxfAE/AhwGfooe1hp64+z0HFT3qW98mtam6VNz8VHxjQgS+8hbYESldQGH/sIs
+YsSHCIRc6DdMqxwP96azMPSWrtN0F/3JeFajAF+BX/bdm6I5S9pcSggtTSp0mRgD
+fs4s9qSDs0clIIDbP8RXPbuVkSYL/i2GjX7xG2ZXb8g9yZ3hcIbvPisaf5edAjlB
+xkaiwek/ALaduBs+5IkzsQHiXJXKvvgRGuAWHhBA2J2A5tt5u/lMx9ZXHIvMUH1a
+gZ3jwgwwrW67Bo+Vssjqn3q4yi5zE9k7Cc5D3cXtRlAtFptbMWwCbHdQYDxbaik/
+HtuImu4GYlZWOjH7R2Lbg5Qc02tjC/5sKTmhO7hIAE3rc0tFDsFmMl9/NO/nuLW2
+o+qE7np3JMhJpIMyvs9L93JL8af2sg6M1RuLr5fVUWzgPuMSCNYrlnQUDIidkDgN
++KJXC8nve/wOlTmadz/Thtt8JQmGObd1PSR+zfLIadcEN20+zLETDuaWmO7rdrIh
+OhYdXlf3qNGwVQdUf30eKcSjtqTcDlAFTGlbTPZstH46KHdbiDn82U1Dh7VSp1IG
+/NB9q0vV/KhMFk1vGysiLz/GgKyLouElUIPK0rLOOVjDkS+TPpHYsE7n3aX4cZaq
+rA/hd0lgSOXjTjOUSyAbVEz/nMBKdF9VKzcDXMarW1WHjI17gpHT+bGpVQ51WgY8
+qO0Iq97YLhBlXxXTeqIApV9G9QMHtd1eV7pc6c37lmtR4vRP3ZoyJ9UyT3wr+oPf
+3NiIBEfiS9qynodNe9TWZULlDN5vZPLhkLMDY7Ir3F2BouEsZwStG6yw2uuQqL2D
+qgtrSrswoR/O+faWdXBs0q56XyvZQZ+aUkV5tg+SlyLp+cnA5EzdyxQWpYUkfe5z
+wvb4npphu9RyUQo5j68bdVFBReQC64Ma7G62JXhuiY4aiM+IDI+XtiNPdKHxDgVC
+wk9LrlzvqmxTf5Oc7ht3Q3LU2C/WjQT2+Ma6QC6qWvSAkoFCavBFoOjwgv/a2uKd
+iL5T14g5jsYVb4zpKvOmmkgcMdmq0N9WdgtrYiBa3a42nQ3CwZTI2MYgy82x4D5o
+LBjI/AEelUhvFkFTnOjlbDOcBR0M/6FsVDjmeaYRnhZljPnsIjfBVTziRNEa/UQn
+4vMebrC6CVdXmRkvTuSo7pEQkOoI7zJXiq0fgDRcWfEjeob6NpIqBfUE9sGuWk3B
+2NpgG7yjNizbnJ5YQ265oX+v+2yVe71L4QHWh6gGjrQ/IeQlSTi6fq8V5Eus+zqP
+zGcc/48gGoMdnWuPEYP3lWktwq9HXF7OM/e7GXe/Szr/yaBdVdi9S+SfeFHOFFQj
+E3cb/v/DVmv30ljs+dhVPbTBGr19/VhZhDiNzjlHUWPl59U5toS7pO8f+RbPh7AV
++Fu9vCAiKBPWO3sS/77C48hWEteRPjarRY1FJwML55aEOXPk2Zds/NprLGcJACPD
+QDsAzwhOWQ1DJqCPKRdQ4xmu967HbdbnYowWJ24WvVKf0PIKvbP7FO7tlPMAwyQh
+7cDIBDifXLSKrN/fpH+LS+m1ACdfdi7qm4AilRK+Y2tWEkjijL35EC2YznuQKO9W
+CmmCmalNTwYndYRovxxsJ9iLh9Tj7H2Phz/g1aBtwIS4OT4AeHLPlQDBdHJnXrpL
+z1sxvxEZawWoM9i81E5A1yro7m4TPjEnDzaWKcmEwqkw5gMzzfhI+M1HBy+VYsC2
+zml0SMDpGSIg3vYs4xDIxpote+4y1tBoixLCTkfFs1O8IJ/5A9BgfCEtyns8M2nx
+VkrXj/BTF5gXYPFbVr/1XoWNfo2L3eYJAYvXWsGCBtUT+cfolTzRbgN7n6DUUAyt
+C9B7bFGbTuPumSxM05ztL5dccS0Afsjv5QYmGcd/j6H5EwRybwjoqTY7S5ahcRja
+chiAMxkJWPqFlphO0pemLiOARbWtYQxPc79SA3juom6QZdMQn9I/o4iLOFYprPpF
+UPftVqpJcTwY4t639tjjMfjOV0yKRR3wONdUcTi5YuRvaekjDBCuUFnf/a6Z02WO
+AyduDkzFNRxnpKxc5iCjtsM235kh9EIhXDfnGEB4rThq97h7jfLspVXMuXEzR13M
+E5b0C3kPeEf4bYxH1w1fHG4lQXGVKIOHLOMJzQahRc8Qe31pkaIH4rmNq6gkCoNo
+4uGpVgyWvPU43opdgjLDjffFPBekS1Kfog7nryGA2QvguGY4SmFNm0EiCcln1ign
+xJ5IKBcKjNp7dMFFF+qnEk681z2U+0NaWi7MOehAZoMy9v6qUNL6yQwUMjYn94TY
+RtcGbajzIRjB7VvJVaEMxEbyekudwvc5kZUKN5HPF9WL6XxNWCR3C33/jtnGCxcp
+c3+xa/w6M0JZ48zA1zarBDAh4xfKp9zdk4cOleUrF6/4fBdZtxJfuo4hjTAy7fLg
+22K+pEnpmBsThtROXXTkxqT0lZobT+mFG9UCvIXPPWNw0M3zHpkF8S+I6roab6ND
+0A1xszuZ7Tmg4/LYl86b6nTFkwa8Aa97gIwBOooK3XGXBxxF0RQR3Sd6P2d8OjdI
+aAnflx3TXyluSbXq8vWJ75LFbgpD2p5GI4Ari4MOid/kmhFJ8Njr/qIxxWxzBLde
+uKCTqMowyULs7F2W0MCXLZtwD6U+3JoRP1lEj6JAQ1rnrXWx4DUWQNODlngUmVm/
+FdmlFVIJ6c8gFJMZ9D/5cHMCH+wY7jKPwDCH6TCDKV029nW2K5yMm+eXNVio0/xn
+13Z34aKmh0lLUq77mYC0yVwOuCwEui2ZM2e6+UEC7shWQmiU9bqEKnBijJINdo14
+SSnmtFibEAQksbSsAP1vb+tZEz+gJAantxpNjuiMHcjuNGXyk5DOsdRZyYFuYCFA
+Mm+I+edJk2CM6bJPkZNd6ePlXbO0By7yaj5AInPxyor3pTaVs39Ks+AVG8CVRZtU
+Jvhxw8rSKwCfFGBEMKNbFXo/3K6/s5is0SZkEkjkf9rEHqjQ75G9bSmfHDiAjuCe
+kcrJ2LNYuyQrgc0tkxM6Vu8myl2RYJv2I0vvAZRXf9QRfxf2VzNzBr+60cibPZFz
+w5IsJZdAuX+2abzm4l+fKhoBJVIJ8jCQfOJEUPoaVPFVI29os6TZJiikBcrX1gG8
+Pmn8ZLasg3mS+aGxT0xkBajz9Cenei/XIQHZJ/NHUXdaMDSFnJ/jp/KQvGkbXz/c
+teqClr3sLPM1OL3dm03SkT3UC5Miprz9jvPeQgdOdo028SeII58C83lR88JnFbyM
+bINtmiGJC570GjgjaD/UXSmgnR9p/GzAwiAXeTW/9mg2iAZdqHMFghIzOuv6HBpa
+ewb3VQX/kr9CyK6giWtZw0BO1RfXE9YP2ulifIbN30xhBv96v5jbbW/fTHkw/b1j
+osFClxxqG3pNpFJKoBokvEyX79rN3e8XPYpNMgUZb7MKJJZE2Mg4G201U50yaTYq
+OJAn38jf6pMtMDhnELyhWi+Jl8ea2bVm6tzCHtjr60mdU4PG/h1svgNShKokEX68
+2crnGEhYchqPxMzvk3CRF2jH38JKubp1UT5G47IWeFZO4RfFDUiMFEdrNdNlwjjk
+ZxIBaIADGOmprfYVyBVyOlCqUrYqLq0Qf/Nk4N7JcHEjcXcjJYsUuWzIpWU+Dbor
+aXQEmEUpN4CWar1nPKUi/dlWHJQ47kmgRQFDVoaJarW9Tu8JOnWSVbejE/1m7jSm
+0LKJkhte4tzRC4oqJd7DF6PMQHZOSdbvAvCOv3ZwQmy5bBoPLuE1lHnMxnT14Zl9
+mFZDhfa8YzsrH8KhNptCkQCtYYlkLonVtSiJTl6CqOjsQe0KAug1upu7VnUdwpLb
+6OnWEoaR8Y9tCRCOuCxgZSSCHT518oMAmT35pDqK6+5SWhdleqCsfdNWJ77pWlkg
+kU4uDDDLapQoHbxAhUs4aGMlkFvwyfqHkvHtcPWfMcBINtibwGKOvxYtv/NThChY
+2S0UFa4fp0U5LjobEFqY+nryiwL2Fo4tBT7h51JWKkQ78qO/jGTAQO4Cm7zltF1l
+5Ubq0Ki1b8bcx5Ou9zL9WE0Ak2U+jAn+NJbEFd+FpDPofpE2jsnU10DpVyqUn5Lm
+ZTjogR41SUtpDCxMsfbEord6DFmGdOdR9mdWjVneSqatYAKV3GdrMV4+2V+k0wBs
+wfnSIbHgqp2L84wS+yX9+Txdbh62FWbvLZEy1Cb40d+z+5NKdjkdLbq7yYPdhK+p
+FDGYUUKuHi6gZsGQZETip+irhJ1kzzy1cfSyt3fSh/slITQuN55k9ghVwoHCG8qN
+zphevq4s381rzTCZ9LPpwuX3T6A3E7mcsmguwMyXwADoAoDQ73d6sRhk1NEIktR3
+YBvLDZWMs7laYeVayf7brIfLp87g9HQma4JIydBkr/SXgyJfiQP7wIuZMrdncoT4
+anu8pXc67jF70s1Kvpomzy7g9tydOaYr2K86wCgUAtfWTdMaw5HuiJ9Hvo8n5Xfa
+qRgdrzUwhNAC9qeCt4HS0huiDQBUZ4hc3571B9QSjg1SPOSekc5TJJ+MFq6xbW+a
+taFcXLb6CmRnayD3Uy7gL64wNSaf+h4L5C7nS9EIsnPC8myPdkK77Lw9ouD+jeig
+XHuLsTI2IT45IG4wyuy27Duj90K73WK7Z0R3eof2h0Blrcy713dGGtXwNCNoI2DY
+j6ygNDulS8aZ2deNHPyOJpmKrrjlDnlDLADAiGNh+kL1WFD6Cgg5W0PygRCuVNDV
+EBbrcevpxSpq7p1KRm6kpBDcp4ThXARYQL0ld69dBeKE79nMJF+Xy/sXRbnt+05O
+4crGYUy3pm2vFv7vX9wIZ6B3JfNg8y1Fas6ETYn1z5uPmJd8YzACbzU4xFQvxpY4
+6X5fchCg6vAJjk5/DxjiCo66zdRhpGKqmKll+8oETYEuXO9GYrjBfrSSHFMIww02
+QEjrPxwI0JZqWLu87wZMbu8biY7vQHs2f1W+lwNg71BpbriqFbUXOQoiTSl+Ugce
+Px5kP9zBNHiN6efr0eJcgRKRXbKm/1UBA2/zTBuiTuLjZ1p6WzAup5OfMKtyY53+
+f24TNhDBLxjsFaDagtrhXGYAcxfng26sVUsqtCuFwQyonhi5JqEtNAmII6ZmcD+B
+Ex/Uewe7xg2TSeyw9JysaQ1M8+6gAS8G9RKlJtVUw4bWJAZJ3z9VPG40XglNkqdL
+PoAgb8YKtOBHrUdvRBIeccbxn5TN2SyWZfKPUjmRj1BR6JjN1MxJEuOQqOSC4747
+d7qfFT3Q62wSWYGT2SYNoKZpToJMiZkKvAnIj3L21/PD2BKkZM+2WMRcyA1giw/A
+fL0m0ID5WWq9wDkdABwAU0g9Qhxsu7kEXvV+gt6jGIbMmlA8S0fBtQpZnDM+zmez
+yGLdRxUKmyINyDCuxH+VDx+gu9DC04utcUgNapHgHBznsbLFJB9Rvqd7p0uamd8d
+NQyJsjhw2UEgMhTn9WnVAGfUQ6h9bhln1xyNtjIItEUHvpaW6E/bLwI6+3jyLg7/
+sNkDwoqkQul5dl0CtiLCOXYiMOkXTNssuug9SrPLmeiQ+o5dyjuYJXmccdmh0F+0
+UVOrIkCwoO6PXc0z+tJTIhO+qD+7DuxMotVJz9t9hDrVm5AbLJTcAIj07DxwyLll
+CNJaK+H7JB52ztAtnKrsbxYYnxWyODT4+aEE0+6iw7Gmdl90LZuQpTTI5+7jIvda
+Q6lI84GDpyYdGGi4Hodbw4xG3KKs5URiryfst95+4lF1yk5lqY7fVN9QhYRIJh0k
+FSJvNOL3d12nCFNgOeDshzE5W4X2Csm7rBqkxSVuJxPk3tLHMHD/EndErmkfJnkl
+ipfd6NtZKUo5q4J9qJ9vJPDV03DtMU8oyGmUjrLN0m8aPHPkh87HofsiS4PICTvw
+Wlo0NQ1aBQsZGjbcth7OOpYePQSu3zPQ/k2rPqbyY/Y9/h7QHlqKxK0tIz9SwoKh
+lE/5OlOkNM9tCBn016tw1w3S2uMCUt7gN0OhZUcwJVGEGOHAyX+gplKBDdQkLcS+
+Zh/Wu38NNgQHiueMZs9KOPrLIviR/wTTIYwcdqe5XcVaYb1UxubPOMlre6mY92uL
+Rk+EqdWH0VnALtAvQG+/DIMkRyrosqtNkT7LkKnxnZdkAxPucYe/IFTIAUdIQJ/S
+wWO4RFmE04WsXvo/UlNvE6NhIw/gkjmN7jSCbMGdFcP3rBe3seqAosPy7/alcU5k
+3SqkHkkzxjr7R7czYbl/a/tTcILRs3JW8iihLEJZnZkEeqgrC3g6hBxdP+Q+AXC7
+hwiqzOK1dVJNL8FZYVkoPeAco9oZzZAWjIecdAZbFWTM+B6ZuK0CG+n4MDClzQ6L
+qp9OFTsZ3FMpIQnWKrVbohaOLxBp3lH9tvOSJLSjvzZOt0jN8+vRDHkL/TIIk4SH
+Wxvxv/v/bFuYrGQJlzFXquq7amgPo+LONThMIozNTqA2bpE/rtIjkTisoviQLul1
+bX+PEYNSRBA9VIM1dTIIlBJQHung3kkh/NdanI/83ZloPFIvrSu583FustoV9Eu2
+C3H+d3AVvklQ8DV9AmQBpV+MRb3wmEUooWXyMc0PQ4a29VdOFX0FQ9BxocLVWbNd
+XcOpowrxU7WvSBMG0tRjR3o/IH9mcNUOHfro/A7VX5GCikJOR/8qLGXybPCbQjqW
+YpbmNSSbsJj0esmgjlQB+p9CXmwQ0e3GfFuyxYHZenMvnS1hSzMgazKN8c7zai9m
+Ha6FLaInIFmQFlKekHUdfcFU658EXMSAbcrYWeyR5a5TYtUFa2mLfHonwNVg6gmU
+fC95srRKjRsC8yab3f1NsPyZlfkUNkB59qyMLjQK63z2UOYw/Pj5zCovHDE6S0ct
+GbUE61x8guDcfCvAdkKnkGRu6kyP/GYy0K9j62+09OxCohQgcjkbvDEIc0xRaoj2
+Akx1NfLsf214aTKlYjYEtseJYYmKFNyYcNJw2L/2YfbGw+DxGfmZEuR9yq0IIpo7
+yULnAS3KotQgr2ysMJfhIxiSIEwQ8RIai9vcaWlXbRCRogyxhdqJttLF8WRKJOev
+5Il3Cxg3ZjGTfkGkwIM3cB9zKOWweqIroHtyM1/o4yc7MJQenfhwF2lky2hQKpZ1
+YFtHBHlsTvzRanzj8OOIG2GAxZ9V9snf45cHjU2fD8/8Qm8FmYe4PAPqKCmiabcI
+nVGU58kKfUzf6XDw/cxmctgE4HZCLkWL9XkbbD7qFjPsU0o0p39U/oPnifl1qyiS
+qK/YqMr3sKDI5cZcQtf6njeidTonBi32r3AQO2RgnDF2tCsHP2sXVaLd1iT92f0l
+faihiOGpHWhfPlX5Y0MZftUMz+YB937rtHWCgmtlmN/R4fVf7x6Bii68hNANaWXS
+bo2NLtnRkbnFc3eDc6oW2ZBz9FRehyZU1TVPKopyEX7JAWxmj34xS2xW56Zjwuaf
+lA69V4o7v77ndfJ9a/0gTXWNV28dBliKiMa1FtrOEmuIUv4/deoClpf8746XGTpM
+LVlD21oz6InwKQpOdLE3gT733PBW1Su5LQPOBfOLrt4pWiylLPeeVhU6KM6TYWwB
+SqXJcKPBzPEDPKkSq9vq+p9bWIo7pcpaTQT+31r9ccppdGOyMjZvtf0AR7Vpa4fS
+udoFqjaHP9rkBRf+ki4lmwEqlpH8Gsl6nIDI6JpwfKvmwJAeBNyZK/3K6YUeMeje
+7sfioeIEZBG1zdnyd2XpreXnZAdHNCmYWNcHl9FTm1MoLlrIv/WFrUmw5hqntGvx
++G8ZR2z0rt//6LmZVeHgMkRnkL8+p4SxGSVBkhNfhInaq3Pyz1gDJobLcXv/xDGj
+jf+bhyhk9Iy8+hGZxDw6EiJAypdPZDblLKsbiO3Gnr9GXDGqfKJQVSnTC352aqiJ
+vJYe2je/JSK3tirmVl51G6kV5bh3ax3g2lXgO5cspS6X2sL6XXi4jiJe4vFFtQBT
+geBROHh71I2JtmzeblCcF/fyQDI+VdFcnKGEtFIcbgUlAVgb0Lf7foXJljXfNpYb
+I0m+MGLjBVRRSEpJ3rbODXbqDCaG5COgDVDUCGYgYmUe5wkU3UG8pQd03g5RCVBV
+aqABI3vZLlTNt3rths+8aZlJjuog26gsjB3WH3aUKWTu0AkfFnAI6drnzxCRTfBw
+V2e60gTkWcBr0Tx/6Ta4gFGqbugw4Uc/VSm68gKKjqOO5clHfCsXbSboP3JdJxen
+v3gv90ICFNhf7V3o5FhPnSX8fNMy0/sOcChJseMF/urhHwkt1g7XvsTbJSTGT0cO
+ob4nUF/qaHqEJew9aoWFLCkaYerVcTGY9UCBRLumnZVMks8wylyRopwwMtO2Gd9k
+QzYsSZ28ctG7UHFMHEmBLwBbn0f+bUWZ8IMVL2r4lkLPUBPeOjnZhp17vZ/Ai4mr
++0WQxiq6H7NhTg2f3lMw1/AmkIDkvNyj/Zkj1macrr5ljKIhxr+C83Th5b+1uX9W
+VBvZsv2Lkxv8vJypclJO37m2SHalNA2JLzb7PFND5+zXF1TaT01tTgxSsg0RWR08
+VZ+HMhJeKuE1bZcYbysUen5BJmbk2F/KUhKLki+n7TzqLDA6PdwQSIyvxE3d7xyx
+Qx9DZ9OyYNAKbDOoD2oPCwXiBRPPyVj4YLWRjCTDQ4LOeqYnhfWJn6FAItbef+Ro
+0a/ABS3+jiICJlvZxvA51ysIl4aW8rT6KzlWmu2Zu80b9lG2JlplRoFYzHn2663s
+PhzonnIsWMEwVvJDjm03SCwvRHTroPALYba1CmzBh76HarOmkEV82X/J1M1J8ile
+o2LJPnhtMBffRvPMm6SmwJWwjZkeZm49qAOMGS1s5Bcp6Z6Tzo8EkMoUYtuVK6xL
+1w0ZCJFyUpV0FexyO75tjRHjaSQzOnZjKWKWJLk7FXgclO59H+ajTwWp5YrZTag/
+z0yN14ra6nKjLPj7so8CCYoJvnqIgo5r8ckPbzYln1SMONtZO/DR3gp+iIB3c+qJ
+ONfns/rJUNufgv5NkzOAoUqzWX+1CLQi23trwmtlOEfCUisEDO0xDVmHptKxpSwB
+HByzr5vbMFSgAwIRRTqRtAuXd+4lsL2o+5V1SDdvojeqj9nHHjss4C5DBOOLenw+
+/VBlS1EET8IquO5JSevga2fcbLDG97aXJES7zgIoraw=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_bidir_delay.sv b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_bidir_delay.sv
new file mode 100644
index 0000000000..17fae364fc
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_bidir_delay.sv
@@ -0,0 +1,76 @@
+// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, the Altera Quartus II License Agreement, the Altera
+// MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your
+// use is for the sole purpose of simulating designs for use
+// exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 14.1
+// ALTERA_TIMESTAMP:Thu Dec 4 07:39:37 PST 2014
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV-6.6"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+R8me71UCEoraht5Yl1N2sx9BPWWocuG+BUD/nUNYtPljvqCrLxHE+Do5SRs+Hf66
+dQsES5xKsUdOxOYpzminwyxANzEmkN9gnhkghnFdJqZ8PPMn4NPBXcri7HDr7wng
+sYo+cni7oneVT4Re01egTZBiQMKLvvor/9Tws7LZJao=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 1824)
+6Fs8X+Tar82PxaZZe0lmEYOHvRvgsjw/0DKMqfSEFVyzo3NXoRssHpCBGGWac9Tj
+on3q4kDmZH4Fofb63XKao2MToLURiGe18kUBc4lQYQSPL6CoFCixofzYa+psElR6
+bvfogmXH+JRCknBDYfSMYfi2IzQu7bIJv+VZNCD2T0OfveWH30O+KwCp9TTSSBbO
+NQEYYuccPgS+isDBErKjwcybaMWNr/wvx3xi+n1TK56Qkb0vXbBqvMmCcCkV9Odc
+lXmtmr8jwC6lDgNzXMDf5is/vXQNxf733UCYeEeNzye3DqmlFcYUPwAdNSaWfFkp
+TTyeZJKYqSOvxRaqx4wZggbqf5L5PYfeYl8CVeVHUDQFXwhchYllGmWMn4bwrU90
+5Wg4FaQ6wJpb3ah2vIpg9xpt2EGR3LDR3QZua+g87t7Mt6HaR3bXjYoPZ8cqzcLM
+9Tl+31zFg7WxxWo/4/Mxlw9S+cxpN20zwx/9IfvobR6naWfEA4ZN7xGbqd4yLptH
+r9NN+tVSLj7tnrNgK8btx7CnVxlMN9JAWqGrHnAt0NK5FInMW6HYUHEroMvCQWQa
+z96supKW2ULqdZQL7wVNFKBCHM7N9bzI6/KmiBO26f0VllzU7pnWV/P9i+kqGDdK
+d873lXUrhat5UvgPmMFk2hH5Nsg/3NhOTygd5JfEnnf+BX2+Vu19f5E4zrVSnkFi
+67H+3xRAPB2c2RMJ8LY/0VeotOmBZtt7/Xt1u2Fg/59fMAvM+lNvlWviSbk7VGnm
+hii+G2WS4AjRL896RDLqdqa4r/zmFI5q1bsfgzJXBSOhaVUjU1ZVVmiHwPK+Kqs4
+wZv5ctDxfQ4AkEsuE6d12sNO0Mns9T6R6vQ1TPuAsnTPRNPGMKVfB6bph5MQTlO9
+GJZ6Z8URyZObtpl45R054ZG2L9m8+QtxXqq/CAlMx2/+gXZEyKbUOllcFu0bv0ZZ
+bri1sjK1WEOVL5rj4kTHk+iRjcs0fyptING0392G8u35Vlms9DKRClfqbBC8vqIU
+GrtYAbeFtyANtuZcwyWXVSSHARQDevVyv1VQz0Jbbf6mnx3nJDQOzf4mKBY7pWGq
+Kh1AfZOOF0sXilF6216zqDpjbH4GUuZq7GfUmlACw3EO1ZCFw5c6A7bjnsJWHqYk
+l8MKf2zgF2rwjauj326P5iKtKyxQLo+CpeoFopVnS3sHR/gfDxRsfP6bxvRDj/uJ
+pKcGaKHbYyejIhFUQCIxKkNLTnaXLnNVagxeDhy4vySAygBiJl+v2H7oQrvEUnJ1
+knEwPtG/GzY1ytv/9oEXttdykitfERZYIvByT+rjkvukP6UoFJkOl0BhyFEh+w31
+l61K9l0/I/hMdspdiSnR5uk9zzHt0wfxjjToOlIr/4OKE1ChGigEy77EeiDT8G9N
+i+0IN7K08w/SzQ20FwymKNtcay91dHRzoHYmEUhLOjgO9N8MD9/zGPnV2q+Afnpb
+ctgbAwlvJixWLaWBsV3sIT3Ah6x65EnfwxnLfB4sOKvf18kD1HNqN08hYTCA8DxV
+rfEjzLTQ+4iUy8W2ZBBInvclVn9ouMj/vEWIuXUIyU4kVS5cdtpRlCliHiqBHhPX
+4EFXcWHOeOXAjYWEF/wpovL7KlHwM0c7bX4aF2eQpHbpZ64HPO+oFMr7oNvVuuhZ
+sTtDUciwKixss1JXwW29RpaN+2CR/qD/ujAAcZYCTR9gBIGvtqGe00DXyKt//Sa1
+hcx7ku3Qhpvi5WhftKERC24b5uGzQe9gQs1OuslX8ud/wL2YQ2oKTYdKNEUnRqq/
+yCUK7I6F+aBb+Z2/RwVv0zH8pFC0VS3tRpLxJ4gVuoAv12d4QWRnOI0PyTQ58MhK
+Ftj8b8mSWBCla7UVcmuVcjaFzGuXLFf75pzzhmBpzZ45qnQT0rI8x/BZAmOckihG
+rTOy/0JRdMut07kkJzl+5hgu5XYS8U9UCQTxw9Nku/fXcdc2kzBdvJj/KBHG/9SZ
+F6MC6v64qL06SmEtjgYVuSV6GcWWgQQdF9xgZmLO3/HFpHtyjHZvcpll4vmP3Qk5
+wAqAssAiYAZ9FlqKqkxc1Jc0I3YFsM8GRI8V5J/H448nQwRc0gUqvorrFaLxTqpU
+MI5xDAnYQu/LTTM1FAtightx2seZdKW4tCFp7IXsTyBBcHW56NLgnO+FVgUZvk6w
+pnSWrw0Av1QAgz4JIsOhdftTVfYNHFJucBWa4N6L0/mgv71C7E8inN6v2YzIHQTb
+Z/1SSsfUZZCjnDWZEsmUItuyjvLtLObUiWcxtGWjG+AjFtth6w8kWjKja2LD5MCh
+ghdQn69E4IDPmPOuv8b28mUkVAc8Ydu3OeIdPxGAo2k3GPk6MouKqH8atBi3uult
+qGD7W02amvItD8yvwdpRTK2FzU2/8JadZnz631qxYM6KxqqJFeNG+qEP4N9zIHAf
+`pragma protect end_protected
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_per_device.sv b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_per_device.sv
new file mode 100644
index 0000000000..426597e5b6
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_per_device.sv
@@ -0,0 +1,397 @@
+// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, the Altera Quartus II License Agreement, the Altera
+// MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your
+// use is for the sole purpose of simulating designs for use
+// exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 14.1
+// ALTERA_TIMESTAMP:Thu Dec 4 07:39:38 PST 2014
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV-6.6"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+Dxij4Xpf7RomJwrgFkJrEq4tiyDF+GF2RSRpK/p1GxGnyteu16OHIcnuEzBtLvbH
+uOwlRREXNB6qXZPwQTiIB12hRo0f5KyQ1fhf5FCI2iTUQKX88WNFtxDATTByS/q3
+xaWx8rFZKMPFNS81dvdwrHTlExM/+xBfen0gTn6BwHY=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 17200)
+y9Nzln+Dww0BreEtL09mp4wz/gmUIzVfj9TlLNjGFkdLTxnKYiiORLNc6TBgp4ti
+jRb4OUA98UCR6t1SxILXJify43v/7LeyYKuq09TlTFkNkbc7wfKVamKvUGYLuQWl
+RYnh9tv1vBL51zZA2kQzzKVTEfiX7SUKHqaii0Yi/c10yQfL35y3jKdPZ9Kz2FwZ
+u4VdeUpZX8+Px6UMJQRUZxewcvkaLgBCdnM15XgeeBJjxSlYwqTFM1/vrnoHP8UT
+XlHULWeutQJ0pzxFUPjPEICOD6RMLfBUm6z3WzwOv6YlD+0Q5U/j+cyprdZYdVXQ
++XXxmo/pye7BzH/8M0/C37XpSSgYKtI1weOvWuRRo8407o1LdFxye4qCymaSL9ud
+GHhA33nbawKlDH+GklL5DvHtdPbAfpv1r5bPYJ/ylaXlxwX+hStcPXy20L5jKiAc
+7Y6PCrE7sU+CLeA9LNepf5rZZrT59mclfRCorZBzNQII4aJQj6proNktPtO1Uv+9
+h73DzooKvWrQdhkmXDInW2K8h9pPetgYiYQmNbwdhlL1nbxH6rIn1C/aaeM1MhPg
+ptklY/xS7OHBj9N8bhS9uLjJ2PM44PbvwyuRf0NBeuwkMFsmB9XSSOyWkUi1+llu
+CSMBKz2ItpB3GL1rlSJH6ympWWug13bgv/CGQw6rpIKVzSgBUePrpMbTYRwUqeGw
+/yg9HYh5s1aA60cXtnCODhSJ+LDhrv2SGhF1PnDEo726S4nq0FubEMjfYY2tdr9F
+yzz3sc6D26c4A8xoSIwLvXAPo5zRMDZkerPkZ2OhMJLRewYtA1Swv9LYn6BcTaq4
+sJXp4r1OlzKUjJz2T1tyG1tR32qZTJfb2o/pu3amdvmgje+jKwg1yc0k0Q4LV2MH
+PfllhThWnmUsNAhmazBkx0dcBDCvdEogwS/+Ksu0aOR4rn1BWaYQBgk81ccalJVY
+HagGk6ybHkawCYdwIXBhhWcAtWpq5X+BQpEVW+29C3ar5ThAIaxYO0fzVs75GOUo
+q/t49Q2/ah8rLJFN9SZkzisGruOPOZJLr/vJCO0+MG8GfxOZ+4qKg5xoHkIcbw14
+70ISfJ17hO7ecZtVIv+rJyjiiyPhN86ZGD7qI0KEU1pRPAWdSxnbrmaOgcBtfcFx
+ev/ujhDqHzrqmjWtxV76xnhju9/6DS3OdPSGI+rkSSEwceX0CUHboWg0dwXheRDv
+NA7p2snAEU1VjFJNyvxzfOD2ktX9N9qGK5QgT+4XWID/sq00GIGc/ROxLDXUD4dE
+LM1eIffy7l8B7pa7QIpx/yIdAIZOc6DuBkqZ32kYBl+rZen+v0O1a5GDcBT9I7WY
+FaWB9cxjbcezmBASaUvYGm7QvSA3nX7KUn+d2+Sn6pk7BAzVyk9QqrMbMKjLBDgg
+YGuKjFlLokIFpgU7JkEZ4UbrFoUayJm4qEPy/r9VMuYjpSCIJQ3l8JphEzkZRT9m
+nAJt69qhKL8j8A3FkZtW0/SfrZSw9EFkacn0zKavImz/aYYCsuhx8sXHCNqnJrXP
+RXuxDtatnLuAYHnSlvTQuCzVobXyGMIRt7W0l6O5VdmffSBoscJ4ureI/KNkkNNw
+lScY0xbe+Twsdvbc0FSNvOPyl9prfwWp1JQFxgIKraC0MQTsVCZRuWJU3XkDfbId
+mmgW0ev/YPEcDrRCoeB9DZ8wBdw/qZ79LPxSlTObh2MhGoJcTmExiEdNgtU2ClK5
+v5tl4oHz4/GMDy8xSDJ30JO75smS5cmxap0xbrd0JxjLTL7n87DnpQP974ZGxOWL
+HHo6GMJ5xkEexUwVmVMLmNMEN6lhNKCRktvsRzFjJ5UtvBzDQZ91bPxE2WlGLvwF
+KRMTSkjkHWMT3sRcd76NweNZzuoL2lW+ugXsBGWiUDQu1g+pHVa6RWEVBBoyZJud
+TGU+ezXQIv0reVYNCtg1p2+ABljh0oYJOyLSOsNKO3AlykQ73VbNJfC+tw4QAvuf
+cm5JMdT6Qre5Mb/sEv08mDcvErFvALPFsMD1mds06i38UE9208qFcBwNctHUMqyN
+PEqUdxe3S9WSFdjwQwzVyTpdExSwOC1pHYyxzZa+5zyMVbZe76M6SplcKfcOg8np
+AL2vadwFJ8OYU/26RkSeU6i5nAsqgK9aGu8eaAf4vlqcvDKkhzLhGOHRNIID26vF
+LrsVeXd9RypCYtdhWs012S8dx6oRniaYyV1j+V1yI5yO0T2TDRMngz257xpBQSUb
+eTlvfn/3tEyUY/57x0PJDv2J0jK5oVUmdTIVHoLe8WKwV1cX1kSgBD/rU+L0j2pj
+zTdLQohl2cwfNg0E0bqsyydfNWJFW8gXIhayxXiwokq7Wa+0WEpmojVenZrlIqVh
+cWBBLee21lhmm8fMfg5QXbD9grfCBZhc7Jc4XYZwDXIIGdPNTiZseOXn4IyLV9NF
+l+yB/NxSVLNfnngOnTGkWf6axq1gcBUsC5uVJSQEjWonf6OZcrRsQDZEV2uLAZtP
+i82GYp3KyANd9iy+JkyHQFRrpk6cqxXEnpzmes4aVu2Xtgz2RNC4IBUq3c/b1szK
+G0MSvIzqYB2dOuE+IncfJxWtVSzBQ9P3vnhmorNKEWhYWtYVhhDnPljeFVFSs14Q
+yEr1bpCCODfHhDg8WGk7WHvl1ygRYnq3saO1AUcaSaEQ9Qni6Iho5cTxJtaThP8Q
+e642nI4t0rbqMIbIDWXgtYgb0Olmk75a8ZDIMKPzqU6V6tAkvaVfDXbLvdxzWKZ0
+6i/0r6JhFT8RhrJhtb2FILVTKgtQO28NtZbOEC9scWInoNmTJAUBDw4FqxJ/DB2q
+yfrzTJ8mjcaJ5vZVMELxVPfRKwDmAsvi2zyyVTdpINSq2orAUTLAlLR/OgcvBxNX
+LeqTbi14XO1K0j8hxrCSTQsbzSnV5HeYFR+kGdt2IRdcdEi9WhLy6uY2NPu/S/wU
+zlzwYro90XMKGmrxoau8Mpdq6LpA4HyWNhxmUm/jiu1o3Foov6aC1uC4AD1gQtly
+xlkJPM60HnTXHhS7do4z3746wXqoXofo76lPB5D/CXI5sqgtph0Z2505hvxtdiCd
+fC6U9bT/6NcpbBi7YpsVZBMnu725NHpG4Wv7QiyOF0ztLEDpm0eLvNa347cIp9au
+LOuy4eNMRuo4gchsGOsd5N5Ji78MbbLEblokv01W1IVG/b/wHWq/GLecgE1Jl/Eb
+ERMWacMyQuprvAGSvThJv5XRSG8De4oNXi6milGOmJG+8HHSmYmC9d53+aLWhhSk
+a7Qm5Aac4Nmndw/sQExdlPbEAXFuVZ9fcR8vkCGDVUW/Pheeg6RqimynQ3pTz/Sc
+8jl6qux3gu5J+oYiZGtBr0wMJkkB2XIXl4f5yFaVC1KlAC7rK+hqIXd51kaav4cg
+0aulJZNytHChpeCme6etZruWOdzARUoEneUzGKXtVxbSxmulE0pUVu+hn8CGPlYK
+Qsm0wzVy5dbR78gS+1PRqg9OF8BuVBqRGAZChVHlHAPQtb0B4PPPCdLzu6NP5JRv
+PRhOOMJf+V+oc/lOdB7Xqub9GpOfwvW2CVv4DFYt0mXWcWbrh70YT8Mi7uZLUykD
+PisNwj0X28YdEDIjoUE3Va0shzYtW1DqiamRFytn+FyrTAJglueqiASWOL664ROc
+IIT/jmok+vCN4FJPmYLrsjGiK/42y/u8VOK4Rgg0t1S4j9Sn+CTQ3P0ohOOK3+Ke
+0A8yZiK6SWBtT/3clQSydp3c7nw3V+vFEUD1JiZsHli5jAJRY1CNvF3sFcp/ly5r
+IR0ScSuIokkn0Arm384NRgNZNwIZk5A2pgcGJ0C6gEqnMu0lMlMyFMYL3PGw/4Vh
+HKRqD18m0z7SEU0hh2p/uH4z1lUcLeKNN8uz74PEteblomSGUAj0K36EIF7lkfkk
+MfO4dHb+zTNpTPaGz9OOW6w0J1fDSwV3K5dSjSw5XRtHK0TOaD3+YZNpwPCY7k+4
+BzxW12bx7Y/pvJcLjmkGVxzFjVrlBlG7gkAETkqx3gS3yiEtfVQfRFRWrllxx7+B
+uk17PGkGWpc/UpwqjXQveF1bYglgGSAg4O4dKODImhgTRyjhiryob7nSL4IGlmh+
+KAohvei4Jjy7u1UYMU5EJ0YGphVKr+9u6zAUXeilbBVfdZX/QzbVZweITwyHF77b
+e60VRieoBFfN7pgk8ZAlBo/9SBbol62nXp9+YKmEy3bbtS4njV/3kgeWiqxR0zs2
+3jO5QPXXeDV15RkvYDMp33avD0WBakKtnVTOVs4elHZDi11kez+TUQjPgO8/3Vdf
+qA8T6LSWibAbl0IYY7nmbB+jjkJ64aM6o/3uxdPOqBYde7+YZvA74rJutN5vd4zZ
+3FYy9jzrRfG4/SiDBC134oypyIR7tTuQgYxOrjXBEz3UaZMTwv4LMLstW4Kxq0G5
+sOQoowNuaxpt1OataCC2uy3cSJs5zPt+Gdk+ABtg5hRcTd2zE6iBU2NkeZWJnGO0
+Dfo34Ar57WrtH17oVMl2vZSFJ/BILFXdUXiSW4hrVZuBP0j3fZRdo3X/By00+umS
+SnYcCwiFrQI4baO6WfAfSUhYq1TcGQwQBhugO8Vtim3/nofJx9C8LeWc/ifmAiVq
+uEHSD1+2Lhlf47V0aN68etA+7WKrgLU+FrvCJvs/GN54sUNRL9Rl9l3/lnFdvzzl
++NgfyG9VWBzs3Np9kxar3Z6PUkA4hm71QHAJL9aC8EJYbZxA25b2OcoUV8BIeoFD
+GqWvg4YusjHezD+UUaSnOP3/dfrTnZpD9BBjBuhg/aGM3ph4n1HJ+3AYOo4aew7+
+1gSqmBqmC7UUQ09gijuhlT7mubuRqdBPMKRveLFALVUs+5lS37VtRYyRSYheP2y8
+P2RSI6m+M0op7di4WzCA4cJ4TnECgB+rd6sYybRRKs3cRIFW89FlDkC1wQsT1Pab
+AOs7PUN4IczvHClwiINGjuWF1qMFRUnsa3MhruWLqctO58FB+Ju8XlEwjmENLzTj
+3HEg5IkizmUCJNao0vZRrpmg2XYO6lks/uPIwhhD97vsO1RQ/OtYbukPypm+FCsQ
+J9gEb7pD2zKv1WJz/HN07D71RSKjoaZrxtUr8iwCAlvwmnyID6H3gpMFBMejHXrT
+qp5LxuPf264JBj/xi/hH3hCJZE8QQuCV+Ez8MjV0ZM7YTdK7/Z0Snh3msT6j+Log
+sv9eH08c8uuBdgej9IyQPgUJyNxB10KkTHeVdrfjfgrnDZ3lMuv4f9igfKjouQoN
+7D77UxrfpreubZpUf5ILVeCBVKMBmMOTR7sHEoqflOFaoSXgqGCztFK+pjKtHd8t
+H/mVnJsKCPDbGjlTCG8Q4PCvIOyeiyFiAxldhp3WX1ZPCmdg4dFPYzkMZCZBfcqC
+mxV4zpuhBf9/rSXzoDD/ObYDDhga9sKsGgF5CbBYf7UpMrIquy1Hz1nKwfBhJvlp
+omHegb1HkqoRy8KvPXPaoavGeBsPBRmXmzDA9q0ynA/ifp82UQHw8vw7zWiBSXFd
+6s/ES2frOVltIhS7xi4VvQZEn/luoLY4KXZJS6T7O5UreIVCggkr1sv17oCOiZ6Y
+LtD6dY31P3isdJ46uPS3+hCHSwLxy6WbT1V+ypQnYDPpozWu+ffGpMbG5TID0qCx
+0W2l1E4zLUwSWAbBK6W7yEvdeFjcYygukDm3QhoDtL+ICHHxnLsRhzBRYEvX397J
+rf8cgthDYbuVV6SrzfF2GiOMqSNAp+RtmeIn99FDGstg+1/eMwvdp4toR6y5zP7O
+fuKKhIe+2NITGkC2p/Zh+sLsyXSYmkr39+4UOD+hFix5oxuq1Oo0zYpMK6O/Hw6G
+EhmbVbyw8JiIX2f4CG6oNPEZOdMqGQvEEJ0pJtEuAJU/ZhqQqUGefNgjfTX5GBkW
+2A+QAw39KCb3vbuvqLoirams6XE0RXvDe3AAdY95vUbdWqUPGIdIVsh4mlNxkH4O
+GOLUUuyo9pUiV6sO4i+bt7sigfdstejkoz5UJtPwFkAa+918AQBLzPELu8J+CG6+
+sOwCnHXVZuIpFkMwu4U6lCsEKeumNS4WeO8KO2M3Vc6VvclISK7rY5WZcQWoYEe5
+QdDXq4nrsbeDKBHG2gNDToR8NpOSTyH+QVNguC6nIxVKBMlaFsbefDuzLymXTRJH
+T4hdsPK/dg7Bny0oa5GsV/NaPu0I9u7LxueP/CC9O2ofhRPP/kMNzmqGtLbgAIG1
+VMIKRvNPQZjoZosLK52sjC03Lt1fpk5QX5kBGKEpnMMSc+sqkucLAmSrRlncf4zR
+xD5mmihuPO7wvLknTpOrkegcBJaJJc8sZpXag+0ezTe3L/l0nQw6vRzjmu73E4mO
+Q9E9Y2iYTvYgm94O/+aVWPOrszETE4wDv/ftyYwKMdGi3RqDQuay/9eS9fDbCf++
+SJU9X0PTxh8jpiYtNcnlGB8ZYGgADtM051Gdpu17Ye6a6OlmapAIhZku7jGdKOjl
+2dL2YeaaPLwkfKs9TRfhKSyu6zqtaVanMN7Dj/lz79fX1GlYVdagQEHTtFfA5OEr
+O4w77QNkS6u06qXu/QjjwnYtNXPHO25nOpE/l9QC4kqxiWwn/rc90t627MPISWEq
+3OPs5zLaQdMU/88qYH0oPcd89weA9765VNysmC/NP236B1j0wZw7wJH2vq5DxgOg
+XUiK8kuPczun7wQCHCzw2XXYeJTzsn3GXRWuBY29Sd9ORS3GkOs6p6AgkJrNxSwX
+h7hSHDuTTHCaIvzSXbiZnzTY+t0jY0H93L1TQerJTyYlJE/Nohqj/zBEhKY/0EYC
+BNNZl+UOVWt1NkiHiRZXaNfhDF9cbAEkkrFXTgIAeImgY5WJrjxL3JTGYxFZF7Ro
+SVVXwio27jaS/KTs82btVyrKSgzdJZ1DpAXaIEgm39DMszHVjLOudVUmW5FdQOQx
+hbbyveUMFerxhhuXrxPJYxcyNLt6a4oyZF/LCyMtgTlGbKRks3pQgUWYdbKhVFpv
+YezxChfO2A0kqqf6K+btqHvOvdKJXdlMHUy9MVzPkX2dRG54b+Uz2kSAwlZ+6Gsz
+w0ww9BVD/UdOiD7Wn05ddUJ9+3BSyBm2HlUQQJBk9bPLCHPhvHqun3VlZZX7TvQI
+WOkH9OUyW11p/ZCrQsep+/AFM3rOtlcvFGpQI/N/me0oKZdHf3b2UiMVxhVniLXA
+AJ2iz1mfdUJAsqSZfiZCZZA4suy87NFV1x6GBeQhY9rCAKAKg50OKIiJzbWeRdeK
+zB/9PbsM5FdpEMgQP8mUpwDvnEc7B4R/rwuJCX1/rjcm3uo83q4LcqbHUw8+kJfZ
+VmaLRnLutn6+hkmHuGNdep8Al2hROJSdCSBDyYn4LlBCC2UCADFHR8vX4mzgcdBd
++LQaHybfwJz18Xex6MrWJ6O+YAeCCFADduwD7M5gwYuYX9qv+0hX5rOpnSNnGm9C
+Yia7OxGS8FhR/9Z68OaJo88zQbRqEHEXUSobXrYKvGVLuwgG54hdpC97NMdbJEzT
+/KKRW2TzQiYvKol57TktGDo7vcOdJUS8DsMC2cB0vqDRSU3x8X2vIWcP2G/zMavI
+SSPOotkWAcCB8tdAqUVmyamGoSK2BIY5z8J6tUwpVTpU2wUiCT3lKADNXGjHM95R
+ITOpO9zJJMqI7BAUnQ5fkpQdTAQnq1CJrDNX0eMGMHNh1Rf775IUz5lpgoSuZbMk
+yzmYMi1QLhQ5YY4CdcZTPZ6NRHm1hIB72r1SWXFvMT1iFstER4EoA8lapwqEEOx7
+nmXh2hmGlaZMZvhyIDzKoyWocUDddCABb/AHjgbg5YpTbQW4TiTJpNB7GE51FkDd
+Yl/TKIF9Y6MgG3YIgsqdme2Z7mxOqnxBuloTHdfLMDMF45kGwH4z7aTGjt6lqrFw
+jlSw5iBvEttcDt6gfizEMTw6MIYLkxjOXQChxKnF1D9tFdmwdrcVrb48Hrf9kdDZ
+wGoNzstzHm7/kxYoo9eOHTJa7iHH6Uky3/syQeLpCgSNjlAfAW8+qTfY6xTYtyLb
+yUiT/t2SBVGKy822rYOabWlPwUQZhPQ79+tiWpbj8NGWkmtO5by/muUMAlk0hvsL
+eHJ3QUVIm8HpCr87stYwIqspNlYcFySh8iZurd6eGo7mWF50B7h073xrAkgpwJJl
+NXdnImvXjsuJvBv/DYzERoACmxKnWsLjDGurNdQFPH2ZA2K7J+lj9l1PFb8kWA5k
+c/+lLvRKp0Nbaf6WoAB4oRR0/V7Ip+viwICa+xvSrxS1k88qGMhGf0daxlmfT74W
+FeFDM+l01LbD+cawGaYaOSOK3FAfQM0KpgoT7LwLmLd1z0IonMGIg60OODDTJsWD
+a9UENtvCfW55V4tQIZpZIyM/rGeC+lCysJK6JwglYCdbJXQyM/LhUmlYh9p8vpUJ
+M3ybWOf/CUdM3/2PjGr4sfSU5djeuSL41gWiEN3qgFo4U2IcYKumikBQqWsuuZ85
+Wb7iU3FExqVQ5TRA7CmJIRu9QURjabexwAFWres2b/7EOeVx9122VKSkzoTmt0j3
+dGCfkBhxu+wXiKG8M7q8+xmy7T8dIav3MI1RqqMjZmBhUsWDg1MagKYIS7RXKW7X
+vj2qgY26az1tPSyRUVEpZZFyAD5Zu7rlQ7u+QooZAYvhNYdUULlFFoejzRqGrSzi
+8t8YobkVrbGsbUa/w+CDTj71g5rxnzKH6bT+F5eR5eaWAqTbAQNAlwLg1sSfcW0T
+89yqYxoAuGGBY+Xr0K10dSP/oxx2Ii/1Lq/a4wQtwIkvRiYllp4K6xFscIx0JMxZ
+IaBh/QQ6Y/6+kTgDkkqujC8Z58pBv8f83zkSqx6xTvZzwXhopiGmgm71Ha/nLGIM
+ainGW/Z4V6Q89zUri1m3MfTb1onOcb2yPYvokDRz/ZD3XRvZ6POdyNxw6XZzfV6d
+GqBncpJL+EsJEjW/e72+p4sPTFFbdfo4mKeT3y13KedfPZZFJe+a51X3pAsgqaHS
+QAVXUHjBHinn+tXwtn/4/LleunfkygyLs5kcMcu5mLPTVqV/ywedmSlC0R2x8qgp
+L+2nma6IxMe4db0Gprvkp4BeMpVCtzHK9jG9SP3K9regfToBZmDVju0BSQKrrhoz
+WtM+IXT+rTdwW2PALD2Xp2L5gfYyOKilQlVC+2HQu9yDdipXNqG22bOvPVFb7HN1
+wOsOtSWhp80qFMpHYUykOWlQbQeKkBThmTT0VRsQjSwKRzKbf8EAr9pZipmZXraX
+ZmtV2DY2s5+BkWerODepZrwXUP/f2XJ/+Bljl62HyaJ9W0KtMoIiQFIb0CRQnVx7
+e/TtSS4miQMFspGaFBXQFGRw2X4idApb5nvgyv/lCHOfCIfstaRihGTYbOqYlBIg
+mqZRbNLyVrviNz+qXZ4XTckSAg/XR7Dc2rf0vuph+n9hmuRkmKemwiJWx1ckLn+6
+l+g0ZAehQnKen00Yp8VfNr44dqBh9Rn3j7OwZqb6r5cc8tCibfLdyT8jJhAB/QwW
+axsgPMA6zm73W8PV5mTxA4fpI3zaepThuJq16qi/Gs89oiiHr00TphmHUqSpy/aj
+IBUsmSk6L9mnCtBPP+qnhoFbB2fKgLHET7sADiZy3xnAzIxxduVOEI0Jqq+AaVy/
+0X7V27waFKK/csTjmk1KQ2tmiS30VJmnPWo4rk/CE1k9KxD5tESqyPRYGbLeN13v
+/WwSdGW7CJUQO9cAod/qgoftQ4ZzviNwLiohRRgk/JX7DdVWL77TYVoFvqj20q8v
+6KmkwFZz+L0Jr7zAcsVj1JJ2Z3sIOMsxUI/IbbU579lfrxWhWHF0h0Feue3rH2iw
+t/HbYlXSb/qUJGya4+PwsgFj851Q7g4bv1iyrxEiZuNMr9wJB3Ic1keZbYRUdNl/
+WlS0Zo5iS6NYdw76pkfNjrNalyyY3AGNEmXZ31u/jv9ghqQKsvEGdKOQmil0L0jL
+EmigS6VYaMUV+juSJxyfkrBjFHmiUwMnu9CuqDZleK8tKG4iq9K5newqpn+qeiPQ
+tk4Wka/m5pc+RaJfUEadHXmJRZmQixtvG5kmhKn63y+HPvqpPMRn6mODWKmiisg5
+rzs8c25zLlcMinbajj09DuzSttWQX7CBBnDDva8PwMMpmZKqCBAoc/YUetgDFseL
+bXYooS1KXagr12wpJztGxU5GgWPAw759fPrIX7rOjKPE4tukEiRc2oo7noFEsxa2
+CasO/vq1VG2s+uNpHLlNvBCRSqQKk5hDZZPnTUkYOePBifSB7IMNm3P5XfhMaLZF
+Q7sjrTIx53jtijcQbd67quLIauLDWpnMVxQswrWFd41Cqa7ajyWVMasXu4g+4ava
+JWRxR9vXYr8ccIEWPNBep7NRoPvGEloOE4WxWIu8xGR0HzWffqfn6YjOnUQx00Rq
+F0FRj3OVR+LYsAaxJ6zsoFjZ4kKwvp4nQPv3ZUpYd4pSzGJqSX3xRPA6y+u/fWe7
+meToMRNBo05q/xqX1j72qYfuA/XTiObU3j7PFS/aEWB2W4tPbO1lcy17x2kSVFqo
+TyQrXC3kYwTq5/zBrWXDzUmAK27JWR7z4xdAz5gx5iOKKsnHAUMPL2zI9jHO6NBz
+OqnYDBQSphipas3DVAyHHs7VSWBCdR8bbXIV3SMjimQ0nff1QxG3kR8RXWjV97yW
++Cy4gFT/BQHzwgRme48sMq+DdK6+7iXLQNbyZmVbkbBYl651STcdl3D1z2xBWbxd
+rBnrEpDH6oO1zpOAMAt2TtqUBH9tgxKZPH4nX3dY5EDRIcz8GR/Vw0ZEIDxLk76Y
+4Kely1m5HkSA0zC8xjsPpo3pShxzqcBqP/qxVg9sPSIK1fG4YLeFwOUmmbBwCKGY
+qVmhYdXIP3Py8c2yzwoMZ4sVlEUeMmIjPIsYoMGznZxAOUadT06o1BnEUXvLQUuA
+4PFsxGcqSiU0BPGw52zYfbTeXnQxMT1QaMsfkxL9D1riZMSFe7IK2GwSnTGxgPMK
+Trp7eZ/xqCZKsguBA89Ukxi42eqvA0sgIWPXS265dNsrsvoLI6BKbYHvDKPN6ber
+P5MGFgCHQeG4cMm3DCM0PW9m6M9FRAdWz6nyL5AYADqcTJVUEc5Yg0rzCmopqIVM
+Dg4JjwgNhpE7bF/RkqvzhijFSXp9a8EOQ4Q2py4cOOBhg/tPZy2w6TUhlGBPCgdT
+MEILG3XgImjf6RpKyA03ey52+Ax4/hZlXMkTyyMOEp0Vije0Bz0DxCQ6FYcjAsCg
+GlyTRK5aYasEnPLQ1JtyNHwSMh3D9zlFTfofD2rbb1CTh5TQNfoicI8SxRbA6Add
+DN8M8uo4bbwhjqgVmY24vVSBY6ZONA4ghW6s9fDmyvQSMv1qkdSG4pSqeT4YezFS
+qqgMpP7hrpV8zNwx4jrk7QhgD7vqEqRJEMk0GY9hZHWkHjcx+0efzebNHRi+u7fj
+AGAaQttnLDsxvbPDiOmZDxX5hr06gVMeG6xYPw1VwEBeIVOUI5cWzpyLyTJBjy/7
+UwTKeOjXPEZx9R1GliEyYqqp9ptX1XE7Oj1o3GSzIfmETNsqC+8idA4lXyTEdEKH
+m1qLlYg7GnceKXWSnXUJBe1TLLEMy25rxUODS763G+gAyJrnt/susS0LUVGcmEdf
+OOeza+ZPwJlGm6LRxwJCeTQT4ELlwUuw2x+tC6OwTDWuO4Y+f2tEDTVCemThcyQl
+W4saE/XW92tn0Zfkymphu2SdXwW5gXqVzp8oJGoyqPKPHUlz8CHY9JZx6TKmqhld
+j+tKNWgouDIt0BEuWYju3vVzj1cga60SgKlX5aUTq23ryvWOl2sJAyYJ7QFdaWTj
+eHcmbchjxbo9ESivO0PNufTfpl7p7uJ+3Jklyu75f5IEldaawtTClZqZOyHgYFBX
+bvNC7qlpEhV6YRBf0QhDFIhG+x02uB3MqLz9BpWGI8wKBZYftj5g0mi1Byi1Pmmh
+TLoy/wSa8DXcHJujBpnMJrpCXwwwXu9CnFiB1HIhkM3c05gwj3TFcIIReeg9IsRd
+6BlplNVZqILcQQan9zmfh/aLb9MRlGycvAZcsLhZBXFJ8r0Qs30HmDbz0gaCJD11
+5wodILtt9b+KlSDYkCdsb7M4J/LAGQagj54bePUH0wRVggJ37OwD7aco8H0dMxsC
+hAioEm2HPhCUPskz979/IMPmt8Rf7ONLUDAaob5n3uGBtQMCTchY4Na7WXAk9Crl
+g/PPdYqhRG52gdpJGa87hY9lyB4JvwGbdRPO5IQ1WusfpISVZMULWA3BnmM3tQm4
+QUfXjrXyYwqJbFWVN1wpj5JYxO6cPrFkJLpoKvx1orW7C6PAm8VSr3+c762LyqvO
+wk9byCNiMLF+iW0CuNagdEa7rFLYztD6/YTNxjB0HnXFE05Jyk/W0zwiP41R5UeS
+gjrlVeRM86h9KGB/8zhfolYlJIBlCyyT4aT7VD8OgUnLIiQqnVJoDVa1NgPWsuOD
+GhHapaE7hJB5f1ecFgjDf+ndKY2cEd07Ph11AJzSOJwhlxMsX6jQ4FUeix4JVkB6
+FGRsdo/ogyCmm+tu9oasxEVG2FfSsK3fg/qsHs20u7qq2bXSBTskm92jnwMRgtbJ
+YiPZHIp4DkdujVz8lSXQXVb4LvmXbHn/go66HRBlSIo4IQMrdHmyE6n0tK2+2uO/
++1dAw8YHTQrdVheO8kTSIvQwbP8vMeWcV/xFjofKD5R9BGPRQGn1dx4l9604XnSn
+xQ+Gv6Jd+UEj9XJ1risIuiK04loF6vvMa8pFv3lXxzYXP6n28xkwUjRygTDRNv8X
+qzl7+GjpL9V0tWIr3VQM2RU/0PdTLt0P/uH1IX0gYWQPtcTXhCllOTRfBgPCV1ri
+jRO3aj4ZItRa1XWvlRZcscus1txE0xA82utV5rKB8JVX3rd5gMo4f5T2bsybGi/C
+zM3emKGY09wCqypdWLVUX4y1CjRZOf1zJJCDYZiQiE8ExKKwTno2rE4/4Ocy82q2
+szlLcfZ07584urV1QTf83Ug5bmzA1inX7DzkHpC+oGDyTKqI7p2j1cd9etL6my4u
+/hPuE4wN7cgJRikYxvmyb2Bsf0MccthJao/pPYFDYzJ05S+iAFWqxhDdQwhG2Pko
+qdl4Li8mCU3OHL9HrGclKyEjNb4vmf/wuyxvcZxbw8yvN3adVBnp5KCQexozEmo1
+De7KwhV5XILKB4Y8sGkSjmj+R3x0P+70TX9xVc1DTCSX38t2oLs6fWkmiX91Pt2F
+rBYZ4hMRGmU9FKZgh7Xlt+n0ii8t9Yb8wSwD4rYO5pQzSjksq5CoKDrv7O74DbUg
+DxEDh9QWiqNgc2nY5aWcZe8JJeuKy7p9iZ4lwYNaxL2dRAUa8ymrVCNFt5IAIUVV
+ZK1s4bprtKqXYTmtxPGSH8NYOOa+itWUPBxhnjEZoJUo0AlS6XLB5a8PKdLN+yaH
+3fNYsFL+YOFJYkED9Soq2HGn4tWCwvzPjQr2ic5Z8PbSJKwYnu3SDtM6tVnI/O70
+KBk6mfL/RCcqaoYK9yShtXqSfL0lb2Y2wijVMyhJbHe1GQL8vP8+Uii+pUaxLhgh
+Z76B+YuMC/GTJS24lrFOpa4pFNP0hqfnt1uCOwMqQV2RcphRJyqUX0sPD7H6X6UI
+GlJiaSXTy1rFJL3RgMht4xOPuI2eiLPy/Qcomhdrk6ey/ifsrmBCJc9R/R+gfNRC
+4oEqGA3Ui+5VGBeTaehG7yMrNz6aLwEWa1TfLWV3GWDAhByA5fMgUuA0xPfHZXHV
+EWwTy+/6wwGK+Mxmbc+wEZ24D3MGOjA6W5P4dQR5JfHgEtnQ+7AZ4R6yzZb3MtVe
+HMFfKCG2e+6YXVtlo4BXRLyxFJgb18wIww36gSpZn+uF3olWC7Cy3ZK2oG9N+LTp
+k5z8HJ1qGtBANTRRvWt1q5JoJWr7KrEH3TS5ccHdQSPeopmmByynyVSHABBGSUcg
+skfxMQYmaJkjw0HYTP+mv+hMpzh/CJFb1wf+v4kxVidj+9A9i8Uqo/QPadyjzdpv
+y45RDk0mueXTWVYUYjtB0SVAEOQfTq63HADsMFFygPhzOAxVNCW0/ofIYaEr4uC3
+Ma5Szx6JxbsQs1jF+ia/xkDOrBOydhKuK3+N9dRKKAcJrUFnLY2PshcI/g3W4Yhy
+dTkFZqHkcsVATK5P3GhYF/HnYffNCZJsNH+u5B6qNw76jYkYBmV2LsgMHV49Qh18
+VG/FwJMIogCIZxfHpyY9dmgqBsvHZjtdNoWMmNo/YrAaEaLS80TItq2NTLkQndo5
+kQlW70x/a7YVrPgMZkzY+lNYnkwJT+wEaejPhEpqU9Cj4bUEyYZIibx06/6q/5gN
+Yj+IbhwO26pQC13x/RQfsoNlzhc13tAHWgAgRZwIgRqH9mQ4dKkJApo6QZjOHUNB
++YJVoNWWITMSjOPNg7AZJ+Cb1gec/BV9rksqjvDa9XMlLdYxdYrPiKaExyTrnmun
+LsF16qZ0j5PS+EOhEJ5DYarIA3OtR20f1/bYeQDT1EWuseQB9iI4I/tRilyZHOU0
+cycO4fr3abB/KroQEg4C9nCJgw+4hxjQHOLk3o4uyuNUIvqhASMJe0JRyIomTeBm
+DkResx0sEN0UYg5Vh2ENZjQhyOZNwOhqGJwYdQutiRxbL8Ci2Pr0craA4h43KW48
+AQXq8GJMyXa4iGfAJj24enj2lo6pzzxUV+e5FtnxpC4TBT/SECGa9I+TUpiWceQ2
+e0aZJHAX9ath9Q9LMbu5nISILiHf9djNxkBe2ISyd/V6ifKoPlHHtJWPM1sOl4ys
+4v63HKhmnELeDjEpXo1FokZ9hV02xe4FaoCOSq3qQ5qbJ9nY8EYIy4sslNbOf6Cp
+2g2ddt+nqAKlUl2MnuUN9o3ncSMqJ74qVDuzZdqJ8pQ9G5CjAbaj+gyENvyibdB+
+NEhlvdISITOJ3XYIVEIrp49D7Hh8DU5fXY4CCNgZM6eVTo6wAaKTz8RqefOr/Uum
+EfZ7LkLgnzp4Wo9U1GEejRz5VEmy2T0xZeQaRDzwAcFvenXHwCN9YS+PW87WjkRh
+s1LUz6i1T09ZQAjn2i36mBuLSrw9C5mhY43loTcUQvkB9XLlZCi3bgh741IJH0rj
+ssnZBqeFQUox8Uc1qpi+h8DrNAWV/OoLL6JlynbVYnrvVpS6Hj4eKrNYLB/of2OM
+Lg+z57Ag5OFWGPHld86MLjS9N4UWNrgburZFLulf3Rx47FfIxfTRfnoBp2iYF/CL
+Mq0vzKJa09BSDfn9WG5U2ggRQtj0J1K+wy3/CDBADcY+Wc/CDK2xZrelJ48v4iBD
+oijxkR1/ssAkZ62137IuZtJKxnO25D6LUxHb8f158t5ldR76WX9nYbrn6eEefNx7
+a3jnBkf0CqiYFvE3WAmHV0mvK5aAf94CRoHGNlFJtQr2fwiXNbCatzNWF0R5lEpk
+jgJfazNTgks87xidB4Iytjl2qLpEt87Z4GP5+No3/K17Pb82CnXo4JEzMrTYa+Ym
++JkoxnkKXNZxgPB4vInvKHwAbAfgPXYizRAHuXHTfufkHtHpK3W2nYw1Cdnp0SOT
+f6CkqG/eheK6t7cs2jDGraXVfjcalIZncaNn7XxqGaT/tGneyfKaJGZZfBLK6yCP
++ntFl0hZM9uMFsRhnk8fDDGEY4UmW++lSdbbXSeUKHwoJdkuddTaDZa1CKV7SCji
+Ts1GGJEdnhqlzcGQI+cC4SgIxJFPJSq/ko2v+1DmLpxaQKx+bDk8LD5TDH4wuSOb
+QF1b4VXeYnBt/LH1RQsmn7mKbDfuzek9nAY9KhP9nTjwTwGFk9CshUfpAGeaVNQK
+nJcgZv7mJCBJ+zV+tjf15Hmg2ccLO3XTCMRgD/AQqJGubEqYBRfPz4lIWI4iWCqt
+EDMj0XgdSeq7zCcE1iphg32bKhMsc8LzXVPaFNGkqmv9zVYIYLpzwKOsa2W4fhA4
+38UIduWnK56GDzKtGEKqWXMGS5eBz0kihAx3FS62ooLryq/ur9phmyJY2c6vigh7
+P8UjN11b9GReOc3ekO9/n5nr/y1OVt/lMCqxCFzxy5nsUfxcYHHMv35nMCyZzR+I
+wdT2h7raGuNzeAkGVUVTybKzDbRpvukVVdFS6yFRMquw8cFyxGnVitt8t8TsYscM
+rWIfYwZ4A4U60s4sAbG/DiWMhmCea2G7e0XWewzMuGYTIodft1awah10F+VH9F3Q
+ieUKTjRl612ZgLKuezbtK0i3J7TCpkS8vTJE89E/R/oRaHXRxbeHoNWYQo7wDI8z
+sh8Bo+cjZ4k3GizdWvbihep78VEx/FjS7mFDRF8MfcIy5PhkJKD7nA31aGlrpwcZ
+OVprZb4BTZCxhkXvmyGcO3y1cwPoq6OnRaNjdzz/NQmZekWOsusy1A6qOr2KF9/h
+N12wgv9y0B7AB6WS6hcpiR5TM/Zb1Se/+WI+gfC9r3ugSkweJexbjEIDAKIb5yhi
+TCfu0LyvBw6lndHG8HnLsfb9wPNkpwGBTOllpOjZMFpDOqcADQX9CBsXR9Q8zZAS
+cg9d6IvrQ4IH3kjMf/IEIYcGm0O12Kg3iY6me/qMbPncpQ5HJtRX3BZEPBIapf9B
+7rAlSZ6ZiZa2k6CFnwnJ2sswFHUTkILqbFJrFtgVHltoQgwqPur6M96N1v2M6ECr
+J4N3cYuNK4LxfiXdE8uGTyArHVVouzwwrxif+wbTvoT6nIp3w/o8QCiTlAA6LSm8
+KqeKelGlqJjXt8avVrS+vBXrsYd9mFOjvPx/B/TGSTGrd0Pv/R4P0u9ahh6GGBce
+YKWm373MPc2KffJoisKl31OGxcUMDVqXzGha9qeC4XE3RzEIPuhkuwcSV+8QgRMJ
+1R0WiR8C3yRmfgOstk/fs8YhTBQbvqPl8p78CeihrLSLWVqeazcLJNycWuxarxdy
+Qy22UJQSRHO1QHc7muLxs/pCMAeQ28c0RATQ6WSh54Pi3xqiJwLm/YV7yGuyoKto
+LlLBkfq4d2wvKBWzCGIZr42oTqXAQIr/NZfBhp5TjaHk85NhHr/NGhxCzTxRnMCL
+j2B+L73uvweQ6u4QQGdmrwfBrTbpMvuRUslBVVMPoU61EJV1Kwd4gyJuee8XBSjo
+VgvKQEJox6u3PCkJlS7QaQnHYk6gSUMr6Gkdw/bJ6PNTiAvwmh6zDMB4ZXDub1X1
++qLMhC7YEiVWP+jygnL/tDrRIBeZB6BeZG/qRZUG4JZvBNlNbr1WQGmiXTRW+fcF
+lAx5orxiDeRxI7CU7WZAIHPSScdv6UmOqmFCknrQMGO6vX69uUl2SqwOU2rEdbxn
+BaDRlTfuNTnvJOMcDK6/h1L2LFI1+y0+nE43SGAkzlRyXPgswXfMkY+jHDCJCLGK
+2QrFx+CQ9A3VeJzLEqjoQz0MIZv69RYAyitdrNOBU7TjCjgb8zaVNlEjAbbOnDx0
+XVjCYAzU4x2R9T4kZTUpFNctxVN/CmFOOg/QYrdcbhA0XLSKGC/9x4c6yDLh+GMt
+aLMals5QUW+oSgSsf8YQ1FdDPX1jSNzWP3ZCyOUUKSBXWuLMtIjPLBmeBkTA5DkW
+zB5yaLejYe3RBdJ3T7p7Y7rGcqrrJ+K/5ChUoM1Cc6jKpwXEyYyRXvVnihNqv6oV
+0af1+4UsW9FeNrl+Dvu2i8kpFIR8ne5FcCiPBuu0diD0+qSLI0aWMzTlT2rRcKei
+uRl7WEQlE2ADSEpDjnP9UuTaH18KuUq3PKXrqbcLaebzJ52xyY12lSXiCYtIS0yP
+mnkGJgZcYUQxNeNgeecvTejwYXAa4OUoeRT4QM+35CLesw/CUW4Ewgy+HnwOEhIh
+qyNTd/evTUiIvYDCMxGPoWlR57Xyx+ZY2QvTpDacJkfMpGG3MuzX+vItQRbRd0f9
+yz30s/8Uogm3/X7e4jJDfvwpkW28+O/OE/KYkpmwNk735Hg6xv7oYF3+Llixf2vR
+2N1Gv8AxjHjmzqRHqBiEefurNtqEJWBp+GSL5ASNA66XjLe0IVH+1Epo3VjRUwkw
+dsD28SRKTcOyL63SirHQNMfHh1tkd2qyZCBWpEnykwjG08GWHU4rtCp5dSaHNQpP
+q+eK7Ga+MQ5Bm0fd51PUNo25N+i4ik2Z4D+mLsVmocSvXYA5dqMJ3msQXwyTS4JQ
+cWP83A0isejtzH9xoXKIKbxYhOmsLkYvlWNVacKOBSKRlmzr3aFkWCRABnYtAEUq
+jqFIcSQq78jo4dVb0KPTeZy/4c3k3F8fztsdfxdGJZPmGqlEylOC8ORIzhZd4N9F
+BF4uwMQ3RseH0UkvhuiMZbU0p5FpH7+5RTWqyzfjvn9+MJie7S2vTq+SbMBU+klp
+FUamDPatXZT/eH1tHMiSbmev7lQ4aBFfeHkQpeCUZ0PlSUPvJ76uKoGLcAGagOqC
+vsDANM2IoOFDFIfpIAbOaFy0sOwStsMorETgQMKEcDlTdFL9WX4mxjLTO43N4K87
+7hCCWwxxb7/qht7ZjiKQg0hNtmMqFoCIx5MLl+h+Kom0uJMlFaDq3Ln8zFd+xhjQ
+MDEdUV2BksZT/mIXRYrTNO5LI8ZpXaOOl/hHEigV1furijYSPZligcVCvL7z2OHy
+ZtBW7c008Fat38J0Q8OwWD2SdRnZivNbsrxrzEUW0nlUkYYml8OhZ6hEdBFA+1Uh
+NS6UsZufOsfRgLS6+8kujlHWwvBniCyvBPzCUWx0ORRRGqDIFC6rWJAhrSkGEbX5
+R8aSgebeB4x+ON1lYwAif+E08ziupLQBH3Y2KaDh36rnQlHmSmD1XFmvmdTAwm5Y
+HCtnUZgmARxKLuvKqdhTwtOHOVK5VV4lhwsF/Jhr5jjbKnX/YlfeDNNa79AS6P4k
+RikvYTGz7zAkyvcC6eqU3aYO+ahnf6KSROrz5an0Tmxz18bIOnuUlmMZV5/zUvKK
+si/mWwjrtp7b0nQkmtX0xRL15EGQ0NWkEgHAPdbQ6Dj4jjU493qAMrx/HP7JuM8P
+ky1C7W+qVB6w/2Qsh9mfzLzoiYgAyjDuTKLxecbopS1h2TiEWCh/wjcUtORlu7B4
+8l96RkW0MYMgdX7NPXr90WCcdszl5KP369v1XNsY3p+LysQ9/Fbt2e2nTe2eVBPs
+DtSCzyndHTAnvS2Pv39ppEBE023ANwhMof8Gt7vosEIVjLb7nBX4Woy8J3JaPms0
+YUvwrGC09MlOhLwm4AJj/YGYcdgkVcvuqNZ8e6IzU/l0s7vNpJiHxklWRWXQ8jr0
+h58ffWb5mYDFnSd1FbG7nhwdPJd5JBG+tbJEi+ejYe52zYFhmW7LKIh8oT7A6b2y
+ylaF0UD1bBt5qn/+qT8r98txiLqHL1o/sAwMmng1NxL+4F76ie4WJRObc4TrO84G
+vhlLt65XZ7IKeVvTf++vQ3K0ygOy3oiQB0haoFjz6Dj0QloOsM3Fq7jK11BSjYBi
+VcAnmzHgC4SHsJv2YrAbEDW+ULpidGBEW1+f48kp6ITgy1DtimEQuVlynDSOmb+j
+aldOoRHgK96dUC9F/lMQw05VvG5PzuQV7NiMz4j8qjBFnH61/aHCGxI2Kdk/Qv4n
+4egsQ2us9hzjz2pn5xdwVknndfq9owGVqCqsrrlY/ft4go5cmjiCIhn94475hx7b
+wHwrbltM0AZLKHGGPWjHaIezVMh6gKUHdKEJmZBIjPNseRtxzF/BDi/v6BaYxH4H
+ATN3R2k/UXG9q1fzuCHcP79IZnQ9IE2whro4fPh8TQ3S8tIBiUJ4hi1pL1Yw6i4T
+fbF90xlD6y70JSqA2oDpvMeW9kq07D/CChCTw59y9pE64N0DTdb7xm46ckoojTTD
+gOVBXYWdE11fkzTFbIZNAhvJ0FaZP3cxIKfBStZFSIHmgSFfq65Ix5UjCqcwO5mG
+QgcykBz+ZByU8G/0qB2M6LBu5nMk8ph3EIaB8KYrOLX9eHhYJPGEDSxR0FyuIl+F
+Gn3DAGdd+I6HOTlVXHt9Gs2tc6qwcjWRNdjcZG1I5DmIyLgvI9IX63v3PP2ZPZBL
+IZ8YymvjjsWb10ES0q4HPpydOsAJNiS2qGzjFErIWxR7/BcAp30YC+J1l1leRLme
+DbF2744jmFRlYhBCDQ+0iq/2zv3jTy6ysC3RkJK22SVeen5Q3ow4jksd28MPkfwB
+jx7hb9pQTgrpONsEh4htXXX2AaxhJd50q4aVIWSHOMvPXRTNnukDwdsjarh8Xovr
+WnzCTMnWybdjlCbq9bN6xjQx/bUnthuuUMykxJlLShAWwhpE+BoWQeJUHs6iRZUF
+AQivcijfZIEuPFF3UP3x8bLN6empnH1pX+ANIw79RcmC48if2V/1UqAh3lwNsonh
+tm+peuXPeFWTB3UItPERfgI+6Q46n6sbChpLUriF6q+pN2P9qVwdvB0Jb0BCRxxq
+Ejjq2nmD80EBTi6P2C4YfKntreDtDyYNrx8BvyoNP2OILcBVimr1xOYTPj1f2USJ
+JgtGV+eZ8Jauk+eT5Yg3tKDikUcVV9ieeErPhXeuNLONct5pGGCrr8IidKB2EncE
+TWyp9tdBf36/dQKTiYMDqX/ina6pggy+5+Sr83GvscaCvFzZo/M3pyIzI2N/xGSp
+eJXaZOp7NUZ2dmMEY3YgNKlH4CU+kVb6Rd3oeUq7cBomUYb+a/hdA3SArRPOKQ39
+9EsojRCPghqAphggwBECAuvRcakLBKfHd6gKeNMsJxRWNRzIzyZc9fKhCDgSOtBC
+GfnJBRP7rDcjohLnFcNI8VStOiA6V4RwSL5XtWdxzb+crmNNv6Z1kATq0LeOQjQT
+Ace/LY2MWLY32iA8GuoEIzmNgwNMqKSO+MXLwMugO4CmmhErIkGRO2wbUWQcbvzE
+MtC42JoZWtwH7+PJXFMooGd0QqAVusvynQ4A7emA3m2cAFWUDlfahchQZ2TA7Q80
+miVOSmXsEprlpVzDpJ4zp7XNy0xA7atCmeBwOueJV9vBAUmtazj7BXWIS3AQFb+z
+YKCwMQju/HnBPNSy4lwXupbGSekRgInLz/Jx+MuctyQd/OuAsQ8HizrPX7yRX9+D
+wkdRjC7/li2AbddRIE089ELaUCedClo/H2PX+gzuoNwnTnRDYbPjyV5ygXGPS8vM
+c1RmzK0Ndu2lG7sy8pTt1rqXaeFem0Pqf39rrZyO8TLpgiFOakwG6bAC7hoAUNig
+DqjYfhtBJDop4/ycBlquWVA/yFzS0alCaMP3ZraOyLE4U5W0BjzUqh+SKYN/WXpv
+HF7YbPgQi4q+rXOQLJv8LMFVPeG9Og5uswk8nkHAudKVlfNakkqAiZkesLiXBkTD
+L3swX8CqIDYOzHVBi+3V7MzmNfh/RJCmvdRDQWDgokwSabtf9QRIaO2TqoGr6f7x
+oOytoHPjZ6OIYKy1GHxZN2wjc1T/Z6eHso7xHIQXPp7nd3qy3C72MuNujg+ZR0bo
+AhsD3G3XW21iUBdOHMRN7xNImoeepC3YbKrDL4TJd3fliNbK2/vZ4NpVmwusMcJS
+4FfKFAtzgQUPmsUDV9yQXwyRWlVw4MjguEm82d+sStM7rVv4+N+BWR2Y1CGXqWxU
+QNizXe5uFDPNc9fczV+t3G1f10XeBR423dXNjWvSOIZ+I2MMxsJXH9SHTAlzdfyY
+TsiLvcFWu9O/Alhlhtry1qNzESoAbLL99A7LOwZG/L8XhBBEs006onTED8OXpIPh
+GsN8LZHU+MBuXXFoMCElzmuRz3dgfDVLpuD8iz6DnJB04UUEx0KPc9LmaLfTQUNs
+fS84RJEpQArVmtv3VlXu24f6FHexY9G4Z7THxMsfOaXvDL+jkuJyul5ZFyk2LrFh
+MNhnXsCztoOPvriNaCyEGBGdlFN1fvf2GWFKhUnmxqG6xv0flrqYs+xV6WOevlC1
+J8+VXfqqkzJCgldOY+prm8mBcjNNPDkaMoKuYQZ7TQZRCfPN8a01dAwBPmS53tbR
+r6Yr+bIc33VHJF4wW3c7fQ9j6V3Ln2I4aLSOy33rC2KJDCidekJlxbJxFdOJBmjO
+cR78b6Ba8h1x4Puv+Ha2ttJ8Rvta3GcndqZ7hrQgH2dehaz3LK2NCfw8Q3Enhidz
+kf2Ug/nNTyb8Ec6JK1Hq2muDYHCOGUqpiNjVJoW+d/A56fzjGjtybzu8QcxFw6p0
+kTzfKXfkXMPjF3IQsr/uURNKx1/NqgrVD9i5RMtBHR04BuysteRlM2ENQEuomwVD
+fUN47SI9zNBpLluRN3EQmfUQ+KbEFhuCxq5/tvNbDPmO1o61sJC2gDSswoOAos6c
+PkReorOC6Mm2vG7FXoW5iKC3m+PxV0LRLJVDvHYft19Se5uTYxCQgC46/EfuSUZ4
+IMynzHxIRAYyz0D0jBEkc4Ts6mHiggFVvPA+yhgUn0Qo6CdEe/nMNH77kjFpSjTE
+eEw3oW8OHYq9Gh7jMEi5hJ6K2xjQcCbe8DEmdgbs+Uk4UOR4pfalFHpFo1QXBJ2U
+271BIa74bFYOJfW4tS/DFt80hrYyeSw7FkF+QZ6hVZPNshh/8HYJX0gz4gZHqMRg
+fSbCMqrK4hBD0dWF4L+AVymkN6YYr4JIOJELyF2Bb668tZfmMXeejuxK/NZqQIoK
+pq0EkQ5sBz4VCTVE/jUdP110eoO6kkeYDreBAJwVxNfeY1xMT1vo104UyJOM68zy
+0FnJK58tj7PGhYAOvIZaLUMQcId9bvwkiEdlhfGFZ3LuQlX16iwpqaVzZjGY+/Uc
+Z18fIzeoG3ETzD6KUy/xcBJI10oJHuF5r9NExp6tooebLX/SP94nD4DUjspCDS34
+Oy/M0FQu/XzTZ1/AYPa8z/Z6927sebZYKChc89i/cJbnD0edB6xe05ZbV6VkikJN
++WxJXBYOuiJyba+85bKGri0SDcSadSw3ijXqzS1hxR/EL4uGzNqgHh/1KB8NnXQz
+ijODF2wgEl4oMQF3HgCv7MW1xP94+MauLh7aKhJaIpUm8hhvXbAAUdbfXat8LEM8
+5FYnMs1TMm/JjooUeFXfCbVX4z5yaMp1KbbMEnzpNayMo/mBF/+JREBZSrgacNol
+mmbDJJkthfJHkg/ck02e8A==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_per_ping_pong.sv b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_per_ping_pong.sv
new file mode 100644
index 0000000000..e99b010e59
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_per_ping_pong.sv
@@ -0,0 +1,291 @@
+// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, the Altera Quartus II License Agreement, the Altera
+// MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your
+// use is for the sole purpose of simulating designs for use
+// exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 14.1
+// ALTERA_TIMESTAMP:Thu Dec 4 07:39:38 PST 2014
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV-6.6"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+q3/pUdp1d+/UmYZ1iV1PVJjCRYIPfoOjEywqgWrqC8MU8BxCM1OCax6t1+3bz6X1
+4rJIACZCv4IMG6F4DzMHpYymMWq3zEPb5kdSlTbO3lyoO9FfyABYPd+PnQr/FVUD
+fP3ojHD71NTgus9nA4NpjraWs8U8KMMgw3SxwHkfSq0=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 12128)
+VWBFpx/Bh+AKKnzuIsu1+OmMUl1EPtLxiXDU6utUeEuBeKdpWw6EqwY/UVs8nNn2
+W0y7S6q89j0Kdy6BH93hmSe2iw8zFI5sjGQYXsJxZzk3WVj/2xAGrdBkBB/iokmt
+ubQxPovdD8/RsjZqu0pUlSrs1w1gkdRT+m2Ay2OHb5j7Mle6OLFGIk18ssp/Aj+R
+oEFNkEG9JCs572TyGm2tm1tsoBUidKdllyKXvEERDMRHhGl/mN2YCWs2pyUQbMgX
+dSG8kf79pQRrH188AKQ1RNyMfQtEFyFTPRXYBL/O97ojOQ7a2M7QhTORbn7Y4lVM
+nu2W1LpMH4nI8QPORsBfFkeLUNeY2DhnEEaChMLzcauCSNRlNBXcUZHFCHMXONjj
+F6b9BAvygH20bhaZz8pj5YfQSSEmsr3ydgkpYZx0Fz/Feu9o+PiBPTBCrTbXaxzM
+jLToXdQ532KfBqNzjxtXk5jNyRi+H+7kDDmSqsa3emtCyo59QR1hGZgTPg0fF25R
+dhunP+68MzCXEoPv+X8xexMNhMk1EEXPajJlry1OEXLoccwj03R+8R+62654rIzA
+1xsUKNiiOM4l7nVqndCGWX0nwb5V3x6xboKXzUayzFYsAxEa9AfXukGrA9KdmnFS
+1fXsmPOez21id6DAGgWuv4TeGi79VLK1cBldXu/Rvte34zhsLcakIdbyCwo+Stv+
+BWaSWxDmUASBeZdlAlzGqQ/Zyyh9GQwRrlMsibRWmI3ehw3mpYIM2Ijw2qRi12y8
+/sWEPTEvHksIroY6JFhR8yyqmln84DNzwLjtPXCrxkw1thRlNWuaEnLJKnD+/efa
+nhcQ+LsT3Ql0LzHu3oZ0fnxOn1fxfQZFWhqRzsy/nPN+CdHSYRy8wupIDGsmwxPq
+o70S/T/oz1dex8XIYr7GtOoGQSN2w5mjIZcO25TOiFRMN4+/98b94QfC9DSlMH0P
+kbmpJnGk65+HlgkkdwhX8zu5LEx5fObcU/6TIkwGOP0PBwUw9nuu44ZO/ZLWhD/Z
+6K99GOspqTW0BDq05AoDt+gqUEYyC/0gmNjzxW8Rmeqi5++oLS/sVPRv8xIqlkUz
+COFHfIsvkV0lOscD4GUG1Wv3c79r6UnET69/IQWg9TJ4sBV0QrERwSwcbaFSs717
+TObnJi9y80R1FrJ5PfFHiZ9uJak972cWC/KGqs1zUn075SxFK+mZLjwvHJKCilRN
+sXBUCTHgqe2eiJo+ZGCHgONX5uAEri6SR3e9XZH5Y0UXRxpDsfi892aUEi2KzeLJ
+kiH7+uOwIskfS7q/LTmWJuCs0FrD0L+s2eO4+/cMHOLWmMl81P0RZUVvFTCmkYa3
+5OCFW9soWoR98zR9GR1DC3ljo+BZr5i2Fkn2ORA0jUmNc0Z8aYbrn7XaCp8lIiP2
+bHRh0OX3ZzpRXJnBbu2IUKSmL2UgIn+tV5Ap5gekLjM6YV0PnBsWcm1gg8SEQAON
+nQCM5yISp5YW+kPMZVqCVMA5/rkYP46f8lABwpeo4P+m72ebqDFH/Fa/f3euln6t
+Tdu4R6MhXoC88+Hnp8FNXXVid1mPUFGJrhtuKcMNbCFyZgSsDjSnj4439dzP8cYS
+EDFBd9bGp1UU3zLndgJAkFq+YFvvTrbbt9z/8BQ7Y7mMfMNzBBq36HaDTrKMg8fR
+bB8SrXFytaGuiU2G5c6pT/fMIGSiDHDEZ1rVY4M5bdJ9wp1BCenmxtartSZynVfK
+QK+ujF1KK2dOM1vUzmrB7e0CiInAYyYIzAraxlRyo0n+5acNW6vEYEjSbV0NduCr
+0PyJQHmHGbB3XTaZgb5cChPHmB/zc6bCxTLSFpOHlpePHcQiXASYM5CdWG1gngxz
+P6jZOAj32gThZhcgxMvBui7q/biUpurapeux3EwFhOfGy2TfkcgqJzrwr8UsasJd
+fa6uKzCXyBEJx/A4DeoX7GE+dHoR9CIXZiGEyHQPFuFlK9POQKO+xCnrRUY3ocoD
+aIEZVKxno0swLhwLkJEYTZA+KwKU/wxGEkoxUKGDMxNByl9groPwzvBJthVhtHt4
+ghj7euFUmp+Uqit/DRGCTiW8fs7pXozTFI1aUuOheQ1xltB5/elfu1XFUjzxORH9
+MPwsIiEbwqt31DR7ZWXemFzUH9KIYoqHwPIUhvAQPPxMUeB5MtQXUgqMNvx/p2nC
+SV0JoGfVgK+7d886DdcWy/csMghl7KAJ7ad/3RqoKs8k9uMxAz15YDzsCBQ8kBFk
+N8cpDBgfba9YDsOh1ac8ejZXrhauhqsiFP0fjW04d7CleKIo1ozV1MJv17CTmBtR
+aPEJ/0JEElCzJf7gy6gRGTiq4aAXs5Xe4WLIZP9f2gdc9kuf3Mq5SluARNLg16t/
+IAPvI+Kp/nl8KLZRHI4wof1QqZ6tON0X/7Lhe+wHm70DcX+0+fKlRicu+d7j+s0K
+A9uyszlqkQqCjlMHEnRuhP5MA8DkdMS0AGIU7idKpovg1mtl6HCPNR0yVs5BJfNg
+YQgY905W0i1mJUKP6zoDTkBTSGYgmZCLIkXsNlMChAfuO1uDjvBdgg5fwLGe3KT3
+VJ++QSC2hc3xbIaAVkAxJqtFMjWQkzgch5WJIGRvxYIiqicf+BH4hmRY4EPrIaXy
+2Cb4QVUiXNEBmOi+idZI9yf12iJK/wWLg9GzopqWY8k8fGaWQnkK8HI5nuxdbdmy
+CfZfmyv4JhVB7l06oUsbn/gkmU3MX5awp+QIjZ9SBrCCvn+3x+Zj1v0RkpPdYrda
+bb6KN+Gl86wuT+eiIVPZZ6pUGZKbqJGEUU3kr3buGyZ+BF2Qgi7HAu/1TGpkC2ab
+bCe5fnyBNzPRwiJpU1ig9IIOmEXQrZKYTWJbVvQgNzlt94Mewixol3VJtPXpguJt
+mQl+SuBzgzO50vFVIpL5nwwFgS+1XF29CqI8lZHc6S48HIKO6amu+G3Q2Jc0Rfwa
+P0c5zoe8uB0XOlMyZi7nz1jRjwSPtw8qszFZF6kfWB7oTiGKEZdiSWijao+gC5Uq
+lCwBn09XP4gypN6lmC9AeXo2GyDfDVIzfs0p0RvL51vrvI0YJRfHu0yEU10xi6mr
+jhCwLSQYPmsO5crvk05JZSK1+dgYWOi7ho6EuWrsOh0awknuwXW7E4uWrAk9aBDE
+LusfpqoTtI7LyC/j+lU4kNHGTwo5zhINcDRu0uye36bPNw3UEgvkq0IcBF1CG8AS
+7GLEuIdw688U6uorCA7FhfRSSZR/JJDG7wqgQArlcS/FeG206ko+Ahi8LUh6OhHc
+4rODWdHVEH2qJE1SW0wjL42TMLixrTJm9uIXCMgxMzBGH2O21PtXoP7kHh2mMViQ
+dzorZgog8b5CaElxJECuva+d16uOjAQ6YpwowhCxOmVu29Cq9ZXsPMds7IVIdMpk
+ZQcCIBiOBAnS3DBncOZH9VUgh4ViFeJwArQ7FjDAd3RuFmdQIRvnLfKzAOxWVcDI
+Nk0YCLlfMKuJawntM/oOoE/fULwTn6ILp0PVnjmAcDlmf+vHgvEYVb18E/PxsQcY
+EP6c5s0gDkWK0BLmzmd6Ox2yzXDFfVMdRUBWLV6xyZsZ08PehBzLnFXYRbPj6KfB
+tCvHv8hgMT0Y+a6Fhzjd80mNsFaBFji0cNRc2WF1/zR4KBsOaOhkoFg7vFFZi3bp
+ZzWRcPIBIA3OfEYElfT+EjUr14aauv7BlhQvwhDon7ciWpmJndPf9F6ldgZmnmRf
+RLeFsdxRPzLOVU7COPo3s4x/DNEvfAyhgVrx90ro71xLus8ZBeA0NFyCvKf5OOoi
+TmZ/K8zzG25e8vQVvrwmfMbqMJtCAEY1y4VcNoSCcRuM4aspdEU+Hh/yOCmC/A1q
+vd0UZfcdszSp4NcV1PSKUxykZEXgbkW0Z/ZbN+15nzmOyTd9zwMVEqTJatypVQjV
+298mxupC5k5aaaON1eDhGuHJVAJEPLOMfgX9yZ3bkHQR6lwE2PQMYk+Qm/2i5zoq
+aT5mVNpMkZJ+9IwOkNnRt9YdPZ2aMn1tJz+3UTSkx7RlxP6+LjP4x8vO8ugLN26s
+HRtXv/zogMGmCTFV7+Xrh/HdGOWLZuQnzv2ogR6sUezVfP+rjeOUs+EPyW+lUetZ
+pqCZkwZJlU/ni8boyAn7H0wXvOSbsgaby8fAx0QK0El1W9uzV4HBPfNGwk5nT6Mg
+CQpLfLbdvC6PRrKKPtvNI+OA6ZeAeWal392SG7dDcFSatoptOZpxfTlsbObcxWc9
+WNEeiLLfE+R+CtTYgQuoKnlgn0oSH0rhWwfixKOLG6HPkfs7YGJP9rLvRVq7Q7M8
+x/YToG+Z20m/NvfIGBF657rIKcZbQBuuxhCMgFc4sq4EaJNWZM5eqpcj0o04zF1v
+i/VS2TwL59G4Sx+MqKMpR5tOFLaI7+oQAHsd/GHRx2ACNyHxZkMKUWSmmZbmpTzZ
+HT3jzEn/p/5rz3V/fkCZ4doPkvJCQjDfHwCDnKodpXPGJ3l0wJ8kU7LtwnioZ65X
+ryQok9eqkwB8mh/mhrMgEpV9DtlCkhoGa1b/BRP9MHB8YUB6ek+k7XPUJMMUvLtI
+HjAyLjRfCY4+AV/J/rIMbDp4tKOAMgRRT5mDmkE5Trwg9/vvL0j1tY3bKf6OXAqZ
+eudMZOBomXn+S+fLbYnDPjTwjoUku6YgOnxZEvmWIu8fgbiNS0Wzycgl39LPmq0f
+KhujO4PQFF0T4benrGjgpwrivdQRrso1uH98l9GwSPhz8ggpoXc0IwaE8F+U66Pd
+yOgqJvFj3tCJyKlpm/yYh8AwTAC4nZSkKO3Q3adC8L8dZKUdzsT8cy4jPNbHgbOJ
+Pb6wYAE3S2pQf90TJPR2KYvYaHNF3rS3EV9Mf51+q6vdQ9WyYX6bS488wSAd+Vp+
+kFwOGa8+O9l2FsHgNui7w7GsBIvjpekA8RIXOFsRFfV+66abWRh+lH7JTKAtA9HW
+RjET5vO1c9qvIMhyeWXail4NDrIPIdWyvM5+yW3YiDqeX7rgC4JLou2d/Dl7vt5t
+66zzW/USXko9JfQKEg+KBnVGQu1AH9z4m6DPWGKdvnoSKzgwBQo8EHYBCpINm92i
++GJipBH8o0hcvU0lar89BKMT4NEu6ublT3jN+MmyOL9vWmaRiYrkZ0fQWK5ZDU0r
+6V4r3HauukdJsGSKHxD+gmnA2BXzHe25tbC66ZbRfHyZyXzW/yLIzwj5E7UqW2Ov
+69LrI2IOhRdz52zvkRcJMrWAP95X0S5PqwyVbjKUtUorMEOf3LzDlTxxa13NXXpI
+UzIT56Ai85XqoW6PSPOD+4pOr0L5U/JOeLR0bflZe2P48CXidTuhp5Cdw4DHacXl
+xqx8qNJilLGA+AH5SZUc2DvlXujwL1AOzOw2C2ad7HTAS3Su4/WJZ5gQwkRkErei
+HCT7p1eTPVFMgwMn9FoNTu0gVs7uxXqlXODoBOEummph8qBBb59HS+qy153OUq2P
+AuC4GvO0cPQhgzD53Gyax73L63pV0FVHbEKrMO03alrILvK/uKxfNH3zXHnzYP2n
+FdFFPof6iuzNVrCQgxlw6olCR4KADdzEpeo52VNBcH7MY3T9ZdcpABLMn5ID24xd
+TeSGGVoa+bMT5Su2qWyFseBOUrOauddU3ceECR+ao0wGb8NR/LZB77g60VyxP+XF
+dF6UZPIJcM9e+sMivApwebH+vjBsJxVi/8sU/+uoR61AhwAms+0L1qdWnXhtu7/p
+PQCDqOD0Tx4zE/zpxRp58f5VDYrNCtQArSRrzXCSYiV4zdktS4lAyHLejZEb7P3r
+mFvzQ2zOLD0DhOYmDFtRiJdeeMeVykA7vDyRvSA+Zndbod0W/Np55oyRfd4ERhtE
+uRXUowHMs0WHeNIrEt0LOgtFXk4xFlOf+LXh4KxBs6UdbT/M4kwmim3gDKBDkq59
+e87O5KfxW8FhdpE964l/0VD2F8nnA4/dBkB17//tNyKN4aap9xDhzNN/qlM/7qrO
+dOmcabGDqbd3H09go5OIbUxvaUnpR2SbPGYj0aEuyOmf7tCg4P507XssQU7iJc9h
+0g2XMsf0Uv9h497KkcXqDba7N7hiupD7hZD5On7C8E15Mi+bVjWlOKgo5Djw4+Nl
+0QJd4D1IiqskP6Pj6FU1Hk/v6UKyIqfq9048VPhLWQcqJ8Dylt/JKBaniIL+7DnA
+w5LFuKHCflMk6lTNIEAMPy0NuBwINgrpWQtu10YLvOamjJZmD1f/EEaeHqci4PRW
+9+pNSwuyzEX8EUGhaKhzlgcr2f4zV68C0mO5XDXZ2Sv11wo1WTtYc5Ut4qOZV9DW
+2UQgSR5dPPRk1cWfwbwVg6/qc4v2Nx3NN4Ik9GUI9zo/eA1TxcIT+PnfwVH7zBhP
+Ded81TIhAq8BgFzDlcH3C/drVErA4hnkZJozMztkD0A9BtishDLtdlU07V/0WOs6
+vtS5YTtuFynnbuYSEVkCumeBK3oXMHjMSlx3rSEy8xisbcluCy07NotRPL3ImwC1
+yKHuHJMLP0GRffnbEfERP+A57QQhk9//uB/mD3dwALWxM3m/SbhqaXPsEkb8+/er
+15t33oWJsixLkUUFBAHnMTPOhZZAncGGin+7pZHPei+ov5QlCF+ngIG/SaSi7Qpc
+9IeO1IALoppEiTzuPwUrBRMVhs8lzHOAmYSLLFLMKi5WegjLuWgsG3Xhf3J6gJIl
+gglO/DW196rG+XSBqRxwLELFsOcRdRjZipWpGomAFT5kn/TXGGIzKgWWI+gasJpU
+EZQqaI/jZP8SRI/b/kVyvjweYWO9/EKq6XNTiwgXppllMrW/rnDwj/RbX6n1P8wb
+aNsDvDHrrR2eYUf0JcdrFeTlV7KfglHXYwgxPVAdrHZIp+apxigQfmvVZ8wQREVo
+5NKEJzMJ7fDTiTa7o+EYyRV0FgHfW2yULz29/tPZVLVEz1cburWqKbqsaDtc53Mm
+77is4/Kv5eI1GCZSD74Mm7YL5oqGDrHH0ncQYWPyImO6tF3qkWiTGgk9uV7wnmlk
+sZFKRYOtUJ57uX0Pt3WHOup6IxpkabQGkirEUEmFOXovMeLgVNq4Eqp2HauARrau
+7FYeTWY6iAqyji6GVK9tv5RtHrbHdlCLT19SZXFID3frdG682MRkFbCBVVhlJtd2
+pctSLtU4wVCRQrEiBVFAK7CsbYxrcnF/DYwseSctldoSYyS+dMslAMIpxSeGXgFG
+8+2rxMfxYRRXGL7MuQMdkL4g7M+3WrHUGyjO9+WElHkf0h275+bG25/lbXfP9yCq
+nl4dy2Tx6viRnGJZQ/qeV4JiP7ACwSmycrjV7PkbUm2bXhfK7ByhUt7In3Q1Ilg3
+QCnqUhB6egJPKWSQinvDwMh18tlei8VsNiP/PaSyVxE6U/F1t75KqZfdA41XaOC/
+29Hdl1cdypoNeJHFwgCe4DuQWNpqWuKsw1XrJvybOs2yp9ug9UzbrvxW+6tE4SAu
+yJtA+ipnA+JmcSy17bte7MVFZX3KFljme8lcSE2rxg7u/68AtTzNCwpG9D1lRhe0
+OCAakpfJ2lxlmQMJZkNcc0Ufx2hSb3wIvNMjaNL7UL+/jEEpBqiaJS92shsSnQba
+LzdjldXJIDskInKxUzeH06fJVJ1Wl2jUvaIJFv94EjASr3tdj5YEfzIYYqLGN1yb
+zQujbPbCxS89LPC3+s4f4a2hHZb+80bS071oESLSgPDZUL2f1nijsb+qXi8xWf7c
+45U+TpqbOF31wFlh4ue7j49I7e88zWtjIXmiVGiK41i7iGJKtgOEa3M9iI4ZCxbr
+L1DHCk1jTHxwI5ZI/fyk3HkNVvm23Tm8JGz7Tar6z8yvVstLdz+j13LUcpBDjs+A
+86BaqiZws0Lq4jrTPBdDbHePNCpKfBkNzgvSuz4Aq8zY2HmAye0C+UDCWlRroUJG
+szEebRVlROiZ5SphPjrFfaJaWrw8G0ucC97Y3m5bGuclaYcYIZ33xrAMkN3uJvfV
+GVzdteqqwhhlvn3a/gKeKRTIOrbaE0fUdleUXeNTsXyAShCBNcHhteFfTQA1j+E+
+WcfIYUAkbOmMNiolNS/RzSzylxDjbG2y1J1ZsR83fApFwRHCjAlQzzLpLfijWgrW
+0Yy8a2pbWjtYWa1LA9ZunYilr5XFxD9/4avNlkXgwJNx9yK7iizRLHjCL/z9G7mH
+9LYMdGrtILfostjzHe9OfCVnc8z+HqdntG9uD499bvpGSghF7HweTuJ+vijJWkQ/
+rvGzEay+pIbabWqJeEH8a+pwW6IEpuC5Y+uExjjd6hiJfVk1pazYB5N+v8GXjC0/
+LX8vKtRZvoYspt8kXBoswmk2BqqjVdET6Y/xcuvatnBeaxxwFN8OiBCss5SZSUGV
+6paD3TWSiyvlYe3Uzn8wKWE6RuxwxZt+WDjyWQSQx+IVtTkuqVWVBROcS7zJVPUb
+rAS0e2jtS6tw26oHf9Avvh2QkbxzdUrcuGqLKJHmDgqAEglMW6t+805CCmGlWkEC
+OOc9rNStf2EYczUqrSc49Okl/vK4y06syyG82wwhcBL9rAzlcXnXmJJANCC/vRBj
+j95W1KORXpR2ECdchLG9FjHYOtuRgOvM51MszKt6jiZGJpc5TLXcLHcL/tKWQ5XL
+G4SPkXIyol4XS9S8pOuux3ONTSwaWGC/AoyO5gAv+ulEya0EvM2LswW7IpB8N0lh
+ZVHJF0mSYFndRHgEANBjRj5JY2WHhvEsqrtCWPEqw7ZrWCxboZDNwNbDPGjXwS4E
+Z7a0TlS0hr6FiJM/uvi5VH+lx6bXq5nYrJFMLc3Bcx2HiufZkmYnOrwPk4S9mSYg
+QPlYDZ1hqzOSQYhfyELHvBHoFaaD7BmVQHP8oCD/ryO/YLDrLZ6CNE+V15EziFcn
+xsJp0L8ep/3+7F4V/j80W3FtND/y2sBDEjYMUvSxq42ke2rnxvsMD2Y2vJuxrpX3
+aqVpQRXUwkdFVfB5A/N2sYDFgbM05E9muSr88I1O3Fh5wdhmvOnpIHbAzzbZGZ1B
+KmPIHYYIBvXStVgocudqEIxcnry/7vqPb9OXnXLunPeYyN+svtu5UKey3t14eVwO
+aoUVp3p8uWvzt/Q/hyMK0Gt8Q3hc2/HHadER26doq15p3POBS7c0wUCbqqu9t5aa
+en08LlVj8XPUHOdV7rrOm9iLTkci11gMC6regQE3aOaX+d6Rkl6MnQBqBnuxw7a/
+2ecAn+mSe79fnW3rUW96xVPtWH0x7KWlJVz4OarDEbd0LZtKdAdR+5gDppAuyyTQ
+Rxbv4uI00PH+Q9/8/CyRnFpLdsVNVzAcySuYzBaswatXPWDA4jsd6zeMtFae/yiF
+6JoKi8O/aOka3Fy32O9EaPALJ6SRYfsmW1+AbdBSoeJ5G+divwZDfJ1gRBMTbmX3
+LoUFbWC/rxXR2rkaP1Yi55w06dOLboAH7UX8tTL+ExgoPWprgOmp2ajGEZsnBcNy
+337A/4kXNQkg/HIPBzdG3kqcFN6gTFCZx2PJlXMjrUg5XUDSMI2zuJFi8ekQIBnW
+o/JlYcIcb3TzbFlFqUBWsndxSLcu7v+SqfmIaIJK7LubG2JxsZiN4xLKHNh7Bbs5
+Udu8jKRM6WDzcPPJW1i1oarkFxbc2P2N8gXixrG9c72TjNhX8YEVWuvqust2k1ZT
+9ltLNp5rFnr9L1D5rwD/jF6kGsGLnycTopB7QkKJOdmxcOf6axLJudKt5Xu5E90f
+PHJ8UNenpJ7GIWzD/0SMApyMJ+4VtoTHBK7UHfUu/lsNFk5RCdtIIb+ysTk34Kyh
+7nX/a3WLaGpqsC8dkR9OAFzSiJrXNi2Oc90A9or8eKUXoA2jVcr6PoHASyaWUVin
+x/suUfZe2nnxgRIQNVipsgOy8+xXfwA7llHuG/sjNIH3QVZJuhHjPdH8aTMYpD3o
+6Si4ea0h1uZJBTQhplXB7osnMkDgYtr9pEmbl4vC0hM7PzQlEMGYd6rA+SwP+niR
+/kFKznih03QWDl324TDh2Vzwdp7oHjB6waaczthQ3TQaJs/xYvV+O5qwIcHoDqe1
+Cm3C7/kMdcNCC58oZ71A0+YC0PeJ0Mm2ybWCVE8EuYGD/5OSijFmzsmtxjq5yjdW
++6hVK0/JUNYQ14JnyEbRNq0BM+BVSVqJGQTT4Q9vtJzdV6MZpYtOskyhN7jULYVA
+A2l0MY0s8OjYFxIrrUR4b9Oqpm2/avj1mYDS2UxtxU3T7MBZkBZ0SPlRzzpSaP8t
+2pQL1bI+pCVLvJ0gtOjXpTPIg7cY+REv0JleE/M2Z5PIN4BIQIIcVG0vtzbwyegr
+DX3DymT4xxiiShHzvhV/X6KjPHOBDbf/PSd4RSAVkSoGcjFntdOaz1i6qJhHuPoq
+ZeTzHbfe/ucd0dRxgZrHSGE3Hmu6eSltzEQSYTZy5biDJ6lIJuDH1pNrfpx7TC9z
+PiEWSsZkrYmmD94CNxltvyF1qaHYNqDFQEiqnFaMKJGQ7esHDD8qSrqweHa0kgmR
+SXNW/2g8KV3jdGGdoX7+ugG44ZTY94akUzDpRC1p9TW+ZcmZfK5oY/8HDF8DAXw3
+zDFyc9tLImWmVqeydoh91iBOicMOFVPMTiavEX46jH+m58o3LHOHLmGQR7IH4byD
+OgLTTxLr+qcOlTGRG1BaI84ofm4iqxaSnFsloaeX5J2l8otm9sMJb65+vXBDeC52
+ph4703qkHfxQl/ZMOcs6WKPCtiRv6mhK3yJfH5QbFvc0uIVN+adoZvaUUiR9Q5C6
+sI63SDPKLEneqz28HzJVZ8Tx0L0mh7klNW719hlnO5P3CgLXHFPpvIjwJIZlvyw0
+CoZEWcXcaEHXZ/GupJUf1aB3vuu6A7MQScAScG1iLleCNMUzHDJGNIn+ZqTb3mjs
+PzRGgfQ0XYEqqboLfPFpbeJwxz7fx/ru4mPcsk/6tBuuveQBgRM+GKW6QYscFh0L
+yEKW+phvtt6iYGIUsnHD0YsStyVdtgCzQ2bTaPLKM59Q+rU3ZwMRw8CPnmoqG/qh
+bvjrKW8viaI0ka8C3tc+6yWVdylxsRf/mPsTqzrDwsnqtDLCbLYa1pfz7uOTKQgT
+ex/glfbGumgbdVkut9islXJ5p9DhMRSCl6SiTVfywDlhA5r64gpJ2+YnVlcw4eSa
+8L9vzHr6WjwSYY7Fw77LM8IeJtQHHx2PF2LDg521KWygxaYCImIBkufg3RFnQ5Gv
+iSwvvDoRrgozK8L5hPVSfx80C20qKJk0bhw9SyHF5VXL3YIIw6ztAiJa+TIeSt47
+cJcWOytg/QR1hgcOkD0nFNCU2Zx8k3+Ap15IKgBwHJNIJJGaqzyT52PMGN25rEgT
+rFL9eNCUrrkEbf9wcpSSSealBdlWHLqmERJqh5jFjBAYMZPdHr3uPDA7ek5OTQ3F
+oRGnn4fyZ2DcZieFSDaohcOl4as2ONXB5ONt7yOEjG7ZpfKZI0l0EU92KhRrmLc1
+uX4zwFJNGYlLoXrnZg95SFv42YcPowXZbw4xP/FttLUxBE8uVDcDp+wDD7OH0i4t
+SzfWExX7PCITpRwXm5bAHtDXTp/LWxE+TgrNfx35ZpTW8TxdKpuasO+HSnhtAAsF
+EAN5Rqu6cwyA4df7QOgrvWhAoWdW7L1xyZWcUPMrtcr4c7v75UlTILsrXus/7g1z
+1fRD86skv7wNAZp9MEITD0QaPVSSt8IMf5cWT6akpLaZnLAYqzDNBL4UGOkSy2Ns
+dnPEaldbTo0ySzgSzAEPqJ7Zd2tzQDtHfO7Zi2+JfjINr7CQC2D/8DUDEoYSnihS
+qWoWDRycRx9XiaVAAruXVq8WjesPc4AwwhnSh2tDWgJo2j3y6KHJtesXBEkJwq9a
+UlgGXvwIS2xZ/4nz3VNV71bW50WAm05is9M9m0N8z42daPmHXs3Ne2xVV9o6htrG
+Mf/hy6353NRynSbT5RexulK/cinWpFk9c42oEIMsPhpimM7IbzJpnqYiGD4pSEJq
+Y/LrvwrKC2HNTYrJ6bsG09drqAuMDmgQ2YPwl2cGSocXaCFQq2DXEPob0d0kiOL8
+24O/Z90KgMz0TC7sgan0BXQa1U/JosyItX9m39D58hto1E281bJghw5r8T5JdeQ5
+rPtOf5PP65DsZL+LE4yZcr01NKXh/tHCMqsDUsngQzc1rcEF7Mzo+MZVpki4oIN7
+gn4CtdJq+e1hbi6AR8lci3ljlqOz4LJvnKSNI4X0b7qfPxqSR26xkf4Ycar5mAvQ
+AmgzGZ5xKGH/P+rlE+vlSRMyg8k6tYEb53BDsPZ6VDbxhNmFzrFsPEYvP4AuP8jH
+3UBwRIoU/dXR1QNHFp4hii8PUdrUzHEXPTBzZZ2QVGaW8deu8Enx0cueWZLzgrsI
+rJ3+5CNRGdfcjoZg/p8b44b80JdJ15Di/F5FughkpnhzEAFrM7OV4fB1E3ztJdko
+UqbfK4+nSyUtbIUj90dBNroqfV/zNPb63xLoUPCQOwmI59k38EFPyopqmPnHZKnE
+fNwh0tyDrVw7XYHjyKAalBieRmEcZHont+bQsLz3pPv6vod8U5+eQC1SSUnToRZ+
+BXAsyqGihuOZvTuVSWLXmxOaUvoTeNUMcMY+0uFaCd82cCD6mRCjodsXOLXeIp2h
+Q1Hj2AbEtiiFu2TRw6orVd50JGTMH4K7Febq8CYggMnCU5S8tQpwZNu/EUNZssXH
+otSL5nBqVFJkx3MHe7lNk1tVY5CGDCR5R89eRwzPJUxt1r8WhNZPTVvkxdULWbhG
+nya9pjItyujb0/6HJQDnhheH2Zl8N2ynjQ7YhGH6zzUnNPLrcEb4JJ17MZSYGFYJ
+WbeT5MxDdxKshQ/A8raYEsRopgstn7O1+N1NpKYTTXSACaTUrqEvnNBYhi1HMJg9
+Q11Qb5r9LDyZ2fiJ2nrdHlMMLI6rE/bNdOIOmU3Nkhe+Jj1MpdXIhOBHTlg0lpRJ
+HY/EIFVbQkO9Qx6wM+sf4pfg4G/ceZSgaRWBuTJbLaQ431ULv3+49s/DWIN8Uk+t
+WG5GPZkuilggsOqALqUSXnWc13ru8sthqCKz0i58arcIWJ6YSWR7JZn2WzJaiMHt
+CB0fiVaN41KOc+kiqRJ/b9J+aXfzNHWuxab+jYjL8guLR/MN9R3xkUskwQbYUi2o
+sfbZUvSkAB+NLCUaLsAswNx1fKCNdNh3rQDMRaLVAGN9J4yQuD/fBcd455eBmtfZ
+KtVlBok4fVS1xzZugARZObuhZYIc8r+s4Ztk9wZwwDIZFAdp1QY/pTk/jYkJ7s6H
+YbloEwdsWRntw0/8OVbeMIuCJn9KhMWXYnGYm7r2K/VVBv1oGTNStPMX9jxqJf4G
+0FA3BsUb764J2xCSmHdfFxHMJJAof0gN+x/Skph82q7InMip1aC7MGTsAXXJ/lUX
+SThrXomK3RYz7UkcGyOp29dXBmijI1gaXoWC2Qy3oizQ7e7aLM96vb2mir44eFae
++AdHTGPZyJJbhnEqFHpkfxFnV+irXueXk9H/tn7MmffzAHC3czN8TMqckECa26iv
+Jj6+N0WfEwCknPCd8eOSHKBhTIjeV80H1xleIr1848BbuDxIc++FSunpyTVwNseZ
+/ZXUAP0eh+CdbrsAMJCCRdc/OlyEMBRVE/85mDY9fVA+rzoGBc0QzU9UblA3jhmd
+j2OY8vL9Aa/uZfcXhJLL23HFgzNTAJ3izWfzVD4/fHbydlDOfKk6Ad23t/LiMaW6
+GBfMgq5k83l/MuTN/j7G6NoqFN4G7ECvG/4W/vyAD27iptyWof9V+oXBp/5abWSn
+8OsAonQQW684DuKciH4OaATSQEwNF9eI/chPYytOUWNycYQguk4dqD9Di+d2vFh8
+5Sn5hW/IfQs9fsn9lRzGMhgqMIufH3tZV8rtTPRrkyNHnDTVSu3KBmF+y1JZFyPD
+WhLTIxpbgCe/5xnLywoGPSjy0W9WyUWwnAfy5jRC77NZFQIQhDNyJsgv8L3/NCDk
+C1HdDgCccls7S5Qht8l5gDbWJW1lQVhE3ZxehDCHfWwsY4e7qA2lu7Cnb/m8DPVx
+6je2eirInWJxDD5gbhK6KOTfcZ+tsCt3Srcu26LI8W8pkdMWONkvfiAUruthXoMm
+ayOLtKNXS3eQc446oCAvuBL+/2QRoGrtNPn5oBUBXb5eCkH0tzXqumX/aP3vQ1Nu
+/JV3XCKko4dLjcx5Tp4ZC78m3TImADeSFQVmkd5qzZ5NC1ORnCc5NqdSWm7R0gWL
++nk+TkEhnEdllImd80apBdwnG8P+kFLy42Zjwj/yj88+XtvC1G80NVwSFzIMkDdP
+Yat6nad3J+Ay/z4kc+vA2UdMh8UpSzSJV3EWGUgrYheqL6zEpGchn55cN/qdmHjY
+WSy4/ZFm0upO9meFO8SN7xieHoiDwYO83GSGY/vv3TZrE/LmJeBDTBvqT0Zy25Mo
+hCOMvRF3MBepLHkz9ii8+I02FEGfuAX5c01/UDcPpMQWcFKnBLglC99A12MeUqIz
+X0Hb216PVqMxHUpQ2KKRS0aYGpA685yIBbGOiG53GgKU/lE882uTlB63WAeM3Vwu
+RwQahWkf86c4NTWz6s9CA8RpS62TzBmVLPaet86z3O24A0bnTBdZQvh7z0qoNQCZ
+xFa24tpOz7+zpQFBW1b5QYLoge9xcMLflXZbWQzUDYbgVqqNHzQ3pnfwNJIjsums
+LqZFMV4KX0/X9YZXsUuY0Ygyn8v6UBH+wdShLVwA8OAu30MJEs48nVweksq2H5Vy
++HR6QjZiCuWdnoPfeYZ/yQmLpuF48eiCFp7towhx64OgGIww9qh4J7s0Z0/FXdzd
+IcLMRFJfVsHngDpmLKFsf9TgPmIoMY6ABBe2dRzG9qsjQSKCs5HFaBol6uXy+QL3
+uwkvOc1f1VhhLnW361L/FcSghyL3DyxYJR1nxdPHp/vOZU7ulgj2PHxXKjXRjAmo
+a3R+Ei+bM2Hrt2hOfOxh9fpT0sptpPLh3ac4fuUoP9kF8lcABsXAMnpH2P0KidpI
+YATfEvlauGRVYrCTAPc0ybTK/Li9gXPDWxBBpHwxzzAc+EKuknGY7LFUjSEO6BhF
+j/EcE7gbYUnvBfl8jGifjMcPmW3Td+7HtKmIxdA4/SLBb37TTmZb7sQC3r34Fs4x
+MPi4ZCNvHAWF/5zp8b6zF2K1AnxGwFONUZ6vgwyQ+9/Xqycrd2IPjTWEgr8WsQrR
+AgeRDBJuU+wvKlEWqgE/CD3AAeI1yrcy5Uft8TXDxgQUsRnpoMaiFB8sP0K0aRFo
+tkj1Z+c6lvZwpcwr1pK/SJxFYnzFC5XqgQ0+KMdy0qdF6eoKGMmkEKs6aTU1mvoc
+Sej0gbmYn2wtMo/vLOQ8gsdULyAiDkqO2AzFobp8kGKYjRpFyMdUKBPSS3cM+3jN
+3jPBW/YhqroCsuoodcxEQolpGPoDHdDTjeIrILAw/bR2in2AZOK5Wy3N8vF0jZHw
+zLETskRvOCDIEoTnrcvHpnrqI/XQBZx1h7uiliEn+tj6ywdp5gtOxQSbB6jbG7Nv
+Z40uFyZuQ47lf3myEOnhz9FdiVkZB6aipmViKbO4kM516PXW6MNO4iv74TAzgRY9
+NnQLe6YMsOCKDeim6zPU70w/QnEuM2mjreX5fje0ia5/KjsrNOinftbasHH6akXd
+pHXE3sqEosc9sdp56vmc+eC2moFLt1A9lmo4LVakE3yBkC6Ix5/sh3pdruv1gV91
+hZ0YDvG8mFU5aTvL3ReJTNt2Y5hdxHJYl+ghpGQECc8M7tCbnZouL6TO/cZ4NBUu
+M0zEjYiqQ44uDzXOT3FHAhyHYSgpHBgzXEkKswfRXByfKWLIUwG3K/Eo03K+6mSy
+zZGm4VVbX1wKmCT/Ewi2h+zFt8zYQAXDUrqdsLjMU5jN4WoHVxAvPuHA1JEc0ES8
+9M0GA5rvXk6IjwC6ZYQBXLZuuGBiYg30EdwFEd6FqvmglDEMnm1fYj3cVQ7q7JtD
+bdL0VGLXWUdWQ56FAtuukvcDbNKfJmZzBbvq/33ET56DRW7cAtqGyDit2lM+DQfn
+b4RCPoe2pS8dp4bd0Xw00mTuxQq2mlrRZObRuUW3hq7s1v3fqlL1MgtOZAkiEHOZ
+GJeVaPi/LL9g5Gx2gFJfiRjOGGmUBR/KlAK7lMadGuxmchsX7471Q6Qo76sKb5cW
+5i1U6rEuqWpTUqaeUkJ5qOb1h1YWl6zLtIHyGZSYBzZUDX78hilwIHbJUL/dX5/e
+DtoBREfgsRHUlI2Oku3c5DmJfbnZ7cLyhWltMN+TVNg=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_rank.sv b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_rank.sv
new file mode 100644
index 0000000000..2fc44b9b68
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core/mentor/altera_emif_ddrx_model_rank.sv
@@ -0,0 +1,1423 @@
+// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, the Altera Quartus II License Agreement, the Altera
+// MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your
+// use is for the sole purpose of simulating designs for use
+// exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 14.1
+// ALTERA_TIMESTAMP:Thu Dec 4 07:39:38 PST 2014
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV-6.6"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+DeMrN1hDh8bbGr3wk+HPO79gHcDYx3L+odQTIsjdWiGOWrcG55OZMGL8UY0Yi/QR
+mPFkok1/6+T8TM70lTeYK0p/p7Mctjdnyqd/gBFfjbyVNi3OxC5Fn+EQk8Umm7aj
+u1KfGQG+ddiNB6Y0cvXxHts3VZ0WHfGhTAJsOgAJAT4=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 66480)
+7HT3gWHmiUDvR0WTeNOZmV0OKrcltDhN9Uyfbg4eTxFliOBRao/CN2llNZ6MKpPa
+4+NKfrR5tTgCNqzZzu2ZVE3AIOWvORPv++JMkOgig1prIC21PoseUFdYAGX+PI9j
+wcdzj8UFmYeEhCXI+PpPG1r9ShNeFplq51AG/Uwa6vN11JmZitm/yxo2I3kur5XH
+TAeaCsK1fnJaVQO5w08WOH2W9QJIY+x4QSMB+LfF3wTk4qzEYB5Cgw7X9pM2pVV9
+hvWb/REfiaHIZA1XUI+OgZEy7/mGlhKyQf21tpSACXvukDihghZYNUyb6SfWW+z+
+8NrIRb5p7b2FQr2+lzXJjjIs7UN7t8E+BWuNER5lT0nQXtJXzTFuhERPWYgI/gZE
+lhjAbNI7OkUmNyeBTCUF7FhEYpT86PqXDfjlrEe4HIca5/GVy1o6erGVQ3HkJKeV
+uglzWeqs3ccVb1UESf3ASC89Azo8ICycW6Sc4C0GU7hn1jnK9vWebrElnTYc1hb0
+RlnRu67lzA9s1PLT062f1FekDjVo5/pVfdLaU4IMuD21vwEJ1na80J7ELIxMhpj3
+Uxj1kgLyOvaw8Fv8IV0BGXXQuSJvZkINH6Wdhf2qBTs/z53w8eANgVEGi91bH3Uu
+CnBBi4q2ADJjqo4pl+y3BVrAYzelbT5sYQYMx17OaD8skpd1cgLhRNltM4Kno4R3
+yQvURqtgvEVJ82ENwHJNOGQu1Rlr2fXO6grpvabD2XaeuuOmmGeGsxvAkPYjvKCm
+vvujPNZ47qYdHEswZ8ZV5RJ0Go+nRPaGJH1wg+FcXJcFp8MhzMBLhoimLzgHv57c
+OwgT89szPpnWn8EDCIndODdeesY2XpTq27dK0coKyeLd9+NrRPr1ARHpIhmLI1/b
+CyBDzIDjrx3KytQmrP1yTqs3MJhwQXLelcyJUIA19OrMy+txzbFQS9PY36CWFi4f
+7aIizcKkGboL5IhQBDx4qejiMgeYwCCDa3crxVCAGj7lurSMjKoIwGarEEaDQC8K
+tO+a6Zjv+KpBiuDThz1vuwzwMsD5Yvh7ucYpmkvSVnNuYwfvfeuFfV/a+LeA+GPO
+YGcx28KtOQMwZqfLOHeALQn7Zze7TiIpmBBMtx42QYNMEQJkxc1Q03KNre1gaM/o
+wTqAyRndH9ZLt8cDA9J2vyhFcaH5pnJH7ceCSnKE65cnvBGysVLaVk4MrFe8ymzK
+xHvyg3hhbfZ/9UhnZzr0e31i8paFKnvr81WHYc7cyrij3CHFAKZe3LoQKUnqHkgh
+LG8bu+MwQejrGCOi/w+MgdZEPeJrFNVMtsG8bFWayu9UcqRf/MOaIL1qOWm2Kgd7
+quhjfkw9fTzsRWn9DmmREtqs0UtBBquAGBSgHttm8D7QJU3vZkK54dD2YiMrXZAl
+Z0ajoKh+l4OvGaJ5WKhqmkD93qjE7HNiijeKn7fpZ8j5+RgUnKCoZaNHEec+jIWN
+tKsccLh65sjNDIPgsfsPR1tDbuOshwlP1IHPJgIRgrNqR4+L5OoPPoHAXSu0qBmF
+gwKRLzINfwfPQt9rkT7uAvEVQ6YI32VmQfc+tS9O7r4FtO31SQVkW/d25f9i7xp1
+XZ/2YKrSxPKXEfFCW3DKNhGaGQkCY/SXVJ27dtiFqKwTk2ZY0S9WPXTIV9vqU7AZ
+BZDv4DFzCU2hX50mvBG8aXJZWUtbbjL8OVjrfQ9YrpECvubT7TxNzAdLL7ZbRBOo
+kLcoJ0d+vT/HI42wuGgO7niU5iANK/AyFeCll9qIEQ05QEJ5NCnd7WhGPJUgT/fd
+wUGAoCITL8GcfOwMTD0jn6cmmtq4ffWWj4kPFae/yACM7ISqvBsriuZ68MK+00MB
+LodjaxImJpB4rzftWW/11kByAOI0ZDWWK8MfPFyQhKEcoJeoy+f1z6zpnkEPNbq+
+kNzRxgpqtOIUN/3peXgMc0qVSWSRH/O4gCvWhOjk20Zh8bA5hF7602RO4DH9Ui0K
+mczaQ42cm/iuvU8EltTEc/G5sYZepp3qOogNvn9ZFUiMccruX865YRknu0m/04Vg
+BY00nwmG8g10ex9ggoFDs64ERdGP/thbRivke6MDag5WzNCV24oLFjTpKi7YPnl+
+P63iijUEK+OgfGwEBFr9JeyZpzARYdl1cvxxy/0v2K3vP+r+zOEmfixoDfhr+aai
+u0wS/CJXYwhq8B58vSb+qUEEvn7hUEC9mYG3eCCGIMB5agfJGn79hl7qwHzQ9aOi
+KpX30N62MDhrktb/BPgSISekqaMaRLATINFw3U6XgVnm7LdhjjkQBnpAyWOA1A2F
+hZIoyrNoQ9Y2qjDI8Oq1CuhodEoqgIMFcvAhLL7R+cGfU+lNGv/HwCgKxE0T4EFl
+nK+3yLpSy2c0oHYVJgaGqy442sGZn7Jpz91msClok2bfM9hQmZwn8eUrTxvk+V+3
+i6J3DAFNZNIvYTIyA9XEEanjgnIJb7hDDDQJxxEfFOTW9QdJ+HqdYT9g4HelOfoi
+U5jEXWbC86s75tqQf3EbEl9RuIIdYJLAHSugLOY6q2upGkFZ6sXN9BPiSaL8h64l
+XPsfZWEVvAsz4tOGdYGVwLAMFyuwmdflXpWl8dXtTV7fw26JVANK0pr1CZpF1dme
+0ajnpbyNmcy4Z0uHyVB2MvAYotC1OULYXlF6kSg9Jl3uYf/VoVwreSrF+5t3kz/Z
+X60Udi4dqKaUE0Q6YxuiLK/NKzfH/FajbtB4nUbJFINrtZov5k05DDHFTVTG1TZN
+SmarWgeScVEyErtFcwr2nh8uZLBimWw0tAULu//PwYT2Nrpj9a+jFqMwq8Z8c0ip
+uoRDqw9L3xsSPQfH2+SSkVxL+1WF8hM6wqZTFmldcEWz1NbT8vbkLloK945IudhP
+Ou51di49ozBL+kP7BGmcwFfn3uZQgkaBJbWHOwXtXLZwNbTAlzOCTP5eEouni5Vf
+0C0BW0WoZ+zSLB/oTLjTqWJDkz6o7/09AVsdSis/7uS4ABg6DrBPzidzY42OFsqm
+Q1yG0C5e6b1GmX5BFL4tACQaKfvtEHTGYsys46KIeojGr334mHowvDefKvU+Gefs
+Acn7uyWrYJhtXaV6jAVCyATXYlYCQ6X91epJjGOxRHM/SXSbuNENwflwzo6wTfC7
+uGFDdeL4uv1AUwfJ/ysXR6lX5z89ycOzBwYqog+IWHJDzIuzFGfeg2TVLIbsdq+9
+XhHOJH21J8g1tXp8THj+qM1ttWm0ZMoOX0YWpNjpPXdG4PY2hyp84mkuuqRJHIPR
+vlW81X1SqNUgB3ufg05smhUT0xQSupDxgyzYUm/A3CD9I/i6K4cFFeqIBboBy8Zv
+du/8yo4+HFw4DP9g73mp0wEjvIFap8o2LRG3Vs1L0RZZz959lp4G/kyhlBAkLkhP
+Gu6Ipo5kUtasQUGGuK0Glz680Ia6zGIBTnQu5l//Ck1WX0nESZU7sQUNqEBw3van
+0DktRXPDMz13I5ytw+FD+N1YetkBE8B4arumY7M6LPqbQdEM8iUN9XG7Sy5tgQKM
+fWpFmMObbeFyItb46RSXhaX0eOis9PflKg29hTJuDN88kWGBd2JozNEZJn/cMpIK
+kdhBpVDQ7hjIYi5LDd0ALN3qQoQGWlSwNnOQNWkYQ+G5AJWPgwliXWd8AMFILGpj
+8iBVjstY0uiOgR2xXcl3AyHY5/p6kx93HRM3hooctOq9oNOsJu/8GvXZcFZ/yuzo
+3M+CujudVRlbxnIEC0neneUcaLYosXjqpuOH674gcYzP35+1ebrujK2TteW6r2S6
+nU7BsnQjRhSTO9Y34HfbbocwktJcBv2FQgLCN8sHkm9/mdbd4GrAhyx5QiQ0QqMF
+h2VBexfTml9YeClCnbM6DVvmXomNhG+mvl0xJpAkrL7M5oL9CFrJPcJY9dI3KpHa
+6w/1kK4/lPZ/qtfs0+Ey1hnhLwufRlkqBLgT/HltnsADo6/FOqaP01bquWjuYQm+
+suW1m12wvahH4Y+LYKyUruPmSjzof/7RtlGujHifdUqeTDTrn9FwiQdvBCq6C9qs
+Wv/PBPQ3z9pS+R94hoaTPetUgjyYb68rozXPiVHc0fnZ8scXsZEi0Z0GKmA4O5VR
+1ghRm/Nr5cT621IdVCnC9u+APxF95PQanCZ4jKigO2ZWN/7vobsu2WhEv8xauV0Z
+Srjgcu/GGTZCdVel4E8ImjUZtL2luJJJdT8T+B4MbfyA1BIMMXNizoNLa82KM+RK
+sJl+MehFzvqSbY+k0ZBRIf7wn8xL95uh46vqfl3CAeJAw6e7FFa+JRmwuHHqKxS/
+COlOqmX0oEonXpHPeo2uGPwmDrMQNI39MFeWQk+h9lXGBiqDbKFIm3rjEAbxYGei
+iuQsZY7F1dlfYs8lh+OxepcaJWasradiqrlWEfPJ4oM+JFaTNcs2f5w+VDjhJTdd
+92/IIaw4KEv1Ak3Jk2c1Q0r00wJdUMKL+0AGQd4weg1EuWl7vnVIJJUYJswkjFua
+7kb2bWkMyv8sqoqXwHjNDXf7/QzwdXeonqNkJXDPJgL0yZx7xadl787xh32o1Br/
+5LzQB+mkd5GcBur6te0odQpli4iTsPbPVaOWr+y0uZu9J5gjx3Icj9vhnoEgmPb7
+n3l4wK6wPejZdEpD1m/PdjxdPI8xmJ2AuNhNco2MkjwTYGaMAKOPn9Ypwp7ReJZF
+uCkDSvkrouLcsiNa0D99HrKrUqI9/YQ9zc9nyyMhvtRx3mJAAsw4sgElp0gCwcWF
+/d4GNMps2ea6dIDCfvmX8/cz+nzrc+2A9typKTxH7xeS9/b28ofqTdvnzNj3gFYn
+WCJMt35S4XeNafOecaLlMNjNUfJfzv1yloJbfuh7xeS2E+5rT2YT4DfkE9yD3So3
+pLLOe1DwjPOGwwBWiqhFLYWNN7a4zV+zhypWIWcv2TD8dpqZPPJmRBs5JGUZGxLq
+4oHXUH3+e6PtSTHABmLd9M4u4kJ2gWfBeR4AwmiohUERKfuodo9XLMNQq9bWydbU
+U4iqvm9apNY2LuDhCsIbTWUFmm0iSlAP+qxuWQgNNRLH1fzEVWKiXdQAr9PCR34s
+aIamsZWaCqWZotXm5yVxW0b4GZID5l/PHuUjqCD5gkTkOFBqaUqvlZ/UaCtn5oZN
+Dpjss05mOsJt0S47pgo1q0FoCKICr4Bm0Mv9mhcO7xM9RprOv45NJdTKKPm8vMp8
+WLhx1F3OSIi23JtHR6Tj2Qc2VsayUTVkfy1lmenlu363zeECbxVRRCZoGz+MLSA/
+WBLmgDys2s1NRYjRGW32P04Yrqf+teKe8weyz12fdMHo0HyGbTWlPEOI3UPsm+Zx
+vd7UR1lPgK1sTVJo/JgeEsbZbz5YmFe7UaSsXl6KwnU3X9LCESafMJtSSL+Es1B3
+ntnsvn7FV9UH1D/TztNtthcE6eruLMB1Gg20Pfvb8UZWvSQRF79BN2LDA9Un2vmV
+3tyirwvtrLVzG3YVNDIDEJCMhIfV4a5dBFm/S2TvPe45dr21hB5+DKkTFqPVZwEL
+7OJJwpqdw93v3ZOv1NEhd4BPXfbdI2ZGqACtN5eMS/b2AeKbNJ7r1c/g2OPWuwXV
+VffId/SqmEUfkljthpp3Vc4qh4T+f20fcFPD803hISnps12VngJd/MtJSx+sOgHf
+h4kSuDIalRyD+8Js7jEwIy7oIdOD2HTzXbFtCfOrWwo9tZ9bsj5mCm/4WN/8NY2L
+qY9qGbWt+1V05ony8N/ZLxJSuYQZuqjopBFnqPlR+4dGtYZxDTPVObPJTdLbyvGc
+xpbjtgfOEr/hajPceIf+eE4ZtfwvbnXPFj3/hKl4Hc2i1jnmtiVka5hAPFzarCbO
+r4nh3iSHFBhMKxRoRha4Li8L27j366yQiI3YgsK/PWgDUg/Yg7ubF7Awq9QWV5l5
+W9Z5RLnBoqA5r7iqAmWHAhgAP9nYK40t9K+plwA1Pp0XFNfB19BR5ScLTtCa90FO
+orNhzCYTKdHeqjxw65ibwX0qXexKVdPonKgamPtuT5riMHtdzghpgjuD7cDmDPG9
+fL/gFyhKmewz69rt9dGBxrElaDy1nKGrxFMgNFIzlKMz4LRQtGtKoMUFl1yKazb+
+9uASUdL9g0jxdnUaXXKhg6kN5e1XdQ0DFA5SOzWCE+ySJNF3gUdijd67+errqaim
+J4t1ir90pGOLBHCeEsuLxsoH1mcHp51e4gf7SrPAxtM4ZEqTVbQmQTGfj7cNYYhd
+5QET++uOcOJvbJYZRHkwFL4zBDIBfKOaKJ0gw8mhGQugcICvUpA4AxI+oAy8YpEo
+UcpFRFLadIE4AZSXa0iyGZita/CLJUAHMK1m4Dm2rKmhFfb3myvByS7S+an8JALi
+f5s9FJkQH8KBssmGzbz8Yh3jiPfkDvvoB2/21cXaTaAAHZRF/W2+zH/NTQYnHOKN
+HTxYZ/h+Q3Zqgb6xe+Hq30jwI6RwYBlzOXV6P6BjrxvWQmn8L2K2QIGHUUSNIQNv
+AA9d8+t8+aOqlp6AXNq1YBDvlvWCZjNm8No9UWa2U0sMXTHgU0ZVWS/lVQcOggmT
+RJ+cF2u4Rf1E0POlsY8CwQSjER7aOOH2dcMBEbABSOYeqoLBboUd6LQLZVkfG8KD
+bI9xz9aRXUz7fomi3CQdejYG7km+l+4DILY7vmQPL6ismGfzFcKuFiFjXwofITYA
+tf0Dujf4yarbef1nJxNKa72Ad2iEoJgwmZgwPEzViYMIo3yrUXCf6iwcjpbR6akY
+txj8jNgDVue29yTmNCNPzUYJR4A/Jb6s4pHmAA3HdgFpM8mfEZoULSh7sM5vaBRi
+eVFJKnoIMWpXOYDthnrL0XdgcFIIltHnm686rD7GAbk2pOBkwJWsHTnLVrlXrsnW
+Q5D4v/mnotUgQbh3kriRoi0gg/G/fcyxOC/KCA2SyU+ChfxHfUNgmpmtf1A34P3A
+4vQ8PGizsmZJE2ALJjvvYPNui7uKCCkUxXCae8o4ZOtOO94oxIYLfzGYmWmcj5BC
+QKLfh60meLEdSKigqLogruqUJCcbF6Qyb/zX8MFxoHcHKYC79hMG9XZUHbhgmm/t
+6wslWmXO3VfiXvn5Fmz07Fdc8mvd1jcWyfGGmpmRVSpz8jJ0vpyxyZ/3fACipZpG
+L1LaouTZTW+xFJNbMrAS/6ROWURNvYkMrTatLsPpmqAE/mJEd7dsL00RioVzZNyB
+eETMOd0BbDXqA1Wy6O9u1IVK00CgJOKPTB5x7UcUqompx+8mnbDT+lCrLxTIucrc
+70HCtopODSjpN1M/vNXXAcVbjWce2XtP672MH06g1d0chbjQbTst2iOnYUezSOgj
+4ojq4VUND4A4taXMOyHfNKYDG9d0877d0CPQxbEzXCeSMKzCeWx2FZIHz+4ntrON
+rGsat/JJfWCCRBvF/8H589adJ3OiLsf59dOH54YhleUZg65GMEufcrmzHIHT5tB4
+qyEfkxaybvSum4WunYOXhBMna1At3NsHgjL8t5I6psOmiqqfS+Us5W4fLVW7IpeX
+Xf1YyXdq2u1QJkZkL3jxfMw3qtcSnRBBdxlvlBcReZJOp2EMU854IkIwgfw64buL
+KqnXZCHH5O1clRi/XOrfa8Hm3wfBRgO5snYT9vKUWXtrzLLtuMlLA3wzBwslgK9a
+zxf8eaKnlnMhkT00LW0EKyKW7pjSJ3qLmcduT32kC24yz+tDwn5/dJQddKE2oOL4
+MCOYMx3xLEmKTubOFEfEE8WiaqY/TKUfDxi/dDxCZQchrVlpDYYxN0otnhUgll69
+5ustTfI7KmOxBWmGWW6H4kJHHVc93YFTWp12Uz6uUptfluANwYBMZBbqk1/QDV3t
+M2Tun8oEB/HZf1zwj9HKaG0OLsIyzklhej741MO3a2kLYTQ6othH21Uml2vAwCKN
+u+touS9DptsSQJKdy6VkAK0k0wH0C1dxX8QDzAc1ICMp4fxOUBXFDV3dX2R+derY
+n1vSibX4EGXpfBsZ4xwttwGScuxryBsK9AJzXgcC4x3HdvWiPHE2oGeT6hvTNbyL
+nRUTSh+er1OZvN4AFqVK9Yto0kzMPdWl1dGv1MX6vg+tP3w0E0mcalRaJ+VxA1Bk
+rzXZzhiqXLUyby5Vj+GiD1O0v9t1UdiL5cjiOQywglJepZHVTbsK0KIYLLJK/+G1
+AR/ttFGc6/uqrUPCYRJrDfzNlyKGWmoTcZ1OY4EiJ1cn7gx/RqfRSxTUUeWpb8/z
+ro+TJb5guuY5LqrA8QyZeLFURZlAVA3HC2EiNuWhypN+AzuJCd0Ap7nm4m1IlpTE
+oFKPW3YYezYEue/SDuDjuO9P9WJjNNOMeDF8KRNmpx9qGDUC+D0eVGMrErLQKjnj
+xdwftMmTX+pru406oBk3hccvDgTfAaxnf1teVtEdCqvCURziq+CXVUTIXWl703Ei
+9GjnDNjz9WEr6lJcUjJhERlNkLz/KfI+HkC9lhy8kmZe869xdBAiW+rL1DE4rOel
+W5M8IXjPOBTPudv/CH+bFb+jFo1NqxYF5NJPEYeEeqKTXfbgAzsc1rr2EmqGMNVT
+oCW966N6ZFgGNf412Pk0fBHJ2UPUDhA+sYoPhur6LSYGoYgPxSNz5ybV215kd1sc
+I+NuMFw36p2pHobAd66v18hUICHwrE0b/ieVSKxTfkrs/7vFA+JaTO6bY3SBbDr4
+lZXm+1xnMdKDdr001B9VLn4tLnXivk19K8BKFAW5ItbJ3IpSKH+MJR3p6xSPmGIK
+uGZ4zQKp8J2v6GsS3VX+9R19aurkh2REAMtGd2+juqZIWB/48uoh9lsR8JT6krJZ
+BARoDEb7xNLtw15d0vCOfRTRuiv6Nb5hm0u6Des5AVktNbvBk3HFE4dOxgSHbrvi
+dd55KEJW624DUHdj3mfZA1KaQJyntj4HmyGwKTxvlcxjVdY916FJmTBnaZ9Apptq
+BuIhVpJSysnJpHdsLrA3KJjYQu00DImVnw9y2karOZyAv/LGzUOl804fCuu8CMMs
+zO7Jk4hzvQLSM3E1a04cX3lAhQbad1l9dUWMTfDJIsjllNLq5QomV+V1bWK6dz/8
+EgBguudmfKgh83qt/lGaRwt74qgIRKd+Kh+f9zpG4FznsS9iYufDqkujGyhpwP2j
+/qZcZl6zu+FjhYjcUiJaudxgpMeznE4rO7FEXmaW0dBNcMzMqPHUSajkrlPl73fB
+rf1/xkTnhVXbKlN/0RUiBjBRI2KfU3NJG/LkyKPGcLD6N3CtDyfyIJ1soAvDNZ4B
+wTOUsD9QFtXTZRTy+ZluMq4KNBAwwqC4+6fQYDGMY2ENeZx+MwF8nZchGS0BtVZn
+9hA8ifszUbiJSRNZh5vVvVEkoU2WN/RuJ9xN/+ws87ka8RtfbKBLswCuLWzl+aJy
+syrlxCICGM7NLrIosSJVmVRjAJmlfoV/8sttEqGYXwyswtLdARMhUQG2ybyvMXCf
+shGwnPeBlwVBrfrenKw48kGSPkk6QCtqxl1JFGipooEMb2/LMdpoJClgDrbQPxnN
+8JZeLNy0IHWepHj27O1xaq3wJZhC2Z0520G/82/Up0v8OtYsiH1I0NtG1pOk+i1H
+yqBf58ph73FZNAnAHklJ1lrHsqCx2Vw8abCXJnQFz2clY6S1QbAXZgDZHRcWK1Jy
+oWFHQbuMJjfHUifj7OxDR0TcPNT2ry+eVmTK3A+DIPLb/cj0FY0hyU/ElOWS9SoS
+STk5+30FXaTDjzgOBnf0HRWec5D4RVdiG/DC4PVMziT77kC2dEXrjP+wkEVZP0An
+ZuBcgDMX/y80T7R14aRLxAqNiprQTUIsWbTA7TmAgrGC/p+iQNlb1+ynN4IlTYjk
+hyLaQg7z4uNl9eFDwsmTWz/39zbpPPrj9+FUTPq3ip764jV0Pjb1RnDHNLcNMcYn
+gnxrhV7YlFTotuT9ZxtHbVAYna6hz6Z+t+w3Bg0/bq/UDOwOjFyZsWzYx++Roajs
+CCA/dMn4+fe4LOc9ty3EijQr36fVxbtkJRRMYMuCveuw82NpTwDPVQYY6PaK1Vte
+bbadGpzx36RMrwa7ep9Br7hDD1ynPk792Y5zpj66r1XHP+JgnejVZupfLAjJKKWu
+uhLTupBwWqyjU1o4w9M8mChuT4TKF/pIZUFeSeoHGqUwDFfOd4hExa0UkeRIzT9m
+C3kAm/1Sb5Xllulfk7iTfWPshG3fSKZ0tS7XMWMIMZrKSu6A/LMFRdTE4GioHOjk
+E4HKiR1rYSxzZ/7pGfE1Vo3IUGy++r7RQB1XdpPvz0fAWwf4vCu2kG6vDbNDxlmw
+G+DDiHvOAGjRUo/Gmv0mGxyPUhmr3jvCljRrNZrzk/KKhajbrS4QU72S8uwJbvOs
+KKTCy5q8B6y1u/CA2LDM617+GIsXOiTleowuJZlOR8LMLRJETeeM/pfy3irBPFLI
+4ClKnyz6YAgr4+P+BqTnwTOtPukfyRXiDoUiv6/hG6jwC/ECOPFmYvhHvpRE/9H3
+eV4lWD8z8hOAIRra5R8Pq6USTLVSxqorW4LQMBPWzs0GN9jEhg6/HIRaDE9AjJqw
+bp1SwEhwJbOxM11JGxXNEn+VnVrtD8GZZldHcGDPvjoiuw8kGLTImU2G0+0UjvQY
+ikEsJYgGx1xDTZuV1FceE94UJFaabP2XWGUJhhqSEeicW85L7ZUchb22l+OPOtYH
+dXlCaEdrpbhgHKrdMgP4DZd2hhh9mfiNqoe383AyicsBy4Q5Xv010af3iPSotAEJ
+yn+SZXbqRhliyL4i/ftAYWPWkZAwikMMvTodZFuOrwM9UD0OvOgITTeBE8hMqIbH
+nquPtKJnzqloElfNljV2N78Cg+TNoB34AjcuKTYJEAx3rhi/ZuEAoVNhPSRvLAlu
+sr3eEuomkyt8TteIAwYbG5Qzvp4uSngkx2zr3DpN6LxINV45rZ0QEONFmTeNkxYp
+3Ud5MDOmskSX3S6BUhGYhr+N/6Z602WrduPWW0IH9wWWniRM5yz3c7POWxg/vI9Q
+Hk5kSV3mUjrYiKRydXu45vxrKGx/0HgHNJWxrLH6sn3/WWILugRdCvB/M0FTLh8q
+O3YoK8RBjBu0S0GGTGIQDLZiITa9fwflfSkrYhxn8Z3nPKKxrWe7MWEC2QX5UFsW
+ogd7OQUr+lgRT2WNova0vWpwaIjsN3wmgFqKsvm4SDVTbgNbzntXayUFea7Wj0i0
+QqK0DJiK853ybYWxM3FcYE36wecWsgiLdVM7UebG8/LG/AUYqnw4nHEAA7/dO/CY
+7VM7cIYlev0Tn2w80UzQDrCl4qNklkOnzL6qOsMnz38/dHinL3NsqhBeAsZNuY4V
+hOOMZ8FFlt7fcKvIPKB33JCCDQy/69//NRICIejXZJ0bE3edtPuT2ctIIA+YFinE
+11VPgV18Fc98E0p0Oqstsm0fcrm1so9RNF0i9cmsyjSleIM8oBrWxO3+m9lOsici
+zjvYfMa6H1WAjOIGEID03rldg/O8RGrsFDHb0d6ZcjbrhT58lxG+OeeeXocVtx2u
+S+qovJRyHMjyYG/lsY9YJYlojI+agGjE/ro6Y0zxWkvSGVy56lB45WN08vHUPfUb
+3gENPjkFAiNciLS8bLiSFMr/QoKEgR9OXpSohvQ6riJrdlIc33KYNBN3sjJDqzF4
+DQFMrybd4HbsDjxb2SUm9uHFipLDJNd9bwS8GwXakUiZYevH9l6258hpiz0Q6+1D
+/FwhDMXOFNcRkWHJaFtMsuLHDNocJxQQeAp9gnuE5BwwFQUA2dDrPjUCx6+/7ODi
+cevgNozmoTVF3tibq6ZuvtTja7XGEF1BN/1DnoZLqCcshOZOoFI7peQwoY+zO9Yg
+7q3iOw1LjqiBi/QQLjrqWjzPq0VBgFtnXRYpKrbdw9ljgbMRHdUJ3qMkBr55j7Qy
+m9HoGU8ZcB4cZT6PQvA/ZM++yjuLpoMk40K3hQV785/y9xi8ZGaEjvDzAULccluH
+UEb6InfqU2rQsMAkWrCx+RVEUkYZRiToqnN2Q3hxohkKUYHJ+mat2RVOc2Ayk8RI
+k+Fuc3c7Nj6oiYvtuya6e0kcxRtcOMkwAhcYTLT6T8rCy+ehd1j8G8aufq7UfsqD
+/GoAoDWPYHl958XkmbtcE+aUoXjAXEsyLe8HMw8fM3YpsBwpXxltFVQ/mx1CiaX2
+lS45Za3Ff4RS04JXdVIJ2TJnFO/TwpP2PYXVZDXA0MMz5MczVfsWaXW1N1bVXuqr
+uehMCkQNBS5xzVzQ5LAqP5mwt0v3Pkq5GjpA1TRwWJLmSm6rg6tjiYquAMAtbeuD
+GD3BGYjfH48c97fI0Ja49DIBiMvY3msj4HIMgxpdmcwcB61GzFdAy359aVxy0SGU
+6bcoWdWRCpVeKV9+pdpX4vkRpdJ4NVImgWyZBbqlkQ8d/SQGdQfYzNx24vuIhp0b
+YVx9kWrjVBdQqgSLKzniG7aphQ4cbKCYjbzUcxthXAgj2FdyLC9whLQQbpO5YGpY
+QXwf9Msq44ImDy9g/yHod23vcuIozWAsuNXdJwc5AJhjwePVbDYXsl5UPXNb0EzN
+LjRELS6D3xDZktI9KA3WlpJ8pJ1W5/5Any4r14lny1FQWvYKXFpwLdxiVYtbxNco
+NA665Pl8hggK0dFEykmP0/w4+VEwmhDthf4JAXeXTvFjZH5ErbT0RW36cTS340YC
+wPvDLZWMKc5B5Qr4p35H5FyhVDzzDtWNK11dkzxY/LM+RtmK8/lXK4BOqejYMPeG
+nXvClzj7OuEyG78xcXczdgAFje01twqqodW5UJob8YlrD/2zxklAgq6UavUB13zy
+xaZf/RiuwwD+SM18vFS1MMt+Ll7oTcQpTYTstBVkzO2X+z2oCsMIy2a4tNkWio5j
+zd0rr6SxjODtENevskpiZKJtaaLJ/R+0Ppu0vO/tsVn6MGWp83rBkV+r5ZPBacrU
+vj6TPdeX3OsLaap066OiGMdtol9BY4cZq/5MytxHzhEUF7SnLDbqxGc+l+ZKa8D+
+tRZTSMv0AEz9AYoCnFTbucYX/OWbWFHm6hSzxmQAUxdafyDrZOcse3tgC3nwohk0
+biReT9lWH+oCDw+RJr8BdFgij3k6h1te7RVAI0KM9QlLGuC5ON8oeav+2sKv8LwK
+5aCHcfiA3DZU9w12fQpCP5rljkWMWDahUy73kEawAkwBgzMj5XbhZFz3/IjR5NHA
+e3GsB1KmpFAUyAG9TtNilnDhEzhZ3HToJjm96P68MijbTNNtiAGsLHNEKvzd5L0+
+1aHWAha7XM1Wcyh6mmeejPPmg2UdW714mCdkKcJ85AX+Va8/pZMjOaijnTXcZZtj
+JnPhQG2LaP8TZF0Q/LIAtVOEjRwywrPtqRh/cUksmS4PDy2xB25X12XkGLLZP5uG
+LyfI+OkOiUXy9lCi89PRRipHe6qqTHiMiCJV62fU1VSrZowy73dZuhdcMOsYTlPn
+p6qlaZeTqIesv8+lXS8Q94u5TE//nCNbNrhu4bd9m5JGzhUpTjuAY/zKVJzi5HGt
+FBQs0MQ3OlZMrcxKj/BcjcRC4NfYNP0PYhEW7zvw8iGsn+t5FP09rJEPsEtsk5ZH
+EmXK3LRilChoLLs02AeAvvX3AJwW3UU/b8AlK8ZmRJ96f6n7l1OzQfyxOLX1GbRd
+K/W+/EomRQYdZw/p9jSlglqA36ySVBPYszBiqqd1w7JWtVjDb+/UgBZ/7fVv9gnt
+6cunrQvJ39hw//PxU/vauKUtc/eDbDweWQYcDeaixQnrI+zrqwqSL2KA/FDOtIR7
+M7YOqHrX/58/roGYGScKC+iJj4BNICBGMslbqcZrPoj9Xz1LbKU+ha9Eas1u5aYQ
+2EPzbIK4iI8wfP2vJ9DpjBSBK8TRvg1YWNScFnK8hir7jAlsVXFBLNClrG0+H5Ef
+U7zxouJtnPj0YiS3FqPsvc4kZaAH3wdKo44y62Bszvzy3AUMg2EAWrhGic4LRtOu
+mKQRejl1e82vtsySoeBKo7aEOGzIiXksDpXsTUemU7aEdkw/8I5tXR6AZv+4z3GG
+hFBxwD54H/fd4PMYRnHYDX+sKRAnu2lGsdfAOnV8XAB2RzveaLAwSOtInCA2a2EO
+lVfj8p1pTGT4wqzSA5/Hj3iFLqnA5gEIfa6Yj0ZQWtSBXEascseBc28ng8WTNx6p
+Ut6jy7tAcpAc7dRaEmNTziFpWU470ImIGBNIl8/ofxYcxh23iqJ3UAwiYLn1qgbT
+LOZy+hiFsrKOKKLt/jY8jyHkk2Rv8/6QrxKBGwKS4iUUTaaDmuzZdc2j4N5mvDGy
++AZxNwoudCo0uHb3K/gszl2XjLhW0dX2aAbo3oyWZSPIJoVSwy/QC6w7m0aIgfM/
+AJpPnD9XYe49hUYxgYUFlqZYKMe3qTvPSe20SvtTvmAZPikps1uxKwnfwwpe+hIU
+QRGg/XvK32RRV7/jyz2MfCTLKMM7lo0ozpGdGlFn6ZP2b82oOJjS35Qjho/mhYBx
+XgBM7MbjlP0I4FXVff+3G0ldyZMf34/LLBsiM3iI9NiNCPm5YOWh35UtGLlTzafj
+sieVum30WpxtIb4eAHPUGHBO1YKuAtK4cxZPSwnKVL5E4aXnPyA+gG2RD6DLcsyD
+kvUNq03kqrKKqEMnDmbNR0PQRLtOXTNNB6FUYJJjd8LyPb/B5hzgig2jULUhXNfH
+9EfmOjCTQyTxvXeN/srR7M049Z4sBl4h6syst55pZ4TBJAa2w2wL6wev9rhpwEUM
+QDJRdyRjDP7vqgMkmcClZzTMxtZqJCOkpgXzGc/ecPxVEl9z51MSSgJXnbFcpk8q
+MmO3fUVMn26mjxEFLTeSwERvswZidhzZGbD/Gkj2p0fCxYwYRVH2xVtNDKSqjXFl
+P5/xOct1a3CgNGOGY1iBRMNKSdMiaRtPXILtVFAWFUvfrp0aYcwm8XUVvBoNyV52
+hmjwjcNj1FSpbqjsxO+LD2vfFYnLUWmOLGbjnPkJmRT0mzTnMsnLX+EjsO9HFXc7
+nHzYTP1fWiUcQKJPKmpYn/X4W94WDqYhBIE353WKXHf0QnNmlAVr9sNioId9jD0G
+5zyGtJ8H+7ICDfWCIsTAF4K065GQKk8kyFO0pmSbrOaQxnAnVFVf/q5x46wEUOkT
+JUVi7LqB3NbrZMokG7RUDOSMbAmAwxhv6d9uVC4mekZltGHMitOoCa96DfDaVsDg
+j/52Se3g+2YhwHvIt7uRF0S6x+dihIVTRmy0815z/YsDs70JKFDNND4tT/cC/BON
+sKLrZk3KkFEz+/Y/r1eNZv44cTBiFNzIB5HHDCGoNG91F3W/udS/NHzj84KP2BbJ
+6Rz9cpBXH7FASCNCkNKOKz50AaIxgqTA/3eDkPAPjAd03wM1YoLri4NDoL8dDJG1
+RSCbBh6F/Voxl2p1sJYH0UDoM3zSp4L+6sGAMuXTcRWNcaHUfbo7SBENCzrF0ABP
+NxGhuFggQ6hO6bpEhhWvCJHNo11bjD3HHOFmrLr10rZV2FiDZLLmAKx9Eo9q66WB
+3liilU2RmuaRrtfUNpOJa9H9S2F+caY4wUezHMV0v4wAmo+GZC4qfNnaVehSlPJV
+J1PP/3mnAorbUEFNJf9JTt3ZYGFGu9CBo3BBN0bjbPo3tvChEGfp9I3cXUQcbS48
+z/qQ6AlCYPtoE1PCs9BtG4/7JdSjsv8VFDm8WViqTfzPlOnzlJ9TuM7xgrmAEejT
+1F8q4AdkCk4Qk5pz5gE8nQfi+zY1ytbYStUlPZ+zGCZ/r0oCChBUMLSQYVUqaugf
+FLZ6Ohbj8xNmIp19F8MAvW43B3OJ1pHC9bw8Tdmyi/1lMGkF9AFcBYCYJP+TPanb
+RdfZNQtnOqhXBtDUUBtyjQeuLKag6GIlYX1yKkA201Aov2wCfUdhZ0jN0vGe3MTQ
+LArj3OiU+1kmAn18OVYvjFW4XeCZviDUXvO+pC0Vn97RcRMWUji790oKUSF+Fsl8
+vZ+TelvsGNux/5xNTBCfXh/r+rLZLObsbi95Sf+WB7NE5Q8G2LEetzTVpEGgrRsv
+C+7xQMdRJ0OrkhnX++ZqkFcJyRpKVFk3Mv559AG2MxHb4dz9u+RPo5K5x47t8zNN
+DeI3togSsr0xucrGHkbuAIl9W1795DfUTlyS0L7wz6VA8IKdbBF14oSdIjL24EKE
+78U2t3D+iaS6E7YjTXXdtfSMIFT2uqI+yszeZjvtEi5jqv8x2GRlKjpIrO0fu8Jo
+KOQingeck2y1uoQBPA3wUhkRmvO39Q4WzfTd5GFIIxIgGchZqRs0Pjn6yHHsyCRa
+6coLS1mnQiGr0IChqWvRWwjDvuKV90UT6wvjbSJNkscEwqv5RoNtfUtB9IUC/TXx
+ph7EnnkKlOc2jaHaZQpfRSJm8WqjhdrvxHve0r7XIY0fhaxpO2KaOkF20yQrAJ/H
+5XLQM66yH02LCz6hmSd/+ObaMj/1dYgXEvbBGf9J97V/JqoDOurmWBKRqKi2ULKU
+x/gDLpEGkVe9M5XQI4w0hzJt4ttcCH9vWSYjdLswl6wh8lJxHkPZzaBb6d5UZt3r
+dw1jB6n6+a8rGLG9rr1t147fVrg5HR0Z9icjxiatJixzI7dWovzgOgSDYgSoGAb5
+IXpYzjJx9xPxHli/qRqVJCOpwMCxrHDYZLrVyyvWwnx6SFdJmxQsa2cMnhCqfkY2
+u05AcD7r0FBdsYYF6CPndsoiRCCJfXadn7eJ4SB5aSEoDy6p5RtMArZEVTx8flaz
+u1h44IPT2y3zM3kGWWy2EZA0/0BzoK+7rADfrbLxmvxtj4lDJhGI3pPGgkuVNHVl
+FVRyAwTcHCGB3nD7dWEB9ddDfHnJsTuJyRzxKA/+P+ZS7Vc+aurbV8zFlgveOu7Z
+7eA8PWzqD7rHBYoZ3IlEr6JdddlofU5BtLKv44oIIWKhp/mwVhh8vXKx/UXC5KJF
++LAO8q1G8SEVapapjpqIxo/nzRrWxNGJKNHMUweJe7ZoFUG+0n0EpLEg2HKflGe6
+dZkTyYd5xoxAXU7jZuyT2A3Xvi4k2AxE4sRZsbG6VP3l8Rgqw92NTK7iKFqKOjMt
+j0gdE/a5bSkshczYgfY82HkviYSzBTIkjO3qBl+qbk2mADlIDmAGDmtbwiUbqnB9
+xy6fh/I5JHdWjfgg5P6UfdHEd6Ueejn0krBX8Vdg5fOntz9yfkrGT0gw/P4TJx20
+lGKI5iromJKd/KQfjGbD+Y8BGfHEjd5Y9ixDDqq1X0W0dALjGhcRPQ7RqHPjG5S1
+Cxh1CdRxtUksNtRP/efLWJeaKM1HenTmYMTrCEHVYgSPilxc6dfvE0fDIZfM3KBr
+mdF4V6035tVS5+F4RQ2ZVVUuDrL9Qc5zDUVAguzDi28CWloRZMja7MCzV//5rA32
+vMkxjo0y/PA4BO8lH0zxfFFMkDn+qq+/oKIHDgS2baAESn0IToTiVw/7Ygt9N9Ix
+7kSOeO6OdI4Da1GdRKmYN1JyjHENLmpfBSzLk9byegvTEWzj7iqyQMZm9R0f7ZSM
+ZGzt3LQ60W3IS6qPzsSS7jmG7kRWq09J3a9a95Kjh2nhUDo5x2fZnF5CsGP/8wCp
+PEm1H0Uu2AADPnF3gJinqVbxtY4/J589HXaN3oYJbPPyvtqnN2gW9CqYsbkTCdei
+DGCyAYNaEqwqAsL68mQeZM5WuekV/XYkFZfHswv0FJk05TQ6X9h8HKsgQ4ehYlti
+ix2I2Qu4SJFDwruga1ZdjErcr7XN3yS6v3/7O2XBIdpnFaQq+ypfm+xi1/whVIyi
+sqg9pBSo2IUAUk7UOGPMM/CDLXVsCKvIwEQLFJm/KJGz6sRTljP2ONHwdIy5v4cL
+hK0xXbIvWZVD50OwsaODkgyK6WDsGdCOPLbcA9sWCyeGDGSi5pjzv506KhoWGJ5O
+e0J0GvIHptSHbujBByahacYjCmd1e5vXMvix1OnMidByNKWEf46hFU1J0/a7vj3p
+qQ5P2jOrxTZP3fhmiVYxEerUeb9pa8Xp8JzVu6DFZpwZ3Lkbev7Qdsum/0+fWMPI
+0oVjsKtBJj12Hq7YFvwSFvQufiELIU62NT2LkbZLA1wTyxUlLjI14b/ztofGAoZu
+cmsu+zvnsNuBNqs0RiBbvKIrr+H8hrKWhRNMVEs+pUQxvgrYWBni4femLvhfAwxH
+tzoDGHJjabSM1SStUalQGvvJdBPoWBmZK0jXTyeK0/1GObq9G0YGCFStEsYjldDX
+4ndj3UVm2o7I8zR1BUmRHv4NHtsqoLHbXMOGjslpbkWgxMQGby8uKa09vlVsASWm
+UXYmW52fcrboDg+28tC8nDjwHRP2RfG/rRYpZVSMnUHNGymCNcnX+dT9NAzcbNHs
+wFUZAE/CycVEUblGM4bGNko3iVqPrvxUI70jdjmRRnLInkSwRrYc4tSa//J2OKK2
+hpViibGDYBfJ2i4DeQc5PfbEQlGL0554CEVakX9iDJuoZ/fr4kqRv87ObdjhbmeZ
+y4GZGuxhj9KdeTs2diD8F/2zQ/cPB+fqDTGgblGp2HxU9myafLiQCpQGYZhlgiQB
+WSHVc5isOK1LmnltNQVRnY++H+qil7rdWdJBEb9uNxk6acNulrdbrR4Al1lWOhpd
+CCwZErOcbDE11PLGx5xwdiHMCExz/hiYSZ/VnqkiQtQPRQesLeb4iYD5W7cQNKLS
+YGxJKCd6nT6MjQbBX38n7q3ucjBnkGU93r77UOTR3p1+qGqRho9NNregejBfnlpy
+vuo2rRsyAjf7sElqXC2CMigexR0TE36iHV5ET92N+4l1424wBPeVxBtnVa4Ig0DV
+FUTD30KQPscBNnVHOZHozhBHStTwVcEotzHXOZDQLBtO4U11cSH5bwFtOhRpqMBs
+76PlKghzdQb41DHsgpRt4QEALTP7tya+zR3yyc9OcmXT0V63Hk2doDyz5vZpMXBi
+AlRFK1lYV9KDvCrZwe+midjLHG8ZbGmSIJg5SzAZTutPDAbvGQHMDZJy0PAimlTC
+ifsj0aGghCtot2NFjMwiWl7QVAms5YntI19HJKOyBg0hhUOTnMx6QYOr1bgucHdl
+BJkSgJ7rnk2csBllrvQcaMRseRR1fCG8L8hzZvRj57/wbkhi1Glmzha0kmDmWPjn
+Ren1VNpmF4PRHoRd+g1cYDbDFiNAOK+nW2jwlFTVtmVitiz3LYdE92QufNW9dybS
+nc6LHsM9LhyP+V/dniB4waFsJ/IQa7DAfyQloWyEE6f78anK3IwRwE0OXeeuKhps
+WwKb98ky9pa7UFYHZ3qPOJgghJvvGT3JG5nDnxB0MnzqPUjZOsYXNerkP6jsnE2W
+Sz5Ghl+gG3cjhvQFz/Eahje2vqOiz7tPyPvO5m0XHjqpR9Xk1kXvxdvYZii+3TNi
+V5GacaE/wSCcCFmYRsGf/gvhEEgwVKI5UuHrBsQVtyNxcT2eP5VwEMSuz2CQDclN
+1mvSBKsiAVrKCiFsP2yxKRL2zwFZ5KO8XYjH4bToizKRfqcOSDx3y2ldaslgfpFT
+z+u8gL63Vr9urqHCTQRjbhzgyj7w64pKBJ8c1E08r6erHZe4Af134VxvmIyzsak0
+eaaZn1WlfsDYXSDxHT9QCRxWy3vI6Nw7ssuNy1IECCXWrCc3c4f3UgRpgyqYHwLp
+2P+t60y37z0o4ryK1exXZm4mjksx+c66XpDofWDyJEdLy+ah6YiZoboS25K/sPPj
+bbS4Wm3+xCWl5y1lJcc3lsxXrL1ABzY0jqomLv95FWKgE2Ejnen+HmHn21MQTQ7e
+/hWgFvJ6o4PBsaolqtjk/deRGC4Ttb3OmNmZT0SkVNftnLeQKRr8fhnc3EbkF6qY
+g4QIytN/ijgnN5QHCOurdyLhWSD80jBYfC1ZwyFFo5aNIdooUc2nJ3Lvbg0eyEUk
+iK4Mim/OfKX4RBE8I1Bji0VYGK6Lnd4PEagl7fP/EeG7O8o6qT0mELKiHSFSdDqt
+r6F095nBdEeB7J/KVjVLGf+Pn0lIahExFY1To6NybAnD4C1cqLoHC8M6xo1GUtUI
+X1iQwsaP2xHAdaVVWWzMVYcfDQBx8d+z4idKUasPGIBoatEpIUDvVSpILFoOVqbh
+j18vhDzLuVHauotue6mH3qw3lmAZqbReJr+avKcZqCoXjur+c0qG45Ze9k2ki56i
+AswaWXTk/uQFTf9CweZorNjSgpQdKF6D1VFsWvmEG8wAFr95uqJJA9483tMB9It4
+iI1Ae9R9OioVpf/joGFF5fTm0inCrxw76ioMDd71XF1M0qDoB2EeSSM+noyzN0fM
+N33vpMktiIlRfWFyWZQW5cEOEEDJWPu+L9h8ZWWddbb0xpILGiXbJ/qtJR3KrCBE
+bEl0oWp0eqFhbonM+AmJCK6/+bZY1q+0yGyeqJKKh5mLdBeumK9TKGXQGSJ9+meG
+LpEJky2nGV+hXyGtJ9+q8lJBswHA5sKOy1SKT2hN8/2lePEcaSrtXCKKl4VE95cT
+4c6atq6K5tV6zeGS468+MMxXir+yNeQEUdnRIybU3JHNnyos1H3qWezG8GIV+60+
+VOedOrnPuk8MmhY2STT0LOnV7n/1skiidu46GPn7p29YYBUlzdVIHtFMIL7bzDTV
+u0WZJy4GT5aYcOwgZ/QwQWXKpmw+h6kknl+dwipW2HryD4KoHgz/cWBhsnxPrdFy
+mzJ6GtKlP7DFLCPRr+CZSiQbaftTYMSt+i2garvu8NONP+QMnKLCoiq+iOXoWVAh
++CVrfZT4BKHX0VeN3oYlAkXiCzvWHblyb5fEjonyK6UtiXIlbIbUby5srfK63yjH
+Ppx7ZEVM/15RJEomRUY1rhX7e1tkphHggB6vVnncO673UIDyijd/bBn6a7J0GmIt
+JG6p+mQ4bTl/aC4JSxur44wUdxs7EmbLWpXV6SskvFgHmwNkSSL25s9yE16h2pOt
+/uDAarExHFCnqwyr0Dy5c5+bfYmxujXO6mMIoOHm3PGynuQvPOYc3neFJ2de22Wz
++HAixPZ5P1hfXjA4FkL/AGseuKdvkIl5YY33f47Wwa10zkOuQ6jm6O65n7HAmzU3
+4jWRRf/FVw57FM0Y92G71K/7x1zRNV0JlZbgcl7yXlYjto71t0icNtnhn5KUuHtE
+zeR0DHjiRFKStQpQCH/SAWTtkLVJX9P46KryMEzG8mP5dUnJTns8aHUQ1SDRBN6i
++3X1SfyhZ0brF7w8A1YmV/0qLRrnCPxvcjyKLTu+MOz6Fy1LYQ4UOD4ibqYCt/Ml
+M3HNY9ZF4M44vaUFzt6t+KC21cNUb6s/3QYNjJPP9jrUXYLSl0SveDW6XC4L1YC1
+lXcAIaOK8m/bIYnMwC5FUhVKHTn6YPGaTSYlZ5zj02/qpm5KzcbDjbnYBDSIltQV
+pXvPifr121fDyxkBrTrRfysL3Wm+PjkX5ihDbNaNiflhM3qyN0aQI/yoGuObCVMN
+40syG89VUuQHKjdSi9y2JOF4qizQ+qvrhaxHQcQaFlWCOWm8qqHo1sCMyQSxkEvy
+VJe5YrJs9aN7P6rbNyAWHPMrF4kwFUauXPhhjUk+l40PLVWGbZkSpxHxqTePNHNe
+NWh+NM3BfZmIBCLWrgR7xdgWiFaGX5zvYXPUS/cB0prGDchjSeVKmt/4/zfp0n0F
+UIZP12uXX8/c9V/ie48OIaZme1DcTgYbx6YekqWVPNZn9+gvRtFytuNnNZh/K7E0
+EJ29P5kCBoyeNeWeV2cHASPLSAWB3tdmZx36xB+lGiZ2rYrwKPFQMVoq7JmNr86L
+NY6PXW1LpI7vphgpk2NN3nOrJ576vHdrbaImyXoTZCWBZ4igBRxJ8BRQA8PUCdas
+JM00SWnuWcaKrqYLk+a1uVnEfUjG90u7r8XdCIQhoIGLSnLAONgAj2owbJGZj8M6
+dR65Kbx8203ENoMzopOM4e0+HSaWzw5U1LLoUssIw2kIAITMrsgs2cWOgV2TvUng
+nunPDIk3GmkWk009OlljxuEqk4sych7BmSITDtK2znPnab4/qMLPCwmPKTcexwxP
+7SvSE+oe12di1qVovfKIKX5kjCFtbzcDPV8oaoeB1QGgnMRq4A1v6Ha23rR8HCJa
+0PMJzaw6to/I7HaUu1xi5ujfjA6iijE4gLiiHkjTAuKGt7ad+O/LAqr+2vs/u2yb
+WJugdglJEk9viHfur0nY1ECOZpcxYCevuRXzZB6cwIE5drv+blPLpm/zCsRdoZEA
+bSnHrXl/ez8EXlej1+I5TenNvZoqTczNUiQbyIPfgRmY5+5nOS1eIJuH5LtPAQAc
+Uc1OaWomXgyqNYEueVB9KOgEZMqyHZ0InPML3YfEzUigx1fJoxuoihPuiVX4RqPz
+0VAKp4IofvlBvpR5m/hvmgXoRl9IGnS4zx0NnCmC4/bvvqQ4GXodbaXVnaPSBEC5
+Xnqc+S2Pb5nCBiWKrDI8Wb96zAULUzvpvklbcHPs8ZAXxktWBaXfyxPCWErkhlxw
+exGI+wDZHLi0RSJWRaiLixeLXBApwQ4d9GxNkVOVOeRba5Ydx/EpZXthpBIfms8x
+CW3bZIJxpw54W6CSp1eg01fZoVQbOD8uj6laOmPk8WSeXBOe2jKjKr7rnrfCdNcl
+69KCol700Ak7M1Rblblt01gWeaCzqZBk5nRPFZ7yc1daVBHfUPISUxvDzISVDubm
+wP6cgZzyqchsfLetIUzazwoglN4YoxsvOJMhC2VytG2iX0zV+5p6YPC9mvVUWvID
+E6X8o/7gH5bHG7+F/Fm+/0tH2JkFGpjeUeGjTOCcO0ukGWVQIb+xkt9v/L3qEH9f
+TIqOXLU5OPHkvTB71oC8N6KuAhpwX/bb3Skiw1OUm0WywQS3XWmhNNz7QU99RCCu
+fNVYM8qX3lewFi1iGHHSwK55lwRevkcLslKJaN08fof3YwyImsU+sHc7lf9b1TIM
+MCbjCeP/ONI0R+6lKmTWvYSkP+v4d91OgRfQWbzB9RLXl/DL+DEduaiBeQ0lbRcc
+3b/7NBOhhj5J+In/RtGtAVWsdesac9z2cC0R/IwvXiy7NBMK0adPhKuKcuC7VSN5
+EPbY9U8TYKnMlA+st/iJAbJOy7Gdf9uxPHTTsexp7YicX27TGV3lOIbDb7ETo7Ky
+DPCsjuQm7FhDZ5wWIpOoY1hT2OqFBnmIrWgnAPE/SKsEwP1rIKf36wF8oxDwqnJj
+u8HQjbqA/g+rETfFrQ2upKP25rBktXl05MVeEDym59GZRIYxBJnbTq67c79ToIpe
+zg0Wi7LgfY5A9vp0keUGqNH17XCUiLbT9kMi1jXRXU9UctgyOZSaP3SvXcoAPcRv
+hiLj0tUvEJOkFC+M/izDVAFL09Xewv/R6p6AIIQhK5VNmOoqcawyrtjuFLEAVnfo
+Wk6apJDG8+95NU+1ehyYmcuwALyf7pQLBsGVadnmritjH1s3SyqlgXdgUZ09da35
+6i6LKKOmOzv5shGQ7R8QNr3A2ykC7/X1zG8W6Ko5mvuwfeUxKSi1nGOf8BPGuwpY
+LDyhJuphVUpTO4bPZZtQwxjzdodfayyszDneQMsuHlupC0bM4MlKoHdF2ig9KJIu
+V/IOnFeEiBRWrRtvOV/e04lwliaz9IbhCW6Zo+HKZlwQFAJrfqVvlMvRyoYtKP3k
+wL3YWA++luQR7cD/GpCzplCUcMvqNOkvZGaYB+Z74k/n2PpwbqspQGEoqoykA9yQ
+QSrZngoY2bWDosZdH/3Z4VRLLNlw3pqXU8r/GqlUW0QG9vTX8I/bZE9aT3ObYwBi
+XRVP0H76lkptZJmUiZzGwT5DbNeC4Bv0GSjFjVuJrDmkPqQTgcjxur26eyIkoSO+
+PefpzIboxbQUIUr4A6IXZW7XO+K9htGI8gM0dIJKhhkqu43x8HKrvSURzALjJ1oW
+Nm9nnOKwEQUltRdsvhqbIuHF67mdRblc/ru57sPTg+11RhwnFql+0mIzB71I5dhC
+xCeJI1PTVcU5VKDToE+5tZltXe+8kdkUOlH34ZwhyaESQlyq7v5ArJWr1FlBZQ8m
+RvNwt0CDk4xOyPNSR9fFrLfyyDrYH667cXiYPwjNZ/qrt4mJGZrtsH/E9lEZH+hz
+RRzCOmb0LEPuRSWw8qMPc8z5WFA0SyiX3yS0xsnTGejOSDFOYaLzcGwXOaD54fex
+HzvsAaOnP+goj8BOoPmKgiu/ZnTBzfw8lIp/gV8cVkhPQ3xrcQcz5EDdV7rXc7Yw
+PHBPE3m77DpEgi6lhAH99g7xiBuhoZw3AZxtL06MFY8tX/UH/BAzq9x/jbNALJg/
+j74NtkUXDtVe2lpPLp+5t2k5IprEeoGq1aT4hecC0Uv1+jUQ0Ewj4FeyDT52erM8
+qkVYXm9FsV5WJu2ArQlXL+692obfryil92O8a8y2eixI0O4utSoEMLPk2T3k2VVu
+ek1kscKPJyN4qdWm+bbDmOybQq25K3JcB/oA3usLeA2B9UnxYIy0MIhil32Lao3a
+nfh82Z9DNKeyC4/ICwkeOnQdI16T3es5KvgL1coblJQByAopVLy1cwBlXvMZUhu8
+0YRUxi82R7F50BnoGLj9LeaDCtfNbRqp1MhfdX1X8YE9c5dZWd7swnxd+KMJ9Gqu
+sDQgbtpgPS3YXcF/tfIDW4gzGDP9xgicM/Afpc44uY7J9CtjM7SLWBtI2pj4aUSh
+kiREuFtzJK1eiQsdWUWiTTxAh6D2qkdvMuNGmxP8qc2W3wGmoIfnkicoVHENf9p5
+d2Yzv4BJeQ967OgsMA0Q30EgCzzR2YUBElbCqOozbTSsf5gXXnEdoG1rIWhevlDs
+pXi4koREu93gV7zEICo+LQPF2tXX1K6yp7uzWtoLBGR182BxvRHj5kRJR0r6whr8
+B43qLtwgNlBA5ZwW/LBG/g4+nF8AC/yegS8PKceQk6eoYL7sfTJtMe5mQg5B14/I
+DqWryeWkL6gPEMI1F7XbjUISHj9oCXhRe4HtGSHlDYSTJva0lv4VbNmKPc8sYxfq
+3w60b9tSQaIBurehUJoekPZF9R+Pj4w2p/KJOWML829VcWHikrERF5WpB8KOKwsQ
+wGoJ+8dYdnX9nM11djx7ZlLbKKjgTy91d8PzDWRL+XWDyNcT7SsBlMc9V0Edu9VB
+eBXyDPRqEZ/mFY+qeGgmQXvC/F459CVkfcGErmLOxgZCBa5u1D/yM7g12UWJnKyR
+Fl05dX9xqN8LCaTUA3QZI26VnXEfFbago5iwSs7irpCOLnzhyGAd8r60wplAEoOk
+rxJ5y0EeuRnSD4VN5g7lBxkwY78ir5FJOh24TyNq6snWq20AjwBNGNo8eUuFls3m
+ILcB9Pn1yoiHG5dUHypkwLlFwFR8aDDeSFgZy8Gh0dPNoWF/Ta6SWuQJdZvTr0r5
+RvNo/ev2abRPMeh+PyeY4iBUxwgeFAd0mkLhFWPidDqsX2icH2tM/ngEFHyv9aGh
+6Dj2I6mMZ32HdFjjGOKEYMey8ukHdMLzCPTNifQwNP3m2YpKMfeG0eCS/X1Lx7SW
+sFop0xvcWv/hsmbd3lwFn3N4GSpgfoyt5/brGbolxUEcAjHKzdJfj2RF8/stskXh
+izdDexY5LM/b1BIiOTGIxVP3dmag/lF8w9Oj3dYDaWTlQxybZAhpK8XVLxvmhEiu
+mZdFi9C/xuoPHg0q5k5gVF/PlS8fywPSkHD6uiG/bSdWzOefjWAYzEYlNKK36Biv
+Uiwvz2YTPgc7tBIVplSrWvQkp/VoYwwu5k+Vbc9Ddkqe3hrv2b2I6PCyu5hHq29Z
+2534wFlrTbg/QHzYGsf3LNqOYusigFAvcJbBh2ssP2elTdXgqBCknwNddSNE+Caq
+/Y3EqbxYjoeS0qL8Qs3OvaFLMOb6OrQYUqGaVqgZoFF5ocFEN/83Fzv401FHIRwm
+4QGxf7PymB3oqp/vLUCRQTT2hGHlAKjqYCRhVDNrG/elahXsgYHn/B6hdTm6nw+r
+tsxQmVmOdHWMpVhEnuIdYE5L3Y6ZmXJmqH4fh42+Yfx2bFd50IxBSygNtLAwSii0
+p9/cDSvAoT2ACyQy0xgEeS8nJHNR0B5ofxD69YphWh1b9R4egIosBO0G5BnFOULi
+Mlu0HGx66L8ddbqmbW9i8aVvTPAuAfi6AfdF4/bRo7nB57Q+vNvWJ2ODpB+oHuWJ
+Cb9Qi9xPBh5jY+Dh8Fqqix9i39/YvZtaxkr76eY91nTCE88Nfr9sPNqyIEA0uTAB
+1xi9MnJMZaeXYh50w2B/YAaPdnqux+3ceVeGGF6Q/OPpACTQqVmKKD6hurY4Xk0A
+jWADeSmZ1VgYB3lM6bzK1TnEkUY0ZvSsu4GsRLZNkR2YzQlavFoAYCWDHCBbnxkb
+DW7s9yR4RM+Vu/mgdOYXPgwYIUSsPht14gGibDBJ/ktoAgKamCZM4DTALIyYOV7w
+/Vjc+ZluZH/JqZaWnYQVMh2bB40JesrHAS+sEgV6xVhLWfLJ7lXP6Votwvh9Coxz
+Jo7t4Eprc9YdFqLyeEZfOTXbCA+9qlI9oyETaaJh0IhGhJ+14qP6ROVACwvlOc4A
+0FKjYDuaaU3qtYTO4VepiSU8jKH94qor2PVdl1ZXtWZibDD9l6JDQVcAUGtKTvCc
+5vvA6G0OQy2CSwUibQEYNnCD7z+R99C0cl276VP2xnk0NUF4j+70RmY1qu6FpIb8
+myq3ZJH8NHohfLbewNVFBz/UzSRI+iI/u1P8BEimbtXgGCMyiV8oI7CTG2Mv2GaO
+tDewRtkuMFRTXAL+RLkcxGCLv80oKFo2e+KV4QD8dS9ez5YnnzRoWmTBtnIb63zq
+HnqqhWxaeovEbqkWLeSeaxZahJOpJzK1HRXa0qj/XpcSlA8l3hQZ4gXUEHdUGF6R
+4kD18Ev9JyPxvI5368CVdXjcmAIbr4vDBzX9YJQaCkAvhCxibSdpW103TFSz+lLy
+gPfW+trmwJaM/IshLam61tJyyIpQEvLV0peFvKJGOpMU+pbn2dFKQ2xm6xif/Lz4
+o8r6qLyKtZ6haSIkejYpkDl8rOTDqtLVgak+R91kTx6gjP4Hvs3bBRJdc+DLD14A
+68qvrfFVIkqjjlqj/hCzwEQ/GRWnHEtFtNx8Glbp7Efm9AU5VbXCr3UK9ypSomte
+MYHxFzV5eQVm1jeqg4ipZr8MBkIYuW8hXESie0gC3gNYpgkFwslNoWjQfwWmnqoF
+SrylMWkTJSkTmnWNWaHdHjwD8kMbrfa1abS/DjIIcGKVZ67cKs4MX4jN/mIeAjI6
+PQ/Fz60efTd9Hi0LWgnsHkOFrfY5SLdysTo4ZEjOHSyq+a6/73SGTRIsU2aRXa4Z
+qmD05LarfRcFeWFkWbwgDM03v7EzQdxD1wsl+BWlVsODJmqN+LSftnnQuZC7lVLD
+FMH99ic8viCfwg/6LlTHFEdkH0qtm/+vXX1Abl5I6l6ncZF+gBM9f/eIZc+R5Fly
+WghsTY3coyy6N32kuSNunTdD8/R8q9ocujKuNoUok4bXswkgx4tQzKPavkKkFdi2
+1AiiO/yXkvgOAhfoCjm1NwWdQ27IOeqHnsw1UzF/jj5CbZLYCFcdKzIf7TZuL0V0
+h2K9merziOSV158nBbZ3pMhi+1Flson9HFTr7rRjbfngC8dGDnMAWgpJFEAoiDpG
+hblrWffpCIAIplRE7hqD7rcLND9rsSyvgQ3MYfS+uvIeHCLDIBhEWHyUFK7D6PjS
+xC77+hX18guJMcngV65UK8BsmMozt5FtXmFT8ruyMW0XfZl9PLwoDC166puV7tQ+
+8ze7UsUs22j0371QOFWcsaMoHAh+btQxuEOHYnPS3AL2ZGPwiMSAZC0ALXcJDMfe
+XZJqbTE9e0Egm+mErHmeD6Suuo5wIHuaVox3fd2gS2t81FFEDh951q0ljU9kMkDS
+VUZOXwz2ILEydbtaRWLeJF39/zvifVd7HSZJrA3boj7UVP3CRdcSSWATN+7PWqiv
+7a+TwBzRD6qgwS6cnGTUft1onK3lKZdI10veZFIy/7Sb5GtbpUge0pXLAtaIaR5s
+itNF252pomBAMTCqKMZeUnLRya8WKRBPv1sEUbE/GcDIeWJjDe3gSzQfZ3CN/0dp
+kj0c5qZCMn4t0glv13v+u/e2s8yIGNTxP/PNWHp7i00mX3fo1qUutFfem8QenK4M
+uE+P13eJNeHkWWbDGyWVyKmA2POGsMvlK9WRIs7cQLIKs/DFR/owGHjTeKprSvnR
+zhHYjt+jB4gSIHLSqEhKbdzGqC3SJ9u8AVBNVz2n8emka707sVbc/EztygHPQIYW
+dqp1xEK4wzkw6peCm3ilRcXj7OZVsH7UxYDqWO7LQz16NqgvvjUuLpSexVlB9DtF
+AATQQ6+qTshyg4FKezGNwaSFWEED8bX2nkAYRYXCbPj+OVFSGUUsSkf0fjk9EPxV
+7pBqRkiyy7pGWKbKwSXFLVdKNrSmOIQaX89Gr9ZteEd7DJwugeeFbC6rl+lJPyCP
+aVSKjI7bakiQuQlaJPGeE3zhhxNCg0wPpYQ2d160FkUh6QdjFNSv/IEI4pD6cfWl
+wz7fdoHdGe6fwSxWdFhT2SztExwlRYcnbwyKRAmUi31P8LQNfp5kK1G+8JPMRHUl
+Tg3U3VEjfGfxOwsZSDHhO56AWb/J8PLyRlWgyLxzLDjmSLrxizNmJ1dECNYNALOO
+sVUKFUajHmTQYDi1MF1W14YokV60QAQNeU6IPRHpb+2oaEwaTx1gaipX45Vp5sPm
+g2S011maDIXPGbPkT2DLK1jZhhsktCteQT/rfJ9MiUfLoPCy76iogUL5tCloO4bz
+eeZ1xvTRGcxTWpx5PTrWDt5n2z9qqjCPQUP1ONR9jm7TcZr6xjqxSW0RYiiISLdE
+wAwFEGgigcmuEK1B1ii3BUQZv9/HI/Odk/s/oJtlCDY7uegZ8biKh8gJABB8/Yko
+PRc5GPX0AxnF6aks3vpRYXwo3cWuMlmUyAEol7lnVEMUPN7nH76MSOwEf9JqszR1
+H8ynfvrOIY8QELQGktg/9LAGoBT6ghKfCt8l85KixC4YOD/kVW9xzrk4sAV8+9Wy
+KPLrGErVVGjezx7dW9XS06OGf4xN9GgLti9dAWxvSH7fB9j5Pj4yHEE0/4eDuW8G
+c5ibQxzcv4U9yzRHFGPwzNGlMfSFh7F/2adFHx9vGlVqOWgraJzfz72sR1dMYppB
+bZIxRdAwvPeWqfZzbNaK/8fA7Jtd4Oi2+ZoEfNf2+f5JE/lXTAIslW2Ju7PGdYoF
++AZIAoSRiJlcbBvcWed+/NeQPb6tvm7+O2BVZFJNPbYopPhUUqNs//Pi1tZ6A3zs
+8b3sA8o5yleM2wrDhg8m6MaMsuco29L4tMcMe2NccWpng9sDzKDZb8G5Tfo7zpCF
+9n6F+RBKHKNNRYEAEbpgMpjPbLm9g0AI+thMN2uCmyjW8kNnOhL05guOQkXgLEfH
+jf2I7o9HmgOaqaZRXED+x4PeURMB0N8FpUi+TafFsCpCRIy5pUbMwmbblqA9FKwO
+fEsomcFLf442XeqhgFIPCGMKyA877nrzLq2MkEQBfuTAOkuE1F/4xQcl/uPoixHS
+C1HaaOBH6SpqFDgC8P+kwSCAIM+Le8K233g/NF3ugQgIIPzTVgXAlxnd1dqpA2HU
+oSsgXdPaLnhak/z9VdySVEvwUkASoDkJEOrm71D3flJbV5k60CBerWjuvMSKCdoO
+JT7789jotMknT9bGWpU4oEVe67YfzZZ0sysmGKmk8dfvV2nRhCQcbR8CIvG3FNM9
+oOEtqEnkNVx3RSD80GXV7TYRdjuk3wEW18vIuMVasUOxCJykj04kROvh/Tu54dgy
+ht+rYOHCSbhGNGhhln7Enov/iqYw5XiJmEuNhYA/Yxlg/BI5YvEk2PYL5uyNVIp4
+3AYPnaGPsC7r8GOmMqw5NmsH1HdF2IqSr2mg+GrVZnSR+xlLlnJHomg8fH5IZ0CD
+yeQV01KwaEfs13wSFeGP6Wwe+QlQorEtqL6tDMptz5ttS/uT9HlqyVyUflOygOFj
+qSl450VpGGBJ0psfEWjlNnYDaw9l9PCPeWN5yKYWEzhoJeDd/yd+DaU0NxMF0HWW
+E8+5i2sWpx4RwKW06dFa/fDW3AROZtmJRhQBvoGIPSt1/wdwB/G5tv2ZumPk7agU
+5O3c7O7IX7aORSb7l8Godh9xAzXu1hDt5waEVhvFE7/4bvw8r1S0wo6Nr+awjFvS
+w9jZAXnjP4VZkaAx8TM1jPHmXMJW/jfp6Hv+8LMkaJDM4NNjbpMv/Cn2wBfzba98
+6jBmMJiZG3JGV2f/PoZHGLPkaBR5o0dL7V/Uv9bGdKRu9gi+4fIagRrOqwoPDHqv
+XfcGAFc/fF6Rb11bH3yO2kFPXZMQSa1ulktaFXXXkpL+DMqWocglnLiCcv4uM6Fc
+FFGOkn09JK4xEjsGjG0V+LQtP+FzWVQdAXLNmFdgf0BKxfbTwM3eRO/9RC2oa1LW
+HEtuRuoyLzpbIfzj1xQ4RUGsoQjQbTaIDqFEAS6RNXpVTNuhkP4219dRyY6ESJ6r
+uLUylJ1eTEvQKKxq2bTwlSS3g1IBChpk5JmvCsAP+H9HgsXu9nApu8Zx8+G/vGRO
+vkL/17Qor4zIucvoFa3mxKDvnLc0UkgbJFUMWrFze1eHBgAhqFE7sz1hWB1D20ZO
+L+dLab1bBe7eT37RUMPsZAnvUStIEqUzyfWONJUj9MXvWbILtf/WExlKAo6C0R50
+TQKauPMlUnmKtYAfwcWw6hbePWLZXYdw00zWOE2TvtzKgjC/Q3UQ9ajv/bvEJsMZ
+zK5xMnGVi7SVOiNpZnUV5fniDyVmgoKdPUKD5WHqcerGxNgTI9OMpy1kddT+D8To
+U1Z3t/qxoJeubQ2jc01TuPAVyqbunNmAVMXHsJRcgWsWxw6nVv6MuzjeKIm8q/E0
+ZR8XKnCEowR6qdZvcdJK157rTcQRpuNrEL345EzV97vhnQtuU+O9JhCngrcThpcw
+7+CL5G/di20y+5gGlFMnkpe19gWPZTDi9XWA6WqkVRiIhUiHvoqSJUclZ9C6c6cw
+dERkRwMDeC2It1D51Js3V3tJjCp2RGMPKYvjc+L9SD6BynSSwn18sjxwluFdEUMk
+66QHkCndkJFrXyHj/QQv/tSLqrv/u4n8gwguGJhHwAsHKhdQgL8oVINM7oZVsZDP
+okI5zZJK6sNQu+0wsclNZoy6F8J3xD2Msx2E2h1jLCJYVLb1X8YOCLyjnOt1YAEb
+4Ksb4PrhoGBh+g0mw488THfhYl6MGZuDVR8aWKnd7UvCxI8V6phSoRlgUrcK8o9F
+E5wLy1mESanv0Laj3FZC0CFnvIZ6goh543NQPd38snHad7DN/axZnYVw7TaDFNBY
+dCRz8pAqFzV2YZPSOsr1nvM4tUoBSGJPlDpztDTJTeF5BFleQ5NN3KgAmhhf5ib3
+k7KSsYtqjWqYPOvSZkNU/M9PFyS0O+6lwXm0Xv7zdVvGa5sZCCYW8r9r36hc7bAH
+NVF2v+lxqj/WRlMJROvq/iKc/gr0/kpMO0/+0C/5kmHYxxu6e4QS6OZhIOi2Cx+e
+/aeLiB4ZTBTUP8kexL34gNoS5mV7tno3IubFfVx2YwSD7bMwBvzptoQfelzecyKl
+msHOJRXC3KD0unnbxENxSLbmq9sEY1FB5F3sqyOWy3z1XqfDIBsPQQWssst1QN5N
+TLVHs3QLi8QXyKRJEIlqvD5xsZ3LdyrilqYzsNMUVehALoNjsGQkLkDuRR9U4D2z
+a9CIRXz8/E5klxWPjd3wTsxuBzvrfWG8qa0ldK52Uh7u/Fsnp8Ey81F4aAYVa7Gs
+UZP+o1I1RA/XuUVV14Btp74QPP0UOdtyOfofqUlUIUgibLj21q3cuA74Tl8u6EMg
+RsW6cAYkmqDO/RQFl7iGCYTSv+0yvrwGng96sf2VwG4n4AiYHeuMjsl9+0z8qk4a
+zQYXWwgx5FXlC2tzGjetC08GD5QGkeT784QyqvRA4+cLydR7IkTwtLb0xzOsiP6O
+WHfQ6PaGhQu1X7ohvWCdNafFW8SME7Lrc90foTrJZ9elo/RzSwcybZ8aOB0PJpTT
+v+ihxATkuQv4fRmHjPyIGGiBEKF+OYZ7aWBHmVfpRHgl2hRYlGU57cOJxW5rJnOu
+sHPicKcyzPHHsTkjJ71IOxpFe6spFH/GhyC24C1dNBCP66OX0oCTlB99/35H6P3x
+C8ZzILD575Pb6eYYjtKbEQfC2Uy+USEJ33rNYHPn+crkdJiVqiNsBS4r6Xm6WlGn
+uw5ATBAerW85Sf3ud65BxDnfuvKGwL+5yH4LAl5iM94PA7248Xb8n1CrMvIANdgf
+exXastOq4KN/GvDScUw8q6CbK+ooi4j7nFdaOO1eA8oABJWzjbhQ1sAJOPoCgkqZ
+I+cEcG6i1GcjRGIqUO8/yd4WfJ1SftHA+LdA1R/8464vgN5+FYL1j8iyIdRXU3/m
+O/We9et30HqG5/Wfwbs+Jmta0fGWI+xhW4vYUccclpK+BCVPOOZ73ocgutlXZrCw
+MwmQ9WV12pUV5v2ULWwSgOF04vKMENX0R0qKiOfWzaneqt4+JNbjoACZGr3KX7Wt
+mwBN4NAYNYDG/ieWLRFk5THUMtSSlatZ5WokDCG48XdtqPioVveUB4j9zggz1YDk
+ZQ2nkbdu2WpAGuBAXc+/gy0qumfJOT9Wm45CL2ra6ozDgsIuW/pEaVDQ22lRle4t
+HflQaIrxvfF4RYExPZd5Wcq/ql5BZoGe84030UL90kXyzcbhTISDyJtr6BoSzjHF
+s6tkmf3pCu1DSvMiK/PXdVVYWtdN/mR82DdFXMwyK1zDDRK1bT454uC6mJ4+ub6W
+STn1Cwj2zzUb1pU7uKLmeHPSLBe2mHUePMCcYBbCF09lLWEUn+aqgj3EVGsNtszv
+gf6LsY7l+iq7pVRFAEPYPllQz3uXJjxtnKv4+1uhORjpyZ8adAFrpC5hIZCM2Vdl
+lj5pXoJbNBe0Cpxwnf02i7kdZmAZz50GtXFHbzoZMFfeUiIhpVquvwV2CmhAnbeA
+jrZ5xh5dFJv/5WtMX3J77U8rVEMNJFIjGEVdbjKFHucx8cH3ZqvB/6z+fF3DFXGI
+ZDXmOTMLXaN20BZ8xTqqnd+Hkqjkfx7HDHOZuCBk+4oQ8YBFygYilWV/iGcp838z
+t7wyFqHV4A36qz2U5PRKLk50Wi5xfDSMdCv1aLepNl4j+7OxFYGMtU3/i5sRMbUs
+PraBFzpWxuRTTSs19EZejghUj48eiVj/kjiN4jCMx/87vPLlIzCMlw3Sn2OqlzfB
+9Tr7LfJGwX0UedJjBYgl50ATNPBq24FlO/gHTWwK3orpHOnFjuNiB9j8xavYKcLm
+2+ie29DpYvloojZqXCDlTC4C2bVWhcaYTy7TZnhDWfVCz5q/DGbtuifimQvkqXKD
+afqS8516uqW3ZB6iJWy6JyM5d4JIx7acrSn3mwjSuTY3kHb5sMEfsUOsNyuq5kZo
+Am8gqYo7d9coHfFX0/UM31dcTIjE45NcW6CoYxSQpK0KEgoHeJM2fPO/W1JEfy0+
+cpxP5YoWlq2ozgEkyZDIy4Muy9rUxgQKZqpVeBa7Nqp7mfJLzVIJYy3G8NsmUF9C
+XI/PDOAyPKZCAxj2sWGwlrwd2bEYchpGmK+2YuY9OwxTwm7N8JAKUiz10yU3iiz6
+zUuh8+9yczXzgHoVEie046MOz8IXxNr5dxWYGZa/8lDhvCWwxFMo3oa23sxJn5b/
+VoT7yijxW8ipk+1na5lwZGvPJIqwRp8m7rZ/nNSKvYCsJgbAC8obbHQz+OeJk9vp
+xuolVP4souAYhpuMv9I2J1HRXL9Vg6m4iTpx9ozg39ga5DBeuE8ZhDqKnmH8SE0C
+ST/v+nnGesno5ls+YY6V+v1fKuItB4b80G90jQagWGUneqYnBA3qu8XoAaRmlPFi
+m7/nS7O8bgCZ2sEcdq1N1U163X08BuMYFzC3RH4ygdjqOH11ZDu3GBSOqvgK9hbn
+1iY67DmQZQmru3S9A8LzYjuVI/sVufxeP+4H724zV2NrIdfOnxaSrlWkNrBQWkx5
+wa4SpRLzCUXGfaWMhG3oNow10QByzcfpdunSi93RKCxx75Yd5Z6UfcgKhRvnLkCk
+4OHmexs0RZhQxsoM45XZKQ+o686O5fVx8b6gfNYnSxE7YBr/r4//IjyiDMcQRI40
+ppv5xVJBzPQp+GjfDvDo7r777ZFnOkYN/arbd04Y+gSMnWFjA0S+CiSLSyyRGUBB
+YTgtN9RUwU8nFtapOszUszGcMhw7tYgWdtfytNZCmz8tnTecfHL/HvbVhqmX06aT
+8YA3jZYkSVQk+ecKkpu2dSs4nQN7LJm3wdILZlmRDNpIkRtjrB0nTT6duwMUZyEC
+yaE3Hg4bidnpLlu3auqmRPQrRGhkCIgdc252xmgbqw5nqkdfQdLQzSY7laUIFkxU
+zrmmrz/PgQHmR2LFUjbbIsr8rH8PyqTxAuAeBMVLCSd8gRiCEXIcHg0UmJY1un0k
+XKUz3TaVlZFKmzMphYfjnytoW41BrY5v7ot2mrektXVGfZxrQUH0HU+Ew6WkQbYT
+64BsnnHFiYolTIh3YtZLEX5K0naJB6z5f/uMQKbhSnT83sUk4W7MC98LA/50vXB3
+26qR1KAxwSZ5YTSMoPiHPiOGnifrSxAHDMhVw931FSkKYoD1uGeL/laazbfoGZ70
+hrzcbYgl3poR3r2BJ8rJGV1Lb6xvmTeS4iYMm39DtfU707xJmAAe662Us1RN/IWx
+JUgkQTK6ThY8zJythWvdnBIYllOjC8W8TF3T8Oo1wzqtqUj8X6dw2KSdGTvsaByZ
+vRyGwBb521jdHGAmnir0jYe+qPeFYMlQM5j4WKdTI25ICg+jeEh9hyWr1Tb68nbt
+fmqSkUR2n7cBd21w7cq+iCr9SxiR5pinsdUwtytzmnRmqyuL+bDDoXWwA7XtN9/5
+zFnx8jEQdULKeRuduLSg+l+V8B+cNu2A/oN2w9PB9EJC96J6rJLgDpF91IZqnazI
+yyQb9hTVGCz7claU4y2pjRBSrlEr3pxZuWzkFIyo/RUsq1e3tB3XgG738rYS/EV2
+Bv2yqFkwhELJijjp/MXqYYRUp/aquiGYr+Z69/jb153xxAldLRokqkK5pepW6yoE
+me3xyHM7HKdIHnyl6lAH6BvwQ1xxPZDWxPpIxcM+iXMPLLEDhxBU/owxsrvnMvbm
+IF9ckw8HUNiBDV0Jo3j8g3jHCE7d20G15yFKabK9J/1bxPx4vOcOxiO2GNJsdPZ3
+oFD75xa1LLqtu4YprdLqOJwVt7Jdi+5rOpbZN9uFUDrrGfMOVNLs5Fy01xuLR490
+JiHfUVolo30oFRVYVvLV1e+yjBdMEPHURorBkxBOCe6lQ1ytehqd3Qjs1VZz/Gyu
+TTrgjDWao9fwMFwetsaiMpNIql3UR81r2uDFbzV3eDB1yDJ9fQ6IVM+yLcWdCw5d
++xacgSS2vFGuUQsjMRw3GRWHEHhJhJSKjCQdbVRg4aehltibJVcXqeOOeyFUXheC
+1r7JD4kqolNHgd3rEGv4Jlxv167q3KBP1cSihnWY0OqLKL5Hc0o9YKqIMExcT5kg
+nudCwBAbW77nTMQvM2cCoA2k2BYhWXGs/N81DTjUgATXu1P/SqnqA5qIQDz3HE5F
+y3e4t6xkRIlpFKjDpCLOMUnWEwiP/JgTjKw07phmGYVPsOsgiGACrsVEuorDw1EK
+gxNiPcwgvb30Yd1kaOsTvURCF00il0TgXCcCU9yKSVhjdvHaczO/FsI2Vy+ZI4WA
+kUq8f9cQsUOCGL44nTsjwy4CSxYdv1fCTnmvp/mYcEvyfSy8O6cnsA6FIySu0Fft
+tmAkqPhor5tUgiBeds2J2OBTOGkdHxAl+YP8ltH9GezHHE5wf3RM7CicdQtRpyxg
+yRJl9StQESDegueO7391ZCg0P0dGt/tHYuSNxuguvSDGvEM7qfSQiXLmTnyUoi3J
+YpAZwlQRp6uWb3fpDewGOmIf+CxO9WeSi9nEzjzlMouks5FIAC2zY98qZv7OSbgZ
+J4vjTHJSDezrdny3pRRf9DiUGo4UBkcNjowHwPItKqwv1HK4sy5esF6srAGu2MSu
+Q+QNxMR+GaII6oL2cZODb0SUgMHlaNeNOiL3VUkXI1gys3zCa3Q/QFtkoigYRm5p
+S1u9adpZGy5LEdMvzS+wQ957srxJ/A0cAP194Gf0RYZPD3zITgsndCJ679BzkopQ
+UJTAcRZIKGsiyRpUNuLrjIVLKLzkahMN8IRdP+BraU+sgaZeLZhfGZKhg7lzjr5I
+YoFX557HuF2RHJoUONJ1lXg6Duv5EslNvpVE8dNZ0/+zDvyWYgTXCoPhdU8UbQNd
+EBDD8Z3J/ry3RxjLtIVyZ+bUYosQaHtUkz8rdqg6sH4BtrFy7P+Z7eR0pjcXXO+7
+1HhUx1MUeSnXwIPxRtWDZ/2ZiYhyz16cBnXg9gMaf4wFhzr73jFgC+qmN/euAjFc
+YtDUci3Z1bsOixY3LmfVhjV/fzJ+DAXclb/5MXJL13Ht+kkKVQgCeIE0CzgxAZNW
+2WJHYgVqiIr5mf/MsHg3aNuPMqtHsVWb73Be3XMOTyKvSwClBihb1qFggrM5YLd5
+CKiscXzF9/nBQoTZvlxWhTuuZfsaeDKIi9sw/e4e5GL1bC93DmzFieYtq9A8b0FO
+qsMKxTXHFgI7y0BnVkATPOzc5absSaWDWi2RzgqcPy8dECeKUE4Ott24X7EAPq9e
+wzetB3xhV/Mt/yII5qDHf8G5oySJmgTdtu9IFe67vQeSCJKpz+5U6tIoM76050fD
+jmLf6jIOoVe6ovku2ehohHeYLyU3ydaR28AXrdS7r3bP4DqL6HNmvcPElxxCxexM
+GJxigP6ITbx05qPQg/0FZjzR8re6OdkD/Vxmay4/uMfLM+X1Hn13vvIg8Jyrysm6
+lntGiAZLSF3IpvNhCXlwi3n174v9J2cI/mHDeqV3wgltoTIsReO1XTZZ3gUlpdus
+1cPu/myjU6/WXonl0OeUGXKT4AWA9X9YiEDGxQ8vvKgFBYT0bfxFn+tNcWJAnKWa
+JuPkZeMDL+DfRAAYmXeiSsPfxN2FbOrbh4xGRIO1ApBFoJXwzgwb2bkFwfBi6NL/
+Qr0jFsb+cCdpLwhuj8POQOISA6GSbv9P+DIJ19vfdJXRIGDnHCOhmu7geRCY+0me
+ImdqP2ERELYR51Y69o6ug7P9ydjnWSG/7RtFBNJfYZLoM0902Bu9PnPyU6mdhPMx
+iCHY5r1njNmIji8w3Rkt1zKBC7Da3Rt0z72oDEsqCReLtSa6lzYPv9QCUNhQB/kb
+N0K4dD1Ibh2seM5EQswAfSPZVNHgX+PsxR9DjrBaSWRVW4xAxlW5kWjjLy+bAfhy
+VnnYR29hermdtB/wcs1bByJ/5LYWLpsDNUn9a+yfMRwjgwag+kBSguyaKJXB85N8
+fEc42XT9Zi8YjrvHpJYKvtUTpBYrbzhIwKK0QCorb1WrzipEbID6LuYO1VG1Cfam
+oEf43blDDzCrk60ZK+xL7xjmdkzJCmDFGGxgnM1/yzSgoQvxrzDInZoyizX6Sfe/
+doqQq6Z++QcMTRZtF9eqIo2kPB6GTWBzr1I5zoLIh3kDssUNegOxJtaSFcq+fnTg
+b0IUj8gBopmAy7QoKkrYrXEZf/OojcFJX1OfW1rLIZA9pOT5kRxJmo8VY4cukgNV
+8QLdmUw9OoDRMa/2a5CjaT8BI18XnjzOLXyENao2wvI2tGFi4Y6TFYMAtUZeeSjM
+NHmh+UBwZXkMGd+GyYRGk3FoNdJaKsbfIVQumyEW+gNVcwdtUnxt0Gw/hRpBf2Xv
+fmmYqbohtR4I5+70hmlxFRR2NAJlvGSC1kGb7Y3P5S2eDaNV5luJN2PGFRj38wtT
+xHMCDWtVH4+fEHvXteJ+p2pNGnXhzy0Xitr2c2Y5yK/BXgT8lk0WeeFWsUVm6oKr
+kc1cS9odr8sB95StH6khGVtGgD+ed8aux1geCuJie0qK2V9vb9BmWVoPHvmeTyy/
+Zz9iQK9+rHr4xmEbUdaIFgr4X3cvA3aHNnhxb1rYgWTkUGaht0NG+pd4i/wo5EdM
+vVdtjfNEyElTnTUERwS1/9fZgLjIiWsPXTZunPTmEB/uLHgDYEyHLDZMhqcsc3ak
+X0eyfOCp++zZv1leOPQTttPpkAl5hHhV9yziVG1O4VEoOFZqOdJVEeR0SuyBJkPv
+VPBHqE78vT2McdqgbeTaA/509ksKINI4f6fOhEad7iwmTSyfArxcr5XNgw2dxOXh
+upRD0LPVBZc6y1R5EC4wFN3ODQjr1TQo/SuvkCoprmpfhZRnNH+fUteImDSkXfU5
+eGBbNuCR2+3dbjkXUlRuHRgwRI5zwUp0HqpwTY1M5VkpDeldaMWuD+hBWb18PeFL
+gelr4XoCjxYjF+KfdZhXiDCKl475U9V7ICx+lUzCmGV9/NVIsnPjRXBwEJgtoZ86
+MejqA4Dd3rCOH++bR44yAECsoPKZtjD5w1uyOanPig6N8/w14bWH7SUMpnuBnTH+
+qVuTGP0l7VMytvz+DUl9866pCMeZ72ugkngBignxvL0cSVuQQfX9XwgpnB4+uExg
+Cax7D1fqNMQnpyeVceNMyGzNjaTWgUGgJLm01QclIRWR1pmLeGHnCjaE6CpRM4F9
+67Lzg9PyjkL661OT6x1I13AvQWxdtMqeikrIVI7eUiGBs53UjTHTGoAJsDiSTOt4
+HqggevHzVM9P6c2BfAFviPgblXiQ3lKsm8ZrAhsucPp9I9IN1Qn8Zux9VxOX20GY
+xjcWCEo1LTI9G8vhCy9p0It2SEqGZoMloKIKjLiUZGDjkz6iglokmbeoXKnlMOD6
+anVpqVhsXApfEROzsnb7qlTyt7PUdZtH8YaqyPIk/jPR7U23hsAiMv3ZjO4ybBRc
+/EiPV9LZl+E5I5wHcxRqG/ZqHMqxetp6uRkroG4GCLBNlZ1ISkZOAi3z3g+74Ghh
+ev817mkJKCHsuF/TG6AOxI/JK53818SG3+QgWOGRuXkp51l1u8W5Ge6GfouiYZD8
+x+JH9xccicJ9ulp46fxC3LRmTQ6Kwtl0fyMExpJEefzNgfFpxRyRC59+Bn6X0V9H
+tGPbYe8xhS7TiTqxX71+hCxdpM2Vikyuu1c1+IqYT2Pvk6jzIGmLETBeWbDgEO2q
+jM0wulZTTpseBW/94ps4Qesh14aNKC9sRxhOxKbJfzX5x+SnelOltAylGb4BDtyj
+TgkRYHQ8UGHN+kWhp/BRbeAN71JdYK2N/AQ94Q7Wb6DUccybUyKT70hSDPo6Lx9x
+RCqYzhJEwKhefSEmqZfZ2YtDLAx4Zw9Ub6K2Iuj0GAUmHYHRslj9E72OpETMeSvp
+7Jt/ZSjdbp5umgQyvtnbwV3WLU1j+YdKD3BGqllTPt6hXyo6c+l03VZGWR+ydX9M
+ZD9MltiIozbYv0KcWeDcnLaWwtTBs6vrx4FVs00NZfEbUvoVsnkJqdZa4BGaO1Kv
+FyVU8OAa4ozZwDBi7nz2AAK2pdWvyLV0NR0eTuKJz5eVyXxO43fu3eqRIjFg04Qz
+R1tkMNn1hoECSLmrOupU0KpoXuvabaTxetDu0rUCkuEwI7FuHrEBEtEMuQw3U/5Z
+IFmM0/JqYJu/SRY0RBKlsavt/zkLAqpKQqJefPSI+xZzZLyCeYFowmrlKD3fYS7g
+vXJiO9uSuqFN3XXM3/1Y69QUAqeS+Jlx2LeotWMdqhj0edyki69L1RCGTFFEFWGx
+SD34PsC+jBfV/NIz7JFcd2Q3HMtnOO3h46gpJ6OWpB5N13qM4SqKox5+RpE0QTid
+5QyI+ERFNsdCecOyIXitWpiyHcqxlVXGzndLB3Vnmx/+fvMY8o1P4WAS1Jtt9qF4
+U1W7EooVFkO9kK1Vdv0sNw7t34mRQqkoUdQ+2Io/8il5E880nSfw4TcT+paeQ/tR
+0FBBsCQ3xLxtYWSHFPK20YT36ge5q/gqrDHRxa8tnChxswr63pLpCZzV8t1vzxGq
+2MITP82a4smWUomISBWCPOivdGAy4J7GU1wEDsvnVevJ/JINdMjvoM1jyPJm/Q25
+ABO6G5IjJA8tyyxmLKkAja+TGjqW+riPGpL3SYG3prdOCFrEfayU73j7/O/AADc2
+tkuthCwacd/1l8w/M781bLSfmivCir61lfNlrAWoYlzIJMxi7CnEZLWv34thQBrM
+4CZPgh+CNZnR57/iXE51eVrlhG5buqCx8L4j5O8ZohxkdSYy5hf+tyWMErJH1KjD
+xPQ2XekPFFXi/k+vC6h5kw3UP5x616zS/Qh6UkWfDhSI4P1IJDMsWyEHOggm+2eU
+I8IsqmJw4SJ+e33jTfeTNY/Iqjxm/RvELIkNSYCmVwL975VZHyuAstk5/ZvUJkD4
+Ij8d79FZ6Vk9MSXwbyNnYD98CLFYxryDtUNT9afv/dAgrFEqCxS6QFd+hJsNwSso
+pqiEP4bif5NzZpRYCYitQyGGRGtLAvo97OvJ7ccz7BebrxRK3qLBR7KRREGxdBWx
+NkFARfD6wRfbfhIqGBFzS5yTvKtPB9Ft6wj8FWpELv+nex4gLJqi39X0Wkcwm9o4
+HtqM2uw4w9LOzgIUjHIRWVCuzN3PHg1bkky9KKzS2wZ9P6ydm8gnpDVyGTlWwpqF
+gmMwxiyfLtdplNEzufRXtTGi6LoT8LLwvNM3JINzD20XEU2kIqE+QNRE+2/2ba3j
+2EA2F+SKDSSOT84sbEmZqdaifvlYD5FbKn7t0Ek4ST36s5YMBGo0N/qEkilYyaWJ
+E7H7WrZmB9fvOrciFhgxm6jBfCx2GQJM8XKieYlj0sd/KHBrSfU7Uj/Q91lOEVUk
+X3XzW8V+yaWtVJDWPcNPiJeRcdaDduJUXAJGwHXhH+EYT1N6LGooDVVQVTKpE7N3
+IKsmffCFX36BwdDyWBDV8guxK/9xPUlFlTmBc72WbsACLP3cQ63MEQ8+iZ/btitm
+17BVyzQPtf7AP9jeDgayH/vvJmxdZnq7/XFGEUuPZb7FrcOE+Uy9ef0yDEuVBKz5
+0HFCUyyrrg+4SA9ZClfFhGrE+oUttY35ozdKyrRL2cXWWgZvpSEvCta5mK2UKyPn
+W1Gtqnj4DwaPDRr9L9nLUYW8al8mnX8dwQRAFEtBUmbME2jjMcMtIh1TfSzpFume
+r9/dapPQkCrbB37HFF1vgzelmdMazB1t6wHbclMmphevXPhVjxL/Boy4HyLacDXp
+5e5NnubQFiWRTRcUBrZgLiH9vP7VGKg6VU0167ayM/aEqt6b9HmvSrhWYS68Ni22
+jixoavdOVsOMnbO0nx7gNp8WUbiIMlyfL3XlQz5yp8wWXuRcOSO5y7DhuRZSWwSe
+nwcJL94Foqz/7Jv4qnpzOvxDN/XLofXa3lQPVtFqy+3NShsNi2kL/zkFGDlUYtV+
+KzliGSXyjjuGBUrfxErXeS548h9mWjeom9BvET2cqEITKpKHBTpGAxVgZJLifUMN
+c5tqXdFSwdyc2Jsv69H6Npxvm3vGpf7cgv6XJM2kN9hlZOeBugCIeuBEtqxIYIod
+jpDBNFhpICFuARYlrXCe4FvpvfKlgBlAa40VBhvTHS5JpnsRcJMAh5Pm3w5607ua
+G65NoIu7tgop0YuxZBikIawM7fKeTfh4U72zGMcpDKYDA5KdRJ0UUviwj2IXdMAH
+e7FD2FIF8copGLuXUmIs4gn49fnm+eb1fvvqN5UnYlI1qtjIF7zIHqh40VMaXAxQ
+g0Faf9PIE8RsgdjwIqLf+/Vzpr+K48zkip0nv7QyN6Y4Z+Qju+/Mi/rIViWBOu6h
+YipgpnAfucL8jRvBEYOo12sC4Qsmk318aOuoU7QhDxr+g/F8EFsPitTMh8AxeO6/
+q1++mOT3yR9rFNKsdQMBWrrMPp5+iXMeSkP4ajDV1tNWHqa4zJ6LkKvWxF25UE92
+fV1x3g7Bhs2e5I8HSv/ZwDCCrapL9OQJmnCxv40H5n8Rhu4xlUSrH91ofGIYwCy5
+YWB82ipmO8szklSxAPhqUsPn9KfVs4BLtF8pPNR9xl8YBfTybdmIM8Fa5/54ksfU
+WLiGFBCV7sLJeW/A5b4/sgDWZxkDnLI5P1BfiInbUm8vxzV4Z9fqS2yej+tPP0pW
+2HFoZrRxUDM1l9nsE76r/Tzg3e0e91ET+YXQpWBjc8LLFtfogZ86KlRkWDzQTO6z
+2dAiPCPDWixQWSzvbuJVeNEIAYa5OBx1Ach/pv2x/XN8xaPKwTJk7S8w+yvdQU9q
+0UT4/5OAAcH+bsWvvspr24VWO8/uyAeArtnunE3TwN5DqiBcevrvnYk4v0U4DXVX
+gBJXt1PVkQkj7Pt38CLVRrPj6usfEOycc3Zrj1SF7yeZ6IKAttpv/UOWwS3yoJW2
+4MyVKFkgrg+mSh1f6+/3IaEuh+3iWoEdk6moFXYYWy7un3aOkNQ5/97Jq0ctD8Ep
+uJX2k10mhZXRTN+qC4P5Yto5eGVo+AL8gy1dfnCev3AsxsRj3hUe3UAx2w+yqewj
+ra/xS7w7f1lsTARJpDtw+rRjBOdkYwn/25/nkMmHn9i0O3z/7R7Csl0/Sxl2xUCF
+vMMlL8ceqHjd5wzL6krd+LCj02DYy9EwK1gO61bJ89qSNfwSwZaKxENy+81khIFc
+MiPQwha86GnSsmEsH2lc5gYHg+01LI3iy33syVjFJ7SozOzJNKivoLSvFMxkvYNj
+bNM7y4bUTPSqbcLnaxuAlWTZ+jK3tdsXccW9vT1gCrS+oDQlS+qI4mXwhsVc5HSS
+ybxxt3sptCg0OGSGZ3fM3yJIPYLu1j2MNfLKPDU1sutTzUrcakO0utROuXOy+mLB
+K9x6/T2xI64fhQZX9y3fMTRSFB2c6Jr5DJo0w1TcKRwGqp81I4QSWyb0lsgoclv4
+Z+RctUirCdHCvK1YYtCO/FVjFg8yNHEpvn9u4TCZaMKZ7O4/kkx4TpmFS0XmTeqp
+ah+1OQxJqbFumJ/eVrX/8YfE5WlXZRCctMqZGTwHFd2ARB22xUwBWvlxIvh7/HT3
+ZkWxhRugwvA6v6t1WkKdVh8wEqvGPcdAmiyGhegIcQB9ZUjKvdVAwy95Ysbcc8M0
+epnNnMrPZEXhiH9sks7A3Hzc4cMvePGx689TDH1QYuvLL7OT77hwRBg7o/FOMi5J
+vQWZYZgPh+Rw7rOg5PnHNGt71p9V4baFMW3mtQUJZCCaUJUt99htXZL0fwty4skd
+7ww1DU3nlm9AP8vzBMyCU7UdG4ZHqnY7oLiqooWkwKjIcE85DXURN1ZjRj56kbU3
+SpEIqYpkA/cNZEiCSYQfqsnzPiWd//zbtNBLEy0U9rN5xLwOPnfQzrt/PKretKN7
+QTSbTVPTkV9v5QLFo/wfsTYgg0bpwNyv9MmQI3wjagz3ffeBl90bjIFcHbg4UcVa
+daiitKX1hAhTVOAjns7JlZmLHy98Xw9OQuCzo3S8h5QAf7PkehfClSasLBp5OEJ0
+iot8gwQFGKOBZ2BLidWFo/gS2GjdvLH2S0A+ZIH+Eht6NwaRTnifzkc+QiKDth7B
+kHgqIPWbF0aMN+Oa5qzmGtA+7q5a/3/ywhsBhJrEz5pR2mPOBLRgmrCtskMNTZ1Y
+g5wdsZxBVTtBJf/KRPsFbzRDGwR9JouSF3AOAP6o51FhQq540vf6ZYWSTtDbPtXx
+KEZ5opsGpLqkibQNVuPKEjkKf4n1lpGUpbmcOXxknaEkBMCvWB3YdDhnfAJsUM0u
+tU1bWLULDeOUewcA+5s7cPFVaDgMxcwk6PVW4T4HmIjAWI19upjUh6r2iWhQ3kte
+5iqtZyg1CujXKCIJ+5aVZc5sbtqeMrMMPe7nLErjD/aZPdU7e/eodCe1Ewgf9mhN
+8QpV/nWqNp7Ois/wcfggkCOwqrZvkKlZRC1tCDBVj2eOC23G8zdo8bMkxog8NTfb
+l8zUXGy5XWi3AaQXvRLMMGy+oy3XJ2TZvrDhLsYHbSNESWSmmchD2DUGVNZfTzjP
+LIRBbbwmaecWjFPqxT/Npmg9nXP5a9/+gsmac4ZvqjVoIO+1iXUNBlmM2z/hLlH4
+baMaM3y56pNeRhoNTaU9ObkqKj62VFXDNSAQVxj1Z07LxKZWYDqZ9QLnfAfPi8I/
+a5tSoC8ELng4EMzwfjz7KdJp344UD0W8VpYKP2CjNANqDy7WXw0qr8dzcz9c9Cbp
+dJmqOmQ0KEepzHVwdL6TJY2sdt+g5w7hq+7NqgGtMora2U/wnXopt60p/zFQTZr8
+JCNzZqKh0PNA5KzBwHXLdJ2EI2j+U06U25eLMizXFAfytpJZOktxsd+vJuc8tsqc
+E9KzqnoMyydUwM9eYQBs9DBPiEy629H0HGsY/dnAlka+TgiIdn+dT8PjHeQBVvMt
+cn7TqDsp8R06Km0Oea6C5ZqKHLE3zTFYpQbwo6Ec7J4wJVhBZH6+KVZqHqS867ik
+3F9szIq6fh8gxpqLwnmMjRMDfxVbs7jyloJzrAtZ0lhMX/5DwZFssoCpE9ABU2gB
+TPNiNprLeTOGNzKRS6i8cvMlysvO0Z/fqBLCIYLYbC5w+IJ/9cUlYNE+0oTRF0VU
+qzFcQMFWyFFi/WI0zD8kCZzjI0n2SEb6s6pg2jdYcOzRFNtZZ/E1dEMDtvTtUuDF
+aaqlYAXlVfQG+EpmSDJd5Oon5msoJIYONATr05RfbmE4ZGwUXKZc3Ls7N3CkhDPQ
+99gFnUzXkA0Bcw2VtJUcgD2dWi6CO+fmq5MkJ9Vha/2DwfBTfuo9YVz9LvH9+QJm
+gY1f1ZmEfybHwH0VbmItwnZBhR1WXp1ghM5vhkm5GBXIHJUwDoMAcYDkAetQo/Yc
+RctWBOF2zwVbAEB8SteRQnY2EPs2XQrBPwfF4MDh3bEf7kLrGcEvuqU1RB7FQkKw
+Vj3ie2x61UHOkMGHtHa+Kg5RWaxldyzFcX2epp8xCjfYg5lMgCsHpd/S2VsHaIdP
+UWDYWZ89PoNcEINo1mh1tRcCV/wbhPdT3I/q8OOp4IW1yDBK4NUJQDuS/DiNBfR4
+NmtoT6XnBJCvuSPCISY0xeSGDcz9E0dPNAlzkY/LQgdtBHME9KVjeNTKx0pQ3Juo
+qOpFq2Yvj7VIKeqQCiwSY1eME7vQeVqxv/EYIbqpo9hKguQ4gHk6ReZrJA7uIIAk
+mMVgReGxi9fdH5UrCrmKX06AGyKX+txeban37ZdPAo171T3IYz1xXfVA/g/hbF1C
+CDT4OqtDuLvLNN8YcC0uYAVkE8jmwzQygD0BT21Yt8TpWjmZeBzKmkBA97+U/I1l
+jywsiyAXlxG/TJxRV+rG2WRMPGZ93mTxLUdF0pykDfN46QKf+NbNc7Hpoq1ZYI91
+Kk/86WmfoDmYmmGiqBkzC55+bFS3yGuufbV7OhVvnxiyZ5XqZPTiqKmylBb0aEHE
+0NLxE4uzEbQ+dVVMYhB85q+EkAIpgSiEExMZaGO4LA8Tapx3Tr+v/EAM7BmIUK8m
+S6Im1+JvTKk+cobJnA2HlM3WoN5Lu73Hh3y5H3c6T3YEr1eq87iD5qZ6SMCMJhFl
+6OrPCmGLORA5QlgYOTe5352kwHNAf8uSbNfMzsv8OBICdF5aTajIgOQLISCBKQFa
+HQvEgPpUS1O5FWH7eZyzRZprWUBTI2hCObYIkSJPPLcgAxdPCium/yFlEs5b3DTF
+Aul1iRYNbyRMbSN+5A1jaXo90x0Wgy7+U0Y5xBI6he8rTedxwfb6ba17xHOa8a/Q
+aDzM54qMGO9sqoUwY/dqhBDG8sfasJFZmPvdynY1bOK1CVECGHO4lUnU/mHR+ZZL
+53giWwIGjJKqyfhJoGRFw2HfFav+k38kQfOVJPhHtLqkeqBFigKDzcSNNakoCNKo
+Tc6GED22L7u89am16559jjAmN4qzNzCnVxt4RDr2iVwYVKMZWS3vge7XuSGpPHBy
+2mrXWyPvFhHkoGnR0bq9PpC8Rn+Mn8W92yb1ZsyTFpv0TRa/CunSGZJUnve1Ico2
+POZxHXmJVNc6bwJ7EG1cMNqs59Q8CD9qvPXyc6OSF1vg4GNbj1oUL1p2x0AOdjYJ
+/hC4lPDjjNgz0CG0h3eYVN+aHURxafw257RHvzOkxrsxNceccnAHBt9PU3ptblsD
+F9fUevPPggCC/VI+LdnBWI5U/8/+yoltUHmEEIcm54zlpZtDseYveUBIfEbnAF0i
+kNCuInprOUZDHkYS/lR+A49pOzyr1cCRMnc21bddBF21Qd6D1U6JnmLz9tcdbZtg
+An7y9uaLa5qsewlJxcmq+mn/KnrQAJim7jU0xGk9Dl36iTGxxLYFZlwdD4boaPCQ
+FNdrh9VV18LRCD1VoL5cx/Ht0Jzk1MiTsYuonjoPz7jh8UwEznxx9SoAZRpvpz7s
+PkDCNFAiZq3KrjW8fnay/oYfNLcfrOwmWMhNYg3sSlSM3BTR9lIDEmrAn2xkKdNc
+U+GbjpQcpOxhFrGYdEpJRYvTyxBbdZDgQisaVqQx5I9aLKDNkr5WpOUeiyJWeFS2
+Gyks47WtFEnmfBfKheLzZYab0gqxL0hW+eu4ECBXn49Rg7bFyWSreux0OlJXcJUH
+nGNTPPtpfXxmkhE7VKTxyqqz8rDuNOu+JZZEg+TEPWZ9Wn60mR148IyN3cIvj0G6
+fL1oZkJnRDPR09PB3UXtw1X1HJX/Af2bpr1iwU2r+LzgFmBvnQZHxtat+vwPS8Ue
+p6bQOViwDEadgM2FuI22M/D65VCGbsCbeFLJd0yOtL/T/KtPjT2XYAROgz/0iM9c
+kpevdPEy4IRIIJUZLi238EVS57wuPB4oPuW7rePiZ4Xmnib/JPe/0LBINnA9dlnp
+vcWeap7g6E9E4D2iGo6uWI+zNhI+pnn0KglK1h+cAP7h4nLVriKnO0ktSfSOACyo
+1P0LasdYxUC3yKYZboiMbVm5clc9vh5ORE3YlYa/fw1fvpDbpfhdZUt9yZwhEpYt
+39AYeyGNjk9pdb20SuzZYQ2dtjr3OT+HbhQSepMjgKdsMmW3t5KJ44w+f2fcrDCO
+5XQrcmMrYz2TNlDGWXm5PwYyQo8K6xXBGmhUJ7tLQbaStfSL79IJeFcYd7J+AEUB
+K7ieQCwybDK30hijzglF1Pd8bNjHhYkZdoWXFgaPglTlknxSVudCZD7j8NBU5qVX
+ypYzGHnJYvGVRAXDlZj67vcCStcjGwwbtxV+ep8afXZg/K0oNawLKvfsMM4PmNKK
+v0YCYZYLgfC3HzLm6zFI9i+wFuOeKiYRKkOX4aEzjkbKMbOgebgNooU47YCX4JDg
+ev52V1Mrc7tX9Bcw6oTpT6lMIwIowZKFWJx57oTV7RR7tbluo0VVDDwbL9ej0tGW
+RLNPu44t3tisp+opEZXeFKhW47i3xI12Rnp8e2FcAnS9LmjzpyFPJKTvkKa5vl0s
+Luniv1YATEClKYeHP6dKijDVFPMOHYg+1OCQYiQDLA/m88bXZj1/fDtgA7//tqEC
+FvDZQFWPbtFdF2EVBXRfwPl3RVVqTeeD9GRBcGzUqm8RIx+dlbpIaUS4kDRyJaST
+u6RbtFWKRhIwAOWE60i99JFjLPYG8leDMU8ei9gHJDaRR8IUA+rjhjfWizqXq2wx
+lNCgmWP5aRPWLnEzm/xT3DFUoclYRqhfuJntFO21F07ODibS+skzE62IwNPGA8cC
+TPUcuuc7BW+4mkfhiTh+5taL6LUiZWF2K235gdEtnYxBgmn6IUobDl+XTd8z8lho
+V9FiF9mjz1YCu6kBkIk79f1WsZDHEodCUetNdG8qCJHgc7Ed+vs2f5riXSncurWA
+Y0E3AF3mK875DUR1uBA24D3uX9qlLFH3p7L0GFZ+u0t3pjBckqsByIFJKYeDTyAy
+zELS5o0V0bKPb32N1q7hGAmPXEvLnAMzeesKOoPZb7Vv4XCJcRofe+2Rm6cG9GSk
+yM5srbcbiJuAF3YGsGUYdI76dGZZPpsBCFIF++4bYlmVfnR8p34AKB+WpzEqweVt
+BZxV+0FhRAWr8Fx73NwXE++buCWafnZk65zT5PCn/V5TXnyJziRJANGhfA4Q4RWg
+WzR+vAdEVZGbbQsXCJpIIo6W8v2UdhaoUby7Pi2PnYCjP0KqKuNWWxjb23F5pe2L
+QUN/OraTvv52TPkQVJi3sPLQQyoPzLX7QBv4W8vzPhHCLRJLTTcvN3DZiznVNZAU
+uCcCeR0smdbVXrgNu0qvnp8qWQMpt+y4G6estmkRQyRh/15y6Aou+2U5t6vKZdCh
+TVl0EFNrMRCgXXUGZniHu5HEkveWgjA6UeYgPWhIWtugWW29yEIZmzKtu/g2hG3X
+plEjy98D/1IkNhV3eP4vEUTvd/arNNukImtz95UcAEVNPphF2fJuqpLS6PYSHx0c
+ysAE6MZAQ1zXVmCqWZn5Was2MWxga3ziGkMDj/2f2g7PJW5sL+6LnLJoteGGDM3b
+SnxhMFWe6OrM+vbMquwDr5IgcJQJ0KszcJa+l3IsozRwXWhEPPoB1AHmpSCxEvwS
+mla8THoe+Fe1QqlHi4jMDVMhodwSPDa4PMo5EuZ/5Q3EmgyaFGNUR9MPxOyhM73+
+I+aA6C2vb2Y6ZzMg6VlVFWPaThur2se0MELp9KKTk3qCXNXDORl+pl7A6DjRiGAc
+UUWZK2NafN+HfOXZnV4tYQ3YhJ53JfHkg6lo4xh/Jpl8u38BkiQxpDNGEi4nDXpy
+1Hjjwp3vSkBwbNXyOvLF10pGO2qx6LEI6PVu/ygNSt0pnEgVMuFr77QkR7vOoPsP
+ZMXqzlppve8DX66GJooWOzlIN7Bn+Ofw7aicszdp4ytUtDTV6TBawlg+5gSKT2zs
+Y0uJpIR7EJl0T+nDI/XzKBg8FYY4I+aSsdS8CrMgOOr8tdfYEcHW1oRO2EO6Ppse
+2gUx6IkYdssn3GBbp1wVWlCjQUouQoQztPrKyETGEkKEWYZFBSa+vrPCPEArF70i
+mfLgYWj6IsRgFmckK07+ncYKRcu+ClPCC3En2bFt9Cg2TrtvCwcLF8edyMcK/BbM
+u6QNpVIQZ9IKnh1qAeapSkla/iOjI/XHkIquOoWTowOalVoirWBHWQ5Cn6M0CDdB
+/umqvCK7zdWdFxKyLG3ay8Q8wVJJMc/jRumTJZdpH9/4bmcBxErw+/IbiXJw1aFD
+sLmkEiLGUwNOoos/68DTxJIl7HElQkMONUTAAnT1O+25kD/jqspX2EzTWsBMoXgq
+rcAIC2lJpbJRcOVZTxsu02P4FB2/UczubzaGZVt6tWe4k6IntegyuccNfaxtD1zm
+bxB4gcClLK3huh6NGbdkH51Es4a5ovCBIyL77uFSE4Oh7DHFpcSSwsHP39WIl34b
+F08Gk6LiOUrKwqw+eyWH+Srh2O3K5hmege9Tdh2XWO+L9hmOG3OSqUWzt9Ez3sej
+/MJnqTIkQvvmR6tqScF6qRlzvVw5TZS9HhwgxPXgGgmKyI17BC0ZKVbHhlaUkY4W
+9S0yug5Cf2NKq48FRaWHhnZJYCLjuH9kC08/KBLxXuRNLKH47ttLgvLkJNvwBFaa
+u4KL0t4YORPCxhywkQJ60q4Ww86dekuvnm7eNfKJRubwJuTzB4FQgBeBaOq5OFE0
+1ygS+lyWbg+8Ux8hfT0n0XzQRY51x6tkXC7h5zkBATZKKDsIGx2qizC72tlNup6s
+EZ3IiZJUQ84BZJeS5MSnJcgRDyXlyNqXeoufDc2nAaBYDtXsYDrX28wVaxNWAqow
+H9/3k26dWXwQJOeWQDnNRvcOTyaSRL8YFMMHB86Dqt4qYSN8oL9lWR9ZWxNn5Svb
+chB3+8vX9+v7DKDDJWfVWFR6xOgmPPbv3oQ70paK3wT19bsY/5j/EZ7PsthtMU0t
+RQ/Ud538+RD9dKuxIEqyPCUJaSoagVhFrehEqjmq7vfJ8MgcjltaF68aFEVSLk2N
+ON+Wk+p8j5SqdvzpwXehHTrlZjrvzCnaFsLeZH6JOdvOEPvaEHtSHW0zJlUFG6Ia
+LoN5B+6k1XIKIVNzxzodkfa1l3D92g4XBRSIkymCMzoy5jkXDdJ9jlx01+D5yR+2
+mpSoH2oHaDLuOsGsTTY/KT+EnCPNAHDrcFcsM8URQMw6ff+GVfd2aSSqhJJMC3Ei
+Z4HYE9LNkMupkUT9SZO6BQgC3pPzuBEbqFCObK/PnR7Iznzaa8/zq2f8DYuVGERA
+JzRtJSF9GRaa7mwLpciqFmYsdFOuYhIFZAERLyDX8eW/G8S78infOXyrz/JmOSV7
+ZzbXNghNq4yo4j0KP6H8H2s8eyDilPzrKJ8DMHw/9hEu/5NsqW5/aSW9UNdCCyyE
+mWtDpf3c2JBztaao/ue9o3ydd3aF5sMkbzVeKm0gnu9D8ObB8KGPwQuLZ6KXgQI5
+P0xrtiR0BIQtkCpDZIowoLGpRFU6E+IBkQacF/tSkYZrx/Dh2EX4mWEkDxJgL4Qj
+XsEsJUYpZuaaEudZWk3D56B+NExP+7W4/GMYzMoDv9CjUxe/AF5sU1ovS3Uo17Ba
+XkYmY/vXHxBcXGDt3sN+Vmvx/UnK2/QHGb03Zbb0uhQpFCybKnOKXJNtJiIO2ECo
+iOTKS2QfWaCP0A1B5u/JOU/tQsWlK7y/xOgUSWD74JXuN0g659lNlyZdTzBQLmKD
+y6Hwpc3M6GS9omXESAOj7eXhpFlR1r/lMzhgfhGwv8+QO1+H2GkiuRnS1BK3n9T9
+eY77aAklN9G0mKJzJOdR4Chonga00pNcRRV1rJB09XVTY74hTBoTwqLXBhajJtL/
+kZWCQxE0fmAGq+q2jH7cTKyK4fSBOwKwQywJ46XKOX8eauUQpHKD5z6be7zJyXVT
+L9xCKvXqhyFR3z5tMevP1qw1cEM9lEaYbRw0DCn7mRJ5R8psnLefL8+xzdf71MPz
+m7YUi7y/D24e0IdyzXoMOVYRpN7aQOJJWAHIVU8xuttGxO+Zf4iIFsPi4itjmLeD
+B3l0x34laRNKVNVCkexcydIScR7va0hOEItQZgkgnDTRgW+N7dORtY0xJgL98fh9
+Pxmhx2zWuuP/gdvAUvdhJq2wxosuj2jh4YI4GvEZ0o7wauiVYOIRm7C9jdwM0eIS
+TFqo3okqfzQMd3IE891kcTv3S1dY4HufjpY4S0Fwgtp6fhFeh5kVNAdeBVfqLVpG
+jpIY4wbBOdvgpZryUW8fIxL6tyLGxL4KoFkgjkNzr0oUZJz08jJO0rCJnPdG6SlY
+3U0ZCtWECRsMXQpASc5xLkMLeAnwS04OSPB5FCPxHA2tF/b+SJLUBr70qXXe/Jml
+7vavrdwoGZAoAQb8+Il13X73Vs72bHcFLbNlgzys7jH9/4geK/dOSM902SYKSi5/
+BQDSEXPMuDwaHuOoFCY1zU8mjv3GNsnpmlCBCe/pAhDIEbLB9rzYnPUn4FBRjPGp
+eDGB0r4LxOiXOPDk7sGw/tYJcvbrptfYUJAXF6/FJUYoKjwuH6xubdVrbOxYbjmw
+i73Ie/zilBYCg5tyHyAU2xuGTZF3w0La/5a+kVdIY3WFPJQs7j3AOaAHSxoINaor
+com7ArTAXp2OOhdWGFkhXVyj/+KhMluDVBwRYEHEssfWGSDUko4Rg0weCv8RJ1Lj
+ZLOvFCrFuJbinwHtov427iVBlZcnyrwAjkF3iSGLWtHBQb0i4hc6f565Yk4u7vqP
+pXLYOsPmGFc6VrXUdgEaHg3razahHcqQEoCHe2ZwYjoW0Yl7v4wruAjyhbFIOuYW
+9RjxsUoryYYcg01btskHSpXCmques6NLRU9ah1dnPXmp/KOxD/6odXnRVBVR0bBm
+gqVjirgUi+RlXWDdc9ky4hJ2WTay7TrAE76ezU6HHUioVHaJ863gwk6A4mJc4iVN
+BlVVjKGBIGeyI8CI0TBYUDjX2Anr2wRd9iTON4kCk62B8a0hKWN54zqcKkLfbEAA
+3AOwKoIqg1yKAWhpEAzGmA0MAyuLy6y5e1l9Hao99Q7QyatNL9F7BdNevGkXIbyJ
+eCCjRxJcIvNtn3j0yztQS7TyKxiDTEyk+ogft2T5BuqlVEjI9cr/ErP4kuE7SjxP
+Ao4/ErwsNc4vh12eUuuoChKDihzV8sfBbzIuYEc8HgK61TU499xHliHJKqDKIXhK
+rbvIryZtV2pD/RdYdHUmYbd1C6mrsInJGzGfIo8wNhmjCYJDNngbGULAIioyvunF
+i13TI0xPd2h+ZV5vcj1WGQSBlNECKI4LCQJ5Mmeq9SShxoPhRaqF2BYm5nbGBA2I
+SCA+YZQYK51uN1T4YsjUODTRJjFtsALGzwgxDiqpjUSF8ORZ/xlc8WOX0Q1DtZG9
+5NbVg2jr5UvWlFfqzKcygcHzzGx+no8cZSoz0CvECguoGY5yaL7YVBX8upMuOooh
+gaN/wL4vNaUZPyLTLqpZCxJ1GEtnIwTZ8emNfFR6pepWWbNglpUX2pZndiRavqmU
+x0MM6LFKedwuXqR0qr7sxAL+O/j7+n5F4HuweVEPBJ8ZoQ/bBT6PAsPwqlwn3c1v
+P0y8ZkZckqv5yNCMNY7CmVdnIKQKudk+rD+cBD4RRBhebcL6ucFChtUbQK2hEMIt
+gEu97e26g6bI4l9vLnrkUW/MXcMV6E6tPIWYrt/bZm5ZeQQD8kJ1FfM4estAx862
+mZxqxWt5MXetVljnhpne5QmFV3WKBerafWkiwf3zZq6JeQeG2gn+ttuAxZxdrrMJ
++zTXE4l4H62Iqwimrk0mpj7e5DY98kQo7/N/a3wxNJCAGfA1flBCLGb3dJfDJ/EJ
+Fud9yljArxsRfD4e3C7WHholGS8LS+2vpZi8l+J7RKjCI23tVcZc8KGbLcQeImGX
+vGsD5Dihx3JF6QSR8zUzcLkJ/BVcW0Tq2Lg0LkiNleYQPBTDVcHx3cMYCdzKCR/P
+eeQTNHdyCoHm4e1YlPuGqaBsGAb9H+DvXdzSsh4UyGDXy4DRZB/c9ASqO+SxGjTQ
+WuynuHFN+63Y/Ke2wJvKI/yp9HgBSdyZTjykGk5v3Oz5jV7uGKelrBgj7zwaFfvY
+AEZ2p4xJrIiQ7lfjASfzp6IAg1PbRTpwJZ94vMTZIDPwS+6BbzJ9FC/oAzYWdSg0
+ZYkODAuMJcw9mnFsiXQmC7v4gGLUoUqE6h0B1sdvWK4kkiiYYg69B9hCyzvCYmhk
+BE+sFkeJ0+G5opeYpMnQyeczBgyEkOOi+3LZztmQhPOyNvo3+ycCmq62hq6dise9
+U+yV5ahIcuFPBe/rwJ5M2od2G6687kvF3EDaW5oi0aAaOmWBPLuT/Ggop+RTY61k
+xanfuacms6n4DszFdzwp6QP/Xb7fPWT0QcB0P9NHmI8MC9eLVhQzmj1vjOtnXH7t
+EUttKkr7lllExiyVj5HkWlyhiV09heJnupL8fZ6GRkZCo4aK/kXfMSlgXeSWvUS7
+cfx+MuzgFcwewtmaEP1FkJdIg0jwe8rQ801zUwT0d5UV4GgrROX558uCJRjPvqjI
+5jHdOmugWGw97NpEpKuIdfKyo4ir+wYteVqJTgayIihbhFVzandS9EkFM3gvKgw3
+N9dGNKGRyKQ0sP6GDFpSr1juGu6JX6SF+6x/HxXIiIXjOuby2vE8Ggu/xoD9Gz6r
+60J8eifxJfmDjeiJvJp/KgJMoSZYt/7afNnzDSV0wJjkKno5xBC2vKkkW22hGg0A
+3ums0iD1xMGUtog1QBxG6BLAl7kxhuvGZsuE1ExyXuJoAMRLHDfjVc/Y5kLHYNUu
+H21VLEi7ROBkXq/1rNGPkK0hv7i8S1b7wGKl4eBgt8b3Wcyu1m8017ab/tz1T625
+NhF3jGi+55rPENXO4QV5iDhqDnS7fN2Nmai4wCey0ktvGQcEeOwyO3ljM+7YxIzB
+cedEGONWLHMUaw7LllboXlKIBW3rg0shwRsB3PulPOUgrCiXJL/BrOWl1P6EfHNR
+NM9Qj86+OrO9m9HvcV7CSJH7RFJcJDws5Q2/fEsEBjWVa8k/qaIHdS/TZN+0EapI
+dtcoFKVQkOGF50bMRU8KwsWFdJCERR8rA0BBPqDQwdKXg8cM2/UCpEARhKAxu/9k
+K7WRybXmEC6m/ONGBZNsZ0xgNzjQpdKG2laviIL2d6bqfBN+t8b1TaZ4PbbzhPbT
+J+DARYnm2FOuGsf/sGv3V3UQOVOZ/YoVIqEeeMNvOR9hDt0B1e3+QwUpZhxfb03s
+EZKQJvQqrNVc0iiwCEu2iVozb3+c/yADCztD+Y2rmvyUqvnjoRwQu7pDpgBGrhxQ
+Y/bVTbcOR41x65ZnguZxyiECf09sG/aj937l0Kz4aPhe7qlS+TPJifpppbRUAp/J
+IBboOQXiPnMvGNm8++st2wQLpd03+1I9eI1HVxjCKwuIyopB66f7mdFG6rB4G4Kg
+6xo8W9l9HowdEmdvsn5OhYsYPwJVX7fF5tp9RT47fbYgpfxToGedm3MiN//I9v7C
+rZnvJCs0U90qZRXe/+6FyAWU27lhkBWQOI91TSCZzl+R1UHs/nU0OIZ+8Fx9Mo5g
+2wu4GZSxVuytCvEKzEFXLU6wWW3H9D4qjXlukxnE3qJa0qx8CAi0+fbrqmFuTCRC
+TxbpXPiVj+yzh6FBKcSc+LiORwQ/9T8tpy1BKE2AytAJgxgNj2xBU0OcEqbu0eav
+BYLuJ4hqBEJvEEEaiDW8bt3oeAoMBkN+F2rc0UMemrkZQKHVDuTs3is8xfE8WUCl
+eb5xqoSRP2WSa9RQ7JWzdyeAtvFP7rsmeIaxLpe+fcURRXCvfbbIbz4AA1oqlPX/
+kdWGiugC4jJktsXMe4xdPc2NJ2AVjx+WPCrp0DaG7FtQNlznSqkFi6Tjejp6YfJx
+vkKZLRsCm//hcNOwjxzp9fHyasP6IW7q7bWD+x+yzug1wTbo10my5mHddcv2CMLg
+6ZIZ1JsoQofiGesjtTreDOhRFI/sfkloTJ1ftDTFrnd/oDEySRIwmSU8DeJgWxnN
+lePpLaVHhZnCuQ+asAW9E0jZZLtJ+JdItB0ZIANApuIBhah4I8KRFqdwJu2hyS+Q
+Bv4bUQn64EcdY6ZtPbm0IYh2KzK6Oh9kbgiT2LDQa8p+siOo3OTJ1vYukyz2Fegc
+jubEvI1r2ZIRR+swLM5hGTg0xjkybge74pH11KuHJXqaNcUH+p2FmtFrWo4X/29X
+ygVa8noRqwWhhapt18ZFqDNfhS+HbBNbREMoSqy5R2pSOTjLN9Jy68cMdFkHpwGP
+5dp0+UhbDCtu6hygwRVlbH6l4XKIVTNYdNOrCru2bjMAPbzUXbBXyYiTQcJEWFRF
+tSsoKQZZ7nHkpIPmCMuuWxkjf2DstyF8KvyzvBmptwt/NGiXqozve5dA/DviWRXY
+yR6MlqYPj5yw8TRyXX9vKCaceE3R+4OqcnbXZV03J9LdgmjURD4FwwcesKBHNdFK
+eUX1gzSyCkpBKdj8GihzAbjpSs1/p2dGK3iIpypEZVyjPlNCX/NumBo4epxZ+I/J
+BmCOwrF1rAZ/fJ1pnv+eEuoECkbwIf46mVdsV/w2m1lcqVv4S0iF7OjwTk8B7f9W
+o/KEk3fbcyIYtzB/FOSu/G7/DIiSPkf0FR+HnxbrLzTAhL607n1t2yFer1x28NPz
+lnCwBNJRGSm3s6ddhD0BdMDmYeKE8BPJqt2vrN7kt3PAklJ7JRcqpU+Ajk/qLlvl
+dptBNAlEBJVJ1vHnQvCA4bMpbWycNrR7B+YAAyRyHHYluUhh0dZJUUQmMIt2eVph
+YSc7uDCaQoVkx+vHB0aMSTdLvJuyptO5Ak1KJtwdGGdPhrnF2gl6DNtFY+PLHOvE
+9n9zRUXvMz0ogBRUxHWUBrU8isQGNkJWr381fpbkNw3PS/D0bUeLyJAUl2FEwB6B
+DmwH7+3Ya60e4/5dQ7fJRxYVsiy3ED40bSViXNzktW305s7KfbtCWwY+cquM9pJc
+3rG/hGjlfbISi8kc+n6scG6VMbb1zFYLyK7v5uMfYZJk1KG0L1C3LUrdL3CmcUKG
+vZDuc5f6mAn6THlErYtbIgf5vivGOp/92O0D9siIwlzJH3WVi73bsY0MV3RBe+SO
+kUstuQ8yKDsxLSfEX9eNQyVv3GTtRW87EHGvYpPPt/1Ih0tP7lpnw0xpPr5bQjvj
+OnXnHPdmT/Rdq6sq7o/cTS5zAXPkfBxEaNunm0q+/xIG/abKwUBWj+CZu3HSpplW
+BNm3fweWk42BPPN+nV5lVk/mkwZnwAfgrJkao15yv59YqXjI/EP0xhkwDfz2shst
+NMZ5iw18ND3jk+d48Tkpd3Kge5nC0kjKg+EFrcCjwzsr2beFSiaXcCCoOGwqFs/w
+nJmnaxF5xR8G1JN5qKsRV3KxjzRJJ2KzsqDXIrX9o5r4bx9x64ZM93w7Nnd4lObO
+HGZ0kN6CnoGN3hJdnSiqJSXFIPa6GCPDXcojQV40gmI3wQsFHV/NqpykEWGSCdI/
+dgL2f7dhVAXNx7+8CptSS2+9VrcIu74cHFGUAkqzVxKvil261IeVJKhPoeU3LHRk
+VWQKfrUgdCuAvoTsQIEEhGaBwh22NqZ5V0CgXBc4q6y+2pgV8NV3XYTwCDKH8kWS
+0BTj6yDZsNQv/dBe7PiF4cFGGMzmvFIv45M9p0flW6KeSH3e4FJj7psNmV/8U9e+
+PShuI7aOHUv108bd0JtuDoNLyhDQ3Xxci2b9YzWoqnIasKjSYBjF43f5JUNgN0Ig
+QnP4ieoGFUDIDoWgPCl8Erteq6ZZ258N/FtdpQKKqNVB6ZiL9GtpOx47OtphO7X+
+SeoSAoQUOceJHSmamrSKps2O2q28bWAzGWHMge5QJ3dTXmJd8yGXWXobsDBg8Ssm
+aF4bgH3pBvHr3AJwgh7OWQBNfhedgJSX5l1g28PsDxZ488/Zi3rXIYFK9UDpRJ0X
+yn3j8NC/N8ih6SYj6409Hx6eWX1MbtI6wIXKg7PJXr9w1KXYN+2W6dT4pllQRU/R
+RhJrp4AUfjv3zY6u2Qq3JmKZlmKdw7pxF1/0boJGu8Y+II4aQ9xFJaJgG8smKnfD
+57QeO5cF+kBQhOI2SPhY6Xaz6UKxPjVIlVsdgC5kA395pO4IwYuR7sQiWSg/asQe
+kOkN2+iVoGEigMLLAzzFcPtz+O+oRgNHOH87yNA8Y805C5AaFB1jgs1iD73Q8Lga
+y2UM54CTJkNqiHC1rJ7shBPLIpPGt4ZUeDt2P19Qv54wcgdjLiklKTtXwPM6WESu
+q08Rt1Oo9eOYb3mwM06UarjNdiYFNbQec+3BoXpxT2CEHHIXOhcCVjtD1wMK2mPq
+fWBlGMuiolGIktzLzHHe9D0P7ybcMEJLP2lABHnGH2aERZIf5XnWZWSZFFZXmNCR
+oXoUpjAy1lUdpSpbftF2dCccv2LRD/PWfiJYy6B3eI/lEHNhPJ+bVBEaaCfVACk8
+9cmpp/a+mvtAhOY1ZMvClFyBWS36S3uN9djOeDT0v8+HT9Yf77Go1Dm1/6gn6hC1
+yDXWmFfAJ0cyqDwi6Jw1mRqdwnR0+tfezwjNubbkigFlQMbl+kwp+cR8XkvbELGJ
+ylGmqmbSinSlMVg4Rc3XKDxSugBeRWk26+6/t5ilSLmUVxGil6HRo9rS1SOx0oVf
+v+bgBpAZun0wEn92nip+jxpQzptFgcaW3V6/BOnNdrYHTHjMdj908edLqOYpqbLr
+wrhpI1nW+NNUEKIINvprOvSL19LkuUBf8rXkhTYfyO9Q/hGxLcsQcBXKdo0si1kT
+sOuXY+oQS4Z9O9O4/Sg5z4wXe0guTZW0iEfBeOk0Ihgt3JWBSfiSvm5X4eO8xU6w
+ooC8Bvqrmz8VspoRhn2I4DCJkqhZa3FR0RMLb5TOJPYrULph9xnnqWeqCibEcifx
+GabsIlyAdKi+aI2PtRDe5uoA8RY8QQ/lE0Ri2bQZ5TBDHvdsskl0K47HxI12sJze
+8P/deIqq/wRug+INJx/dL6SIpgl4jN3eO1eF0zSsUoJGZ4ePjQJmX8MK2H5VnkJ1
+SDRGH5u/cOAZXmCHEqotNwIKK6qEriDXDh54ts6MFVSJGOzKCGpMEsnwyruIFK2p
+csjfO1BtwxtLgIiziXvM5ggZrtC0OuQq09bMfkFWVAn2mrFymOjpvxhS8LnUe5GV
+taLAVr6v9J7EMHA6EL+SbnxufGhId2TpzfVzIdNDN+2YwP7SjP6KoKIdIdfgnORE
+AgTDSDWNGjmSX7/7K40GdSMNghCwmAOAg8Vf07zuYXhaCRRDkGqrj+8G62xJ7zdC
+isdo+XAZkFb+gqK+zJuhYtfvfX5PiMGcsw5K07hBqIoF6tqSJEmzEjH8ZBj8g8Xf
+kWg0SrDs8R9++D7M5peoJen9bXOXXKWrZSUTLxxCgDWAJhRk2DCgGX5gsXSpXPA6
+QFU5a4BPUjFsSq1j4cE65jBfv609gi3Kx2c0WxCcmgdfDZAqpx5pViz65B/LwN0L
+d4kkCeSKwof2dSjeKXegrpMzEq3X4NrEpCqUR4Owq3i8pVMC8RNqkHkdjx1q2ODS
+WG3KMxYmg0FaiMiw9plZecWEZ2RTFSzvdMs7AyG+Za+XsrOVzhIQG7WSddwyGNX0
+OSqJzQIFPzaXr95zA7BcTnQhYXYoh/6OjIrYjVznHaHfh0WEOBishb7l+SfLm/Pn
+2q9Pk1nNmRtKgTLtLsSfnVMhbeacH5417vdRbLSKiGI4jW6r93Zi56WAwHw8oY4H
+3LOliDXR0u/bqb5bf/RFtZINJtY8feNlXAo9uG2X+uTWRXjb5VYzaf0XhhAle59R
+qqiEPcxY/23EkRI/KlAamcBbfv7kAxNMrilBlSPGq/vAMPzHS/cVl9IG1X28g2jc
+ww1eqD3XPUgFWpuqScNqaIpFlt47FAJxobMlOMqM5qmAA4xlRhoW+NbNtNf6VKnJ
+SNRDATggOcLVAom07w094XnIxmguvFd3dZ871yCYg0L6M3QDGTtMlcwKQLyFJGmJ
+IWzPFKDFhud2ZZb/JsPuZliG7VcyS3+dxxCh1nXx02K7hHqXEOUY2WqGVhkXVflA
+BNCqK6eH8o+LasAzl++SXm36nHsEpI7G8OTi7TRTvMocliwGkIMuBUmGeZoqUUSk
+TRQS7d+ZiPbmUdEE6SxYi+qr3isvkh0JnRbjS/q+0wBmCq0hHI2nEfyTj0C3ttWT
+n37p2XEatz3TY3oa4OE/pG7sZdFu/Ydw7OzGqT+8hwCrxPGa2YPbkhXAYk0RRNx/
+tjZvSYhkROXEL+yvcRAE1ajP1HNUK+oh1b95jwZm1Uy9pifDTZOLd4FZmL3ud33g
+Ppo1L/wBTjLN7voPd4lkb5mpJUg2mG2ecZK++aGUbbhoykPvK1wtRObsxIiBT3CT
+eKxv9xg1KZ2X0Fbtu5BvF4Jh92cZLwJT01Y15vbOeeTYfmj8SidOaRkgJnGsCYDg
+w8o9LwAUsDhT69sXMliQkhmYgsPi49divleUOGQumgWuSESTd7NegeNchoVP4EHo
+MnH6XkPPtHhdjzsKFg7g9Nfq+4mmFNbV4ZbHF6rH386EKDK5+6ynsZuAPGomqsAT
+pqyz9MU5T/9OuuwVlVprc4tsB4BbmiFs6GS3inA51yEhjmkxpKJmBvtCgSJIBRu+
+vCFOpbARyDnt0QcQmpZEnicW7NBxyplhSZXu/SRWv/VnwGL0QYoVRtSuMqTlaaNk
+sMoD0zG2u3dtDH2Zy6MNgaPBzB1N+fDiDMb7NYsH7jVZCGjHytnaG7CWhARZpeAY
+/ODdukyEosmBZJ5KZ6GqNUdKrF2utuAD3hLvO4un2OFdAlIXIdH1Lo3rEIYAQ9iR
+Rh9x4PIH6VtvdSiRCBmC8LMgcPmsOUGDdQqDQmtN2JB9gngLv3oBcoli1YPx2z3A
+B23HNonvtdOMIpczH+o8tBtRy213I/RB97rfOEOWQvZenBtKVbJd6drSfxZZNPtr
+c/mJGfWvxiXt3K99DoQvkzRumGY4I2qnQsfptct3RpaJ7iKlFuBdbn51UeOUPqIv
+47TRIrxleMjAOEd+yz57vJ6G6dTWnrikj+riPsP3GHVWRP8PN6h0T+R4RTNNb/NA
+fKIJdK5BmZPm2WPw4GMi0lyBPsaVCgwXDoHARy66Hou0mh+LWfG9Llp5dc4AM1SI
+zcpdts0FszEZrDchakOTeZUBAQQWaWEeOV9CmDGAHzCxDDaavKSAs6X01jiuGrFQ
+JOXUfSuPOoXcdo5257IfteO77e1dDsxKrZ9CkCXMdHMzIUFnenePf+S1u6uLexZ3
+Aj/H0J785nzPv2jOAqXGNS+SBdZ6fz7Mlv1kp+udXWzJ5TzHCkr17SIE8GQbGvFq
+2DtcNKcnuJIbdaeyDpjNmNyRKn9nwT8Inu+5j2Uy3WuGEc8/Mh0XMIekAeNuT1pl
+w9rd/6ee+BQC8JpYi329NPJ0mNKay0UhET6tX2EP9RquRozXyUMIg6u7IgrRmG/V
+MwBHUXboSSevcG+78xTNokWUCXSXfSJ2flwvc19WQp099BUb4i5I/wEtO/yiuCab
+VU9szwPlbZua4K+C1nwmKy/sQqnMf1P+pOtdshdXKfd/1zMUTmDvFGHvghMTxgMb
+V3aW5qrRkIljZw9WIMU47CPsLItNK5cZrVMQOa7NqNJgK4oJFvL8HkRlJKKnyAIW
+E3zpvdiBrYZ5SF/bthNKD48UU5bhIkZHr+ayxN8Zz1R0tWZECS0EOSl6z8GtMbki
+9QE6PEsnT+CHrYYAQqVq9LFKa8NmTiSbWdxvPscJMPjhoMv8Tcsutu1uCu/bkrOH
+ZVcSvOu6jMD5YBFrIqvaU+mJm4MSFtPs5WsTou4nTcSmzddWEthScU1FUZK/uugl
+1isUDj825ejtrquht2M24r4IbsEfnILjR2IbqweLNeBvp3jN/G3ZBHqjV2/ZxFCI
+mPnDnSeWWVXuLCj4ix3A+pJjVA8TeDA7P7bitGbMnNPupSxaInpG8nRjF0vMzcOj
+vou8zQMLdNACUSzPzfdXxbqofOYqRM8dgdPuMbK6cJUHRMi2hELp4DmXwz3i6fHr
+MY96fDefu0aQN8eVEW+85KVJAygZHhUX+KBiC7cxSZ4hwLnjNQGvsrkCsluYkYLH
+GUigTUzhEc9VY3RHL83nHNoppDp1fyrctXcbyiRND5E9HZrsx8SChobJyfXR2ww4
+6Ky0m09jwntIIfQMwtAg42TVeXvDlmCbre42b3OfS4SYUzPpHpzqdp7ODJwDEKxy
+j4xycXkd88YpAoEFsdpLHhVE1txq23eKvTdtzB7GFvfQZJBotOeLVX/ha0hmEuhV
+kOg2jMfKXTpPeWFCnhy8iVO4tKKnP3+E23PkCNG7xs74zfzCdY+Mw4xoEPjEnxhE
+gIi4yLcN3osucW9N7tEyA6zPF7YTtC6GXcdx1FFV1XU8IktU8Crywcut7WCgrlja
+72Ory/g/P1L18qDS+956RqKt4YW3Ov+zb2Z8Db4YfsK+cPfZJVDLFDhvwhoSk969
+zhVQRekF1EhWcjAaBMrbwkRyRFArpGux75Ey767z2EoBb72TNEXP3xK9c2o8bAKt
+A8XWFeJqEdDfcPAA0Xr6z7ob64Hz/pMIPIXBenL/MXeAI7l0wHjbj8QQj9q00Lon
+/J+fUD3n55dafw+kp+0M6ZxCkyljBgkkVMlAur+lXQmdIT6gjSwvxu+Tf0Azc9+H
+/b9S/4CNe7ss6jTBu03COV+nSYriNgITi15noKsKEi8DSrDTsNkhatKXuOle1AMZ
+BRF95smhGyFNZRT4cKHfj0jLIBejWbMbVD2xuzCaGW+TO14eg0Uudg4f0SmK83Hr
+QAZphKfyWSIEmVLQw4q2PEJ+zcfZ0E2acY8jNAK1JtX1+ZbD60tA0mf7MMJpbvWe
+9zSc2iGPf94j8vaMJcX+YXx3zd0YAJ/wK5viTvyaO4+ElPRRxVoI0BG0EM/aXsw4
+N40hrFot704lQ9DHipf+Iw34KkDeX6J85OUyAjBGn892MSU/zyA8CcALhjP7fSZT
+ZktR8qc9mdBoD3mI7tKHZKlChbt6sMDIqfR2U6Fb2mUz1KEIyzF+PZ3XoTPscX/L
+YkJkxL4iUZlYWstrf/ONCvNpOIoZSk3SVKaDnGDFIAOdXDf2F4L1gBOn0XwpAPOQ
+7JNM98mH6tJLjZmCnx1Wn94Q3nKokzjk8qC5cJAA8XBp2rSKqjfLE8YJLCr1Iov4
+H8O6MnyEg+k+hCAa4mOmdaWlce5fYuXawE6h6lWuqgkGoh1CdWdeD5MWdU4kBUzG
+2h6RxRSLANnIR3mXULPsrwA5K2uqxq1rrwPNOAkAwfO+zWkXLwcZmYZzcO8sAwWU
+CDq+SQHzWLvv7wuQWAn5CgPBGekjQ+kekseDwBLhm1eSEfTjRgd7W2vL/0Dv/CaU
+uwRC+gPRrHx45XczLcnJXVVq8To0NDQzg9WDBlhpDx3djiHRpToLM1ZkvR1ANdz+
+NnIZ5Jp7JZG2xkWp2iOjCCSNwMKyAqy+QV0CXKtdmuOeUnxYslAGbQp7J1Ck368I
+3u+Kspf/afyw0DazIGCfonbQCw3o+JqzrLmbSZhZ/xF6WGX5ODfi0F7WjeJqSU4V
+dF1Corc+uvkPH66LVwWlex/MRYTh/g/bNMKGkVglVCzuo4WF1u94b/uft0Ip/qyf
+ssDGk8ln9GXObtCc0BNjPBLBcnCRynpl6G0ZCNVusGDg3mDvjSMSdeaa2DKZLZpn
+5wI1PV0Sd9UOO9j9g/IzOrAEwwu3Ab4i+u3jSiN6Hz5UK0F7L05wICMtrLN1Eauw
+wEfVZyjtb9ANxqBE3jUx+ZDDE5fr5II//JXOeucAPydc5EBeoEXetQBhTkBs9cvA
+jEDwJJn4GdPcgwrrXjHkV7hIDV9vxf9gcP8Y4TEwe3W4pXpW2ZnqyREHk41XpjjH
+/QJT1ROTAjTnDPwNkGB0tx3132YzbW4Z1bStU9h5BG15VXSYg2giU1umCM8ov5/2
+F2euHZKJsG/hkUgen6uLUHZl8P6Nmu5Yazs+O7jJkoYtAYWajwbZoXN7cPNZEK37
+Lb+zOuIjO+2vhwR9RyAP0p0jjFBD/goFsTNu+OFI1CeO8cYwxxZkKJzzPLOnuBjO
+KCZhFHe+npqZ1z+5kukwapUaib/CqYtI54wmcHlbm92/gkxYBuLWwodmCMJzG0xe
+qpaq/T/XV+ZxKfGVKoitRmph/4WLw2UXsk2a+JylBL5AJ+TtVIaQPgNXA4zgX/yH
+43v6a1xmJQbzy4aMr/XIrFK1JHehubipJ5khcmTC0b3xVwSBtTAMSH7rEzRjmhe6
+KJfp+j0Xs2FptGcZOt2H+6oLUxBLMLJaSdY1rZvyhlNm1zjV+kyuCCfJOGkrVQJa
+exaFKTSPoUF9AeqtDKsb8kxmQO7jRhIy1WlefjYgiXvdyP+hn6R2mwzacwDBV7OE
+co68bUjMheVRVOnZnFYu5DAf5K7seMtAHj9E3dzBkHlus8Gf19Mv8Y2OMxuEaO8i
+gsZivFQz6CNWwtkbFAgCrKL4pYjmLdZqpGaJKXKZAyMTmP/FyrDuqwTj0/tGo8gC
+neZDpvoJgFGvGL8Ip7uFcf7+0Yo/AgDCcjntYZuVHl2/QsAY12rA6bIMzP+/bgGx
+ZOUp/0hjgo4xJTIcTlp1+EMPT3Sojb/w7U/Uf1KzQEWGWA1LdNzLxOrvO1VSK0F/
+qBxuVgUEbdN7rUjPnQTftovgcxM2ckZGxf2UsXCTzIE956lXFBJRytQzXXAjb7Y7
+/zowkNMl+8sFzreazSZ5XehaIYhtD1Reub92YnhYsAZO5+GIFUVicXLJKWCiRZtA
+DB4mvcKt8t5TPvfBo+TRdvJSx0Rd8hlsrLWOpMf9lZ3UIFc/b3ze0WxwDBn+W/Er
+kZRnze8xvkqb1G508aH4HIa7NW7Mdlyx0D/PZ0HewfCMTl42WdWfVpC/i8ioOyvF
+MxGXQWROk8MxQeeg+lCTss/asadBECOY6l6NS6OgRPB2zq87oco+vwGojOvIuXdd
+R1idofIDDThLiE2v4c891vwEh3zUV75+zrujB1Zh3o4ftpkuTRzSEGisTSVpecJ9
+0kcXChhbyKGS5ZQ1zkOVBovKUchLmUapFLf1wmHRuSH36KaeOBrHe1fTNmcAg1mu
+5LDjV/UVFPPB/wZs/V3SYHTamPB2TJDaYZrDp6n2MDGYKiwcjB7nbedDfGwa4tAq
+R1g+3MeCuggnY9yMbezWEg6sUahQynriaaMgT7r7aSINYL8eDlnVPw2KF7a/ONxn
+JDD0Q7+5IzGaXdk7CsWkhjyhY16rSwA0P3AzIHGpSdh/DjQkDeFcLCdORLaik4iK
+IWt9ykBqE6L/DjRBARDPHZZ/cM7k3XwGfVFxdHQ6P78NfAj5wgdxPTo2G24oYLPt
+SNW8AJP2E1veE3VZNbGz0TD6gCr+XQ4h8K4NzptdKcGjYocD5rzOTAu43trz1hHJ
++VLV9H8hjBlhdcwZcX16R/jCgm+UtTXCuv4Ari2fIhVlvTHpWFZdcN7MkL1OJckQ
+vQWf1exXe931XtN2+pbAkdVDgUhIH4o3phPxYlSbPgs4g4pKCo2lrMbFtlw6vH1V
+/AfSS/bjEJUh0OqNgueW++WwTxkwbFABCrifqvDKwUnNz+TAbzDZn9CI+NrGLSjg
+PGLLBiJk74J1xdPl5nFu0uvDIZagWMdmGu69Ko+d1f0Ul7ChnKEw0UmkinjkhaPc
+llWS7KtkBG6/anf7/QjqpTKbmOMm52oCgPIQyw1Hp1GlI1EOVPqjerdHN2mJi2NP
+kOG6aegQRZ0MiXF8zXSywHlGgbogr8Z7SeB1g0UvnVd9na2sCv0Bxy8fLnzrhOJI
+YjcAC392qv291X9dR+NSK+YvWRqrIe5a0JLRPfFZ8LPoAQXdqMjn8HTIXZH4dbmK
++QJwiKq/vIeg1NRsmG6ZGY/DJtBcSREqLfM7z/Gj8t5luFA9H0xFcrAZFQV7RvXx
+G6gVOu2SpxqV3trM5jE9479tArkx1g7lUxe/rCwsRdKhknXwomH9Plj4OuqLHQU0
+hcdqp6ccHjWy9NJ2f/IZfpRscjkvTLRRPsIt3RV/ZWCKCmp6QonO+GNBij9qfKc+
+f3hGjkKuQ2fdqGEH0gRlPpk1rw5j/ywzQL2yYimXzeIebwmUbogLeJN5e3T7ffAz
+zbvRNlEkauV5KuJI6Jw9TGNJhH+Kya+tS1uWtkG38b8+/Nd0qRd8L7uZ4HpJyUwO
+gg6qRsbrfCbGD31atV7B+7BNRLQYywMv2V4yxoa2r+msTwjV8b6tcIIjhC1DTTeo
+aIZ5mK95ok04uOSMyjdw6AN0JWaIm3r8ZcwucwdZYdu+3pi0RVlOk6DRKgcuU5Gj
+p7ETqtxd5+meRBuurSdaUHlkhzYO2yhuNji/ieYTAQotnYhghIOKPO+QRBdTxfP9
+m2z/FySIUqWW9Yfdj3ehP166+YtaBaoqgqMxnqAE5GYtX9cm4UqGt7AJN8GqTLtn
+7L2eMnwIGiS73vBpC3iMGW4nrRzZ2AobPsWfGMMRLdj4jznDKJFYZDDQoSNfPzRo
+q2EolHwXEqsc18oqaPSPbGc+fK9uEi3BMVsI+Kt9ASxJb+JqfYaiCejZxMqWIb+u
+I6iZhJq1+P6CjJJElRsCF4FJOQWag4X4TnKp37IG69K6GVskMZTNVkt8q+5qBLwu
+XzBku0dxG8a2jd5cjIur2v4DWms/hngDzYqUbJ530pTzzRhySwlvziPdmIrk1lLo
+goxYKN6LZxLcv0y4oKHRzgszR9J0Em1+ahPQs8ROHgn81GjDb+VHgm39XrehC6Ye
+Fl7J/YpLUp8863Qow/kjjcwdL+IQnBWFh+mxVsOxOJyy3unKc0DO8HN2SZ/CtmXN
+yonz0dVeOwMpEqDkDKzRyy4QczDApP3Hpq5EDoFXX7mqPPTZQKkQozg6phI+5Hbx
+K/fDqhYzR8oqvUlk/hoI7DI74bLgQ8Rkt4mG93vX+NWBWsBNpVbH90hKtqcVcKSO
+NSmjO21PB9vgftp459LeDIxehG0tdip0jowU0iOZXJBVd2FxsfYo9joUL6H1m6o1
+iiMGd3t1xFLe4EWJGGxHNMVX/cVBuCv1Uh8LEHAPfpmayXd+gQHuUjhJ4oVKq1z/
+bK27wCHT7+pq8ZFIOB+V3Odxv/3gM0OHElcnxwYbBd75h439xdmWUFsAWobiuhCc
+9URIknJHAO8J4kOcsSwT+BRHD9cb0kdzVQvrEfdMlp2bow9Ac2lnZKostNT70x9G
+yP4O82LOyRFEZFGk49DM84IdmjYcHM7UmzqkIfb5Ebl1hVQWTo31/hOSbDFPcrzx
+a36N5bRaPJ6R1eeTCn9IfVn+SCfRcTHkc4GbXW5EbgW4+6haD4NTk0TYK1/++ek0
+tCyW/PFf6L6BBfa9m0n+BBYTGfQ4lF/5QudtdAWvIoV8R9RthZucxFbrUy7cGrnu
+3fLxiU/u36D/vMYn9McexLZa/MMXOOEL9Fl7iQli2xfG8SW9xtFH6lWSrjzFP0LJ
+ZEcjjcMvq88SHIPfeIGqxilSkr99k4IAP/6N3stuo0gYv/eazngz5vDh5X8jVwX5
+SpY/feDSsvpbfYMS1eHk16EEdQN4SOYe7LNDTlettqmPFLUkWjZQrY8a2WPqu58i
+usXqOE3sELm8/I1Wce6SAMTmu6eYYEXgu21STiMKABwiNMYdUVPA/VnmMSKidKfh
+VO2gs8OixppJ8i6yt9BwSwyLlOQzOgqYEZb6O/0bir9uB2VogtvIg6yyyrQ2Y3zE
+33DMps1mMInKY09DeKa7zzlwdY7DlvQsyMmCgjM9iQhwD3SoxaHmoHAmQCixuSNh
+YGy4b+qufgCzbFiSqIem5k6+w7vJlAsK8KnM7axCpBtefKSGP1+hrlRXWFbLG3yQ
+ATYvsZGZYk3RTZRRM/iExHoQ8PqOsyuJtB6hsw3Y5JWvLyEWJ0Tga4I06H4MPOUj
+qwI0yuZ7To1FFKFrOvm78ayIZz7T3q82YktaWTXBC/fJf5opuiL2g6vcpqRE7dFC
+8J2OX8zijU8g1zSrTTiuQ1MWT2q0wtFzbV5vyZbLpVIICjnbxfNQqBo8AyzcpR1l
+Ag+uGfkVBxdppNGiHgXgclxIqhFQEfqVjK7UkCN+xGc0K8TvOLLHb3x6bv1zSheR
+1B4gJ/L13ABZZvG3d0VtlKLLuffc9dONmt8jNpQNeGe3lo+kAChC+LWdElj/crLu
+HxfTVC8KPk0qVYoHJ1HYiM5kUQa5XPjD8rUSs/DRAocoKqZmNd23x75mZka9GUQs
+VmHVZZbVDY2CInpVZ1IwGiYdH4lLCpHBJa7MPa283ZzlhEb4hPbA34nKAhTHiL6O
+pLFzjwi0+U1d2673PlgZ8bpI6mlVftTVMJYanVnIdH7OIaQQxyO47cNWrYErJmHK
+KS8ks99rplu+xT4S1zwmlT83XMBTyspYDQwqoocuE/HZRYSkg01IjDe8AWQm19CE
+is0hWNfvfgNGcxjVyWPDbanxft5K0iUfJJTxa/1/NNUX6pFSyFHg7BRA3n4wqMGy
+6v3LdqPd+iuv0/ErC78DtABQDQkaGEJE8naNf9GTz6wEKoTHCzZRN8lcuYVdcSef
+JDnatHapB9pF59Rhk+AvqfYp5ysn+ELB1AKjIFPhQPFKcUlYPZuZsgU5e3Q6QPIz
+khg/fiTNiVqh/LG3iBHBffIU34Wdct9f0yy7+oxrGFdCCbDr8Hz8NS534XJFXvGf
+LNdORK/20/NAf5Ky9dTGET9v8XGYDCkiWFqlXJFO9gJYoA5IBSKy1TIb+9yXJ9Lk
+mfTDyH/AxdKVnYw0U8tdZ1gKioVQxrOsgeiszMyLERZkzNPwVI+Oso5U713zRkcg
+r2W1DwuE9hxLh5D1yoT+EkIoPDJIXdmcmE7asO+2Ia5uUCS65n8mQObR4eZ1cCtr
+IWoDUMONCAuODGAStGojeqD25FOyXL8xm5BJDmdP8hyHkGJeOlHkOSmz3Xtt2YT1
+17vMNiSSNr9+okyKgTGmfQAu4KsWSJ3QS2j1WPiXgsShG8ctt0aBh5ic8nL9zWzW
+6j8LcbEHaU1lfXqUjfKMLpx6/HjlD6EmaYLVO32SC+uurfXpvw5vEJbrJ8nUBX6W
+/0XyXMGeQ1YyPIkka8nbT/LmLYRljunVAngGyCp1jfbyO7gNnf/RIMvBUJO3ksz3
+Mxhw0K4gR85y1GKv/NTClJ3Q+o9jR4YDefo40SdH/wPwJowR1OaI84bEtgDP4swF
+66XPdbkGenNsnprgTOVl6Xe+3seHaWurc/sYuCaQb01ckQjW3zBWsc9gkO5TcjFo
+xOPyrFMNmTWgsDWBC3/52R4L1xi4hZ3XjrjZHWYvef+TjNRFecARBImHjdu7JHvx
+UIXDWBRQCUGSr3JpZUtJn6uNpb8zn1xLCiGt5WNYf7ZU78Lp85yRZDl4N7t2VjNy
+T9eFqNkYVaUsj3pf9xiDlHBJbzUVZ2oXh1oUYeK7/DMS+a04uHRM7W60TkuhKs1j
+uQNjXsRigmPZgknXKaXkJnskimVlLVKxIwPQWuZVSTeING0WOnlpNp9ysDlYApCU
+nltEyYDPFexlsV9AqBaMiaOngaqMLc+lEn8vQGBYgemNeT71LLNSE4gh11YNo0Nq
+bLGsjMc17UKjQvL+oeufjzqjDYXs1RKfcGgP6OxGAZMfqm23E4YyXmsjYB7uCfW9
+G9AmzYX1fK4dw1MWpReiZ3hf/Q4/IDMVQIxYEqopJ0zCdakUvuXFtn/HrNoxRo/y
+ZQpQAbKZ5oajbbAOPObWZttiIhJBRcPg9ToGZwbdSokLouRqiYcelawORXkwkiJh
+T+JLcr58lSOpZWm8Y+YmukXRsTx5Q41Ny13nplgr7/pt71WIaBtj82p2B4WCqeVp
+O4qAyf4w+K7esgzOpzfYA5duewke6l0unBZQS7Qb4FAfYoel0JbutOyroVu8H0y5
+yXHNpU+7T0IBrxnBMVxQoGDI1CyJ2jNRWOkOgj7y1+qBROscwhnO7/46bqbw3utw
+GoNqkf7W2QFVRj4hwr+o1nnzF8MPzJnlm1RBlcS1bwGUCtjwuTai+UtWXasx6hHY
+FCQBtZQ5xqi1RFDbaimmHIuYWXgJi79V2Cv5smuKq0fBHLZMYC5ZstWHsneLLbQE
+qvEaFbXfpWEhaASi6ttdwnvirWRMKTRJJ1k58Z0L/BJSHUMc8Uf8OJ6WpI6PBpr4
+33qZYfXMnoV4kwhSAEwEuj7l1PKn4zY5fvYHqrsdJQHXtdhYn4ngQiUBxjHFpdqn
+xoxoEXWXOXbM1YL8aUPUs0l4OlQkrYKTe01x53nfTbHyJT1Srkaktr1kRAXAPEKH
+KNn2xz84UEXoQoGJlgTwnmVmeT2JYpJjwcEfxB1gwfnquag20x300C5LrrazyQKP
+DrmVtzBCHkq2xKW0DkEdijAxaTUihDkBxOBw4mZwuN/CJshkUvArVpVeIJdggV5x
+C/LwtY7qlFWYm1Eeng6wi2LZWn3HgbU0gvILJcXelhj3Q+3kEgZnIBQDgW7X0mIR
+P/BaJkHUNwOivy808ib/SGVQpKhfbJDTSvCiw+TWYfxOjjty218wZF5+crCwhD0m
+ZsIoGsnfgRAkrYhi2UVXSa/n+fhCkYEvb+VFhyizBtdLF2qePCXvt/LmMIrdFl/M
+sD13H81On34oY3szxW712dk/nFnbE6oT0l1npfZV6zxNcdDy54eXtvYujyYw5qCl
+EF7J/8q2lPB8nOr7GIn5u+/MCU42d2aMre+t2cc+aUKj1I5z0Frl306mqBHtm1fK
+mI1LZSiZRH4J0LmtmK0CTc+1GWeJdCofc1Eo3Nj8r64p/nAmRNZspsYQhPFpMEnd
+SaDZ2uJPOkC/2cO8RgZIxwXL4iY6nbU9CpCa/Fh4WlA3xb9P9ti4ovpGaqpqf+aS
+UF9mRrnASZpZ4NyaiJ8rMygC4NV4ZX1l6ddCE2Ght1yWMJpV7uwxA96WOGK+s1sW
+OXu3Vn9+ScMGADa2lS5QdJ80Le/3JFt24blwsaUinZTSZreTmxyiCBzNrJ8JNv43
+R5j8XDQEcG5gMgklW7bJxXphWShP6YScw7WnTfqh09vVTUSykpepiGpP2TZPPwrv
++ksmx+pRwIVgDPoXUdqNrIbi+M+54uj2L58YZrTIWGZZF7gsDinj27Z9RpNrph90
+EZWdnglkkVVhQuAK3IdsT4ExTh4mAsXMRmFrfLs9LHon5jfBcOfmB/N03t1ltju7
+NmQKCbSlaawSzQstAkzDky9DdRUPvnMI/v7c+VI/8ATPHDrhmC+cAreOlLm7j1pM
+Sg8I+x6yUTQo+/S1thp+AXNH9jCJExZOBlOuz0i+h0yLwmAcfHiSN8+UYrN+R8m9
+maXXIm2h37P+yGWLkdzsM81XLj3O4C+r4qc263O/Yc9Y+1dU/77QIG8hVkd/pden
+M9FmR/ls2XbQVHEmBXW2jqoTl1Y76c91H7XF15WZDSwjQykbR4KuzU2I/aD0bt2x
+d5MOb4nDHgSv71AYRaQTBCU3pdEr6QAojWNSsdH8ebapQwg866/n2pgRtfRORrM6
++LEdCuSvo7V/LFIeIRRL+Tz2A3gxEsQCsyXJyOsN5W2RUb4acz3YuJBqd3v2tUmH
+vQ6KoFdeyB3pK3GZFvFHn7l8AAoXT26k6DR45pVh9oIu/oYRtMr7xvdIOavBLH40
+8+8ssdx39fiuUFqKLV3+XwUPWICy/i9ue7FKUoO82SoYZoYeHXtptu3QCrlLGapL
+MCaAsgcZQRwHDrXSTimzryqQwtFWHYJQ+svHGhl0PWM8ye+fKl0DoKkOrbFvjWZU
+IAyfNB5ym+jTCp79LgZz+X0qXRMxJvWlFeG5fXsrN529Vh3v6uR5Z6EhMB+u5mcs
+zzR8IdzbDHVZEvrkCfP4o849GN5Tyov2Rn6Cxx9oGAdR+6h56C0lrCUFP4J9mfpY
+qjJQjOUq4EWDALb45OoErSTYnoENzHNTG5NkqAAeMd7lPkfx9vvrHUZsO0r+RUiI
+2SVBaMFPCtXx108Y3mnDfLmzjWZ33T52oVPgNtMeHPrBwkAH60rDaEHgV3XN/muu
+lwRsiwl5/FA7omyM/ymxgTA1tSSkxeCR7RQLp88piFU3sthFeQ260ohpfvhHV34w
+BBZVJndrcL8x2zlaMXJhSEf8PDmfl6g/1KMsTHRVQgXGkDfWgWm8DbQjvGYVppXy
+0PASTN8WYLpD+nlmimQ1QdIW3F0uVpcb/uMlX0WN0cDRyEg4IjkQ0wgDlu+Xp3W7
+P5j826qrdpPatqn19fKVSjI2IIgO1jR5lgrSrWJm269wnx0/RdtL6lC5bXB6v4r2
+jBglNJZBgTW0bWgYURDxM03zc7XYXEwBvwp9FppL945kfessTXuk2QUQzvrWgPbp
+1LH/3Ud/m5HYp1RPPRxs8aUSDHRbhClRctNcPHIYFJNs6vbLvRC+8RE4iBVIbi1H
+X2Oh6igc1RTk4iFrJL4e7zzSGrsgCaPm6Cw5pPIz/Ko1tU8/ZZrQLdO8sSoDiAjL
+ZvraK1yJWjobYEB92xMPAhIj2n0pOi6MDBFhFEuT7oi8/5Pgd5Iinibzy/w9W6j6
++douZtV3v7Bm1mIXK0J4b7w8cUrLqAxibvm36YonB+SDuIMTb0CPo/+8Z9sBQ7Lt
+7rwL1BdMXrWjg6zt2AQQS5o/k2nnybyPCy6a1o0KxqbeB/6wnawvbxngD/chxfQy
+HJAm5xVj33dxkhBXrvSAEnyhnjvseb/MNrGi/WneTj22rVjGyPVRZqHo20/fkPoS
+Dq+4nmbYt2kymMBAwsUQM/wVQcHu1gd47+uWa++QbeNk/a8GJ37uolBEm4aKF3JY
+Ah62bYQqqZtLoMAh8vEJbQTTqm5VTpkYnGeleD/xtboJFVedY+lGWwypDEWa7/HP
+iv5owItnDQ5M8RzcYz+0wuFozyHQZx+939IyBMgvwKhE5cpUvJLqCQ1c2b1FVyN6
+7EQfTrbdqq0bw9Ium5RGdqanDYHUvea8GZ1jqtAca+UsvN1TnC/MV+6MluC9iQPb
+XV6ymG3gMFBEwUZezx9qZ5FjlqOvqAqz6wtPdyphL88MUNSG0hbymj2GthT8O5NJ
+5cGN4uZLj0Jl/TZMqVS4MLgQxrg0MZmMnoQmiK5SGRMMo51FbTIzz3bwcrpbdK+x
+B6gdOnSV1LZthp4k4lWRwzVPIuLUUiSFhQRWz1Ek0RvmK54JIsOsCzm6Y9n49RrU
+dYP1Kg/d6bq9Odk6VpCrMFB7zBMdb2WPHJgoRqs9Gm6W9x3FrlsZfJDm3VZvoeWY
+ZuGYLAdmEUVnKuaYeh5JVADN4ylj5kHGAIvizJ9pcVdmvQaDvgzQPTV06r/auBQe
+3ZlmfZgW1qZl2insf9uLq6gSU4CeTV+B8ks/TBhrcGKZ6lrIWIl3y3zXd8xsQFMQ
+cM/iZr/ppgJwxnuvALFDbv+Dx7QrK28RkBnNxwMG7aY/xWP3ZEpb3x1xHCigmaJY
+zpaRU+fVmT268Yun05+XF+i4m9w+X6QDyNc5iIQpcCnovFFDbh58VQxiJ1Oh4ZrD
+J2Cm5b9qFi80InIkiQoJZbYSL5DsYl7+wvsyuiS738ctl0Zy7iTrNPlypqhLKTfF
+fopeSCJO6Pw1MLpMNihCMrhwj0sdlHNr2onmqJPMRJ2tY43HTiIBPA/bJ/l6GovR
+1aOH8xisVN9F3d3dLHXXXlOI3TsqpzBx+kTagI7frDB5fUbt7h6WSdO2U3hhQA0U
+XWPcukKoHGd5nzGEYIpeW6D/331jxVuLa4kqPj/pHmU1Fg60LSxlgn8FOuvmhCsm
+aJnz0j8ndCgntTw82rSdFUnPAFcWYAkZe0wgNpAYqG+llqHeKU5bSXEvHLhO8/v1
+V1g97wLTKZgynNMy06fmpGNWYuo/uK5VKVWHklpzBXPraDnAunKCWvzeQmoSR6y1
+hn1SGy3P1wkwWVXjgcYCD3EKPqoqNOMqrXufbJnAkK77IIYN/g4exEvdbhpHVO/R
+gPNPFKHBjAFbVWfT66jw3I+Rf95+qy10rppX0ixr8PCVeBEehorX4RSeOzl6kySe
+N0k1AaaS6Kz2tnXPiurKH9ru0JyesNFoAf332WOr6vyp0yBInSgKLN+J+MaTb+a5
+woeYejLLoiMuJWO21bkmr2mTQNavr6a/dSUBsxnm+Ezbcq12tSP2wofmZ7s/FU5d
+QKF1D7/xFpQESdRMGCUHPdAwsSW1l9KnHbsYt7zqNHXNgy76IhfHWCBbQ0Pfx2/r
+k8ziMYRpaHXM/tWcR8cYMU7XCJtC9fibnHVgjjzAZc3eji2Lw0pWu/zQvKjWwx+I
+OXwtNARcnw6IgzGi83Psor7zPA4A4VEH++gQFVYnx4JvBYWj/zkNkaqvgAeBGS3/
+X01WE8HrJBS4Q3+cq9c34tiXtuO6PYWLLZgW/a/5Xjd7cQHRAjs+DNfvamPO+xBx
+H2jLQQu4xhWCsUuLmtfVowkST/XoTZ/W3iwu4CUYez3ashJdYl5ornaAA2Gn0oR5
++LXzuPwcrGzGsEWjXqy+cO55RZ6whWSwWSZeD+YKceAFePHCNQR5Bx+s+ugCIotx
+Li8H36UhmOsS2jqaVFrbgo7urPGKA0uVSO10STZIPFnNlMkCFGmBY8S7zkN86rnn
+Og8RKRoAiMjQsb9+piJiue/j/YdDD8P9kEgdio941bY5AyguWevoBrXEHLP+tkYm
+v6kmkiR8tkwYuLZYlY1Afxlc3BTz/IuRpnk8wAZan9kaOxoq5Kw/XSBrH82QNlzH
+Z7qvTIInNZD4K2gHSEkJoiXW0R7AqCZR56AQosuSf4wJk/a4kmvNNdq32hl4NCZg
+uz6cD8hhEJ0NBnzzIwk1CLC0oW1z34hQQ+UixU41FRVZqFwazREAjwJBeV8ant05
+Z6ru9u+m2A5odkoGyj9yzhVWPVplwGVI3DzpnAuZ8IxceQk7iGa84BphQbz+72F+
+QQkvBlM6kVoeLzuxtqMfab/u1yRb7zFMHppJycJTDfO8wY5C6HdozpsQHsJn5238
+3VonM3HbOp97xHohQML7DmNvGV8H26uJvGaBVjo3jk1QKhENFU/3KvPtuWE2VtRn
+nqZ+/UEmueUfjb45rmktFEwhftS2Hlt7YocalZ/nDW05j3IhctCkRqZkTJoUGo+/
+ss0Oerup6qS55RKKoQoV4KwGEuZ0y71YMS9sT9Qf6JsYzd3ENzUH9NNwC84eM9ff
+dquXn4J68r9DzwsPpYRIERgKh4JlrzHKQ51y8vCJ/wVrNHxQCW6Uro8Mla8TG73x
+aK6F274+5S3uWxiBq3mwjue4WKAX/acGnP2Xft4xjjJJvBcvhoG5YB9HjAXAwMtW
+cXnalMFAaBSoX153AtVip/2fuFv2H7wtRaSZvUpwtf5rCweOKHR+cnMjKYKUXZe/
+Ww+kzBzVdMuK0CdXLKTavhb7hvJtE97rG+dlgpHIbLvs51mGBuKd9MIi/sShqJDc
+ZVCcrU5JCw6JghukXS8+6jhdUrzx9TV8TZOxpREjbz8L2QaJTG4yKPWLLb0WnT5R
+RMx16Ge5AwIExpKA4gmufmRxkg8wY34AYo+Gc8fd3/zKwMd3e30cDQ1DEfz85Rax
+gvcNasDrS0Aj/0lET/SqrDVYZl9gohAvmMDMSusrTukOoaK7NLdVxKJ/y6SIUHbY
+Bd5xuFKMBrzTLoEM1gox87XXWXDUYlpBIf6XrMkRUp5spIoo2B6wSnU1jGrMY0zP
+X8pSV3KY5QGWKBGl+dlPVWs1tEBOrZshjXF+f6SycikOAzozEyusNHMPI3zVr9rg
+ZZZXDAc81sEUKn07FzK7Zlob38Whs/IoEBsFDXKp4tfIjWsZRFvnt2yhxA4r4AhE
+8xCyu3kV/B3v9HpkbyacA3GB4U8sKt9BzNb2uNod6KviTO7PKF1qKzlWiazgGjum
+JfVir9F9vqWAjmgBCnAVA173LEsUp/nkehmxP8E6h0o/w8okl5SbDPta2JljKZZt
+u1GWnBoy7ROFc7ME6WX3diQWzLVKMl6qbh+Pw+3alHVqLLzYVV5e7RiqVXBNao9q
+RhtwmYURn57GlUsUjcArYvQhP/Xiq5GHqGUYtYfXOgrdHUvpux5C7s8wOk85c70a
+AHHL/dyw5keb5WXYa9ItpTt9SJt0H7Xk/QrjyVAeDtRlTYW3NEKZO30RxtOhJCSL
+HvS0IYAeJRiOsdjck06SJeaDsvEu+CtKGA4h276II3kJ/N0p77njB8/mKRiZwCUy
+BH8eTA4Xy3CplLTl6gbf63HBx+MrEb1SE89kkPjoGIkL3hvaa/4DmOYe6kdw+3zZ
+t82HQq3yWcQAUb/ojvpd1BeM8YuldWXI0fzepWq65OrOEwGj9GuqdGc+n9as66Dc
+c6sg299+DHt98qk4rOH2Naf/heu0woLFMZIf6IAw1bqrD3nuzlD+BzDdBwN4Dkjq
+VAZo/ccZGN8pSOJ3pE6oO1+k9hILPJ2j77Y4dtUu8ZLrE+YyOrtFX+OuK0R+yAnH
+E/w+8fA++rpBuJhE5Gjdgv3VFvad7PLJmEiS15hP5O8rgwzvxqZgIHSqbNcOGB2x
+8ldboEPBaUF3dx+7MQAlh2aO9d8rFO2+kZUbaSLUdOU4Lrvdv+qfSQg8cnFPKfiS
+rl1I5pSC71u3ezRSxoS+mSO7QTWczEhxXBtW1G6pVHIHZ+bJ5UTjyA4oqcpyE31y
+sKeRUy1yAJmCeu+afheCYR91cHZrr/0hoV+Fg6SCuA1KKU1bMkFMtCrPC9xLGJYB
+zPAolaOCHKtPi1B0UQMPmOGI+h7kDyq2NvNYepFDRhk4IXP5gsuxHMOyR+wRzr3R
+SfNOk1uQyXrpN0mFVM6fM6T7L4M15Xp1wowfABuyUxUEIzY8wTeI0iEJb+ulXyPm
+0Vsr1k38SopleI3JfA3lDyoSMqlWJG50ibrfvGtFU9QWrYwvkLIXuJAda3Ugpk8K
+BjoUx6FLOcqJY85psZhvBZbYvU/fOM7Xg0miXGGVt9PzcNbyT0c0FKh7aEvKuIUU
+wvsKsf2nXIU3Pk17og70MowjxnNF9r5fGHUefwPPQUzoOcoMn/wdSYScRdh1F7j+
+ERyKC7HMshorGBJWUIalQicykhfB11D4iPY2aeKD3rWIrL+cyJfbk5kbQwErzcA4
+ExOMutDZyel6bUvUrXaorj7zPYuezF5K+N3ZEjVBJtqvz694gECM3E4eYQEttfgT
+qn2RVZXEz0lRdEFI/JiPntLGTpNLqjH5DG8GkFMhDr+HT85RnUKIo195hr7btLZ/
+03tVFfJYrv90d2NGMPEKcwOnx5XwK3zLH4e7cJiMaFrRD84VyNV+I9zM5xJehyph
+7SMl9ujc/H/bfv5zYx0An3um2QOuieYOaQ8RH9ZE21b6LdK4qHQh+LpdGoYNhvBl
+owW4HypWcDyIJx6dclnYjvckCYHO8aOIFKlt8V3KpPEDAnJn2wliv/0qGpCoE4lu
+TfilERAcHYaMZbK0CLx03aDWNHEIor1smRvmXB6Jc6qqlCP8rixPJ2tn6Eib7eb2
+zlzZk92WZULknOt9UrKtj6i33MAx/BpbFGfEAJZXkYejyNfCzdt+wZk0fRdgTpaD
+tbeiQmJ7uv/IGBw/opkvLvTa9q29EemXgezmMwQ9LpdAzF5qIysOgNPU0ReIFGhC
+zzkIZvjofPWCItX1XBJaqUXJt/h7RZTBXKOzm2wDl7hNhopNdJL2hbk/+aswraF5
+2hZ4srFrLxtGb4k+J0srk7Pj+5gZavECxJSGBFMCG1IjKwuQRzf3sZlQXFaHA3dz
+efs3Pgnah+ouWF3DLFShkcKgnOsHCUXv+SL1969Xm4qbeCEfctdEWbRev9IxMXy4
+jC0hh64gnEpZ0xA9TijvglsRdB/Rn51l29ss1wXdDT1+gBGWmxKHLeTnLTjig3JX
+ijKdF4AyxBYKwuSRFPjnFxjYFzqbdlD3cai8WMiz4XHrRIPMzkKzDNx33CVwSdxV
+lXim3PpfP7ruBclsp4mLiEx/x/tWxAOLPgxqnz9veiV30wJzUhGO1e3LOh8NdL6o
+5n27doOJ1a4oy+IzD3MkQ2ekuqtfmyEPmPtLnPR7GeRJdnXWRogJVeP1oPT4CR06
+I6pO9aug3rQbs3a8B1yl8gyqT1y9v6kAtDW0SaXpTHCusz02PRbi1joVoRNvfhNg
+xTLeCVcynxPpcCmqUhgXkpMes2vSi/QdMYx07UCS0HPGfKWfi3j+/Ayivj1DOlzH
+hyHofwrgy12ioBmEa91zXCopoLzlrDyNvxS+vpCXIgS6nlVVDET+1YPoaqiktzDD
+ixNFzK9Pomxea7SxDIKisVwHMj9BKu2RMZ8YnByXPO7PnAPc3JQr2wVq1OvkdSWW
+0Zcog8PXat9mjkBI6swwH9fUvULoaR15wP2noHVgYxWkNVgxeFaGaO0Ggt93Eg2M
+QN+QgzhdUKYNpTIHkfz7Dlc6dzA0JFb9FBzRhgrI5ZWEYD43XxDNDKWOBCVds/fN
+px6YXpV/c99pJgSQ9rHAzo7bNrHkGezkmMUPoL2+m2Wkl72Wz/56nUk0oUB5H8oh
+AiYbymsrakScoPaQIvGdjQp63HqoJlUNMA934yhs1S3CegydD1OX880cmBS0vCUf
+D8EztHTJN3d1mozalJJks+LO2BcWckeeeXYQJbD24H4MH+NraFq6HpVJxiERgqlm
+brGm0/ofc7yRc7Uh2OYiGAoTNeNhQG+7xEnTuPLrVNYc8DCR5hv2vSLg4HI48NCA
+D/JKwHY46o0EkJfmaVUWXw2NB9PbDQ4UpTwrVQhxT2pD66uCjOTXl3nPqyVAqy7N
+6v5KP6/5QJd6iuW94ZGCOQi7AFlcyaOlfFg9ZfqQERUCpmf9H6O+hPfmHGmQDQyB
+6jeiDW/wpqHcNr+Bx3zKIsYJSQdWmx5m2Vqzz5xuO44lh+xCWBUrh5mg9Bj6MWGg
+jVeLwDWN41ZvxeiPFxnqLToPIHrIZ5Qk/uEHa8C01bonrIej1Yi09+J0PnhMLB6l
+mNGRpjiXWpKJTg0XzWd+IbWhoNIcrIhdcy1I2dT/1D8kITYXsSFiCP9r/UU7KpCR
+vk1IyYjU4UySDkYtMYtQpg4mL/uTfLBIB1hy0TA0LCYqj6/tzKfiKeJlunYihlot
+mNl/dh6kMAhJxLVUY3D2N8Zcu4ouA5HejLkTVvrZMYQ230RZTQ1jyabP3+/JIWCs
+qRgP4GR8GjYUcg5Y3toLSz50TsxgJw6WGHJ+tMFhEinykTq+E1Xp7nM7ojRbjt0m
+A4EX3sGaM6XemE5LAQ/EQedSlBoKNFuBpco1wg/8+SedF4exU93mgM/cLwwBc7qQ
+aMtHlvld0L3S2w4yh7n2/z7h7ahh7XpnShRrfByvlC410KLpgir1arL0/Kb+8vkG
+ssDqC+Y15VJTzdKB73dBTYOTUjQIT3m1V1JlTkO/TRNHFiBgb0qKYVyIxosaid25
+Xv+qWwqtvyLAimtmDrgoNE8PgsVPENOMqlnPIUjsWmvTYL66oywVfjIk3w8KtKbz
+yV+7aRlNkiFnVNb4kyuAvHWxAVlus6C9TZrGA8Hwvr06TjuppCJ6HfvbqfgHnU3P
+cenxRifUFt20pD541M6aOD8MdVlSa2+e6ipzWxjZlrwkFhfalB9AttrLSt2z5cT9
+rYXSX4dtag849hQHceLMVitPBrKO2jeU0PkDxMIj0bRnWFEQZJwNMX5Ea3zjC/J1
+srTHxJszkAyt4lWT0oJDSoDCov22+4zFz5z+S1qVj0TOOAt2Ea0/uqFX8V1Ep/i7
+O55edfiY9YtspG1LFoOLEgDuuYuObA9+ndgtKPGM9uzKPNHqQpC/yOBpJIMhNzeQ
+S/kQHB5F3o0Ik9HWTMG4KesuS8EBXQJmfJD/j3B46oSqOmdU4aCqRCD5twIlszOs
+ddn3wGjmEDBvbELamnbGobPHbzTEcQo6oqUOH9qRQul7XUfzNgME08OUYKW8fLdV
+gVc5/CsUkD2ymzRMWhR6S/L45JzU2Xzowcb1FVAgZkWKW4IdTKmQ85W8JNTLo+x+
+KsCSGzAxqhOJpnQe1Fvx4YtOxI8U74Ck6XvPeXsQaEcdahKRKT6qbGDAoMVhdtXX
+leCOIGujBmw1r9eHXHVEFyGbJSflg2n7gcJS8GgqjPb90DQzUUV/GlTgAHFtL3db
+tmyHyKUF7tM4JCBZNfQsUfuV3eUL2Sur0hA7z7w29pMxg7qxjiAn2DLJpDI1EaIa
+NaAEcAAzWuaCkjMECy6eF2yi76jYySTWcxqfRP21D72kge8h/TZWrE2RoyrCW1rn
+kqolaOtzIHpSOJ7qvPuj1t0GLLZDox4jkJUdBp+v60pMjkTTZ64KJo2mpdUF1EQN
+Wx2hzm0uNVK1dG4dGyyfj5dZLsoparmv6/PcfhjtOgz1Zyd0MO8ubQ9+RoNUNh5/
+gte3AN7lizsTtJ8cHBxPulFX/O8h/pTQXYkpp25rkA06Xqqm+64uUp3QYlW5COuS
+UU6Bk/VeYpZJEQA++0Pl6tnRXJdPWgfyYGGyzonHnZVm9yBhFmX4n2db9r6ZfZgn
+Al7oONACuD3lGSH3OrSRRp5W8PClX2HKcqpqxongbf7P4hVXShQJ3RBK9O6xC/ba
+neIAdOySJF+QpqVRbt1Ci8dQF3kN2icIKKEdePBlLPu5nH27AyP6vhHEl8K3SXeU
+4hb9N4SmuyiO39MmDAPrNiU/PnG6E2/4p7iYOrGR+GA27qJvJQNTsBdJ3E5UCJiR
+xCbdVfgAJqwjolND/vg5Ud72dggaBtsXjDuadXJW+ZENKO3XSyvcsCH+bkO3PSo/
+gv8tx3vyfaJQkvnoFEY4NkUrSCjBiwWvepxpkERwqVZq7pTd6tK7TGN1xE7ZUBAO
+Bx+Uo4UJaAK+3E0vNJ4DyVSS/JSNx4gSac6tt+6l00yAOWFlStseVRDP9I16LptV
+2b0CgoAL0j52g7xpxw34Oml45SSL6SEqcf2VVyWt+piCXJyXvyiot9yJKDfDtSj2
+6COpaQ8OeoVXjesgrIn/UZS+Iud3amRHBtc67oRy/3X8UdNK4k93pKh66d870k1D
+iz8JUUGjnrSpE2FtCS3w//7cyOPTzkasKhlCZbdhIrZbdce1jjeDlQOwqehxrfuV
+zvPQQv+gmnaHoyHyMirpVTpEo1MuP2hh2x7csKuzvNyE14n0QRRY66/HwvBc3psa
+4KHITy5mWsE3CqwWTMpUB6AvO217LQo8ea6wrPy7dXcqnEOjag/Uhbw8z6wlMBaR
+2OeSaKmIbmMppGgiIKf3xU29C6UgUJyd+nudlFQRtazxQNX8TddEeJvj4fb4zE2B
+o6WBbuj4bKY3E0i+IhAfG5K6Ez4RRxDa2ENJJxtwEWLOoUNwykQeXDB2EnhX6cuL
+nhmAhO7MGXReJfXQZrXyOTHKjPInMmwA84WuT2+d/vbDYqdQk+jBBnmlEwncI10a
+j8fXsxJaKsMZikTtAK97FMbWrIhv4Ee7RNF9Wyz81ZaEZpi7UcdU47tHQiiiO7v9
+f0gmjmYhNJDyZU7Ic0JjLYztIZtIbnv0QzxwNFEyxZOuPJYp6Sqf/S6usZl3NOEv
+6Zz1mL0AQw8Xdk7Hb7aQH/WXAUe3YoUw1s/KtH05FVmtByfgKYHk6gKXUwAXoKmD
+/yxcGbbG5Jujk4IOA4jliMTTwBI0EsdkbpXOyXiZzEfZN3vE75d8OkSyLX6SCPws
+iRDFkf76BcyGlhgzLsNMIJGZQmryMzOkfeA4Z7kDLRCJKl/86Z6Kywrtc64ZQw9F
+6PgCdKQi/LrP213Oz33J/svL3AfoQeeTIGDkRKiS5Oh1PyyWn+/TaKI1/6ioVjYX
+dcEen2gTE4sUmQEJ4490m1Kf6OTbpOXK05JrOhrdHXxAaHVgAFQ8nPuZ5hEu7lct
+sf5zaw25lV30Bpw6qSxJ/isLYfy6jHi9zpdJQbrBPHAnUr5VUiGo+DMwrnEV+cy6
+hCCS9Gy6UOy9XnF/HEaR5FRGO3X0K6rcrDt1QomTuc0xKsBMZSvYR+obES7XxmgG
+o54pEFqL9N1P613L4eeJ0QXn05fcU3HJLUmC7BVftqaTRN9YbkPJfyhScCUS0+fR
+uCA3gcZnjHZHhe0h6/mLU3I1faIxACmtgZqP35zm29/hDWcJexvlUr8YvUTXJSnd
+Z3gkwj+8crCoFsOFQFcZoM3hsFeyYd1SeYVEEBiXwbaZ7BeenLbEUVHqiVW8yNgA
+dALabueNqtY6cLIPAYtaMEB48dIOv9jRbVEa+u/leGYKQPq47YLXLcjDk5/Gtpqn
+WeyCuiBFU0TK4+NlAAgQpCwvKk56Fa1LK2Irv8HleB8xihaZEXbhaR4FsQJB+1Xm
+cXaa/rXtg3bynOoppNGF6Z5/GxK+xTl+K68q1+PC/i8d6exCyK7Wrz4BREupZJqo
+f478So2wg0+9RKS0wWnTGRh+TlMkwsvnxP9fTK3PI1wTtB0H7uTcDmT02TNH3eoL
+AQKTwBfEfe3sqCS40eXWWEO1AvC1ejN8FRkRU8X1T+0HzryEUBfqO4q2dEFfbUId
+Kf49zciQoTXe9hEDijkYHQGD0a90sW3H0pdZi6KfvEinJBdKpwOqOj29RyayATF6
+QhWDyUFdKceBFT/1LORbkplN2mQVrSXjKr7vOk9UMsV1yvI1BTAbC0mlxgcQsDt/
+c+chq5DDtMHWlgQHkdxNxGTuo4s4A7IpXXIgdiItPGmuDcTuqPidmXQ8xaHpN5iv
+sZShjxTyIclMB1twOo0H+9kB46vVwMbk4ZqUMMyMPPhSSEMt6f0RB7n5jorNJ2NK
+03aXseAGcRmjfsBxNcSDmFAB3ypxzfTOCoKaSWtvcHbhr94Q6eWbgxdyQMwTyuKu
+THG6Eu28F44pGpICsewmz8qI38QQaTSXNfxpV3R1xPF2jpBZia5CyA5zuqNEMkfU
+jvoavH7yuX24WoSYhH7OrmZhZfOOiFMGMKOEXMZPnkOL+oDiyTr6Fr24AdCJr9gT
+HeNp7vNVFq3rQc0q1AVPZL7RA+PCARlItDD7OFD4pYjWsfKAQp4Tm+gpICzwehoP
+8aYVwnCsurq8j5ZrOE+MW4X/bhZcSoF+NnZybCtSm/sBPe3gHUqz07jFzmTlMM+4
+orc3RaSvbFX4QDwrMEEtzDnIHN228kTGUHKpPQOmYImDu+x1oSafKgI3ASsuSWI1
+HLwjxsZu/vecvqJXwQ+V8ASydlYxvCkd0Q3m14pXDCeJOOLB91L9djYUaJ51/ffL
+s15vDndkOEI94G10qASWf9zAutnYZVpXK4uugWSccMuifFvbLcEw2EMjvsuKtG3c
+oSYq8/+7qtRVbmVc01qo8wRily1GF8YN3Hg5o1lSSPotLslAz3EAeJbtQ912iwx8
+2sYc4ZU8XUQGft22xEZtqljxM3Mc4KnLy6JJYF+D3v3iXH81CM7EoXiFsFYkmXTz
+GXNcrDCJQ9YEZCehEVVGrsBIMCpTFVbnlR4TVnKJCJafyzepsXuS/B9NkV5ovzIT
+hNE6XYULUSI/rr4rF7wSDVAXtOePREGzex+zmBqrM9KUdVUAA/OhQOwJWWz19fnP
+ZBE01SWzMtVHBPSrd5ewX1P9REzHWSxFYYkklki3MsOqbNrn6WH0O1CfiMEldc09
+l2a/FipE0G/N524VRSWQRogQQKoKJAJX9kbeUlTW1bbNdQykOfsD5NAXFmcbaMGd
+js2m4LgMzESv9e0FhrqJLVG0EREAQbdaAj7oRMp9PWE7FqlaTwy4QwGwlfPpouXe
+e/n5LI6x7CE3OgjIpJV4dK4kK03pLWWfkZo4N4FuqCx4SjITlu2ceiZr5uApHYeq
+/abn4vpioSYWtSayYMRZgApDko9h6Zpmedketrdc2ld+UXPmI5Fh7mm1aIH7w6IH
+35YRPoewMWHtfPpeIRhaBxmREdTRqqPio8pqYnirJSOnuM5B6PpFif/BH+TqsU7u
+1YxkzP/gh1fs54lgTwcYTGi6hozgXg+QepY+bD0Oii2CRR8c0LnBcMi4/cYlh5/L
+uoYGfcDRYfb3I6dheKR4P7Akq5ZdxOc7QNIkh68FbxvLnWFOUf3v31AXx4cA7pfb
+E/YoZ9FCha6gmrkXVjja4bYguQsza9eUhZSGuc7ueiU+UaCBHh8Y9IxbJhaY62cO
+Ju988EgefQRVqgvYXM0E1cm5LhAt0TkKhwhNm+QsTyclGY20pdj0XvWFxU70vpUj
+JJf0ar06KPg+t7ICg4+WX49bB3V9bDRpf4ejxh5ZwfEr/EfTzTcLtiYy7uVaE2gn
+Pc5fA9ZauXBratNg6oEKLsCgJOt8tiSnc6argF8b9iQ9Vpijm95e7uV+fGYcEQGF
+eiSXuJ9rnnGuwMY/cVfcO1aaj89i5RoGkrrtDhoAu7MAzhvkOVnm+aRqK6xpZrMd
+HroxIkem1NEtZHmhIqNVCXAMPx2/nYF/DBP5lsUSMWNCldXe0szsPvjWDYBLTsvn
+Du/ntTn7Ed7PvTPTzNAGmiL+H22JxSeSj2KR3El8DLSx7vNkXgcDKnApcySA7A/y
+2ziqlHh9MMa0w9fQS/kHRUWzZkeb+DyaoPt+vcM48fbD0ZNzg+fPqovD14zbmcUG
+M2coczvabifZo8HAMcStZeCDD1k5kgb5UlZQrdMFrFTuxGkFvrQY3tECKUk0cs3U
+JwiW2VyTNvf/G8o4EeS3moIhoKVbeMc/Cs0gPHCkkLA8/4fhFXYIcue2jeBmYtdk
+wMs9APUnKApjzCS4SL5pW6gszIzC+qOLzoiYnQ67GCiyyGnQtKVZdGDjDrnsZH9N
+FN7YI0knERR4/a5ZKRp93spm6mfvMNkRI8o5ZynvapCeK65st1miELEFWQG43fm/
+pxbu14NuHUsROUgbJT/5M9PiEtGRdWkt+8bp5SpHCrbstL5WoLjl7iqX0zcGKQ2F
+8vSSbcD/5MG0GU0vJzPzfwLGaPYY+ZxC84SJmKWPVvpXFSSVN4yoBInulltnxkEF
+hOQk6MefeJuqlQaRbXVKAJ2qE9u1dgx9dB2+Bwv7yDM2JJTYdxNWjdXD5fAnbL0g
+Yx1be3PIR6xRr1wUmLyKxdJHBMZyFFwSuRQaPCZz+Z0bdswwwfotLkXlxUnlrg8x
+89lt5ghtHqn6G7/cHSwcUULMJL5uQe4bNi97+rVZDo3hUGEjTmeQfPBrRSdI29IW
+8gX6GMy+0Vxeoie3T4hBbB3hFx+HTEWDJSKMRrfC22myhl9TA+4aOVaXtAbi4U5P
+S0lXPVG7VaNr/kyY0tZT7DMAEpYjSt2qQxxw/to+zJ5zTERn+TF5E/Wmevldv7V6
+J3fhdS7mgl9Q/tZsuGnW7syYQgMzL+PICEy+Fd/lFsRTp/Y78+zLwyE27bjHfoSR
+YsF/DocOiBKRPvQDvoEXbKV3HiGRaTrvNxSgzPA+g64FdgJVR9kAOJpRK0wW8GWz
+ub9TeJwZIy+GaiCIpe6W+gX8y7hgryBjIsJDbO4T0hKS8ePlIv27mNq/vxpK7XbL
+v9AZgn6ToQnMmgAlHSfZIAM1B16eRFsfh5otshL4QQqd1Qo1lTPsf84Nb9KqYW64
+Y39tMrIHniooaKx4wnaVU+AIjVkKSbH+2J5htZ3L5XQ3vWnvOGFnTfuz1LsKv2XJ
+04fcj28VdFax+bqbPruQpNfYWq+0noDz/Kyx+2mcSOUYn04oYn7oY6evp1Eb76FK
+mSl2xcpWNfUK68WMOlb+ls3nepgHbilkxc6CXQuvM9dZ58wJUxi4hayuQD8QOUfx
+neGLK1b8D05gZPKH5zR5CsaIHvDKE5QKyrQlKHKIo/vJbY+qBSknhSFo+lcNEHms
+5/oCcbfWRX2c6RflRpe2XK7/+zdeyJKpA78mH0PkRCWA9UYWoZMaVAA8f+1uqrdW
+eMBlj40SCxBMvveUtX+ChttOHDRcPnh1M5Jbbgk9LaQqEue5is77/EYFuR8+6QRk
+fyKzr/094SB91CyevEH6IghD6AYzoKJU+lHDtsrGq3/pR2vcFCkig9wnru/Db40M
+eO9eDgGvhlo2KbyZzyze2NwLLI/iAKfZrxvvktXBFXzvZF8GFyU3UfyMmo65FDpa
+B13RqIDlEBeN3/WMfuRryzytIeLqs43u3oQL/9STwgTb3RYceqsWa3TTY/gEJpBJ
+rFXgTFzC6BfE2TE5V3sCUsKsac2xYMG9Rtvw/LG1chrjL4zxAiubh6vXiHvRGHai
+0H3EGXYEaxrG9R7rAepWsjHHc1w01Gfo2eAqdNvB3RhbOkXwnXAL+ECuG71LZx9F
+y7jKUIwTq8rRbBrulEscm1fqi8Cj5SW8gwltUPbx1BAwTsknKJzLCCumacYEbD6+
+TmzoXs0UdgkzoTe/LxGOTxa4tldyngw+0srgXceAbyUmFJXK29uU33iVF5DkWsFA
+1D9cgcaNqwRK2M7KqzIm4J3fBhoPkltb/VZH3aykdRBRnIfDVWCooC90j/CjH7+V
+fpskB2mK8dBI1i9UnjDyE4Nufp2NH0tQ/7Opec7qPuXISyfzJJ1qj0+lD3Ytx9AT
+7oUael3nioGUJLJisvQ1ClV5yxU1VYWZbiuz+fzm1eyEdEYwSQcdPMvZ4Q/Qc7HC
+KV83an3AIoHlH2CtjlrBdP5CW/vSVCzctreDB/y1YlJESnjvRsJE2pddUkjueRp8
+8BDxsGhfLc1QwZBb9CeicaEyojSOhzqU1s3QENs3vJqeqEmAQ3fdKCikA+dBSpmM
+E6ib0VfjpBvVh/RTwuVadEQtfu9VCx9zzPyKre8XQAUp8X+VsqZAvRITThBnDOTb
+J2K6k96qqFOO7NVhPh+B/a/A+rSZteYMesg8oVs7YhLLgqrAGVcAAMzuZh+t9tqr
+ShM6kahnm7cMfCrBJf5ai3MsVCXdJb1IjUUZAlapO4KZ5HPIHN169iA4ea1Gu4ae
+LPuiWG7J4dF2sWKL6EkvzWW/4+5g2SyEJOcpxyEe9ZUVoBTMv6XVm5PALC2Aqh+E
+BH53K1zaua2Di7FkbxKt1/1yqMmc/gZsDklLdGlnRAANR4++fbjAiPTNg1nA756q
+NPLJIBT9WUl3ANhU9SufoXbPHX9XybtHtM78xsZIfC4euNVPUxKYI1k4eirjGj6S
+pusOJN0IfgMlPffl2IjpJt7dz04JZzLWrpVnrfIRdRG5JBaBLhKa6xNHMCRZ+2j9
+yJ399bU8eNMKHTI0ctiX+BVOHDzJzuxWuEQeKaMjYZodGDU1zjYCwHv09m+Kfgcq
+kOnG28g1Pjus3XZYS98zStrJN3mKsbNC7ur8L/oOZ0yWxfcfJKplUn2F0A6kiuNU
+6fS/mY37OXVdUJLrRi8qctCsYYWlxSmIUiN/+cXdI7gjfNgpz1RhMtGKV9vFmlmv
+64JB+/isoqjMpoYKS+4p82wcRxIYcDnTWpMaNmOQuB3F1XCubWU0/C0hj6df59uT
+VzAfve34dKA3eYuFqSE7qwf2etT0NB4aU0UrBQbIb2zKWfg+J9pD+gBa5cvlvthZ
+Szs6lR/BKw8VuhSzNwcGWTQndtmIA+g8ZUB2UQRo/xpmAQelzWIyveiCJqm6mYWX
+ulTmkhi23RzKKtV9WqgFz0JlHG+KF4VvL0HQ4SZvnyRyOQPumdI6UNjACf8tFkvh
+/3jGbKwOICjIFdK6pVAHbEzFLLU1VLFpvkG4HDDy4+6HLIxKFzM9ys7n/aO3/ss6
+JeZIl9pd8n+4XJpIngQocjxC8+vBYxqzfinWXaGE4626pBiTsGKYAgbh+ps2ZV28
+MKiY7x3nmjo9kZyvb44s/PLfDsv40hnHsY1JHXDvwtYlg7/94r1d9SYEoZEzzH14
+V9YhY/xrVFNJEVqPSCCgk3KA4fARnQMdW6qAXDHvybzKi6SPPg47uIQz2HBMXN2V
+knghVQWmQL6QLINxXANQMLA2BejDwSXjTudo4PrkA1L381P9bU+FsuehGNzqbbHY
+d9fM6gvr4iveHUjG1E4y1Gp3IvzDVwTiv3YSC4+FnH5QAm1hSmHtrklltJ/6Pqi8
+62lYbbpN5T9aDbgDwruHWboy0bXJBvGC0va1VvrUC6SuUkgnYLVBTYpzKvZ1T3Sc
+LuCQfhWZFyaq9RetZmuI8L3XiiddOm8gZP8PIhxQvbA3+thbPwvPn6b50/MnXoj6
+fATOaqSLMrA/BGarSuG2b/kf3uJFozxKrQLHCxVvXnsDNsvyH7ikTFxkI48o8UoL
+4NsRMPP7Vgsf5bpns0wPb//MN2mev+EYcZ7Y/rnSojra7PnmkSUfb3C+85RnDgnJ
+DuE0RqwKk/REaXeCWu8uma9q5nTxig86y9225fki+HBoxPSyA2IEkozEAN52h/N9
+bAoO3hiyTyzUcxNPl6spMeFx8V/ugl36f3x2LcYVnHk+zHY3ga2UfJ3X1GPYoZjf
+VTcjQBOgqJy4Go3iiI+Mx+pdGKmFyM+RZongCXiZzOq+aPdingcVVyJxVKvps5IK
+m467cO9CvZRx7J6UnilrqxgJJi/dogKriGGTZvJyrSed76XqJHQ8D15E7cxFWuId
+DIvAvBO0TrNQFl4zPyoAsY2ngns0S3HrexT+Ptn09rDzMsRjYjWb/dH1ZprFBMCj
+Gc6FMdUIUCtEJid/vL7pcLCjG6O2F+EvyXDl7GLVlGjTZUhJrgBIl7R28ZrmqHOJ
+//1CfskTAV6KeQYeSsHENmwlO9WnUnP8HUk06noQiAY0YYvQchGa5GljulCrQoQU
+KZN5k0liw5OxMYm8F98DcbgQ56vUFFrqcJS9J7Tn8pCUzZDeGJf4WQLLx7FXAnjh
+sfv6Zhx9Tt4VPprRkCOtO3LawG/hHK7KiZJFcxFCpSfZ7fitZW7+0sHdzGnk0c2a
+jV6QdiQlAMA9MbaNMNHHafDtJJXad9d+Vyn8tr+904syIrQlx2A8zgH7ilzdg/HF
+I4bwMFsFd3lcIlLFcm4KGoSBB0m7xA1QURdGXlar+qmrb2wxe6IBv+3GHxvm3prs
+875s+x3CvGf48DG2hS/uttLijXZ12AOXM7vpinmuu47Xtooht/R4lGJiHarIKfer
+qTqy3GEJ1gkyDm6FzN4wv6MdbcUaOcJ5G1QaAZuqueUZk+JAeqP+z29+eR33dA4j
+vx8lfsT8SII6LBztPPnWuXTlYK3chlYNpw3K8jEaPl5SlYpdz0YDuGWGP46E4qRE
+7x/H2/7EVYOTThfsMXHL6e65/Qtunigt0TWciK0aJZgGWOx8P0zf2g63H8m803TF
+W7obYOKvbtcwIr8LrIiXwJskuuqzLFyyyXjirsHLFXm6COfV+2GcyhCUaqoigofA
+ckQ2iY19PlW7fIgn/9vSbV2KufVa5IopE9NhpxkltWdBQr3FvgTHIVximjMDW096
+2PPUJXcqbmDti1KCt8BYW9VgV7+OzLorRnWgr14rrTsGLUQtiBK5KAEpGcy5CwMv
+zLvbCcT4Pvkc4HrYNnuGh6Gev+QudR4RL165i6sI5bIHUVz42Gg69pJ9TyA7OXhf
+no3Yb9IXTRoK8LmficSBqtlA8WH9SJtN/QEVacYl3btBrEUJzcfylpXA4VZ//Ota
+J7uSv890nuoLxjKl6Wa7COL8PD57YeTxrJhnmLHJCm09RWwTveghYx8bKAxIbwHU
+nEA63PqrIM4cO5IMbNmhGOIIdze00+f/YOMPQbL9ORCYuDScJJPnGHfh36J+j23Y
+dGMhZk6x5BL4n0Rx2k0glwZz13vArAEiCnEW3HpW2dD+XK5snyrLlRHYBfH3xIrt
+QpL74fYyHfXhuu0Jko1JbUYkH3nUxVa371Dg3cl5OAqaPnE2Wt3iCisVPB6lqI/K
+DtBW2FnRBMtDZg1Q/Bzn+yngjGQ/WBCRt8EBGnVuHXwapJX7brFtakJ2EF3HV378
+IDdv1QymKruFVClyoAJHWbTuDI+JhC7VS+z7G+ikvyVGkI11vZPZgMRXVQ+nPAdO
+/+ogq35kRHWLvW5DL/tv4AKpCKkJqNv5+CBMit7onsxAxcW9m0IT1fisJPDkAF/q
+hzWSIT9pBpYP536WuI9HvlXb0J/rPRxYBPc4v8Lv8W+Ghc6oHk5G3/vLbhWktQHk
+brXkwxiiyCAdo5YPsBHUvc2iBAcTPVgfuyVmoY7AqBRt7aG1OPV3755s0sqPEBeV
+`pragma protect end_protected
--
GitLab