diff --git a/applications/unb1_reorder/tb/python/tc_unb1_reorder_seq.py b/applications/unb1_reorder/tb/python/tc_unb1_reorder_seq.py
new file mode 100644
index 0000000000000000000000000000000000000000..b9cb30a674d9927a88dbc4ad630ec6d8767339a9
--- /dev/null
+++ b/applications/unb1_reorder/tb/python/tc_unb1_reorder_seq.py
@@ -0,0 +1,185 @@
+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+"""Test case for unb1_reorder
+
+Description:
+ Tx seq --> Reorder_transpose --> Rx seq
+ | |
+ WR DDR RD DDR
+Usage:
+
+"""
+
+###############################################################################
+# System imports
+import test_case
+import node_io
+import pi_diag_block_gen
+import pi_diag_tx_seq
+import pi_diag_data_buffer
+import pi_diag_rx_seq
+import pi_io_ddr
+import pi_ss_ss_wide
+import dsp_test
+import mem_init_file
+
+from tools import *
+from common import *
+from pi_common import *
+
+
+##################################################################################################################
+
+if __name__ == "__main__":
+
+ # Create a test case object
+
+ tc = test_case.Testcase('TB - ', '')
+ tc.set_result('PASSED')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> Title : Test case for the unb1_reorder design on %s' % tc.unb_nodes_string())
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '')
+
+ # Create access object for all nodes
+ io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+ # Create instances for the periperals
+ c_nof_streams = 1
+ c_wr_chunksize = 256
+ c_rd_chunksize = 32
+ c_rd_nof_chunks = 8
+ c_rd_interval = 32
+ c_gapsize = 0
+ c_nof_blocks = 32
+ c_in_dat_w = 64
+ c_bg_ram_size = c_wr_chunksize * c_nof_blocks
+
+ bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, nofChannels=c_nof_streams, ramSizePerChannel=2**14)
+ db = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, nofStreams=c_nof_streams)
+ tx_seq = pi_diag_tx_seq.PiDiagTxSeq(tc, io, nof_inst=c_nof_streams)
+ rx_seq = pi_diag_rx_seq.PiDiagRxSeq(tc, io, nof_inst=c_nof_streams)
+
+ # Create object for DDR register map
+ ddr = pi_io_ddr.PiIoDdr(tc, io, nof_inst = 1)
+
+ # Create subandselect instance for pre-transpose.
+ ss = pi_ss_ss_wide.PiSsSsWide (tc, io, c_wr_chunksize*c_rd_chunksize, c_nof_streams)
+
+ # Create dsp_test instance for helpful methods
+ dsp_test_bg = dsp_test.DspTest(inDatW=c_in_dat_w)
+
+ ###############################################################################
+ #
+ # Create setting for the pre-transpose (subbandselect)
+ #
+ ###############################################################################
+# ss_list = []
+# for i in range(c_wr_chunksize):
+# for j in range(c_rd_chunksize):
+# ss_list.append(i + j*c_wr_chunksize)
+#
+# ss.write_selects(ss_list)
+
+
+ ################################################################################
+ # Test
+
+ # Wait for power up (reset release)
+ io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
+
+ # Control defaults
+ nof_mon = 2
+ start_address = 0
+ #nof_words = 134217720
+ nof_words = 100000
+
+ for rep in range(tc.repeat):
+ tc.append_log(5, '')
+ tc.append_log(3, '>>> Rep-%d' % rep)
+
+ # Initialization
+ tx_seq.write_disable(vLevel=5)
+ rx_seq.write_disable(vLevel=5)
+
+ # Wait for the DDR memory to become available
+ do_until_eq(ddr.read_init_done, ms_retry=3000, val=1, s_timeout=3600)
+
+ # # Flush Tx FIFO
+ # ddr.write_flush_pulse(vLevel=5)
+ # io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
+ #
+ # # Set DDR controller in write mode and start writing
+ # ddr.write_set_address(data=start_address, vLevel=5)
+ # ddr.write_access_size(data=nof_words, vLevel=5)
+ # ddr.write_mode_write(vLevel=5)
+ # ddr.write_begin_access(vLevel=5)
+
+ # Tx sequence start
+ #tx_seq.write_enable_cntr(vLevel=5)
+
+ # Set and enable Block Generator
+ bg.write_block_gen_settings(samplesPerPacket=256, blocksPerSync=16, gapSize=0, BSNInit=0)
+ bg.write_enable()
+
+ # Rx sequence start
+ rx_seq.write_enable_cntr(vLevel=5)
+
+
+ # Set DDR3 controller in write mode
+ ddr.write_mode_write()
+
+ # Tx sequence monitor
+ for mon in range(nof_mon):
+ io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
+ tx_seq.read_cnt(vLevel=5)
+
+ # Wait until controller write access is done
+ #do_until_eq(ddr.read_done, ms_retry=3000, val=1, s_timeout=3600)
+
+ # Rx sequence start
+ #rx_seq.write_enable_cntr(vLevel=5)
+
+ # # Set DDR3 controller in read mode and start reading
+ # ddr.write_mode_read(vLevel=5)
+ # ddr.write_begin_access(vLevel=5)
+
+ # Rx sequence monitor
+ for mon in range(nof_mon):
+ io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
+ rx_seq.read_cnt(vLevel=5)
+
+ # Wait until controller read access is done
+ #do_until_eq(ddr.read_done, ms_retry=3000, val=1, s_timeout=3600)
+
+ rx_seq.read_result(vLevel=5)
+
+
+ # End
+ tc.set_section_id('')
+ tc.append_log(3, '')
+ tc.append_log(3, '>>>')
+ tc.append_log(0, '>>> Test bench result: %s' % tc.get_result())
+ tc.append_log(0, '>>> Runtime=%f seconds (%f hours)' % (tc.get_run_time(),tc.get_run_time()/3600))
+ tc.append_log(3, '>>>')
+