From 161c639546b73cf63aa163a0629f444911e530fe Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Mon, 27 Feb 2017 19:34:33 +0000
Subject: [PATCH] -Reverted the addition of PPS delay . This is now a
standalone component mms_common_pulse_delay.
---
libraries/io/ppsh/src/vhdl/mms_ppsh.vhd | 20 +++++-------
libraries/io/ppsh/src/vhdl/ppsh.vhd | 33 +++----------------
libraries/io/ppsh/src/vhdl/ppsh_reg.vhd | 42 ++++---------------------
3 files changed, 18 insertions(+), 77 deletions(-)
diff --git a/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd b/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
index 3f71e89e40..07cab54c38 100644
--- a/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
@@ -32,10 +32,9 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY mms_ppsh IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
- g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_st_clk_freq : NATURAL := 200*10**6; -- clk frequency in Hz
- g_pps_delay_max : NATURAL := 0 -- Maximum number of clk cycles that pps can be delayed. >0 adds an extra MM register.
- );
+ g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_st_clk_freq : NATURAL := 200*10**6 -- clk frequency in Hz
+ );
PORT (
-- Clocks and reset
mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
@@ -71,7 +70,6 @@ ARCHITECTURE str OF mms_ppsh IS
SIGNAL st_capture_edge : STD_LOGIC;
SIGNAL st_expected_cnt : STD_LOGIC_VECTOR(ceil_log2(g_st_clk_freq)-1 DOWNTO 0); -- expected number of clk clock cycles between subsequent pps_ext pulses
- SIGNAL st_pps_delay : STD_LOGIC_VECTOR(ceil_log2(g_pps_delay_max)-1 DOWNTO 0);
-- MM registers in mm_clk domaim for pin_pps support
SIGNAL mm_pps_toggle : STD_LOGIC;
@@ -85,8 +83,7 @@ BEGIN
u_ppsh : ENTITY work.ppsh
GENERIC MAP (
- g_clk_freq => g_st_clk_freq,
- g_pps_delay_max => g_pps_delay_max
+ g_clk_freq => g_st_clk_freq
)
PORT MAP (
rst => st_rst,
@@ -100,8 +97,7 @@ BEGIN
capture_cnt => st_capture_cnt,
pps_stable_ack => st_pps_stable_ack,
capture_edge => st_capture_edge,
- expected_cnt => st_expected_cnt,
- pps_delay => st_pps_delay
+ expected_cnt => st_expected_cnt
);
------------------------------------------------------------------------------
@@ -111,8 +107,7 @@ BEGIN
u_mm_reg : ENTITY work.ppsh_reg
GENERIC MAP (
g_cross_clock_domain => g_cross_clock_domain,
- g_st_clk_freq => g_st_clk_freq,
- g_pps_delay_max => g_pps_delay_max
+ g_st_clk_freq => g_st_clk_freq
)
PORT MAP (
-- Clocks and reset
@@ -131,8 +126,7 @@ BEGIN
st_pps_stable_ack => st_pps_stable_ack,
st_capture_cnt => st_capture_cnt,
st_capture_edge => st_capture_edge,
- st_expected_cnt => st_expected_cnt,
- st_pps_delay => st_pps_delay
+ st_expected_cnt => st_expected_cnt
);
------------------------------------------------------------------------------
diff --git a/libraries/io/ppsh/src/vhdl/ppsh.vhd b/libraries/io/ppsh/src/vhdl/ppsh.vhd
index 6e68e6999c..9a6332cdd9 100644
--- a/libraries/io/ppsh/src/vhdl/ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/ppsh.vhd
@@ -56,8 +56,7 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY ppsh IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
- g_clk_freq : NATURAL := 200 * 10**6; -- clock frequency of clk in Hz
- g_pps_delay_max : NATURAL := 0 -- Maximum number of clk cycles that pps can be delayed.
+ g_clk_freq : NATURAL := 200 * 10**6 -- clock frequency of clk in Hz
);
PORT (
rst : IN STD_LOGIC;
@@ -71,9 +70,8 @@ ENTITY ppsh IS
capture_cnt : OUT STD_LOGIC_VECTOR(ceil_log2(g_clk_freq)-1 DOWNTO 0); -- counts the number of clk clock cycles between subsequent pps_ext pulses
pps_stable_ack : IN STD_LOGIC := '0'; -- pps stable acknowledge in clk domain
capture_edge : IN STD_LOGIC := '0'; -- when '0' then clock pps_ext on rising edge of clk, else use falling edge of clk
- expected_cnt : IN STD_LOGIC_VECTOR(ceil_log2(g_clk_freq)-1 DOWNTO 0) := (OTHERS=> '1'); -- expected number of clk clock cycles between subsequent pps_ext pulses
- pps_delay : IN STD_LOGIC_VECTOR(ceil_log2(g_pps_delay_max)-1 DOWNTO 0) := (OTHERS=>'0') -- Number of clk cycles of delay applied to pps_sys
- );
+ expected_cnt : IN STD_LOGIC_VECTOR(ceil_log2(g_clk_freq)-1 DOWNTO 0) := (OTHERS=> '1') -- expected number of clk clock cycles between subsequent pps_ext pulses
+ );
END ppsh;
@@ -91,7 +89,6 @@ ARCHITECTURE rtl OF ppsh IS
SIGNAL pps_ext_sync : STD_LOGIC;
SIGNAL pps_ext_revt : STD_LOGIC;
- SIGNAL pps_ext_revt_dly : STD_LOGIC;
SIGNAL i_capture_cnt : STD_LOGIC_VECTOR(capture_cnt'RANGE) := (OTHERS=>'1');
@@ -163,26 +160,6 @@ BEGIN
out_evt => pps_ext_revt
);
- -- Apply a number of clk cycles of delay to pps_ext_revt
- gen_common_pulse_delay : IF g_pps_delay_max>0 GENERATE
- u_common_pulse_delay : ENTITY common_lib.common_pulse_delay
- GENERIC MAP (
- g_pulse_delay_max => g_pps_delay_max,
- g_register_out => TRUE
- )
- PORT MAP (
- clk => clk,
- rst => rst,
- pulse_in => pps_ext_revt,
- pulse_delay => pps_delay,
- pulse_out => pps_ext_revt_dly
- );
- END GENERATE;
-
- no_common_pulse_delay : IF g_pps_delay_max=0 GENERATE
- pps_ext_revt_dly <= pps_ext_revt;
- END GENERATE;
-
u_capture_cnt : ENTITY common_lib.common_interval_monitor
GENERIC MAP (
g_interval_cnt_w => capture_cnt'LENGTH
@@ -192,7 +169,7 @@ BEGIN
clk => clk,
-- ST
in_val => '1',
- in_evt => pps_ext_revt_dly,
+ in_evt => pps_ext_revt,
-- MM
interval_cnt => i_capture_cnt
);
@@ -207,7 +184,7 @@ BEGIN
PORT MAP (
rst => rst,
clk => clk,
- in_dat => pps_ext_revt_dly,
+ in_dat => pps_ext_revt,
out_dat => pps_sys_buf
);
diff --git a/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd b/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
index c0db96526a..51efde2ff7 100644
--- a/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
+++ b/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
@@ -24,7 +24,6 @@
-- . Report PPS toggle, stable and period capture count
-- . Set dp_clk capture edge for PPS
-- Set expected period capture count for PPS stable
--- Set pps_delay between incoming and outgoing PPS, in units of dp_clk cycles (5ns)
--
-- 31 24 23 16 15 8 7 0 wi
-- |-----------------|-----------------|-----------------|-----------------|
@@ -32,9 +31,6 @@
-- |-----------------------------------------------------------------------|
-- |edge[31], xxx expected_cnt = [n:0]| 1
-- |-----------------------------------------------------------------------|
--- | pps_delay = [31:0]| 2
--- |-----------------------------------------------------------------------|
---
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -44,9 +40,8 @@ USE common_lib.common_mem_pkg.ALL;
ENTITY ppsh_reg IS
GENERIC (
g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_st_clk_freq : NATURAL := 200 * 10**6; -- clock frequency of st_clk in Hz
- g_pps_delay_max : NATURAL := 0 -- Maximum number of clk cycles that pps can be delayed
- );
+ g_st_clk_freq : NATURAL := 200 * 10**6 -- clock frequency of st_clk in Hz
+ );
PORT (
-- Clocks and reset
mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
@@ -66,21 +61,18 @@ ENTITY ppsh_reg IS
st_pps_stable_ack : OUT STD_LOGIC;
st_capture_edge : OUT STD_LOGIC;
- st_expected_cnt : OUT STD_LOGIC_VECTOR(ceil_log2(g_st_clk_freq)-1 DOWNTO 0); -- expected number of clk clock cycles between subsequent pps_ext pulses
- st_pps_delay : OUT STD_LOGIC_VECTOR(ceil_log2(g_pps_delay_max)-1 DOWNTO 0)
- );
+ st_expected_cnt : OUT STD_LOGIC_VECTOR(ceil_log2(g_st_clk_freq)-1 DOWNTO 0) -- expected number of clk clock cycles between subsequent pps_ext pulses
+ );
END ppsh_reg;
ARCHITECTURE rtl OF ppsh_reg IS
- CONSTANT c_nof_mm_regs : NATURAL := sel_a_b(g_pps_delay_max>0, 3, 2); -- One register more in case user want to be able to delay PPS.
-
-- Define the actual size of the MM slave register
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_mm_regs),
+ adr_w => ceil_log2(2),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_mm_regs,
+ nof_dat => 2,
init_sl => '0');
-- Register access control signal in mm_clk domain
@@ -93,8 +85,6 @@ ARCHITECTURE rtl OF ppsh_reg IS
SIGNAL mm_capture_cnt : STD_LOGIC_VECTOR(ceil_log2(g_st_clk_freq)-1 DOWNTO 0);
SIGNAL mm_expected_cnt : STD_LOGIC_VECTOR(ceil_log2(g_st_clk_freq)-1 DOWNTO 0);
-
- SIGNAL mm_pps_delay : STD_LOGIC_VECTOR(ceil_log2(g_pps_delay_max)-1 DOWNTO 0);
BEGIN
@@ -116,7 +106,6 @@ BEGIN
mm_pps_stable_ack <= '0';
mm_capture_edge <= '0'; -- default rising edge
mm_expected_cnt <= TO_UVEC(g_st_clk_freq, mm_expected_cnt'LENGTH);
- mm_pps_delay <= (OTHERS=>'0');
ELSIF rising_edge(mm_clk) THEN
-- Read access defaults
@@ -132,9 +121,6 @@ BEGIN
-- Write PPSH control
mm_capture_edge <= sla_in.wrdata(31);
mm_expected_cnt <= sla_in.wrdata(mm_expected_cnt'RANGE);
- WHEN 2 =>
- -- Write pps_delay
- mm_pps_delay <= sla_in.wrdata(ceil_log2(g_pps_delay_max)-1 DOWNTO 0);
WHEN OTHERS => NULL; -- not used MM addresses
END CASE;
@@ -153,9 +139,6 @@ BEGIN
-- Read back PPSH control
sla_out.rddata(31) <= mm_capture_edge;
sla_out.rddata(29 DOWNTO 0) <= RESIZE_UVEC(mm_expected_cnt, 30);
- WHEN 2 =>
- -- Read back pps_delay
- sla_out.rddata(ceil_log2(g_pps_delay_max)-1 DOWNTO 0) <= mm_pps_delay;
WHEN OTHERS => NULL; -- not used MM addresses
END CASE;
END IF;
@@ -188,7 +171,6 @@ BEGIN
st_capture_edge <= mm_capture_edge;
st_expected_cnt <= mm_expected_cnt;
- st_pps_delay <= mm_pps_delay;
END GENERATE; -- no_cross
gen_cross : IF g_cross_clock_domain = TRUE GENERATE
@@ -262,18 +244,6 @@ BEGIN
out_new => OPEN
);
- u_pps_delay : ENTITY common_lib.common_reg_cross_domain
- PORT MAP (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_pps_delay,
- in_done => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_pps_delay,
- out_new => OPEN
- );
-
END GENERATE; -- gen_cross
END rtl;
--
GitLab