diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index 91a10a974b24cf71dae6c5de512b44231c4502a5..c01c9f2312af01f99e5c1c905925bdb90e7e0554 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -455,7 +455,7 @@ BEGIN
mm_rst => mm_rst,
dp_clk => dp_clk,
dp_rst => dp_rst,
- dp_pps => dp_pps,
+-- dp_pps => dp_pps,
-- mm control buses
jesd204b_mosi => jesd204b_mosi,
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 1c4e63b52af0ae3879990b45814a4b6d0bcd8dea..251cc2d600bfd1c9daf662ef653053cfaea5e93b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -47,7 +47,7 @@ ENTITY node_adc_input_and_timing IS
mm_rst : IN STD_LOGIC;
dp_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
- dp_pps : IN STD_LOGIC;
+-- dp_pps : IN STD_LOGIC;
-- mm control buses
-- JESD
@@ -127,14 +127,10 @@ ARCHITECTURE str OF node_adc_input_and_timing IS
-- Frame parameters TBC
CONSTANT c_bs_bsn_w : NATURAL := 64; --51;
CONSTANT c_bs_block_size : NATURAL := 1024;
- CONSTANT c_bs_nof_block_per_sync : NATURAL := 256;
+ CONSTANT c_bs_nof_block_per_sync : NATURAL := 390625; -- generate a sync every 2s for testing
CONSTANT c_dp_shiftram_nof_samples: NATURAL := 4096;
CONSTANT c_data_w : NATURAL := 16;
CONSTANT c_dp_fifo_dc_size : NATURAL := 64;
-
- -- System
- SIGNAL rx_clk : STD_LOGIC;
- SIGNAL rx_pps : STD_LOGIC;
-- QSFP leds
@@ -144,7 +140,9 @@ ARCHITECTURE str OF node_adc_input_and_timing IS
-- JESD signals
SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams_db-1 DOWNTO 0);
SIGNAL jesd204b_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams_jesd204b-1 DOWNTO 0);
- SIGNAL jesd204b_frame_clk : STD_LOGIC;
+ SIGNAL rx_clk : STD_LOGIC; -- formerly jesd204b_frame_clk
+ SIGNAL rx_rst : STD_LOGIC;
+ SIGNAL rx_sysref : STD_LOGIC;
-- Sosis and sosi arrays
SIGNAL bs_sosi : t_dp_sosi;
@@ -184,7 +182,9 @@ BEGIN
jesd204b_sync_n_arr => JESD204B_SYNC,
rx_src_out_arr => jesd204b_rx_src_out_arr,
- jesd204b_frame_clk => jesd204b_frame_clk,
+ rx_clk => rx_clk,
+ rx_rst => rx_rst,
+ rx_sysref => rx_sysref,
-- MM
mm_clk => mm_clk,
@@ -224,8 +224,8 @@ BEGIN
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => jesd204b_frame_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
@@ -233,7 +233,7 @@ BEGIN
reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
in_sosi_arr => diag_data_buf_snk_in_arr,
- in_sync => dp_pps
+ in_sync => rx_sysref
);
-----------------------------------------------------------------------------
@@ -247,12 +247,12 @@ BEGIN
GENERIC MAP (
g_nof_streams => g_nof_streams_jesd204b,
g_nof_words => c_dp_shiftram_nof_samples,
- g_data_w => 16,
+ g_data_w => c_data_w,
g_use_sync_in => TRUE
)
PORT MAP (
- dp_rst => dp_rst,
- dp_clk => jesd204b_frame_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
mm_rst => mm_rst,
mm_clk => mm_clk,
@@ -270,7 +270,7 @@ BEGIN
-----------------------------------------------------------------------------
-- Timestamp
-----------------------------------------------------------------------------
- u_bsn_sosi : ENTITY dp_lib.mms_dp_bsn_source
+ u_bsn_source : ENTITY dp_lib.mms_dp_bsn_source
GENERIC MAP (
g_cross_clock_domain => TRUE,
g_block_size => c_bs_block_size,
@@ -281,9 +281,9 @@ BEGIN
-- Clocks and reset
mm_rst => mm_rst,
mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ dp_pps => rx_sysref,
-- Memory-mapped clock domain
reg_mosi => reg_bsn_source_mosi,
@@ -307,8 +307,8 @@ BEGIN
reg_miso => reg_bsn_scheduler_wg_miso,
-- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
trigger_out => trigger_wg
@@ -349,8 +349,8 @@ BEGIN
buf_miso => ram_wg_miso,
-- Streaming clock domain
- st_rst => dp_rst,
- st_clk => jesd204b_frame_clk,
+ st_rst => rx_rst,
+ st_clk => rx_clk,
st_restart => trigger_wg,
out_sosi_arr => wg_sosi_arr
@@ -373,25 +373,25 @@ BEGIN
-----------------------------------------------------------------------------
gen_mux : FOR I IN 0 TO g_nof_streams_input-1 GENERATE
- p_sosi : PROCESS(ant_sosi_arr, wg_sosi_arr)
+ p_sosi : PROCESS(ant_sosi_arr(I), wg_sosi_arr(I))
BEGIN
-- Valid is forced to '1' here for dp_shiftram.
- nxt_mux_sosi_arr(I).valid <= '1';
+ -- nxt_mux_sosi_arr(I).valid <= '1';
- -- Default use the ADUH data
+ -- Default use the ADC data
nxt_mux_sosi_arr(I).data <= ant_sosi_arr(I).data;
IF wg_sosi_arr(I).valid='1' THEN
- -- Valid WG data overrules ADUH data
- nxt_mux_sosi_arr(I).data <= wg_sosi_arr(I).data;
+ -- Valid WG data overrules ADC data
+ -- nxt_mux_sosi_arr(I).data <= wg_sosi_arr(I).data;
END IF;
END PROCESS;
END GENERATE;
- p_reg_mux : PROCESS(dp_rst, jesd204b_frame_clk)
+ p_reg_mux : PROCESS(rx_rst, rx_clk)
BEGIN
- IF dp_rst='1' THEN
+ IF rx_rst='1' THEN
mux_sosi_arr <= (OTHERS=>c_dp_sosi_rst);
- ELSIF rising_edge(jesd204b_frame_clk) THEN
+ ELSIF rising_edge(rx_clk) THEN
mux_sosi_arr <= nxt_mux_sosi_arr;
END IF;
END PROCESS;
@@ -435,8 +435,8 @@ BEGIN
reg_miso => reg_bsn_monitor_input_miso,
-- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => jesd204b_frame_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
in_siso_arr => (OTHERS=>c_dp_siso_rdy),
in_sosi_arr => rx_sosi_arr
);
@@ -467,8 +467,8 @@ BEGIN
buf_miso => ram_aduh_monitor_miso,
-- Streaming clock domain
- st_rst => dp_rst,
- st_clk => jesd204b_frame_clk,
+ st_rst => rx_rst,
+ st_clk => rx_clk,
in_sosi_arr => rx_sosi_arr
);
@@ -480,7 +480,7 @@ BEGIN
u_diag_data_buffer_bsn : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
- g_technology => g_technology,
+ g_technology => g_technology,
g_nof_streams => g_nof_streams_input,
g_data_w => c_data_w,
g_buf_nof_data => g_buf_nof_data,
@@ -490,8 +490,8 @@ BEGIN
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => jesd204b_frame_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
@@ -499,13 +499,13 @@ BEGIN
reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
in_sosi_arr => rx_sosi_arr,
- in_sync => dp_pps
+ in_sync => rx_sosi_arr(0).sync
);
-----------------------------------------------------------------------------
-- Output Stage
- -- . Thin dual clock fifo to cross from jesd frame clock to dp_clk domain
+ -- . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain
-----------------------------------------------------------------------------
gen_fifo_dc : FOR I IN 0 TO g_nof_streams_input-1 GENERATE
@@ -519,8 +519,8 @@ BEGIN
g_fifo_size => c_dp_fifo_dc_size
)
PORT MAP (
- wr_rst => dp_rst,
- wr_clk => jesd204b_frame_clk,
+ wr_rst => rx_rst,
+ wr_clk => rx_clk,
rd_rst => dp_rst,
rd_clk => dp_clk,
snk_in => rx_sosi_arr(I),