diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
index b4a3e724ac15b1dbb00e8375c1ae0e431b58153f..f60e4dcda8561d97a4b9e8665570d81614227164 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
@@ -263,7 +263,9 @@ BEGIN
 
       rom_system_info_reset_export              => OPEN,
       rom_system_info_clk_export                => OPEN,
-      rom_system_info_address_export            => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), 
+--    ToDo: This has changed in the peripherals package
+      rom_system_info_address_export            => rom_unb_system_info_mosi.address(9 DOWNTO 0), 
+--      rom_system_info_address_export            => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), 
       rom_system_info_write_export              => rom_unb_system_info_mosi.wr,
       rom_system_info_writedata_export          => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
       rom_system_info_read_export               => rom_unb_system_info_mosi.rd,
@@ -279,7 +281,9 @@ BEGIN
 
       pio_pps_reset_export                      => OPEN,
       pio_pps_clk_export                        => OPEN,
-      pio_pps_address_export                    => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+--    ToDo: This has changed in the peripherals package
+      pio_pps_address_export                    => reg_ppsh_mosi.address(0 DOWNTO 0),
+--      pio_pps_address_export                    => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
       pio_pps_write_export                      => reg_ppsh_mosi.wr,
       pio_pps_writedata_export                  => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
       pio_pps_read_export                       => reg_ppsh_mosi.rd,
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 507992a5f4c29227bd311adadf09341f11a30089..392b5eac21f078d7f3bbb56f04619092bbfe325a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -41,7 +41,7 @@ USE work.lofar2_unb2b_adc_pkg.ALL;
 ENTITY node_adc_input_and_timing IS
   GENERIC (
     g_technology              : NATURAL := c_tech_arria10_e1sg;
-    g_buf_nof_data            : NATURAL := 1024;
+    g_buf_nof_data            : NATURAL := 8192; --1024;
     g_nof_streams             : NATURAL := 12;
     g_nof_sync_n              : NATURAL := 4;          -- Three ADCs per RCU share a sync
     g_aduh_buffer_nof_symbols : NATURAL := 512;        -- Default 512
diff --git a/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl b/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
index 3457a43125a2fa5d4eb94bef928926053ce98843..9a2dfc13d41dd14086db47ade5e37bb5d0a67b96 100644
--- a/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
+++ b/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
@@ -5,18 +5,18 @@
 # Pins needed for the 12 channel JESD204B interface to the ADCs
 set_instance_assignment -name IO_STANDARD LVDS -to JESD204B_SYSREF
 set_instance_assignment -name IO_STANDARD LVDS -to "JESD204B_SYSREF(n)"
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[2]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[3]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[4]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[5]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[6]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[7]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[8]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[9]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[10]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[11]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[8]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[9]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[10]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[11]
 
 
 # The following is copied from unb2c_10GbE_pins.tcl. 
@@ -2525,8 +2525,8 @@ set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
 set_location_assignment PIN_V12 -to JESD204B_SYSREF
 set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYSREF
 
-set_location_assignment PIN_U12 -to JESD204B_SYNC[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[0]
-set_location_assignment PIN_U14 -to JESD204B_SYNC[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[1]
+set_location_assignment PIN_U12 -to JESD204B_SYNC_N[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[0]
+set_location_assignment PIN_U14 -to JESD204B_SYNC_N[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[1]
 
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
index 9379f069547ae248551f8363d8f4589b5d7e59dd..d8505d23aad7a079426b46e4df19ce35b489d4e1 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
@@ -100,9 +100,6 @@ ENTITY unb2c_test_10GbE IS
     QSFP_5_RX    : IN    STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
     QSFP_5_TX    : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
 
-    QSFP_SDA     : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.i2c_w-1 downto 0);
-    QSFP_SCL     : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.i2c_w-1 downto 0);
-
     QSFP_LED     : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
   );
 END unb2c_test_10GbE;
@@ -181,9 +178,6 @@ BEGIN
     QSFP_5_RX    => QSFP_5_RX,
     QSFP_5_TX    => QSFP_5_TX,
 
-    QSFP_SDA     => QSFP_SDA,
-    QSFP_SCL     => QSFP_SCL,
-
     QSFP_LED     => QSFP_LED
   );
 END str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_all/unb2c_test_all.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_all/unb2c_test_all.vhd
index da908ab84b5a4949182c94267e70a2dcf1797905..a8f9329b66584bb6c36f97a98f187f75488677f5 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_all/unb2c_test_all.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_all/unb2c_test_all.vhd
@@ -105,9 +105,6 @@ ENTITY unb2c_test_all IS
     QSFP_5_RX    : IN    STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
     QSFP_5_TX    : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
 
-    QSFP_SDA     : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.i2c_w-1 downto 0);
-    QSFP_SCL     : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.i2c_w-1 downto 0);
-
     -- SO-DIMM Memory Bank I
     MB_I_IN      : IN    t_tech_ddr4_phy_in;
     MB_I_IO      : INOUT t_tech_ddr4_phy_io;
@@ -204,10 +201,7 @@ BEGIN
     QSFP_5_RX    => QSFP_5_RX,
     QSFP_5_TX    => QSFP_5_TX,
 
-    QSFP_SDA     => QSFP_SDA,
-    QSFP_SCL     => QSFP_SCL,
-
-    -- SO-DIMM Memory Bank I
+     -- SO-DIMM Memory Bank I
     MB_I_IN      => MB_I_IN,
     MB_I_IO      => MB_I_IO,
     MB_I_OU      => MB_I_OU,
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
index 295aa845c5fb19f292f588b1e225ef3655491e6b..3661ee491d9c38c158ce8eef85a346a992e998d4 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
@@ -101,9 +101,6 @@ ENTITY unb2c_test_minimal IS
     QSFP_5_RX    : IN    STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
     QSFP_5_TX    : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
 
-    QSFP_SDA     : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.i2c_w-1 downto 0);
-    QSFP_SCL     : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.i2c_w-1 downto 0);
-
     -- SO-DIMM Memory Bank I
     MB_I_IN      : IN    t_tech_ddr4_phy_in;
     MB_I_IO      : INOUT t_tech_ddr4_phy_io;
@@ -195,9 +192,6 @@ BEGIN
     QSFP_5_RX    => QSFP_5_RX,
     QSFP_5_TX    => QSFP_5_TX,
 
-    QSFP_SDA     => QSFP_SDA,
-    QSFP_SCL     => QSFP_SCL,
-
     -- SO-DIMM Memory Bank I
     MB_I_IN      => MB_I_IN,
     MB_I_IO      => MB_I_IO,
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/hdllib.cfg
index 4191fa35301df194f9fcd9c88d027dc605875df8..902dd1354373b54fd57a1a4dc4b3d01a3bb1dc56 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/hdllib.cfg
@@ -43,7 +43,8 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+#    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA.qsf
 
 quartus_sdc_pre_files =
     quartus/unb2c_test_pinning.sdc
@@ -52,7 +53,7 @@ quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
-    quartus/unb2c_test_pinning_pins.tcl
+#    quartus/unb2c_test_pinning_pins.tcl
 
 quartus_vhdl_files = 
 
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA.qsf b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA.qsf
new file mode 100644
index 0000000000000000000000000000000000000000..905d4998f3eebd104b29da9f2f7afe6ea5efaf79
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA.qsf
@@ -0,0 +1,1522 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1a10.0 Build 346 11/13/2013 SJ Full Version
+# Date created = 08:55:45  March 13, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		unb2_pinning_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.8 V"
+set_global_assignment -name FAMILY "arria 10"
+#set_global_assignment -name DEVICE 10AX115U4F45I3SGES
+set_global_assignment -name DEVICE 10AX115U3F45E2SG
+set_global_assignment -name TOP_LEVEL_ENTITY unb2c_test_pinning
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:55:45  MARCH 13, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+#set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
+#set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+#set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+#set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+#set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
+
+# IO Location Assignments from Gijs
+#
+#from chip planner
+#
+# 
+#from chip planner
+#
+
+# rx pins modified from chip planner
+# tx pins as per Gijs
+
+
+set_location_assignment PIN_K15 -to CLK
+set_location_assignment PIN_J15 -to "CLK(n)"
+set_location_assignment PIN_N12 -to ETH_CLK
+set_location_assignment PIN_K14 -to PPS
+set_location_assignment PIN_J14 -to "PPS(n)"
+set_location_assignment PIN_Y36 -to SA_CLK
+set_location_assignment PIN_Y35 -to "SA_CLK(n)"
+set_location_assignment PIN_AH9 -to SB_CLK
+set_location_assignment PIN_AH10 -to "SB_CLK(n)"
+set_location_assignment PIN_AP20 -to MB_I_OU.a[0]
+set_location_assignment PIN_AR20 -to MB_I_OU.a[1]
+set_location_assignment PIN_AP19 -to MB_I_OU.a[2]
+set_location_assignment PIN_AR19 -to MB_I_OU.a[3]
+set_location_assignment PIN_AR18 -to MB_I_OU.a[4]
+set_location_assignment PIN_AT17 -to MB_I_OU.a[5]
+set_location_assignment PIN_AU19 -to MB_I_OU.a[6]
+set_location_assignment PIN_AT18 -to MB_I_OU.a[7]
+set_location_assignment PIN_AL17 -to MB_I_OU.a[8]
+set_location_assignment PIN_AM18 -to MB_I_OU.a[9]
+set_location_assignment PIN_AM19 -to MB_I_OU.a[10]
+set_location_assignment PIN_AN19 -to MB_I_OU.a[11]
+set_location_assignment PIN_BA17 -to MB_I_OU.a[12]
+set_location_assignment PIN_BD17 -to MB_I_OU.a[13]
+set_location_assignment PIN_AY18 -to MB_I_OU.act_n
+set_location_assignment PIN_AV29 -to MB_I_IN.alert_n
+set_location_assignment PIN_BB16 -to MB_I_OU.ba[0]
+set_location_assignment PIN_BD16 -to MB_I_OU.ba[1]
+set_location_assignment PIN_BC16 -to MB_I_OU.bg[0]
+set_location_assignment PIN_AW19 -to MB_I_OU.bg[1]
+set_location_assignment PIN_BA15 -to MB_I_OU.a[15]
+set_location_assignment PIN_BC21 -to MB_I_IO.dq[64]
+set_location_assignment PIN_BA22 -to MB_I_IO.dq[65]
+set_location_assignment PIN_BD21 -to MB_I_IO.dq[66]
+set_location_assignment PIN_BB20 -to MB_I_IO.dq[67]
+set_location_assignment PIN_BA20 -to MB_I_IO.dq[68]
+set_location_assignment PIN_BD20 -to MB_I_IO.dq[69]
+set_location_assignment PIN_AY20 -to MB_I_IO.dq[70]
+set_location_assignment PIN_AY22 -to MB_I_IO.dq[71]
+set_location_assignment PIN_AU18 -to MB_I_OU.ck[0]
+set_location_assignment PIN_AT16 -to MB_I_OU.ck[1]
+set_location_assignment PIN_BB19 -to MB_I_OU.cke[0]
+set_location_assignment PIN_AP16 -to MB_I_OU.cke[1]
+set_location_assignment PIN_AY19 -to MB_I_OU.cs_n[0]
+set_location_assignment PIN_AN16 -to MB_I_OU.cs_n[1]
+set_location_assignment PIN_BC29 -to MB_I_IO.dbi_n[0]
+set_location_assignment PIN_AR27 -to MB_I_IO.dbi_n[1]
+set_location_assignment PIN_BD24 -to MB_I_IO.dbi_n[2]
+set_location_assignment PIN_AM23 -to MB_I_IO.dbi_n[3]
+set_location_assignment PIN_AU12 -to MB_I_IO.dbi_n[4]
+set_location_assignment PIN_AU13 -to MB_I_IO.dbi_n[5]
+set_location_assignment PIN_AM14 -to MB_I_IO.dbi_n[6]
+set_location_assignment PIN_AM16 -to MB_I_IO.dbi_n[7]
+set_location_assignment PIN_BA21 -to MB_I_IO.dbi_n[8]
+set_location_assignment PIN_BA28 -to MB_I_IO.dqs[0]
+set_location_assignment PIN_AM28 -to MB_I_IO.dqs[1]
+set_location_assignment PIN_AV24 -to MB_I_IO.dqs[2]
+set_location_assignment PIN_AN24 -to MB_I_IO.dqs[3]
+set_location_assignment PIN_BC14 -to MB_I_IO.dqs[4]
+set_location_assignment PIN_AW14 -to MB_I_IO.dqs[5]
+set_location_assignment PIN_AN12 -to MB_I_IO.dqs[6]
+set_location_assignment PIN_AK15 -to MB_I_IO.dqs[7]
+set_location_assignment PIN_BC22 -to MB_I_IO.dqs[8]
+set_location_assignment PIN_BD19 -to MB_I_OU.odt[0]
+set_location_assignment PIN_AR17 -to MB_I_OU.odt[1]
+set_location_assignment PIN_BC18 -to MB_I_OU.par
+set_location_assignment PIN_BB15 -to MB_I_OU.a[16]
+set_location_assignment PIN_AW17 -to MB_I_REF_CLK
+set_location_assignment PIN_AV19 -to MB_I_OU.reset_n
+set_location_assignment PIN_AY17 -to MB_I_IN.oct_rzqin
+set_location_assignment PIN_BC17 -to MB_I_OU.a[14]
+set_location_assignment PIN_A29 -to MB_II_OU.a[0]
+set_location_assignment PIN_B29 -to MB_II_OU.a[1]
+set_location_assignment PIN_H29 -to MB_II_OU.a[2]
+set_location_assignment PIN_G29 -to MB_II_OU.a[3]
+set_location_assignment PIN_D29 -to MB_II_OU.a[4]
+set_location_assignment PIN_E29 -to MB_II_OU.a[5]
+set_location_assignment PIN_C29 -to MB_II_OU.a[6]
+set_location_assignment PIN_C28 -to MB_II_OU.a[7]
+set_location_assignment PIN_E30 -to MB_II_OU.a[8]
+set_location_assignment PIN_D30 -to MB_II_OU.a[9]
+set_location_assignment PIN_B28 -to MB_II_OU.a[10]
+set_location_assignment PIN_A28 -to MB_II_OU.a[11]
+set_location_assignment PIN_H27 -to MB_II_OU.a[12]
+set_location_assignment PIN_E28 -to MB_II_OU.a[13]
+set_location_assignment PIN_K28 -to MB_II_OU.act_n
+set_location_assignment PIN_C16 -to MB_II_IN.alert_n
+set_location_assignment PIN_C27 -to MB_II_OU.ba[0]
+set_location_assignment PIN_A27 -to MB_II_OU.ba[1]
+set_location_assignment PIN_B26 -to MB_II_OU.bg[0]
+set_location_assignment PIN_L27 -to MB_II_OU.bg[1]
+set_location_assignment PIN_F28 -to MB_II_OU.a[15]
+set_location_assignment PIN_E24 -to MB_II_IO.dq[64]
+set_location_assignment PIN_J25 -to MB_II_IO.dq[65]
+set_location_assignment PIN_A25 -to MB_II_IO.dq[66]
+set_location_assignment PIN_G25 -to MB_II_IO.dq[67]
+set_location_assignment PIN_D25 -to MB_II_IO.dq[68]
+set_location_assignment PIN_K25 -to MB_II_IO.dq[69]
+set_location_assignment PIN_D24 -to MB_II_IO.dq[70]
+set_location_assignment PIN_F25 -to MB_II_IO.dq[71]
+set_location_assignment PIN_N27 -to MB_II_OU.ck[0]
+set_location_assignment PIN_K27 -to MB_II_OU.ck[1]
+set_location_assignment PIN_N28 -to MB_II_OU.cke[0]
+set_location_assignment PIN_P26 -to MB_II_OU.cke[1]
+set_location_assignment PIN_K29 -to MB_II_OU.cs_n[0]
+set_location_assignment PIN_H26 -to MB_II_OU.cs_n[1]
+set_location_assignment PIN_A16 -to MB_II_IO.dbi_n[0]
+set_location_assignment PIN_M21 -to MB_II_IO.dbi_n[1]
+set_location_assignment PIN_K22 -to MB_II_IO.dbi_n[2]
+set_location_assignment PIN_D19 -to MB_II_IO.dbi_n[3]
+set_location_assignment PIN_G30 -to MB_II_IO.dbi_n[4]
+set_location_assignment PIN_R32 -to MB_II_IO.dbi_n[5]
+set_location_assignment PIN_G32 -to MB_II_IO.dbi_n[6]
+set_location_assignment PIN_AC32 -to MB_II_IO.dbi_n[7]
+set_location_assignment PIN_E25 -to MB_II_IO.dbi_n[8]
+set_location_assignment PIN_F17 -to MB_II_IO.dqs[0]
+set_location_assignment PIN_L20 -to MB_II_IO.dqs[1]
+set_location_assignment PIN_J22 -to MB_II_IO.dqs[2]
+set_location_assignment PIN_B19 -to MB_II_IO.dqs[3]
+set_location_assignment PIN_L31 -to MB_II_IO.dqs[4]
+set_location_assignment PIN_P31 -to MB_II_IO.dqs[5]
+set_location_assignment PIN_N33 -to MB_II_IO.dqs[6]
+set_location_assignment PIN_T33 -to MB_II_IO.dqs[7]
+set_location_assignment PIN_A26 -to MB_II_IO.dqs[8]
+set_location_assignment PIN_K30 -to MB_II_OU.odt[0]
+set_location_assignment PIN_R27 -to MB_II_OU.odt[1]
+set_location_assignment PIN_R28 -to MB_II_OU.par
+set_location_assignment PIN_G28 -to MB_II_OU.a[16]
+set_location_assignment PIN_J29 -to MB_II_REF_CLK
+set_location_assignment PIN_L28 -to MB_II_OU.reset_n
+set_location_assignment PIN_J27 -to MB_II_IN.oct_rzqin
+set_location_assignment PIN_F27 -to MB_II_OU.a[14]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[0]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[1]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[1](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGOUT[0]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGOUT[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGOUT[1]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGOUT[1](n)"
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to INTA
+set_instance_assignment -name IO_STANDARD "1.8 V" -to INTB
+set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SC
+set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SD
+set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_ALERT
+set_instance_assignment -name IO_STANDARD LVDS -to SA_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "SA_CLK(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to SB_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "SB_CLK(n)"
+set_instance_assignment -name IO_STANDARD "1.8 V" -to SENS_SC
+set_instance_assignment -name IO_STANDARD "1.8 V" -to SENS_SD
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to VERSION[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to VERSION[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to WDI
+set_location_assignment PIN_P16 -to ID[0]
+set_location_assignment PIN_P15 -to ID[1]
+set_location_assignment PIN_K13 -to ID[2]
+set_location_assignment PIN_L13 -to ID[3]
+set_location_assignment PIN_N16 -to ID[4]
+set_location_assignment PIN_N14 -to ID[5]
+set_location_assignment PIN_U13 -to ID[6]
+set_location_assignment PIN_T13 -to ID[7]
+set_location_assignment PIN_AU31 -to INTA
+set_location_assignment PIN_AR30 -to INTB
+set_location_assignment PIN_BA25 -to PMBUS_SC
+set_location_assignment PIN_BD25 -to PMBUS_SD
+set_location_assignment PIN_BD26 -to PMBUS_ALERT
+set_location_assignment PIN_BC31 -to SENS_SC
+set_location_assignment PIN_BB31 -to SENS_SD
+set_location_assignment PIN_AN32 -to TESTIO[0]
+set_location_assignment PIN_AP32 -to TESTIO[1]
+set_location_assignment PIN_AT30 -to TESTIO[2]
+set_location_assignment PIN_BD31 -to TESTIO[3]
+set_location_assignment PIN_AU30 -to TESTIO[4]
+set_location_assignment PIN_BD30 -to TESTIO[5]
+set_location_assignment PIN_AB12 -to VERSION[0]
+set_location_assignment PIN_AB13 -to VERSION[1]
+set_location_assignment PIN_BB30 -to WDI
+set_location_assignment PIN_AT31 -to QSFP_RST
+set_location_assignment PIN_K12 -to ETH_SGIN[0]
+set_location_assignment PIN_J12 -to "ETH_SGIN[0](n)"
+set_location_assignment PIN_M16 -to ETH_SGIN[1]
+set_location_assignment PIN_L16 -to "ETH_SGIN[1](n)"
+set_location_assignment PIN_H13 -to ETH_SGOUT[0]
+set_location_assignment PIN_H12 -to "ETH_SGOUT[0](n)"
+set_location_assignment PIN_L15 -to ETH_SGOUT[1]
+set_location_assignment PIN_M15 -to "ETH_SGOUT[1](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to PPS
+set_instance_assignment -name IO_STANDARD LVDS -to "PPS(n)"
+set_location_assignment PIN_B9 -to BCK_RX[0]
+set_location_assignment PIN_B10 -to "BCK_RX[0](n)"
+set_location_assignment PIN_D9 -to BCK_RX[1]
+set_location_assignment PIN_D10 -to "BCK_RX[1](n)"
+set_location_assignment PIN_C11 -to BCK_RX[2]
+set_location_assignment PIN_C12 -to "BCK_RX[2](n)"
+set_location_assignment PIN_F9 -to BCK_RX[3]
+set_location_assignment PIN_F10 -to "BCK_RX[3](n)"
+set_location_assignment PIN_C7 -to BCK_RX[4]
+set_location_assignment PIN_C8 -to "BCK_RX[4](n)"
+set_location_assignment PIN_E11 -to BCK_RX[5]
+set_location_assignment PIN_E12 -to "BCK_RX[5](n)"
+set_location_assignment PIN_E7 -to BCK_RX[6]
+set_location_assignment PIN_E8 -to "BCK_RX[6](n)"
+set_location_assignment PIN_D5 -to BCK_RX[7]
+set_location_assignment PIN_D6 -to "BCK_RX[7](n)"
+set_location_assignment PIN_G7 -to BCK_RX[8]
+set_location_assignment PIN_G8 -to "BCK_RX[8](n)"
+set_location_assignment PIN_F5 -to BCK_RX[9]
+set_location_assignment PIN_F6 -to "BCK_RX[9](n)"
+set_location_assignment PIN_J7 -to BCK_RX[10]
+set_location_assignment PIN_J8 -to "BCK_RX[10](n)"
+set_location_assignment PIN_H5 -to BCK_RX[11]
+set_location_assignment PIN_H6 -to "BCK_RX[11](n)"
+set_location_assignment PIN_L7 -to BCK_RX[12]
+set_location_assignment PIN_L8 -to "BCK_RX[12](n)"
+set_location_assignment PIN_K5 -to BCK_RX[13]
+set_location_assignment PIN_K6 -to "BCK_RX[13](n)"
+set_location_assignment PIN_N7 -to BCK_RX[14]
+set_location_assignment PIN_N8 -to "BCK_RX[14](n)"
+set_location_assignment PIN_M5 -to BCK_RX[15]
+set_location_assignment PIN_M6 -to "BCK_RX[15](n)"
+set_location_assignment PIN_R7 -to BCK_RX[16]
+set_location_assignment PIN_R8 -to "BCK_RX[16](n)"
+set_location_assignment PIN_P5 -to BCK_RX[17]
+set_location_assignment PIN_P6 -to "BCK_RX[17](n)"
+set_location_assignment PIN_U7 -to BCK_RX[18]
+set_location_assignment PIN_U8 -to "BCK_RX[18](n)"
+set_location_assignment PIN_T5 -to BCK_RX[19]
+set_location_assignment PIN_T6 -to "BCK_RX[19](n)"
+set_location_assignment PIN_W7 -to BCK_RX[20]
+set_location_assignment PIN_W8 -to "BCK_RX[20](n)"
+set_location_assignment PIN_V5 -to BCK_RX[21]
+set_location_assignment PIN_V6 -to "BCK_RX[21](n)"
+set_location_assignment PIN_AA7 -to BCK_RX[22]
+set_location_assignment PIN_AA8 -to "BCK_RX[22](n)"
+set_location_assignment PIN_Y5 -to BCK_RX[23]
+set_location_assignment PIN_Y6 -to "BCK_RX[23](n)"
+set_location_assignment PIN_AC7 -to BCK_RX[24]
+set_location_assignment PIN_AC8 -to "BCK_RX[24](n)"
+set_location_assignment PIN_AB5 -to BCK_RX[25]
+set_location_assignment PIN_AB6 -to "BCK_RX[25](n)"
+set_location_assignment PIN_AE7 -to BCK_RX[26]
+set_location_assignment PIN_AE8 -to "BCK_RX[26](n)"
+set_location_assignment PIN_AD5 -to BCK_RX[27]
+set_location_assignment PIN_AD6 -to "BCK_RX[27](n)"
+set_location_assignment PIN_AG7 -to BCK_RX[28]
+set_location_assignment PIN_AG8 -to "BCK_RX[28](n)"
+set_location_assignment PIN_AF5 -to BCK_RX[29]
+set_location_assignment PIN_AF6 -to "BCK_RX[29](n)"
+set_location_assignment PIN_AJ7 -to BCK_RX[30]
+set_location_assignment PIN_AJ8 -to "BCK_RX[30](n)"
+set_location_assignment PIN_AH5 -to BCK_RX[31]
+set_location_assignment PIN_AH6 -to "BCK_RX[31](n)"
+set_location_assignment PIN_AL7 -to BCK_RX[32]
+set_location_assignment PIN_AL8 -to "BCK_RX[32](n)"
+set_location_assignment PIN_AK5 -to BCK_RX[33]
+set_location_assignment PIN_AK6 -to "BCK_RX[33](n)"
+set_location_assignment PIN_AN7 -to BCK_RX[34]
+set_location_assignment PIN_AN8 -to "BCK_RX[34](n)"
+set_location_assignment PIN_AM5 -to BCK_RX[35]
+set_location_assignment PIN_AM6 -to "BCK_RX[35](n)"
+set_location_assignment PIN_AR7 -to BCK_RX[36]
+set_location_assignment PIN_AR8 -to "BCK_RX[36](n)"
+set_location_assignment PIN_AP5 -to BCK_RX[37]
+set_location_assignment PIN_AP6 -to "BCK_RX[37](n)"
+set_location_assignment PIN_AU7 -to BCK_RX[38]
+set_location_assignment PIN_AU8 -to "BCK_RX[38](n)"
+set_location_assignment PIN_AT5 -to BCK_RX[39]
+set_location_assignment PIN_AT6 -to "BCK_RX[39](n)"
+set_location_assignment PIN_AW7 -to BCK_RX[40]
+set_location_assignment PIN_AW8 -to "BCK_RX[40](n)"
+set_location_assignment PIN_AV5 -to BCK_RX[41]
+set_location_assignment PIN_AV6 -to "BCK_RX[41](n)"
+set_location_assignment PIN_BA7 -to BCK_RX[42]
+set_location_assignment PIN_BA8 -to "BCK_RX[42](n)"
+set_location_assignment PIN_AY5 -to BCK_RX[43]
+set_location_assignment PIN_AY6 -to "BCK_RX[43](n)"
+set_location_assignment PIN_BC7 -to BCK_RX[44]
+set_location_assignment PIN_BC8 -to "BCK_RX[44](n)"
+set_location_assignment PIN_BB5 -to BCK_RX[45]
+set_location_assignment PIN_BB6 -to "BCK_RX[45](n)"
+set_location_assignment PIN_AY9 -to BCK_RX[46]
+set_location_assignment PIN_AY10 -to "BCK_RX[46](n)"
+set_location_assignment PIN_BB9 -to BCK_RX[47]
+set_location_assignment PIN_BB10 -to "BCK_RX[47](n)"
+set_location_assignment PIN_B5 -to BCK_TX[0]
+set_location_assignment PIN_A3 -to BCK_TX[1]
+set_location_assignment PIN_A11 -to BCK_TX[2]
+set_location_assignment PIN_B1 -to BCK_TX[3]
+set_location_assignment PIN_C3 -to BCK_TX[4]
+set_location_assignment PIN_A7 -to BCK_TX[5]
+set_location_assignment PIN_D1 -to BCK_TX[6]
+set_location_assignment PIN_E3 -to BCK_TX[7]
+set_location_assignment PIN_F1 -to BCK_TX[8]
+set_location_assignment PIN_G3 -to BCK_TX[9]
+set_location_assignment PIN_J3 -to BCK_TX[10]
+set_location_assignment PIN_H1 -to BCK_TX[11]
+set_location_assignment PIN_L3 -to BCK_TX[12]
+set_location_assignment PIN_K1 -to BCK_TX[13]
+set_location_assignment PIN_N3 -to BCK_TX[14]
+set_location_assignment PIN_M1 -to BCK_TX[15]
+set_location_assignment PIN_R3 -to BCK_TX[16]
+set_location_assignment PIN_P1 -to BCK_TX[17]
+set_location_assignment PIN_U3 -to BCK_TX[18]
+set_location_assignment PIN_T1 -to BCK_TX[19]
+set_location_assignment PIN_W3 -to BCK_TX[20]
+set_location_assignment PIN_V1 -to BCK_TX[21]
+set_location_assignment PIN_AA3 -to BCK_TX[22]
+set_location_assignment PIN_Y1 -to BCK_TX[23]
+set_location_assignment PIN_AC3 -to BCK_TX[24]
+set_location_assignment PIN_AB1 -to BCK_TX[25]
+set_location_assignment PIN_AE3 -to BCK_TX[26]
+set_location_assignment PIN_AD1 -to BCK_TX[27]
+set_location_assignment PIN_AG3 -to BCK_TX[28]
+set_location_assignment PIN_AF1 -to BCK_TX[29]
+set_location_assignment PIN_AJ3 -to BCK_TX[30]
+set_location_assignment PIN_AH1 -to BCK_TX[31]
+set_location_assignment PIN_AL3 -to BCK_TX[32]
+set_location_assignment PIN_AK1 -to BCK_TX[33]
+set_location_assignment PIN_AN3 -to BCK_TX[34]
+set_location_assignment PIN_AM1 -to BCK_TX[35]
+set_location_assignment PIN_AR3 -to BCK_TX[36]
+set_location_assignment PIN_AP1 -to BCK_TX[37]
+set_location_assignment PIN_AU3 -to BCK_TX[38]
+set_location_assignment PIN_AT1 -to BCK_TX[39]
+set_location_assignment PIN_AW3 -to BCK_TX[40]
+set_location_assignment PIN_AV1 -to BCK_TX[41]
+set_location_assignment PIN_BB1 -to BCK_TX[42]
+set_location_assignment PIN_AY1 -to BCK_TX[43]
+set_location_assignment PIN_BD5 -to BCK_TX[44]
+set_location_assignment PIN_BA3 -to BCK_TX[45]
+set_location_assignment PIN_BC3 -to BCK_TX[46]
+set_location_assignment PIN_BD9 -to BCK_TX[47]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[4]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[4](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[5]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[5](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[6]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[6](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[7]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[7](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[8]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[8](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[9]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[9](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[10]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[10](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[11]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[11](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[12]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[12](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[13]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[13](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[14]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[14](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[15]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[15](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[16]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[16](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[17]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[17](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[18]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[18](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[19]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[19](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[20]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[20](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[21]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[21](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[22]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[22](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[23]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[23](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[24]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[24](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[25]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[25](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[26]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[26](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[27]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[27](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[28]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[28](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[29]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[29](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[30]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[30](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[31]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[31](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[32]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[32](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[33]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[33](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[34]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[34](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[35]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[35](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[36]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[36](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[37]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[37](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[38]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[38](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[39]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[39](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[40]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[40](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[41]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[41](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[42]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[42](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[43]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[43](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[44]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[44](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[45]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[45](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[46]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[46](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[47]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[47](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[4]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[4](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[5]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[5](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[6]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[6](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[7]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[7](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[8]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[8](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[9]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[9](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[10]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[10](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[11]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[11](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[12]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[12](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[13]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[13](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[14]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[14](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[15]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[15](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[16]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[16](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[17]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[17](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[18]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[18](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[19]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[19](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[20]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[20](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[21]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[21](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[22]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[22](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[23]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[23](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[24]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[24](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[25]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[25](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[26]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[26](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[27]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[27](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[28]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[28](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[29]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[29](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[30]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[30](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[31]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[31](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[32]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[32](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[33]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[33](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[34]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[34](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[35]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[35](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[36]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[36](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[37]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[37](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[38]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[38](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[39]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[39](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[40]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[40](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[41]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[41](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[42]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[42](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[43]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[43](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[44]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[44](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[45]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[45](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[46]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[46](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[47]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[47](n)"
+set_location_assignment PIN_V9 -to BCK_REF_CLK
+set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
+set_location_assignment PIN_AL32 -to CLKUSR
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[2]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[3]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[4]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[5]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[6]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[7]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[8]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[9]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[10]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[11]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[12]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[13]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.act_n
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.ba[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.ba[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.bg[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.bg[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[15]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_I_OU.ck[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_I_OU.ck[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.cke[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.cke[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.cs_n[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.cs_n[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.odt[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.odt[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.par
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[16]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[14]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_OU.reset_n
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[2]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[3]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[4]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[5]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[6]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[7]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[8]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[9]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[10]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[11]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[12]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[13]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.act_n
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.ba[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.ba[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.bg[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.bg[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[15]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_II_OU.ck[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_II_OU.ck[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.cke[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.cke[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.cs_n[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.cs_n[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.odt[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.odt[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.par
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[16]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[14]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_II_OU.reset_n
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[64]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[65]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[66]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[67]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[68]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[69]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[70]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[71]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[8]
+set_location_assignment PIN_AU29 -to MB_I_IO.dq[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[0]
+set_location_assignment PIN_BC28 -to MB_I_IO.dq[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[1]
+set_location_assignment PIN_AY29 -to MB_I_IO.dq[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[2]
+set_location_assignment PIN_BB28 -to MB_I_IO.dq[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[3]
+set_location_assignment PIN_BB29 -to MB_I_IO.dq[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[4]
+set_location_assignment PIN_AW29 -to MB_I_IO.dq[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[5]
+set_location_assignment PIN_BC27 -to MB_I_IO.dq[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[6]
+set_location_assignment PIN_BD29 -to MB_I_IO.dq[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[7]
+set_location_assignment PIN_AR28 -to MB_I_IO.dq[8]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[8]
+set_location_assignment PIN_AR29 -to MB_I_IO.dq[9]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[9]
+set_location_assignment PIN_AV27 -to MB_I_IO.dq[10]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[10]
+set_location_assignment PIN_AU28 -to MB_I_IO.dq[11]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[11]
+set_location_assignment PIN_AW27 -to MB_I_IO.dq[12]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[12]
+set_location_assignment PIN_AT28 -to MB_I_IO.dq[13]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[13]
+set_location_assignment PIN_AV28 -to MB_I_IO.dq[14]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[14]
+set_location_assignment PIN_AP27 -to MB_I_IO.dq[15]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[15]
+set_location_assignment PIN_BC24 -to MB_I_IO.dq[16]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[16]
+set_location_assignment PIN_BB24 -to MB_I_IO.dq[17]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[17]
+set_location_assignment PIN_BB23 -to MB_I_IO.dq[18]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[18]
+set_location_assignment PIN_AW22 -to MB_I_IO.dq[19]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[19]
+set_location_assignment PIN_BA23 -to MB_I_IO.dq[20]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[20]
+set_location_assignment PIN_BC23 -to MB_I_IO.dq[21]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[21]
+set_location_assignment PIN_AY23 -to MB_I_IO.dq[22]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[22]
+set_location_assignment PIN_AY24 -to MB_I_IO.dq[23]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[23]
+set_location_assignment PIN_AP22 -to MB_I_IO.dq[24]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[24]
+set_location_assignment PIN_AN23 -to MB_I_IO.dq[25]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[25]
+set_location_assignment PIN_AR23 -to MB_I_IO.dq[26]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[26]
+set_location_assignment PIN_AT23 -to MB_I_IO.dq[27]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[27]
+set_location_assignment PIN_AU23 -to MB_I_IO.dq[28]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[28]
+set_location_assignment PIN_AV23 -to MB_I_IO.dq[29]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[29]
+set_location_assignment PIN_AR24 -to MB_I_IO.dq[30]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[30]
+set_location_assignment PIN_AP24 -to MB_I_IO.dq[31]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[31]
+set_location_assignment PIN_AV12 -to MB_I_IO.dq[32]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[32]
+set_location_assignment PIN_AY13 -to MB_I_IO.dq[33]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[33]
+set_location_assignment PIN_BD14 -to MB_I_IO.dq[34]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[34]
+set_location_assignment PIN_AY12 -to MB_I_IO.dq[35]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[35]
+set_location_assignment PIN_BA13 -to MB_I_IO.dq[36]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[36]
+set_location_assignment PIN_BA12 -to MB_I_IO.dq[37]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[37]
+set_location_assignment PIN_AW12 -to MB_I_IO.dq[38]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[38]
+set_location_assignment PIN_BB13 -to MB_I_IO.dq[39]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[39]
+set_location_assignment PIN_AV13 -to MB_I_IO.dq[40]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[40]
+set_location_assignment PIN_AR13 -to MB_I_IO.dq[41]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[41]
+set_location_assignment PIN_AR15 -to MB_I_IO.dq[42]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[42]
+set_location_assignment PIN_AP15 -to MB_I_IO.dq[43]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[43]
+set_location_assignment PIN_AT15 -to MB_I_IO.dq[44]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[44]
+set_location_assignment PIN_AU14 -to MB_I_IO.dq[45]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[45]
+set_location_assignment PIN_AU15 -to MB_I_IO.dq[46]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[46]
+set_location_assignment PIN_AV14 -to MB_I_IO.dq[47]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[47]
+set_location_assignment PIN_AM13 -to MB_I_IO.dq[48]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[48]
+set_location_assignment PIN_AT13 -to MB_I_IO.dq[49]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[49]
+set_location_assignment PIN_AT12 -to MB_I_IO.dq[50]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[50]
+set_location_assignment PIN_AP14 -to MB_I_IO.dq[51]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[51]
+set_location_assignment PIN_AN13 -to MB_I_IO.dq[52]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[52]
+set_location_assignment PIN_AK13 -to MB_I_IO.dq[53]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[53]
+set_location_assignment PIN_AM12 -to MB_I_IO.dq[54]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[54]
+set_location_assignment PIN_AL13 -to MB_I_IO.dq[55]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[55]
+set_location_assignment PIN_AH13 -to MB_I_IO.dq[56]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[56]
+set_location_assignment PIN_AL15 -to MB_I_IO.dq[57]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[57]
+set_location_assignment PIN_AM15 -to MB_I_IO.dq[58]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[58]
+set_location_assignment PIN_AJ14 -to MB_I_IO.dq[59]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[59]
+set_location_assignment PIN_AJ12 -to MB_I_IO.dq[60]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[60]
+set_location_assignment PIN_AL16 -to MB_I_IO.dq[61]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[61]
+set_location_assignment PIN_AK12 -to MB_I_IO.dq[62]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[62]
+set_location_assignment PIN_AH14 -to MB_I_IO.dq[63]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[63]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[4]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[5]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[6]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[7]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[8]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[64]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[65]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[66]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[67]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[68]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[69]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[70]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[71]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[8]
+set_location_assignment PIN_A17 -to MB_II_IO.dq[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[0]
+set_location_assignment PIN_B16 -to MB_II_IO.dq[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[1]
+set_location_assignment PIN_D16 -to MB_II_IO.dq[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[2]
+set_location_assignment PIN_A18 -to MB_II_IO.dq[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[3]
+set_location_assignment PIN_B18 -to MB_II_IO.dq[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[4]
+set_location_assignment PIN_C17 -to MB_II_IO.dq[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[5]
+set_location_assignment PIN_E18 -to MB_II_IO.dq[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[6]
+set_location_assignment PIN_F18 -to MB_II_IO.dq[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[7]
+set_location_assignment PIN_R22 -to MB_II_IO.dq[8]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[8]
+set_location_assignment PIN_J20 -to MB_II_IO.dq[9]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[9]
+set_location_assignment PIN_L21 -to MB_II_IO.dq[10]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[10]
+set_location_assignment PIN_M20 -to MB_II_IO.dq[11]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[11]
+set_location_assignment PIN_J21 -to MB_II_IO.dq[12]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[12]
+set_location_assignment PIN_P21 -to MB_II_IO.dq[13]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[13]
+set_location_assignment PIN_R20 -to MB_II_IO.dq[14]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[14]
+set_location_assignment PIN_N21 -to MB_II_IO.dq[15]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[15]
+set_location_assignment PIN_L22 -to MB_II_IO.dq[16]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[16]
+set_location_assignment PIN_G20 -to MB_II_IO.dq[17]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[17]
+set_location_assignment PIN_H21 -to MB_II_IO.dq[18]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[18]
+set_location_assignment PIN_N22 -to MB_II_IO.dq[19]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[19]
+set_location_assignment PIN_P22 -to MB_II_IO.dq[20]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[20]
+set_location_assignment PIN_F20 -to MB_II_IO.dq[21]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[21]
+set_location_assignment PIN_G21 -to MB_II_IO.dq[22]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[22]
+set_location_assignment PIN_F21 -to MB_II_IO.dq[23]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[23]
+set_location_assignment PIN_E19 -to MB_II_IO.dq[24]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[24]
+set_location_assignment PIN_B20 -to MB_II_IO.dq[25]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[25]
+set_location_assignment PIN_A20 -to MB_II_IO.dq[26]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[26]
+set_location_assignment PIN_G19 -to MB_II_IO.dq[27]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[27]
+set_location_assignment PIN_D20 -to MB_II_IO.dq[28]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[28]
+set_location_assignment PIN_E20 -to MB_II_IO.dq[29]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[29]
+set_location_assignment PIN_D17 -to MB_II_IO.dq[30]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[30]
+set_location_assignment PIN_C18 -to MB_II_IO.dq[31]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[31]
+set_location_assignment PIN_F30 -to MB_II_IO.dq[32]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[32]
+set_location_assignment PIN_L30 -to MB_II_IO.dq[33]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[33]
+set_location_assignment PIN_M30 -to MB_II_IO.dq[34]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[34]
+set_location_assignment PIN_C31 -to MB_II_IO.dq[35]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[35]
+set_location_assignment PIN_D31 -to MB_II_IO.dq[36]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[36]
+set_location_assignment PIN_H31 -to MB_II_IO.dq[37]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[37]
+set_location_assignment PIN_J31 -to MB_II_IO.dq[38]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[38]
+set_location_assignment PIN_F31 -to MB_II_IO.dq[39]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[39]
+set_location_assignment PIN_P32 -to MB_II_IO.dq[40]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[40]
+set_location_assignment PIN_R30 -to MB_II_IO.dq[41]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[41]
+set_location_assignment PIN_U31 -to MB_II_IO.dq[42]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[42]
+set_location_assignment PIN_W31 -to MB_II_IO.dq[43]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[43]
+set_location_assignment PIN_P29 -to MB_II_IO.dq[44]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[44]
+set_location_assignment PIN_P30 -to MB_II_IO.dq[45]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[45]
+set_location_assignment PIN_V31 -to MB_II_IO.dq[46]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[46]
+set_location_assignment PIN_R29 -to MB_II_IO.dq[47]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[47]
+set_location_assignment PIN_M33 -to MB_II_IO.dq[48]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[48]
+set_location_assignment PIN_J33 -to MB_II_IO.dq[49]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[49]
+set_location_assignment PIN_H33 -to MB_II_IO.dq[50]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[50]
+set_location_assignment PIN_H32 -to MB_II_IO.dq[51]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[51]
+set_location_assignment PIN_J32 -to MB_II_IO.dq[52]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[52]
+set_location_assignment PIN_K33 -to MB_II_IO.dq[53]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[53]
+set_location_assignment PIN_K32 -to MB_II_IO.dq[54]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[54]
+set_location_assignment PIN_L32 -to MB_II_IO.dq[55]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[55]
+set_location_assignment PIN_AB33 -to MB_II_IO.dq[56]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[56]
+set_location_assignment PIN_AA32 -to MB_II_IO.dq[57]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[57]
+set_location_assignment PIN_W32 -to MB_II_IO.dq[58]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[58]
+set_location_assignment PIN_U33 -to MB_II_IO.dq[59]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[59]
+set_location_assignment PIN_Y33 -to MB_II_IO.dq[60]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[60]
+set_location_assignment PIN_AA33 -to MB_II_IO.dq[61]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[61]
+set_location_assignment PIN_V33 -to MB_II_IO.dq[62]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[62]
+set_location_assignment PIN_Y32 -to MB_II_IO.dq[63]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[63]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[4]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[5]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[6]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[7]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[8]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IN.alert_n
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_IN.oct_rzqin
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IN.alert_n
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_II_IN.oct_rzqin
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_REF_CLK
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_II_REF_CLK
+set_location_assignment PIN_B6 -to "BCK_TX[0](n)"
+set_location_assignment PIN_A4 -to "BCK_TX[1](n)"
+set_location_assignment PIN_A12 -to "BCK_TX[2](n)"
+set_location_assignment PIN_B2 -to "BCK_TX[3](n)"
+set_location_assignment PIN_C4 -to "BCK_TX[4](n)"
+set_location_assignment PIN_A8 -to "BCK_TX[5](n)"
+set_location_assignment PIN_D2 -to "BCK_TX[6](n)"
+set_location_assignment PIN_E4 -to "BCK_TX[7](n)"
+set_location_assignment PIN_F2 -to "BCK_TX[8](n)"
+set_location_assignment PIN_G4 -to "BCK_TX[9](n)"
+set_location_assignment PIN_J4 -to "BCK_TX[10](n)"
+set_location_assignment PIN_H2 -to "BCK_TX[11](n)"
+set_location_assignment PIN_L4 -to "BCK_TX[12](n)"
+set_location_assignment PIN_K2 -to "BCK_TX[13](n)"
+set_location_assignment PIN_N4 -to "BCK_TX[14](n)"
+set_location_assignment PIN_M2 -to "BCK_TX[15](n)"
+set_location_assignment PIN_R4 -to "BCK_TX[16](n)"
+set_location_assignment PIN_P2 -to "BCK_TX[17](n)"
+set_location_assignment PIN_U4 -to "BCK_TX[18](n)"
+set_location_assignment PIN_T2 -to "BCK_TX[19](n)"
+set_location_assignment PIN_W4 -to "BCK_TX[20](n)"
+set_location_assignment PIN_V2 -to "BCK_TX[21](n)"
+set_location_assignment PIN_AA4 -to "BCK_TX[22](n)"
+set_location_assignment PIN_Y2 -to "BCK_TX[23](n)"
+set_location_assignment PIN_AC4 -to "BCK_TX[24](n)"
+set_location_assignment PIN_AB2 -to "BCK_TX[25](n)"
+set_location_assignment PIN_AE4 -to "BCK_TX[26](n)"
+set_location_assignment PIN_AD2 -to "BCK_TX[27](n)"
+set_location_assignment PIN_AG4 -to "BCK_TX[28](n)"
+set_location_assignment PIN_AF2 -to "BCK_TX[29](n)"
+set_location_assignment PIN_AJ4 -to "BCK_TX[30](n)"
+set_location_assignment PIN_AH2 -to "BCK_TX[31](n)"
+set_location_assignment PIN_AL4 -to "BCK_TX[32](n)"
+set_location_assignment PIN_AK2 -to "BCK_TX[33](n)"
+set_location_assignment PIN_AN4 -to "BCK_TX[34](n)"
+set_location_assignment PIN_AM2 -to "BCK_TX[35](n)"
+set_location_assignment PIN_AR4 -to "BCK_TX[36](n)"
+set_location_assignment PIN_AP2 -to "BCK_TX[37](n)"
+set_location_assignment PIN_AU4 -to "BCK_TX[38](n)"
+set_location_assignment PIN_AT2 -to "BCK_TX[39](n)"
+set_location_assignment PIN_AW4 -to "BCK_TX[40](n)"
+set_location_assignment PIN_AV2 -to "BCK_TX[41](n)"
+set_location_assignment PIN_BB2 -to "BCK_TX[42](n)"
+set_location_assignment PIN_AY2 -to "BCK_TX[43](n)"
+set_location_assignment PIN_BD6 -to "BCK_TX[44](n)"
+set_location_assignment PIN_BA4 -to "BCK_TX[45](n)"
+set_location_assignment PIN_BC4 -to "BCK_TX[46](n)"
+set_location_assignment PIN_BD10 -to "BCK_TX[47](n)"
+#set_location_assignment PIN_AV18 -to "MB_I_OU.ck[0](n)"
+#set_location_assignment PIN_AU16 -to "MB_I_OU.ck[1](n)"
+#set_location_assignment PIN_AY28 -to "MB_I_IO.dqs[0](n)"
+#set_location_assignment PIN_AN28 -to "MB_I_IO.dqs[1](n)"
+#set_location_assignment PIN_AU24 -to "MB_I_IO.dqs[2](n)"
+#set_location_assignment PIN_AM24 -to "MB_I_IO.dqs[3](n)"
+#set_location_assignment PIN_BB14 -to "MB_I_IO.dqs[4](n)"
+#set_location_assignment PIN_AY14 -to "MB_I_IO.dqs[5](n)"
+#set_location_assignment PIN_AP12 -to "MB_I_IO.dqs[6](n)"
+#set_location_assignment PIN_AK14 -to "MB_I_IO.dqs[7](n)"
+#set_location_assignment PIN_BD22 -to "MB_I_IO.dqs[8](n)"
+#set_location_assignment PIN_M28 -to "MB_II_OU.ck[0](n)"
+#set_location_assignment PIN_J26 -to "MB_II_OU.ck[1](n)"
+#set_location_assignment PIN_E17 -to "MB_II_IO.dqs[0](n)"
+#set_location_assignment PIN_K20 -to "MB_II_IO.dqs[1](n)"
+#set_location_assignment PIN_H22 -to "MB_II_IO.dqs[2](n)"
+#set_location_assignment PIN_C19 -to "MB_II_IO.dqs[3](n)"
+#set_location_assignment PIN_M31 -to "MB_II_IO.dqs[4](n)"
+#set_location_assignment PIN_N31 -to "MB_II_IO.dqs[5](n)"
+#set_location_assignment PIN_P33 -to "MB_II_IO.dqs[6](n)"
+#set_location_assignment PIN_T32 -to "MB_II_IO.dqs[7](n)"
+#set_location_assignment PIN_B25 -to "MB_II_IO.dqs[8](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to "MB_I_OU.ck[0](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to "MB_I_OU.ck[1](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[0](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[1](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[2](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[3](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[4](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[5](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[6](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[7](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[8](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to "MB_II_OU.ck[0](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to "MB_II_OU.ck[1](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[0](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[1](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[2](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[3](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[4](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[5](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[6](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[7](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[8](n)"
+set_location_assignment PIN_BA33 -to QSFP_LED[0]
+set_location_assignment PIN_BA30 -to QSFP_LED[1]
+set_location_assignment PIN_BB33 -to QSFP_LED[2]
+set_location_assignment PIN_AU33 -to QSFP_LED[3]
+set_location_assignment PIN_AV32 -to QSFP_LED[4]
+set_location_assignment PIN_AW30 -to QSFP_LED[5]
+set_location_assignment PIN_AP31 -to QSFP_LED[6]
+set_location_assignment PIN_AP30 -to QSFP_LED[7]
+set_location_assignment PIN_AT33 -to QSFP_LED[8]
+set_location_assignment PIN_AG32 -to QSFP_LED[9]
+set_location_assignment PIN_AF32 -to QSFP_LED[10]
+set_location_assignment PIN_AE32 -to QSFP_LED[11]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to CLKUSR
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[8]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[9]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[10]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[11]
+set_location_assignment PIN_AN38 -to QSFP_0_RX[0]
+set_location_assignment PIN_AN37 -to "QSFP_0_RX[0](n)"
+set_location_assignment PIN_AM40 -to QSFP_0_RX[1]
+set_location_assignment PIN_AM39 -to "QSFP_0_RX[1](n)"
+set_location_assignment PIN_AK40 -to QSFP_0_RX[2]
+set_location_assignment PIN_AK39 -to "QSFP_0_RX[2](n)"
+set_location_assignment PIN_AJ38 -to QSFP_0_RX[3]
+set_location_assignment PIN_AJ37 -to "QSFP_0_RX[3](n)"
+set_location_assignment PIN_AN42 -to QSFP_0_TX[0]
+set_location_assignment PIN_AN41 -to "QSFP_0_TX[0](n)"
+set_location_assignment PIN_AM44 -to QSFP_0_TX[1]
+set_location_assignment PIN_AM43 -to "QSFP_0_TX[1](n)"
+set_location_assignment PIN_AK44 -to QSFP_0_TX[2]
+set_location_assignment PIN_AK43 -to "QSFP_0_TX[2](n)"
+set_location_assignment PIN_AJ42 -to QSFP_0_TX[3]
+set_location_assignment PIN_AJ41 -to "QSFP_0_TX[3](n)"
+set_location_assignment PIN_AC38 -to QSFP_1_RX[0]
+set_location_assignment PIN_AC37 -to "QSFP_1_RX[0](n)"
+set_location_assignment PIN_AD40 -to QSFP_1_RX[1]
+set_location_assignment PIN_AD39 -to "QSFP_1_RX[1](n)"
+set_location_assignment PIN_AF40 -to QSFP_1_RX[2]
+set_location_assignment PIN_AF39 -to "QSFP_1_RX[2](n)"
+set_location_assignment PIN_AG38 -to QSFP_1_RX[3]
+set_location_assignment PIN_AG37 -to "QSFP_1_RX[3](n)"
+set_location_assignment PIN_AC42 -to QSFP_1_TX[0]
+set_location_assignment PIN_AC41 -to "QSFP_1_TX[0](n)"
+set_location_assignment PIN_AD44 -to QSFP_1_TX[1]
+set_location_assignment PIN_AD43 -to "QSFP_1_TX[1](n)"
+set_location_assignment PIN_AF44 -to QSFP_1_TX[2]
+set_location_assignment PIN_AF43 -to "QSFP_1_TX[2](n)"
+set_location_assignment PIN_AG42 -to QSFP_1_TX[3]
+set_location_assignment PIN_AG41 -to "QSFP_1_TX[3](n)"
+set_location_assignment PIN_AL38 -to QSFP_2_RX[0]
+set_location_assignment PIN_AL37 -to "QSFP_2_RX[0](n)"
+set_location_assignment PIN_AH40 -to QSFP_2_RX[1]
+set_location_assignment PIN_AH39 -to "QSFP_2_RX[1](n)"
+set_location_assignment PIN_AE38 -to QSFP_2_RX[2]
+set_location_assignment PIN_AE37 -to "QSFP_2_RX[2](n)"
+set_location_assignment PIN_AB40 -to QSFP_2_RX[3]
+set_location_assignment PIN_AB39 -to "QSFP_2_RX[3](n)"
+set_location_assignment PIN_AL42 -to QSFP_2_TX[0]
+set_location_assignment PIN_AL41 -to "QSFP_2_TX[0](n)"
+set_location_assignment PIN_AH44 -to QSFP_2_TX[1]
+set_location_assignment PIN_AH43 -to "QSFP_2_TX[1](n)"
+set_location_assignment PIN_AE42 -to QSFP_2_TX[2]
+set_location_assignment PIN_AE41 -to "QSFP_2_TX[2](n)"
+set_location_assignment PIN_AB44 -to QSFP_2_TX[3]
+set_location_assignment PIN_AB43 -to "QSFP_2_TX[3](n)"
+set_location_assignment PIN_W38 -to QSFP_3_RX[0]
+set_location_assignment PIN_W37 -to "QSFP_3_RX[0](n)"
+set_location_assignment PIN_T40 -to QSFP_3_RX[1]
+set_location_assignment PIN_T39 -to "QSFP_3_RX[1](n)"
+set_location_assignment PIN_N38 -to QSFP_3_RX[2]
+set_location_assignment PIN_N37 -to "QSFP_3_RX[2](n)"
+set_location_assignment PIN_K40 -to QSFP_3_RX[3]
+set_location_assignment PIN_K39 -to "QSFP_3_RX[3](n)"
+set_location_assignment PIN_W42 -to QSFP_3_TX[0]
+set_location_assignment PIN_W41 -to "QSFP_3_TX[0](n)"
+set_location_assignment PIN_T44 -to QSFP_3_TX[1]
+set_location_assignment PIN_T43 -to "QSFP_3_TX[1](n)"
+set_location_assignment PIN_N42 -to QSFP_3_TX[2]
+set_location_assignment PIN_N41 -to "QSFP_3_TX[2](n)"
+set_location_assignment PIN_K44 -to QSFP_3_TX[3]
+set_location_assignment PIN_K43 -to "QSFP_3_TX[3](n)"
+set_location_assignment PIN_AA38 -to QSFP_4_RX[0]
+set_location_assignment PIN_AA37 -to "QSFP_4_RX[0](n)"
+set_location_assignment PIN_Y40 -to QSFP_4_RX[1]
+set_location_assignment PIN_Y39 -to "QSFP_4_RX[1](n)"
+set_location_assignment PIN_V40 -to QSFP_4_RX[2]
+set_location_assignment PIN_V39 -to "QSFP_4_RX[2](n)"
+set_location_assignment PIN_U38 -to QSFP_4_RX[3]
+set_location_assignment PIN_U37 -to "QSFP_4_RX[3](n)"
+set_location_assignment PIN_AA42 -to QSFP_4_TX[0]
+set_location_assignment PIN_AA41 -to "QSFP_4_TX[0](n)"
+set_location_assignment PIN_Y44 -to QSFP_4_TX[1]
+set_location_assignment PIN_Y43 -to "QSFP_4_TX[1](n)"
+set_location_assignment PIN_V44 -to QSFP_4_TX[2]
+set_location_assignment PIN_V43 -to "QSFP_4_TX[2](n)"
+set_location_assignment PIN_U42 -to QSFP_4_TX[3]
+set_location_assignment PIN_U41 -to "QSFP_4_TX[3](n)"
+set_location_assignment PIN_L38 -to QSFP_5_RX[0]
+set_location_assignment PIN_L37 -to "QSFP_5_RX[0](n)"
+set_location_assignment PIN_M40 -to QSFP_5_RX[1]
+set_location_assignment PIN_M39 -to "QSFP_5_RX[1](n)"
+set_location_assignment PIN_P40 -to QSFP_5_RX[2]
+set_location_assignment PIN_P39 -to "QSFP_5_RX[2](n)"
+set_location_assignment PIN_R38 -to QSFP_5_RX[3]
+set_location_assignment PIN_R37 -to "QSFP_5_RX[3](n)"
+set_location_assignment PIN_L42 -to QSFP_5_TX[0]
+set_location_assignment PIN_L41 -to "QSFP_5_TX[0](n)"
+set_location_assignment PIN_M44 -to QSFP_5_TX[1]
+set_location_assignment PIN_M43 -to "QSFP_5_TX[1](n)"
+set_location_assignment PIN_P44 -to QSFP_5_TX[2]
+set_location_assignment PIN_P43 -to "QSFP_5_TX[2](n)"
+set_location_assignment PIN_R42 -to QSFP_5_TX[3]
+set_location_assignment PIN_R41 -to "QSFP_5_TX[3](n)"
+set_location_assignment PIN_AP40 -to RING_0_RX[0]
+set_location_assignment PIN_AP39 -to "RING_0_RX[0](n)"
+set_location_assignment PIN_AR38 -to RING_0_RX[1]
+set_location_assignment PIN_AR37 -to "RING_0_RX[1](n)"
+set_location_assignment PIN_AT40 -to RING_0_RX[2]
+set_location_assignment PIN_AT39 -to "RING_0_RX[2](n)"
+set_location_assignment PIN_AU38 -to RING_0_RX[3]
+set_location_assignment PIN_AU37 -to "RING_0_RX[3](n)"
+set_location_assignment PIN_AV40 -to RING_0_RX[4]
+set_location_assignment PIN_AV39 -to "RING_0_RX[4](n)"
+set_location_assignment PIN_AW38 -to RING_0_RX[5]
+set_location_assignment PIN_AW37 -to "RING_0_RX[5](n)"
+set_location_assignment PIN_AY40 -to RING_0_RX[6]
+set_location_assignment PIN_AY39 -to "RING_0_RX[6](n)"
+set_location_assignment PIN_BA38 -to RING_0_RX[7]
+set_location_assignment PIN_BA37 -to "RING_0_RX[7](n)"
+set_location_assignment PIN_BB40 -to RING_0_RX[8]
+set_location_assignment PIN_BB39 -to "RING_0_RX[8](n)"
+set_location_assignment PIN_BC38 -to RING_0_RX[9]
+set_location_assignment PIN_BC37 -to "RING_0_RX[9](n)"
+set_location_assignment PIN_AY36 -to RING_0_RX[10]
+set_location_assignment PIN_AY35 -to "RING_0_RX[10](n)"
+set_location_assignment PIN_BB36 -to RING_0_RX[11]
+set_location_assignment PIN_BB35 -to "RING_0_RX[11](n)"
+set_location_assignment PIN_AP44 -to RING_0_TX[0]
+set_location_assignment PIN_AP43 -to "RING_0_TX[0](n)"
+set_location_assignment PIN_AR42 -to RING_0_TX[1]
+set_location_assignment PIN_AR41 -to "RING_0_TX[1](n)"
+set_location_assignment PIN_AT44 -to RING_0_TX[2]
+set_location_assignment PIN_AT43 -to "RING_0_TX[2](n)"
+set_location_assignment PIN_AU42 -to RING_0_TX[3]
+set_location_assignment PIN_AU41 -to "RING_0_TX[3](n)"
+set_location_assignment PIN_AV44 -to RING_0_TX[4]
+set_location_assignment PIN_AV43 -to "RING_0_TX[4](n)"
+set_location_assignment PIN_AW42 -to RING_0_TX[5]
+set_location_assignment PIN_AW41 -to "RING_0_TX[5](n)"
+set_location_assignment PIN_AY44 -to RING_0_TX[6]
+set_location_assignment PIN_AY43 -to "RING_0_TX[6](n)"
+set_location_assignment PIN_BB44 -to RING_0_TX[7]
+set_location_assignment PIN_BB43 -to "RING_0_TX[7](n)"
+set_location_assignment PIN_BA42 -to RING_0_TX[8]
+set_location_assignment PIN_BA41 -to "RING_0_TX[8](n)"
+set_location_assignment PIN_BD40 -to RING_0_TX[9]
+set_location_assignment PIN_BD39 -to "RING_0_TX[9](n)"
+set_location_assignment PIN_BC42 -to RING_0_TX[10]
+set_location_assignment PIN_BC41 -to "RING_0_TX[10](n)"
+set_location_assignment PIN_BD36 -to RING_0_TX[11]
+set_location_assignment PIN_BD35 -to "RING_0_TX[11](n)"
+set_location_assignment PIN_H40 -to RING_1_RX[0]
+set_location_assignment PIN_H39 -to "RING_1_RX[0](n)"
+set_location_assignment PIN_J38 -to RING_1_RX[1]
+set_location_assignment PIN_J37 -to "RING_1_RX[1](n)"
+set_location_assignment PIN_F40 -to RING_1_RX[2]
+set_location_assignment PIN_F39 -to "RING_1_RX[2](n)"
+set_location_assignment PIN_G38 -to RING_1_RX[3]
+set_location_assignment PIN_G37 -to "RING_1_RX[3](n)"
+set_location_assignment PIN_D40 -to RING_1_RX[4]
+set_location_assignment PIN_D39 -to "RING_1_RX[4](n)"
+set_location_assignment PIN_E38 -to RING_1_RX[5]
+set_location_assignment PIN_E37 -to "RING_1_RX[5](n)"
+set_location_assignment PIN_F36 -to RING_1_RX[6]
+set_location_assignment PIN_F35 -to "RING_1_RX[6](n)"
+set_location_assignment PIN_C38 -to RING_1_RX[7]
+set_location_assignment PIN_C37 -to "RING_1_RX[7](n)"
+set_location_assignment PIN_B36 -to RING_1_RX[8]
+set_location_assignment PIN_B35 -to "RING_1_RX[8](n)"
+set_location_assignment PIN_D36 -to RING_1_RX[9]
+set_location_assignment PIN_D35 -to "RING_1_RX[9](n)"
+set_location_assignment PIN_E34 -to RING_1_RX[10]
+set_location_assignment PIN_E33 -to "RING_1_RX[10](n)"
+set_location_assignment PIN_C34 -to RING_1_RX[11]
+set_location_assignment PIN_C33 -to "RING_1_RX[11](n)"
+set_location_assignment PIN_H44 -to RING_1_TX[0]
+set_location_assignment PIN_H43 -to "RING_1_TX[0](n)"
+set_location_assignment PIN_J42 -to RING_1_TX[1]
+set_location_assignment PIN_J41 -to "RING_1_TX[1](n)"
+set_location_assignment PIN_G42 -to RING_1_TX[2]
+set_location_assignment PIN_G41 -to "RING_1_TX[2](n)"
+set_location_assignment PIN_F44 -to RING_1_TX[3]
+set_location_assignment PIN_F43 -to "RING_1_TX[3](n)"
+set_location_assignment PIN_E42 -to RING_1_TX[4]
+set_location_assignment PIN_E41 -to "RING_1_TX[4](n)"
+set_location_assignment PIN_D44 -to RING_1_TX[5]
+set_location_assignment PIN_D43 -to "RING_1_TX[5](n)"
+set_location_assignment PIN_B44 -to RING_1_TX[6]
+set_location_assignment PIN_B43 -to "RING_1_TX[6](n)"
+set_location_assignment PIN_C42 -to RING_1_TX[7]
+set_location_assignment PIN_C41 -to "RING_1_TX[7](n)"
+set_location_assignment PIN_B40 -to RING_1_TX[8]
+set_location_assignment PIN_B39 -to "RING_1_TX[8](n)"
+set_location_assignment PIN_A42 -to RING_1_TX[9]
+set_location_assignment PIN_A41 -to "RING_1_TX[9](n)"
+set_location_assignment PIN_A38 -to RING_1_TX[10]
+set_location_assignment PIN_A37 -to "RING_1_TX[10](n)"
+set_location_assignment PIN_A34 -to RING_1_TX[11]
+set_location_assignment PIN_A33 -to "RING_1_TX[11](n)"
+set_location_assignment PIN_H17 -to S10_ETH_CLK
+set_location_assignment PIN_AE13 -to JESD204B_SYNC[0]
+set_location_assignment PIN_AD13 -to JESD204B_SYNC[1]
+set_location_assignment PIN_AC13 -to JESD204B_SYNC[2]
+set_location_assignment PIN_AA13 -to JESD204B_SYNC[3]
+set_location_assignment PIN_AA12 -to JESD204B_SYNC[4]
+set_location_assignment PIN_V12 -to JESD204B_SYNC[5]
+set_location_assignment PIN_U14 -to JESD204B_SYNC[6]
+set_location_assignment PIN_U12 -to JESD204B_SYNC[7]
+set_location_assignment PIN_T12 -to JESD204B_SYNC[8]
+set_location_assignment PIN_R14 -to JESD204B_SYNC[9]
+set_location_assignment PIN_R13 -to JESD204B_SYNC[10]
+set_location_assignment PIN_P12 -to JESD204B_SYNC[11]
+set_location_assignment PIN_Y13 -to JESD204B_SYSREF
+set_location_assignment PIN_Y12 -to "JESD204B_SYSREF(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "CLK(n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[4]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[4](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[5]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[5](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[6]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[6](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[7]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[7](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[8]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[8](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[9]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[9](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[10]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[10](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[11]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[11](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[4]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[4](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[5]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[5](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[6]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[6](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[7]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[7](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[8]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[8](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[9]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[9](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[10]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[10](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[11]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[11](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[4]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[4](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[5]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[5](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[6]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[6](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[7]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[7](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[8]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[8](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[9]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[9](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[10]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[10](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[11]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[11](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[4]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[4](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[5]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[5](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[6]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[6](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[7]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[7](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[8]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[8](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[9]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[9](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[10]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[10](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[11]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[11](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to JESD204B_SYSREF
+set_instance_assignment -name IO_STANDARD LVDS -to "JESD204B_SYSREF(n)"
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA_JESD.qsf b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA_JESD.qsf
new file mode 100644
index 0000000000000000000000000000000000000000..8f88388e0f3d8635bc242444f0b1314ada914447
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA_JESD.qsf
@@ -0,0 +1,1522 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1a10.0 Build 346 11/13/2013 SJ Full Version
+# Date created = 08:55:45  March 13, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		unb2_pinning_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.8 V"
+set_global_assignment -name FAMILY "arria 10"
+#set_global_assignment -name DEVICE 10AX115U4F45I3SGES
+set_global_assignment -name DEVICE 10AX115U3F45E2SG
+set_global_assignment -name TOP_LEVEL_ENTITY unb2c_test_pinning_jesd204b
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:55:45  MARCH 13, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+#set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
+#set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+#set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+#set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+#set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
+
+# IO Location Assignments from Gijs
+#
+#from chip planner
+#
+# 
+#from chip planner
+#
+
+# rx pins modified from chip planner
+# tx pins as per Gijs
+
+
+set_location_assignment PIN_K15 -to CLK
+set_location_assignment PIN_J15 -to "CLK(n)"
+set_location_assignment PIN_N12 -to ETH_CLK
+set_location_assignment PIN_K14 -to PPS
+set_location_assignment PIN_J14 -to "PPS(n)"
+set_location_assignment PIN_Y36 -to SA_CLK
+set_location_assignment PIN_Y35 -to "SA_CLK(n)"
+set_location_assignment PIN_AH9 -to SB_CLK
+set_location_assignment PIN_AH10 -to "SB_CLK(n)"
+set_location_assignment PIN_AP20 -to MB_I_OU.a[0]
+set_location_assignment PIN_AR20 -to MB_I_OU.a[1]
+set_location_assignment PIN_AP19 -to MB_I_OU.a[2]
+set_location_assignment PIN_AR19 -to MB_I_OU.a[3]
+set_location_assignment PIN_AR18 -to MB_I_OU.a[4]
+set_location_assignment PIN_AT17 -to MB_I_OU.a[5]
+set_location_assignment PIN_AU19 -to MB_I_OU.a[6]
+set_location_assignment PIN_AT18 -to MB_I_OU.a[7]
+set_location_assignment PIN_AL17 -to MB_I_OU.a[8]
+set_location_assignment PIN_AM18 -to MB_I_OU.a[9]
+set_location_assignment PIN_AM19 -to MB_I_OU.a[10]
+set_location_assignment PIN_AN19 -to MB_I_OU.a[11]
+set_location_assignment PIN_BA17 -to MB_I_OU.a[12]
+set_location_assignment PIN_BD17 -to MB_I_OU.a[13]
+set_location_assignment PIN_AY18 -to MB_I_OU.act_n
+set_location_assignment PIN_AV29 -to MB_I_IN.alert_n
+set_location_assignment PIN_BB16 -to MB_I_OU.ba[0]
+set_location_assignment PIN_BD16 -to MB_I_OU.ba[1]
+set_location_assignment PIN_BC16 -to MB_I_OU.bg[0]
+set_location_assignment PIN_AW19 -to MB_I_OU.bg[1]
+set_location_assignment PIN_BA15 -to MB_I_OU.a[15]
+set_location_assignment PIN_BC21 -to MB_I_IO.dq[64]
+set_location_assignment PIN_BA22 -to MB_I_IO.dq[65]
+set_location_assignment PIN_BD21 -to MB_I_IO.dq[66]
+set_location_assignment PIN_BB20 -to MB_I_IO.dq[67]
+set_location_assignment PIN_BA20 -to MB_I_IO.dq[68]
+set_location_assignment PIN_BD20 -to MB_I_IO.dq[69]
+set_location_assignment PIN_AY20 -to MB_I_IO.dq[70]
+set_location_assignment PIN_AY22 -to MB_I_IO.dq[71]
+set_location_assignment PIN_AU18 -to MB_I_OU.ck[0]
+set_location_assignment PIN_AT16 -to MB_I_OU.ck[1]
+set_location_assignment PIN_BB19 -to MB_I_OU.cke[0]
+set_location_assignment PIN_AP16 -to MB_I_OU.cke[1]
+set_location_assignment PIN_AY19 -to MB_I_OU.cs_n[0]
+set_location_assignment PIN_AN16 -to MB_I_OU.cs_n[1]
+set_location_assignment PIN_BC29 -to MB_I_IO.dbi_n[0]
+set_location_assignment PIN_AR27 -to MB_I_IO.dbi_n[1]
+set_location_assignment PIN_BD24 -to MB_I_IO.dbi_n[2]
+set_location_assignment PIN_AM23 -to MB_I_IO.dbi_n[3]
+set_location_assignment PIN_AU12 -to MB_I_IO.dbi_n[4]
+set_location_assignment PIN_AU13 -to MB_I_IO.dbi_n[5]
+set_location_assignment PIN_AM14 -to MB_I_IO.dbi_n[6]
+set_location_assignment PIN_AM16 -to MB_I_IO.dbi_n[7]
+set_location_assignment PIN_BA21 -to MB_I_IO.dbi_n[8]
+set_location_assignment PIN_BA28 -to MB_I_IO.dqs[0]
+set_location_assignment PIN_AM28 -to MB_I_IO.dqs[1]
+set_location_assignment PIN_AV24 -to MB_I_IO.dqs[2]
+set_location_assignment PIN_AN24 -to MB_I_IO.dqs[3]
+set_location_assignment PIN_BC14 -to MB_I_IO.dqs[4]
+set_location_assignment PIN_AW14 -to MB_I_IO.dqs[5]
+set_location_assignment PIN_AN12 -to MB_I_IO.dqs[6]
+set_location_assignment PIN_AK15 -to MB_I_IO.dqs[7]
+set_location_assignment PIN_BC22 -to MB_I_IO.dqs[8]
+set_location_assignment PIN_BD19 -to MB_I_OU.odt[0]
+set_location_assignment PIN_AR17 -to MB_I_OU.odt[1]
+set_location_assignment PIN_BC18 -to MB_I_OU.par
+set_location_assignment PIN_BB15 -to MB_I_OU.a[16]
+set_location_assignment PIN_AW17 -to MB_I_REF_CLK
+set_location_assignment PIN_AV19 -to MB_I_OU.reset_n
+set_location_assignment PIN_AY17 -to MB_I_IN.oct_rzqin
+set_location_assignment PIN_BC17 -to MB_I_OU.a[14]
+set_location_assignment PIN_A29 -to MB_II_OU.a[0]
+set_location_assignment PIN_B29 -to MB_II_OU.a[1]
+set_location_assignment PIN_H29 -to MB_II_OU.a[2]
+set_location_assignment PIN_G29 -to MB_II_OU.a[3]
+set_location_assignment PIN_D29 -to MB_II_OU.a[4]
+set_location_assignment PIN_E29 -to MB_II_OU.a[5]
+set_location_assignment PIN_C29 -to MB_II_OU.a[6]
+set_location_assignment PIN_C28 -to MB_II_OU.a[7]
+set_location_assignment PIN_E30 -to MB_II_OU.a[8]
+set_location_assignment PIN_D30 -to MB_II_OU.a[9]
+set_location_assignment PIN_B28 -to MB_II_OU.a[10]
+set_location_assignment PIN_A28 -to MB_II_OU.a[11]
+set_location_assignment PIN_H27 -to MB_II_OU.a[12]
+set_location_assignment PIN_E28 -to MB_II_OU.a[13]
+set_location_assignment PIN_K28 -to MB_II_OU.act_n
+set_location_assignment PIN_C16 -to MB_II_IN.alert_n
+set_location_assignment PIN_C27 -to MB_II_OU.ba[0]
+set_location_assignment PIN_A27 -to MB_II_OU.ba[1]
+set_location_assignment PIN_B26 -to MB_II_OU.bg[0]
+set_location_assignment PIN_L27 -to MB_II_OU.bg[1]
+set_location_assignment PIN_F28 -to MB_II_OU.a[15]
+set_location_assignment PIN_E24 -to MB_II_IO.dq[64]
+set_location_assignment PIN_J25 -to MB_II_IO.dq[65]
+set_location_assignment PIN_A25 -to MB_II_IO.dq[66]
+set_location_assignment PIN_G25 -to MB_II_IO.dq[67]
+set_location_assignment PIN_D25 -to MB_II_IO.dq[68]
+set_location_assignment PIN_K25 -to MB_II_IO.dq[69]
+set_location_assignment PIN_D24 -to MB_II_IO.dq[70]
+set_location_assignment PIN_F25 -to MB_II_IO.dq[71]
+set_location_assignment PIN_N27 -to MB_II_OU.ck[0]
+set_location_assignment PIN_K27 -to MB_II_OU.ck[1]
+set_location_assignment PIN_N28 -to MB_II_OU.cke[0]
+set_location_assignment PIN_P26 -to MB_II_OU.cke[1]
+set_location_assignment PIN_K29 -to MB_II_OU.cs_n[0]
+set_location_assignment PIN_H26 -to MB_II_OU.cs_n[1]
+set_location_assignment PIN_A16 -to MB_II_IO.dbi_n[0]
+set_location_assignment PIN_M21 -to MB_II_IO.dbi_n[1]
+set_location_assignment PIN_K22 -to MB_II_IO.dbi_n[2]
+set_location_assignment PIN_D19 -to MB_II_IO.dbi_n[3]
+set_location_assignment PIN_G30 -to MB_II_IO.dbi_n[4]
+set_location_assignment PIN_R32 -to MB_II_IO.dbi_n[5]
+set_location_assignment PIN_G32 -to MB_II_IO.dbi_n[6]
+set_location_assignment PIN_AC32 -to MB_II_IO.dbi_n[7]
+set_location_assignment PIN_E25 -to MB_II_IO.dbi_n[8]
+set_location_assignment PIN_F17 -to MB_II_IO.dqs[0]
+set_location_assignment PIN_L20 -to MB_II_IO.dqs[1]
+set_location_assignment PIN_J22 -to MB_II_IO.dqs[2]
+set_location_assignment PIN_B19 -to MB_II_IO.dqs[3]
+set_location_assignment PIN_L31 -to MB_II_IO.dqs[4]
+set_location_assignment PIN_P31 -to MB_II_IO.dqs[5]
+set_location_assignment PIN_N33 -to MB_II_IO.dqs[6]
+set_location_assignment PIN_T33 -to MB_II_IO.dqs[7]
+set_location_assignment PIN_A26 -to MB_II_IO.dqs[8]
+set_location_assignment PIN_K30 -to MB_II_OU.odt[0]
+set_location_assignment PIN_R27 -to MB_II_OU.odt[1]
+set_location_assignment PIN_R28 -to MB_II_OU.par
+set_location_assignment PIN_G28 -to MB_II_OU.a[16]
+set_location_assignment PIN_J29 -to MB_II_REF_CLK
+set_location_assignment PIN_L28 -to MB_II_OU.reset_n
+set_location_assignment PIN_J27 -to MB_II_IN.oct_rzqin
+set_location_assignment PIN_F27 -to MB_II_OU.a[14]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[0]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[1]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[1](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGOUT[0]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGOUT[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGOUT[1]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGOUT[1](n)"
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to INTA
+set_instance_assignment -name IO_STANDARD "1.8 V" -to INTB
+set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SC
+set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SD
+set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_ALERT
+set_instance_assignment -name IO_STANDARD LVDS -to SA_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "SA_CLK(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to SB_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "SB_CLK(n)"
+set_instance_assignment -name IO_STANDARD "1.8 V" -to SENS_SC
+set_instance_assignment -name IO_STANDARD "1.8 V" -to SENS_SD
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to VERSION[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to VERSION[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to WDI
+set_location_assignment PIN_P16 -to ID[0]
+set_location_assignment PIN_P15 -to ID[1]
+set_location_assignment PIN_K13 -to ID[2]
+set_location_assignment PIN_L13 -to ID[3]
+set_location_assignment PIN_N16 -to ID[4]
+set_location_assignment PIN_N14 -to ID[5]
+set_location_assignment PIN_U13 -to ID[6]
+set_location_assignment PIN_T13 -to ID[7]
+set_location_assignment PIN_AU31 -to INTA
+set_location_assignment PIN_AR30 -to INTB
+set_location_assignment PIN_BA25 -to PMBUS_SC
+set_location_assignment PIN_BD25 -to PMBUS_SD
+set_location_assignment PIN_BD26 -to PMBUS_ALERT
+set_location_assignment PIN_BC31 -to SENS_SC
+set_location_assignment PIN_BB31 -to SENS_SD
+set_location_assignment PIN_AN32 -to TESTIO[0]
+set_location_assignment PIN_AP32 -to TESTIO[1]
+set_location_assignment PIN_AT30 -to TESTIO[2]
+set_location_assignment PIN_BD31 -to TESTIO[3]
+set_location_assignment PIN_AU30 -to TESTIO[4]
+set_location_assignment PIN_BD30 -to TESTIO[5]
+set_location_assignment PIN_AB12 -to VERSION[0]
+set_location_assignment PIN_AB13 -to VERSION[1]
+set_location_assignment PIN_BB30 -to WDI
+set_location_assignment PIN_AT31 -to QSFP_RST
+set_location_assignment PIN_K12 -to ETH_SGIN[0]
+set_location_assignment PIN_J12 -to "ETH_SGIN[0](n)"
+set_location_assignment PIN_M16 -to ETH_SGIN[1]
+set_location_assignment PIN_L16 -to "ETH_SGIN[1](n)"
+set_location_assignment PIN_H13 -to ETH_SGOUT[0]
+set_location_assignment PIN_H12 -to "ETH_SGOUT[0](n)"
+set_location_assignment PIN_L15 -to ETH_SGOUT[1]
+set_location_assignment PIN_M15 -to "ETH_SGOUT[1](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to PPS
+set_instance_assignment -name IO_STANDARD LVDS -to "PPS(n)"
+set_location_assignment PIN_B9 -to BCK_RX[0]
+set_location_assignment PIN_B10 -to "BCK_RX[0](n)"
+set_location_assignment PIN_D9 -to BCK_RX[1]
+set_location_assignment PIN_D10 -to "BCK_RX[1](n)"
+set_location_assignment PIN_C11 -to BCK_RX[2]
+set_location_assignment PIN_C12 -to "BCK_RX[2](n)"
+set_location_assignment PIN_F9 -to BCK_RX[3]
+set_location_assignment PIN_F10 -to "BCK_RX[3](n)"
+set_location_assignment PIN_C7 -to BCK_RX[4]
+set_location_assignment PIN_C8 -to "BCK_RX[4](n)"
+set_location_assignment PIN_E11 -to BCK_RX[5]
+set_location_assignment PIN_E12 -to "BCK_RX[5](n)"
+set_location_assignment PIN_E7 -to BCK_RX[6]
+set_location_assignment PIN_E8 -to "BCK_RX[6](n)"
+set_location_assignment PIN_D5 -to BCK_RX[7]
+set_location_assignment PIN_D6 -to "BCK_RX[7](n)"
+set_location_assignment PIN_G7 -to BCK_RX[8]
+set_location_assignment PIN_G8 -to "BCK_RX[8](n)"
+set_location_assignment PIN_F5 -to BCK_RX[9]
+set_location_assignment PIN_F6 -to "BCK_RX[9](n)"
+set_location_assignment PIN_J7 -to BCK_RX[10]
+set_location_assignment PIN_J8 -to "BCK_RX[10](n)"
+set_location_assignment PIN_H5 -to BCK_RX[11]
+set_location_assignment PIN_H6 -to "BCK_RX[11](n)"
+set_location_assignment PIN_L7 -to BCK_RX[12]
+set_location_assignment PIN_L8 -to "BCK_RX[12](n)"
+set_location_assignment PIN_K5 -to BCK_RX[13]
+set_location_assignment PIN_K6 -to "BCK_RX[13](n)"
+set_location_assignment PIN_N7 -to BCK_RX[14]
+set_location_assignment PIN_N8 -to "BCK_RX[14](n)"
+set_location_assignment PIN_M5 -to BCK_RX[15]
+set_location_assignment PIN_M6 -to "BCK_RX[15](n)"
+set_location_assignment PIN_R7 -to BCK_RX[16]
+set_location_assignment PIN_R8 -to "BCK_RX[16](n)"
+set_location_assignment PIN_P5 -to BCK_RX[17]
+set_location_assignment PIN_P6 -to "BCK_RX[17](n)"
+set_location_assignment PIN_U7 -to BCK_RX[18]
+set_location_assignment PIN_U8 -to "BCK_RX[18](n)"
+set_location_assignment PIN_T5 -to BCK_RX[19]
+set_location_assignment PIN_T6 -to "BCK_RX[19](n)"
+set_location_assignment PIN_W7 -to BCK_RX[20]
+set_location_assignment PIN_W8 -to "BCK_RX[20](n)"
+set_location_assignment PIN_V5 -to BCK_RX[21]
+set_location_assignment PIN_V6 -to "BCK_RX[21](n)"
+set_location_assignment PIN_AA7 -to BCK_RX[22]
+set_location_assignment PIN_AA8 -to "BCK_RX[22](n)"
+set_location_assignment PIN_Y5 -to BCK_RX[23]
+set_location_assignment PIN_Y6 -to "BCK_RX[23](n)"
+set_location_assignment PIN_AC7 -to BCK_RX[24]
+set_location_assignment PIN_AC8 -to "BCK_RX[24](n)"
+set_location_assignment PIN_AB5 -to BCK_RX[25]
+set_location_assignment PIN_AB6 -to "BCK_RX[25](n)"
+set_location_assignment PIN_AE7 -to BCK_RX[26]
+set_location_assignment PIN_AE8 -to "BCK_RX[26](n)"
+set_location_assignment PIN_AD5 -to BCK_RX[27]
+set_location_assignment PIN_AD6 -to "BCK_RX[27](n)"
+set_location_assignment PIN_AG7 -to BCK_RX[28]
+set_location_assignment PIN_AG8 -to "BCK_RX[28](n)"
+set_location_assignment PIN_AF5 -to BCK_RX[29]
+set_location_assignment PIN_AF6 -to "BCK_RX[29](n)"
+set_location_assignment PIN_AJ7 -to BCK_RX[30]
+set_location_assignment PIN_AJ8 -to "BCK_RX[30](n)"
+set_location_assignment PIN_AH5 -to BCK_RX[31]
+set_location_assignment PIN_AH6 -to "BCK_RX[31](n)"
+set_location_assignment PIN_AL7 -to BCK_RX[32]
+set_location_assignment PIN_AL8 -to "BCK_RX[32](n)"
+set_location_assignment PIN_AK5 -to BCK_RX[33]
+set_location_assignment PIN_AK6 -to "BCK_RX[33](n)"
+set_location_assignment PIN_AN7 -to BCK_RX[34]
+set_location_assignment PIN_AN8 -to "BCK_RX[34](n)"
+set_location_assignment PIN_AM5 -to BCK_RX[35]
+set_location_assignment PIN_AM6 -to "BCK_RX[35](n)"
+set_location_assignment PIN_AR7 -to BCK_RX[36]
+set_location_assignment PIN_AR8 -to "BCK_RX[36](n)"
+set_location_assignment PIN_AP5 -to BCK_RX[37]
+set_location_assignment PIN_AP6 -to "BCK_RX[37](n)"
+set_location_assignment PIN_AU7 -to BCK_RX[38]
+set_location_assignment PIN_AU8 -to "BCK_RX[38](n)"
+set_location_assignment PIN_AT5 -to BCK_RX[39]
+set_location_assignment PIN_AT6 -to "BCK_RX[39](n)"
+set_location_assignment PIN_AW7 -to BCK_RX[40]
+set_location_assignment PIN_AW8 -to "BCK_RX[40](n)"
+set_location_assignment PIN_AV5 -to BCK_RX[41]
+set_location_assignment PIN_AV6 -to "BCK_RX[41](n)"
+set_location_assignment PIN_BA7 -to BCK_RX[42]
+set_location_assignment PIN_BA8 -to "BCK_RX[42](n)"
+set_location_assignment PIN_AY5 -to BCK_RX[43]
+set_location_assignment PIN_AY6 -to "BCK_RX[43](n)"
+set_location_assignment PIN_BC7 -to BCK_RX[44]
+set_location_assignment PIN_BC8 -to "BCK_RX[44](n)"
+set_location_assignment PIN_BB5 -to BCK_RX[45]
+set_location_assignment PIN_BB6 -to "BCK_RX[45](n)"
+set_location_assignment PIN_AY9 -to BCK_RX[46]
+set_location_assignment PIN_AY10 -to "BCK_RX[46](n)"
+set_location_assignment PIN_BB9 -to BCK_RX[47]
+set_location_assignment PIN_BB10 -to "BCK_RX[47](n)"
+set_location_assignment PIN_B5 -to BCK_TX[0]
+set_location_assignment PIN_A3 -to BCK_TX[1]
+set_location_assignment PIN_A11 -to BCK_TX[2]
+set_location_assignment PIN_B1 -to BCK_TX[3]
+set_location_assignment PIN_C3 -to BCK_TX[4]
+set_location_assignment PIN_A7 -to BCK_TX[5]
+set_location_assignment PIN_D1 -to BCK_TX[6]
+set_location_assignment PIN_E3 -to BCK_TX[7]
+set_location_assignment PIN_F1 -to BCK_TX[8]
+set_location_assignment PIN_G3 -to BCK_TX[9]
+set_location_assignment PIN_J3 -to BCK_TX[10]
+set_location_assignment PIN_H1 -to BCK_TX[11]
+set_location_assignment PIN_L3 -to BCK_TX[12]
+set_location_assignment PIN_K1 -to BCK_TX[13]
+set_location_assignment PIN_N3 -to BCK_TX[14]
+set_location_assignment PIN_M1 -to BCK_TX[15]
+set_location_assignment PIN_R3 -to BCK_TX[16]
+set_location_assignment PIN_P1 -to BCK_TX[17]
+set_location_assignment PIN_U3 -to BCK_TX[18]
+set_location_assignment PIN_T1 -to BCK_TX[19]
+set_location_assignment PIN_W3 -to BCK_TX[20]
+set_location_assignment PIN_V1 -to BCK_TX[21]
+set_location_assignment PIN_AA3 -to BCK_TX[22]
+set_location_assignment PIN_Y1 -to BCK_TX[23]
+set_location_assignment PIN_AC3 -to BCK_TX[24]
+set_location_assignment PIN_AB1 -to BCK_TX[25]
+set_location_assignment PIN_AE3 -to BCK_TX[26]
+set_location_assignment PIN_AD1 -to BCK_TX[27]
+set_location_assignment PIN_AG3 -to BCK_TX[28]
+set_location_assignment PIN_AF1 -to BCK_TX[29]
+set_location_assignment PIN_AJ3 -to BCK_TX[30]
+set_location_assignment PIN_AH1 -to BCK_TX[31]
+set_location_assignment PIN_AL3 -to BCK_TX[32]
+set_location_assignment PIN_AK1 -to BCK_TX[33]
+set_location_assignment PIN_AN3 -to BCK_TX[34]
+set_location_assignment PIN_AM1 -to BCK_TX[35]
+set_location_assignment PIN_AR3 -to BCK_TX[36]
+set_location_assignment PIN_AP1 -to BCK_TX[37]
+set_location_assignment PIN_AU3 -to BCK_TX[38]
+set_location_assignment PIN_AT1 -to BCK_TX[39]
+set_location_assignment PIN_AW3 -to BCK_TX[40]
+set_location_assignment PIN_AV1 -to BCK_TX[41]
+set_location_assignment PIN_BB1 -to BCK_TX[42]
+set_location_assignment PIN_AY1 -to BCK_TX[43]
+set_location_assignment PIN_BD5 -to BCK_TX[44]
+set_location_assignment PIN_BA3 -to BCK_TX[45]
+set_location_assignment PIN_BC3 -to BCK_TX[46]
+set_location_assignment PIN_BD9 -to BCK_TX[47]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[4]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[4](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[5]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[5](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[6]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[6](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[7]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[7](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[8]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[8](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[9]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[9](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[10]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[10](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[11]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[11](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[12]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[12](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[13]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[13](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[14]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[14](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[15]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[15](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[16]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[16](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[17]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[17](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[18]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[18](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[19]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[19](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[20]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[20](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[21]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[21](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[22]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[22](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[23]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[23](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[24]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[24](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[25]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[25](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[26]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[26](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[27]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[27](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[28]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[28](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[29]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[29](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[30]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[30](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[31]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[31](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[32]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[32](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[33]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[33](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[34]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[34](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[35]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[35](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[36]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[36](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[37]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[37](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[38]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[38](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[39]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[39](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[40]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[40](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[41]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[41](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[42]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[42](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[43]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[43](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[44]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[44](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[45]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[45](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[46]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[46](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[47]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[47](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[4]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[4](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[5]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[5](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[6]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[6](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[7]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[7](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[8]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[8](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[9]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[9](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[10]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[10](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[11]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[11](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[12]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[12](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[13]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[13](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[14]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[14](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[15]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[15](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[16]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[16](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[17]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[17](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[18]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[18](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[19]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[19](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[20]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[20](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[21]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[21](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[22]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[22](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[23]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[23](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[24]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[24](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[25]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[25](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[26]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[26](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[27]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[27](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[28]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[28](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[29]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[29](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[30]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[30](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[31]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[31](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[32]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[32](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[33]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[33](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[34]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[34](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[35]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[35](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[36]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[36](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[37]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[37](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[38]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[38](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[39]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[39](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[40]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[40](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[41]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[41](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[42]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[42](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[43]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[43](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[44]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[44](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[45]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[45](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[46]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[46](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[47]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[47](n)"
+set_location_assignment PIN_V9 -to BCK_REF_CLK
+set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
+set_location_assignment PIN_AL32 -to CLKUSR
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[2]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[3]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[4]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[5]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[6]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[7]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[8]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[9]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[10]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[11]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[12]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[13]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.act_n
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.ba[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.ba[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.bg[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.bg[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[15]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_I_OU.ck[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_I_OU.ck[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.cke[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.cke[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.cs_n[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.cs_n[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.odt[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.odt[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.par
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[16]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_I_OU.a[14]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_OU.reset_n
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[2]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[3]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[4]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[5]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[6]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[7]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[8]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[9]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[10]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[11]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[12]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[13]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.act_n
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.ba[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.ba[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.bg[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.bg[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[15]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_II_OU.ck[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_II_OU.ck[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.cke[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.cke[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.cs_n[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.cs_n[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.odt[0]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.odt[1]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.par
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[16]
+set_instance_assignment -name IO_STANDARD SSTL-12 -to MB_II_OU.a[14]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_II_OU.reset_n
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[64]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[65]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[66]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[67]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[68]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[69]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[70]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[71]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[8]
+set_location_assignment PIN_AU29 -to MB_I_IO.dq[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[0]
+set_location_assignment PIN_BC28 -to MB_I_IO.dq[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[1]
+set_location_assignment PIN_AY29 -to MB_I_IO.dq[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[2]
+set_location_assignment PIN_BB28 -to MB_I_IO.dq[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[3]
+set_location_assignment PIN_BB29 -to MB_I_IO.dq[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[4]
+set_location_assignment PIN_AW29 -to MB_I_IO.dq[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[5]
+set_location_assignment PIN_BC27 -to MB_I_IO.dq[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[6]
+set_location_assignment PIN_BD29 -to MB_I_IO.dq[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[7]
+set_location_assignment PIN_AR28 -to MB_I_IO.dq[8]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[8]
+set_location_assignment PIN_AR29 -to MB_I_IO.dq[9]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[9]
+set_location_assignment PIN_AV27 -to MB_I_IO.dq[10]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[10]
+set_location_assignment PIN_AU28 -to MB_I_IO.dq[11]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[11]
+set_location_assignment PIN_AW27 -to MB_I_IO.dq[12]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[12]
+set_location_assignment PIN_AT28 -to MB_I_IO.dq[13]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[13]
+set_location_assignment PIN_AV28 -to MB_I_IO.dq[14]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[14]
+set_location_assignment PIN_AP27 -to MB_I_IO.dq[15]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[15]
+set_location_assignment PIN_BC24 -to MB_I_IO.dq[16]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[16]
+set_location_assignment PIN_BB24 -to MB_I_IO.dq[17]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[17]
+set_location_assignment PIN_BB23 -to MB_I_IO.dq[18]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[18]
+set_location_assignment PIN_AW22 -to MB_I_IO.dq[19]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[19]
+set_location_assignment PIN_BA23 -to MB_I_IO.dq[20]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[20]
+set_location_assignment PIN_BC23 -to MB_I_IO.dq[21]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[21]
+set_location_assignment PIN_AY23 -to MB_I_IO.dq[22]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[22]
+set_location_assignment PIN_AY24 -to MB_I_IO.dq[23]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[23]
+set_location_assignment PIN_AP22 -to MB_I_IO.dq[24]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[24]
+set_location_assignment PIN_AN23 -to MB_I_IO.dq[25]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[25]
+set_location_assignment PIN_AR23 -to MB_I_IO.dq[26]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[26]
+set_location_assignment PIN_AT23 -to MB_I_IO.dq[27]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[27]
+set_location_assignment PIN_AU23 -to MB_I_IO.dq[28]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[28]
+set_location_assignment PIN_AV23 -to MB_I_IO.dq[29]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[29]
+set_location_assignment PIN_AR24 -to MB_I_IO.dq[30]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[30]
+set_location_assignment PIN_AP24 -to MB_I_IO.dq[31]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[31]
+set_location_assignment PIN_AV12 -to MB_I_IO.dq[32]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[32]
+set_location_assignment PIN_AY13 -to MB_I_IO.dq[33]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[33]
+set_location_assignment PIN_BD14 -to MB_I_IO.dq[34]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[34]
+set_location_assignment PIN_AY12 -to MB_I_IO.dq[35]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[35]
+set_location_assignment PIN_BA13 -to MB_I_IO.dq[36]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[36]
+set_location_assignment PIN_BA12 -to MB_I_IO.dq[37]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[37]
+set_location_assignment PIN_AW12 -to MB_I_IO.dq[38]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[38]
+set_location_assignment PIN_BB13 -to MB_I_IO.dq[39]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[39]
+set_location_assignment PIN_AV13 -to MB_I_IO.dq[40]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[40]
+set_location_assignment PIN_AR13 -to MB_I_IO.dq[41]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[41]
+set_location_assignment PIN_AR15 -to MB_I_IO.dq[42]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[42]
+set_location_assignment PIN_AP15 -to MB_I_IO.dq[43]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[43]
+set_location_assignment PIN_AT15 -to MB_I_IO.dq[44]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[44]
+set_location_assignment PIN_AU14 -to MB_I_IO.dq[45]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[45]
+set_location_assignment PIN_AU15 -to MB_I_IO.dq[46]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[46]
+set_location_assignment PIN_AV14 -to MB_I_IO.dq[47]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[47]
+set_location_assignment PIN_AM13 -to MB_I_IO.dq[48]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[48]
+set_location_assignment PIN_AT13 -to MB_I_IO.dq[49]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[49]
+set_location_assignment PIN_AT12 -to MB_I_IO.dq[50]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[50]
+set_location_assignment PIN_AP14 -to MB_I_IO.dq[51]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[51]
+set_location_assignment PIN_AN13 -to MB_I_IO.dq[52]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[52]
+set_location_assignment PIN_AK13 -to MB_I_IO.dq[53]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[53]
+set_location_assignment PIN_AM12 -to MB_I_IO.dq[54]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[54]
+set_location_assignment PIN_AL13 -to MB_I_IO.dq[55]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[55]
+set_location_assignment PIN_AH13 -to MB_I_IO.dq[56]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[56]
+set_location_assignment PIN_AL15 -to MB_I_IO.dq[57]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[57]
+set_location_assignment PIN_AM15 -to MB_I_IO.dq[58]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[58]
+set_location_assignment PIN_AJ14 -to MB_I_IO.dq[59]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[59]
+set_location_assignment PIN_AJ12 -to MB_I_IO.dq[60]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[60]
+set_location_assignment PIN_AL16 -to MB_I_IO.dq[61]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[61]
+set_location_assignment PIN_AK12 -to MB_I_IO.dq[62]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[62]
+set_location_assignment PIN_AH14 -to MB_I_IO.dq[63]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[63]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[4]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[5]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[6]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[7]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[8]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[64]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[65]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[66]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[67]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[68]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[69]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[70]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[71]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[8]
+set_location_assignment PIN_A17 -to MB_II_IO.dq[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[0]
+set_location_assignment PIN_B16 -to MB_II_IO.dq[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[1]
+set_location_assignment PIN_D16 -to MB_II_IO.dq[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[2]
+set_location_assignment PIN_A18 -to MB_II_IO.dq[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[3]
+set_location_assignment PIN_B18 -to MB_II_IO.dq[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[4]
+set_location_assignment PIN_C17 -to MB_II_IO.dq[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[5]
+set_location_assignment PIN_E18 -to MB_II_IO.dq[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[6]
+set_location_assignment PIN_F18 -to MB_II_IO.dq[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[7]
+set_location_assignment PIN_R22 -to MB_II_IO.dq[8]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[8]
+set_location_assignment PIN_J20 -to MB_II_IO.dq[9]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[9]
+set_location_assignment PIN_L21 -to MB_II_IO.dq[10]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[10]
+set_location_assignment PIN_M20 -to MB_II_IO.dq[11]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[11]
+set_location_assignment PIN_J21 -to MB_II_IO.dq[12]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[12]
+set_location_assignment PIN_P21 -to MB_II_IO.dq[13]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[13]
+set_location_assignment PIN_R20 -to MB_II_IO.dq[14]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[14]
+set_location_assignment PIN_N21 -to MB_II_IO.dq[15]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[15]
+set_location_assignment PIN_L22 -to MB_II_IO.dq[16]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[16]
+set_location_assignment PIN_G20 -to MB_II_IO.dq[17]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[17]
+set_location_assignment PIN_H21 -to MB_II_IO.dq[18]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[18]
+set_location_assignment PIN_N22 -to MB_II_IO.dq[19]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[19]
+set_location_assignment PIN_P22 -to MB_II_IO.dq[20]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[20]
+set_location_assignment PIN_F20 -to MB_II_IO.dq[21]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[21]
+set_location_assignment PIN_G21 -to MB_II_IO.dq[22]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[22]
+set_location_assignment PIN_F21 -to MB_II_IO.dq[23]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[23]
+set_location_assignment PIN_E19 -to MB_II_IO.dq[24]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[24]
+set_location_assignment PIN_B20 -to MB_II_IO.dq[25]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[25]
+set_location_assignment PIN_A20 -to MB_II_IO.dq[26]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[26]
+set_location_assignment PIN_G19 -to MB_II_IO.dq[27]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[27]
+set_location_assignment PIN_D20 -to MB_II_IO.dq[28]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[28]
+set_location_assignment PIN_E20 -to MB_II_IO.dq[29]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[29]
+set_location_assignment PIN_D17 -to MB_II_IO.dq[30]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[30]
+set_location_assignment PIN_C18 -to MB_II_IO.dq[31]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[31]
+set_location_assignment PIN_F30 -to MB_II_IO.dq[32]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[32]
+set_location_assignment PIN_L30 -to MB_II_IO.dq[33]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[33]
+set_location_assignment PIN_M30 -to MB_II_IO.dq[34]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[34]
+set_location_assignment PIN_C31 -to MB_II_IO.dq[35]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[35]
+set_location_assignment PIN_D31 -to MB_II_IO.dq[36]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[36]
+set_location_assignment PIN_H31 -to MB_II_IO.dq[37]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[37]
+set_location_assignment PIN_J31 -to MB_II_IO.dq[38]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[38]
+set_location_assignment PIN_F31 -to MB_II_IO.dq[39]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[39]
+set_location_assignment PIN_P32 -to MB_II_IO.dq[40]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[40]
+set_location_assignment PIN_R30 -to MB_II_IO.dq[41]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[41]
+set_location_assignment PIN_U31 -to MB_II_IO.dq[42]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[42]
+set_location_assignment PIN_W31 -to MB_II_IO.dq[43]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[43]
+set_location_assignment PIN_P29 -to MB_II_IO.dq[44]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[44]
+set_location_assignment PIN_P30 -to MB_II_IO.dq[45]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[45]
+set_location_assignment PIN_V31 -to MB_II_IO.dq[46]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[46]
+set_location_assignment PIN_R29 -to MB_II_IO.dq[47]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[47]
+set_location_assignment PIN_M33 -to MB_II_IO.dq[48]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[48]
+set_location_assignment PIN_J33 -to MB_II_IO.dq[49]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[49]
+set_location_assignment PIN_H33 -to MB_II_IO.dq[50]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[50]
+set_location_assignment PIN_H32 -to MB_II_IO.dq[51]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[51]
+set_location_assignment PIN_J32 -to MB_II_IO.dq[52]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[52]
+set_location_assignment PIN_K33 -to MB_II_IO.dq[53]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[53]
+set_location_assignment PIN_K32 -to MB_II_IO.dq[54]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[54]
+set_location_assignment PIN_L32 -to MB_II_IO.dq[55]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[55]
+set_location_assignment PIN_AB33 -to MB_II_IO.dq[56]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[56]
+set_location_assignment PIN_AA32 -to MB_II_IO.dq[57]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[57]
+set_location_assignment PIN_W32 -to MB_II_IO.dq[58]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[58]
+set_location_assignment PIN_U33 -to MB_II_IO.dq[59]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[59]
+set_location_assignment PIN_Y33 -to MB_II_IO.dq[60]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[60]
+set_location_assignment PIN_AA33 -to MB_II_IO.dq[61]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[61]
+set_location_assignment PIN_V33 -to MB_II_IO.dq[62]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[62]
+set_location_assignment PIN_Y32 -to MB_II_IO.dq[63]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[63]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[4]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[5]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[6]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[7]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[8]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IN.alert_n
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_IN.oct_rzqin
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IN.alert_n
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_II_IN.oct_rzqin
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_REF_CLK
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_II_REF_CLK
+set_location_assignment PIN_B6 -to "BCK_TX[0](n)"
+set_location_assignment PIN_A4 -to "BCK_TX[1](n)"
+set_location_assignment PIN_A12 -to "BCK_TX[2](n)"
+set_location_assignment PIN_B2 -to "BCK_TX[3](n)"
+set_location_assignment PIN_C4 -to "BCK_TX[4](n)"
+set_location_assignment PIN_A8 -to "BCK_TX[5](n)"
+set_location_assignment PIN_D2 -to "BCK_TX[6](n)"
+set_location_assignment PIN_E4 -to "BCK_TX[7](n)"
+set_location_assignment PIN_F2 -to "BCK_TX[8](n)"
+set_location_assignment PIN_G4 -to "BCK_TX[9](n)"
+set_location_assignment PIN_J4 -to "BCK_TX[10](n)"
+set_location_assignment PIN_H2 -to "BCK_TX[11](n)"
+set_location_assignment PIN_L4 -to "BCK_TX[12](n)"
+set_location_assignment PIN_K2 -to "BCK_TX[13](n)"
+set_location_assignment PIN_N4 -to "BCK_TX[14](n)"
+set_location_assignment PIN_M2 -to "BCK_TX[15](n)"
+set_location_assignment PIN_R4 -to "BCK_TX[16](n)"
+set_location_assignment PIN_P2 -to "BCK_TX[17](n)"
+set_location_assignment PIN_U4 -to "BCK_TX[18](n)"
+set_location_assignment PIN_T2 -to "BCK_TX[19](n)"
+set_location_assignment PIN_W4 -to "BCK_TX[20](n)"
+set_location_assignment PIN_V2 -to "BCK_TX[21](n)"
+set_location_assignment PIN_AA4 -to "BCK_TX[22](n)"
+set_location_assignment PIN_Y2 -to "BCK_TX[23](n)"
+set_location_assignment PIN_AC4 -to "BCK_TX[24](n)"
+set_location_assignment PIN_AB2 -to "BCK_TX[25](n)"
+set_location_assignment PIN_AE4 -to "BCK_TX[26](n)"
+set_location_assignment PIN_AD2 -to "BCK_TX[27](n)"
+set_location_assignment PIN_AG4 -to "BCK_TX[28](n)"
+set_location_assignment PIN_AF2 -to "BCK_TX[29](n)"
+set_location_assignment PIN_AJ4 -to "BCK_TX[30](n)"
+set_location_assignment PIN_AH2 -to "BCK_TX[31](n)"
+set_location_assignment PIN_AL4 -to "BCK_TX[32](n)"
+set_location_assignment PIN_AK2 -to "BCK_TX[33](n)"
+set_location_assignment PIN_AN4 -to "BCK_TX[34](n)"
+set_location_assignment PIN_AM2 -to "BCK_TX[35](n)"
+set_location_assignment PIN_AR4 -to "BCK_TX[36](n)"
+set_location_assignment PIN_AP2 -to "BCK_TX[37](n)"
+set_location_assignment PIN_AU4 -to "BCK_TX[38](n)"
+set_location_assignment PIN_AT2 -to "BCK_TX[39](n)"
+set_location_assignment PIN_AW4 -to "BCK_TX[40](n)"
+set_location_assignment PIN_AV2 -to "BCK_TX[41](n)"
+set_location_assignment PIN_BB2 -to "BCK_TX[42](n)"
+set_location_assignment PIN_AY2 -to "BCK_TX[43](n)"
+set_location_assignment PIN_BD6 -to "BCK_TX[44](n)"
+set_location_assignment PIN_BA4 -to "BCK_TX[45](n)"
+set_location_assignment PIN_BC4 -to "BCK_TX[46](n)"
+set_location_assignment PIN_BD10 -to "BCK_TX[47](n)"
+#set_location_assignment PIN_AV18 -to "MB_I_OU.ck[0](n)"
+#set_location_assignment PIN_AU16 -to "MB_I_OU.ck[1](n)"
+#set_location_assignment PIN_AY28 -to "MB_I_IO.dqs[0](n)"
+#set_location_assignment PIN_AN28 -to "MB_I_IO.dqs[1](n)"
+#set_location_assignment PIN_AU24 -to "MB_I_IO.dqs[2](n)"
+#set_location_assignment PIN_AM24 -to "MB_I_IO.dqs[3](n)"
+#set_location_assignment PIN_BB14 -to "MB_I_IO.dqs[4](n)"
+#set_location_assignment PIN_AY14 -to "MB_I_IO.dqs[5](n)"
+#set_location_assignment PIN_AP12 -to "MB_I_IO.dqs[6](n)"
+#set_location_assignment PIN_AK14 -to "MB_I_IO.dqs[7](n)"
+#set_location_assignment PIN_BD22 -to "MB_I_IO.dqs[8](n)"
+#set_location_assignment PIN_M28 -to "MB_II_OU.ck[0](n)"
+#set_location_assignment PIN_J26 -to "MB_II_OU.ck[1](n)"
+#set_location_assignment PIN_E17 -to "MB_II_IO.dqs[0](n)"
+#set_location_assignment PIN_K20 -to "MB_II_IO.dqs[1](n)"
+#set_location_assignment PIN_H22 -to "MB_II_IO.dqs[2](n)"
+#set_location_assignment PIN_C19 -to "MB_II_IO.dqs[3](n)"
+#set_location_assignment PIN_M31 -to "MB_II_IO.dqs[4](n)"
+#set_location_assignment PIN_N31 -to "MB_II_IO.dqs[5](n)"
+#set_location_assignment PIN_P33 -to "MB_II_IO.dqs[6](n)"
+#set_location_assignment PIN_T32 -to "MB_II_IO.dqs[7](n)"
+#set_location_assignment PIN_B25 -to "MB_II_IO.dqs[8](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to "MB_I_OU.ck[0](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to "MB_I_OU.ck[1](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[0](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[1](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[2](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[3](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[4](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[5](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[6](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[7](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_I_IO.dqs[8](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to "MB_II_OU.ck[0](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to "MB_II_OU.ck[1](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[0](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[1](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[2](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[3](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[4](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[5](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[6](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[7](n)"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to "MB_II_IO.dqs[8](n)"
+set_location_assignment PIN_BA33 -to QSFP_LED[0]
+set_location_assignment PIN_BA30 -to QSFP_LED[1]
+set_location_assignment PIN_BB33 -to QSFP_LED[2]
+set_location_assignment PIN_AU33 -to QSFP_LED[3]
+set_location_assignment PIN_AV32 -to QSFP_LED[4]
+set_location_assignment PIN_AW30 -to QSFP_LED[5]
+set_location_assignment PIN_AP31 -to QSFP_LED[6]
+set_location_assignment PIN_AP30 -to QSFP_LED[7]
+set_location_assignment PIN_AT33 -to QSFP_LED[8]
+set_location_assignment PIN_AG32 -to QSFP_LED[9]
+set_location_assignment PIN_AF32 -to QSFP_LED[10]
+set_location_assignment PIN_AE32 -to QSFP_LED[11]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to CLKUSR
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[8]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[9]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[10]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[11]
+set_location_assignment PIN_AN38 -to QSFP_0_RX[0]
+set_location_assignment PIN_AN37 -to "QSFP_0_RX[0](n)"
+set_location_assignment PIN_AM40 -to QSFP_0_RX[1]
+set_location_assignment PIN_AM39 -to "QSFP_0_RX[1](n)"
+set_location_assignment PIN_AK40 -to QSFP_0_RX[2]
+set_location_assignment PIN_AK39 -to "QSFP_0_RX[2](n)"
+set_location_assignment PIN_AJ38 -to QSFP_0_RX[3]
+set_location_assignment PIN_AJ37 -to "QSFP_0_RX[3](n)"
+set_location_assignment PIN_AN42 -to QSFP_0_TX[0]
+set_location_assignment PIN_AN41 -to "QSFP_0_TX[0](n)"
+set_location_assignment PIN_AM44 -to QSFP_0_TX[1]
+set_location_assignment PIN_AM43 -to "QSFP_0_TX[1](n)"
+set_location_assignment PIN_AK44 -to QSFP_0_TX[2]
+set_location_assignment PIN_AK43 -to "QSFP_0_TX[2](n)"
+set_location_assignment PIN_AJ42 -to QSFP_0_TX[3]
+set_location_assignment PIN_AJ41 -to "QSFP_0_TX[3](n)"
+set_location_assignment PIN_AC38 -to QSFP_1_RX[0]
+set_location_assignment PIN_AC37 -to "QSFP_1_RX[0](n)"
+set_location_assignment PIN_AD40 -to QSFP_1_RX[1]
+set_location_assignment PIN_AD39 -to "QSFP_1_RX[1](n)"
+set_location_assignment PIN_AF40 -to QSFP_1_RX[2]
+set_location_assignment PIN_AF39 -to "QSFP_1_RX[2](n)"
+set_location_assignment PIN_AG38 -to QSFP_1_RX[3]
+set_location_assignment PIN_AG37 -to "QSFP_1_RX[3](n)"
+set_location_assignment PIN_AC42 -to QSFP_1_TX[0]
+set_location_assignment PIN_AC41 -to "QSFP_1_TX[0](n)"
+set_location_assignment PIN_AD44 -to QSFP_1_TX[1]
+set_location_assignment PIN_AD43 -to "QSFP_1_TX[1](n)"
+set_location_assignment PIN_AF44 -to QSFP_1_TX[2]
+set_location_assignment PIN_AF43 -to "QSFP_1_TX[2](n)"
+set_location_assignment PIN_AG42 -to QSFP_1_TX[3]
+set_location_assignment PIN_AG41 -to "QSFP_1_TX[3](n)"
+set_location_assignment PIN_AL38 -to QSFP_2_RX[0]
+set_location_assignment PIN_AL37 -to "QSFP_2_RX[0](n)"
+set_location_assignment PIN_AH40 -to QSFP_2_RX[1]
+set_location_assignment PIN_AH39 -to "QSFP_2_RX[1](n)"
+set_location_assignment PIN_AE38 -to QSFP_2_RX[2]
+set_location_assignment PIN_AE37 -to "QSFP_2_RX[2](n)"
+set_location_assignment PIN_AB40 -to QSFP_2_RX[3]
+set_location_assignment PIN_AB39 -to "QSFP_2_RX[3](n)"
+set_location_assignment PIN_AL42 -to QSFP_2_TX[0]
+set_location_assignment PIN_AL41 -to "QSFP_2_TX[0](n)"
+set_location_assignment PIN_AH44 -to QSFP_2_TX[1]
+set_location_assignment PIN_AH43 -to "QSFP_2_TX[1](n)"
+set_location_assignment PIN_AE42 -to QSFP_2_TX[2]
+set_location_assignment PIN_AE41 -to "QSFP_2_TX[2](n)"
+set_location_assignment PIN_AB44 -to QSFP_2_TX[3]
+set_location_assignment PIN_AB43 -to "QSFP_2_TX[3](n)"
+set_location_assignment PIN_W38 -to QSFP_3_RX[0]
+set_location_assignment PIN_W37 -to "QSFP_3_RX[0](n)"
+set_location_assignment PIN_T40 -to QSFP_3_RX[1]
+set_location_assignment PIN_T39 -to "QSFP_3_RX[1](n)"
+set_location_assignment PIN_N38 -to QSFP_3_RX[2]
+set_location_assignment PIN_N37 -to "QSFP_3_RX[2](n)"
+set_location_assignment PIN_K40 -to QSFP_3_RX[3]
+set_location_assignment PIN_K39 -to "QSFP_3_RX[3](n)"
+set_location_assignment PIN_W42 -to QSFP_3_TX[0]
+set_location_assignment PIN_W41 -to "QSFP_3_TX[0](n)"
+set_location_assignment PIN_T44 -to QSFP_3_TX[1]
+set_location_assignment PIN_T43 -to "QSFP_3_TX[1](n)"
+set_location_assignment PIN_N42 -to QSFP_3_TX[2]
+set_location_assignment PIN_N41 -to "QSFP_3_TX[2](n)"
+set_location_assignment PIN_K44 -to QSFP_3_TX[3]
+set_location_assignment PIN_K43 -to "QSFP_3_TX[3](n)"
+set_location_assignment PIN_AA38 -to QSFP_4_RX[0]
+set_location_assignment PIN_AA37 -to "QSFP_4_RX[0](n)"
+set_location_assignment PIN_Y40 -to QSFP_4_RX[1]
+set_location_assignment PIN_Y39 -to "QSFP_4_RX[1](n)"
+set_location_assignment PIN_V40 -to QSFP_4_RX[2]
+set_location_assignment PIN_V39 -to "QSFP_4_RX[2](n)"
+set_location_assignment PIN_U38 -to QSFP_4_RX[3]
+set_location_assignment PIN_U37 -to "QSFP_4_RX[3](n)"
+set_location_assignment PIN_AA42 -to QSFP_4_TX[0]
+set_location_assignment PIN_AA41 -to "QSFP_4_TX[0](n)"
+set_location_assignment PIN_Y44 -to QSFP_4_TX[1]
+set_location_assignment PIN_Y43 -to "QSFP_4_TX[1](n)"
+set_location_assignment PIN_V44 -to QSFP_4_TX[2]
+set_location_assignment PIN_V43 -to "QSFP_4_TX[2](n)"
+set_location_assignment PIN_U42 -to QSFP_4_TX[3]
+set_location_assignment PIN_U41 -to "QSFP_4_TX[3](n)"
+set_location_assignment PIN_L38 -to QSFP_5_RX[0]
+set_location_assignment PIN_L37 -to "QSFP_5_RX[0](n)"
+set_location_assignment PIN_M40 -to QSFP_5_RX[1]
+set_location_assignment PIN_M39 -to "QSFP_5_RX[1](n)"
+set_location_assignment PIN_P40 -to QSFP_5_RX[2]
+set_location_assignment PIN_P39 -to "QSFP_5_RX[2](n)"
+set_location_assignment PIN_R38 -to QSFP_5_RX[3]
+set_location_assignment PIN_R37 -to "QSFP_5_RX[3](n)"
+set_location_assignment PIN_L42 -to QSFP_5_TX[0]
+set_location_assignment PIN_L41 -to "QSFP_5_TX[0](n)"
+set_location_assignment PIN_M44 -to QSFP_5_TX[1]
+set_location_assignment PIN_M43 -to "QSFP_5_TX[1](n)"
+set_location_assignment PIN_P44 -to QSFP_5_TX[2]
+set_location_assignment PIN_P43 -to "QSFP_5_TX[2](n)"
+set_location_assignment PIN_R42 -to QSFP_5_TX[3]
+set_location_assignment PIN_R41 -to "QSFP_5_TX[3](n)"
+set_location_assignment PIN_AP40 -to RING_0_RX[0]
+set_location_assignment PIN_AP39 -to "RING_0_RX[0](n)"
+set_location_assignment PIN_AR38 -to RING_0_RX[1]
+set_location_assignment PIN_AR37 -to "RING_0_RX[1](n)"
+set_location_assignment PIN_AT40 -to RING_0_RX[2]
+set_location_assignment PIN_AT39 -to "RING_0_RX[2](n)"
+set_location_assignment PIN_AU38 -to RING_0_RX[3]
+set_location_assignment PIN_AU37 -to "RING_0_RX[3](n)"
+set_location_assignment PIN_AV40 -to RING_0_RX[4]
+set_location_assignment PIN_AV39 -to "RING_0_RX[4](n)"
+set_location_assignment PIN_AW38 -to RING_0_RX[5]
+set_location_assignment PIN_AW37 -to "RING_0_RX[5](n)"
+set_location_assignment PIN_AY40 -to RING_0_RX[6]
+set_location_assignment PIN_AY39 -to "RING_0_RX[6](n)"
+set_location_assignment PIN_BA38 -to RING_0_RX[7]
+set_location_assignment PIN_BA37 -to "RING_0_RX[7](n)"
+set_location_assignment PIN_BB40 -to RING_0_RX[8]
+set_location_assignment PIN_BB39 -to "RING_0_RX[8](n)"
+set_location_assignment PIN_BC38 -to RING_0_RX[9]
+set_location_assignment PIN_BC37 -to "RING_0_RX[9](n)"
+set_location_assignment PIN_AY36 -to RING_0_RX[10]
+set_location_assignment PIN_AY35 -to "RING_0_RX[10](n)"
+set_location_assignment PIN_BB36 -to RING_0_RX[11]
+set_location_assignment PIN_BB35 -to "RING_0_RX[11](n)"
+set_location_assignment PIN_AP44 -to RING_0_TX[0]
+set_location_assignment PIN_AP43 -to "RING_0_TX[0](n)"
+set_location_assignment PIN_AR42 -to RING_0_TX[1]
+set_location_assignment PIN_AR41 -to "RING_0_TX[1](n)"
+set_location_assignment PIN_AT44 -to RING_0_TX[2]
+set_location_assignment PIN_AT43 -to "RING_0_TX[2](n)"
+set_location_assignment PIN_AU42 -to RING_0_TX[3]
+set_location_assignment PIN_AU41 -to "RING_0_TX[3](n)"
+set_location_assignment PIN_AV44 -to RING_0_TX[4]
+set_location_assignment PIN_AV43 -to "RING_0_TX[4](n)"
+set_location_assignment PIN_AW42 -to RING_0_TX[5]
+set_location_assignment PIN_AW41 -to "RING_0_TX[5](n)"
+set_location_assignment PIN_AY44 -to RING_0_TX[6]
+set_location_assignment PIN_AY43 -to "RING_0_TX[6](n)"
+set_location_assignment PIN_BB44 -to RING_0_TX[7]
+set_location_assignment PIN_BB43 -to "RING_0_TX[7](n)"
+set_location_assignment PIN_BA42 -to RING_0_TX[8]
+set_location_assignment PIN_BA41 -to "RING_0_TX[8](n)"
+set_location_assignment PIN_BD40 -to RING_0_TX[9]
+set_location_assignment PIN_BD39 -to "RING_0_TX[9](n)"
+set_location_assignment PIN_BC42 -to RING_0_TX[10]
+set_location_assignment PIN_BC41 -to "RING_0_TX[10](n)"
+set_location_assignment PIN_BD36 -to RING_0_TX[11]
+set_location_assignment PIN_BD35 -to "RING_0_TX[11](n)"
+set_location_assignment PIN_H40 -to RING_1_RX[0]
+set_location_assignment PIN_H39 -to "RING_1_RX[0](n)"
+set_location_assignment PIN_J38 -to RING_1_RX[1]
+set_location_assignment PIN_J37 -to "RING_1_RX[1](n)"
+set_location_assignment PIN_F40 -to RING_1_RX[2]
+set_location_assignment PIN_F39 -to "RING_1_RX[2](n)"
+set_location_assignment PIN_G38 -to RING_1_RX[3]
+set_location_assignment PIN_G37 -to "RING_1_RX[3](n)"
+set_location_assignment PIN_D40 -to RING_1_RX[4]
+set_location_assignment PIN_D39 -to "RING_1_RX[4](n)"
+set_location_assignment PIN_E38 -to RING_1_RX[5]
+set_location_assignment PIN_E37 -to "RING_1_RX[5](n)"
+set_location_assignment PIN_F36 -to RING_1_RX[6]
+set_location_assignment PIN_F35 -to "RING_1_RX[6](n)"
+set_location_assignment PIN_C38 -to RING_1_RX[7]
+set_location_assignment PIN_C37 -to "RING_1_RX[7](n)"
+set_location_assignment PIN_B36 -to RING_1_RX[8]
+set_location_assignment PIN_B35 -to "RING_1_RX[8](n)"
+set_location_assignment PIN_D36 -to RING_1_RX[9]
+set_location_assignment PIN_D35 -to "RING_1_RX[9](n)"
+set_location_assignment PIN_E34 -to RING_1_RX[10]
+set_location_assignment PIN_E33 -to "RING_1_RX[10](n)"
+set_location_assignment PIN_C34 -to RING_1_RX[11]
+set_location_assignment PIN_C33 -to "RING_1_RX[11](n)"
+set_location_assignment PIN_H44 -to RING_1_TX[0]
+set_location_assignment PIN_H43 -to "RING_1_TX[0](n)"
+set_location_assignment PIN_J42 -to RING_1_TX[1]
+set_location_assignment PIN_J41 -to "RING_1_TX[1](n)"
+set_location_assignment PIN_G42 -to RING_1_TX[2]
+set_location_assignment PIN_G41 -to "RING_1_TX[2](n)"
+set_location_assignment PIN_F44 -to RING_1_TX[3]
+set_location_assignment PIN_F43 -to "RING_1_TX[3](n)"
+set_location_assignment PIN_E42 -to RING_1_TX[4]
+set_location_assignment PIN_E41 -to "RING_1_TX[4](n)"
+set_location_assignment PIN_D44 -to RING_1_TX[5]
+set_location_assignment PIN_D43 -to "RING_1_TX[5](n)"
+set_location_assignment PIN_B44 -to RING_1_TX[6]
+set_location_assignment PIN_B43 -to "RING_1_TX[6](n)"
+set_location_assignment PIN_C42 -to RING_1_TX[7]
+set_location_assignment PIN_C41 -to "RING_1_TX[7](n)"
+set_location_assignment PIN_B40 -to RING_1_TX[8]
+set_location_assignment PIN_B39 -to "RING_1_TX[8](n)"
+set_location_assignment PIN_A42 -to RING_1_TX[9]
+set_location_assignment PIN_A41 -to "RING_1_TX[9](n)"
+set_location_assignment PIN_A38 -to RING_1_TX[10]
+set_location_assignment PIN_A37 -to "RING_1_TX[10](n)"
+set_location_assignment PIN_A34 -to RING_1_TX[11]
+set_location_assignment PIN_A33 -to "RING_1_TX[11](n)"
+set_location_assignment PIN_H17 -to S10_ETH_CLK
+set_location_assignment PIN_AE13 -to JESD204B_SYNC[0]
+set_location_assignment PIN_AD13 -to JESD204B_SYNC[1]
+set_location_assignment PIN_AC13 -to JESD204B_SYNC[2]
+set_location_assignment PIN_AA13 -to JESD204B_SYNC[3]
+set_location_assignment PIN_AA12 -to JESD204B_SYNC[4]
+set_location_assignment PIN_V12 -to JESD204B_SYNC[5]
+set_location_assignment PIN_U14 -to JESD204B_SYNC[6]
+set_location_assignment PIN_U12 -to JESD204B_SYNC[7]
+set_location_assignment PIN_T12 -to JESD204B_SYNC[8]
+set_location_assignment PIN_R14 -to JESD204B_SYNC[9]
+set_location_assignment PIN_R13 -to JESD204B_SYNC[10]
+set_location_assignment PIN_P12 -to JESD204B_SYNC[11]
+set_location_assignment PIN_Y13 -to JESD204B_SYSREF
+set_location_assignment PIN_Y12 -to "JESD204B_SYSREF(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "CLK(n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[4]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[4](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[5]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[5](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[6]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[6](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[7]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[7](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[8]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[8](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[9]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[9](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[10]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[10](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[11]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[11](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[4]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[4](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[5]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[5](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[6]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[6](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[7]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[7](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[8]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[8](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[9]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[9](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[10]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[10](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[11]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[11](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[4]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[4](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[5]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[5](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[6]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[6](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[7]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[7](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[8]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[8](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[9]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[9](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[10]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[10](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[11]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[11](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[0](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[1](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[2](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[3](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[4]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[4](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[5]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[5](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[6]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[6](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[7]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[7](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[8]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[8](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[9]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[9](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[10]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[10](n)"
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[11]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[11](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to JESD204B_SYSREF
+set_instance_assignment -name IO_STANDARD LVDS -to "JESD204B_SYSREF(n)"
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/unb2c_test_pinning.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/unb2c_test_pinning.vhd
index cd2d07767b3de98dd7e1475d84b03f29a81826e5..d889293a3cc01ed3f802c87bab4e68779a8a59ac 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/unb2c_test_pinning.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/unb2c_test_pinning.vhd
@@ -102,9 +102,6 @@ ENTITY unb2c_test_pinning IS
     QSFP_5_RX    : IN    STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
     QSFP_5_TX    : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
 
-    QSFP_SDA     : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.i2c_w-1 downto 0);
-    QSFP_SCL     : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.i2c_w-1 downto 0);
-
     -- SO-DIMM Memory Bank I
     MB_I_IN      : IN    t_tech_ddr4_phy_in;
     MB_I_IO      : INOUT t_tech_ddr4_phy_io;
@@ -198,9 +195,6 @@ BEGIN
     QSFP_5_RX    => QSFP_5_RX,
     QSFP_5_TX    => QSFP_5_TX,
 
-    QSFP_SDA     => QSFP_SDA,
-    QSFP_SCL     => QSFP_SCL,
-
     -- SO-DIMM Memory Bank I
     MB_I_IN      => MB_I_IN,
     MB_I_IO      => MB_I_IO,
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning_jesd204b/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning_jesd204b/hdllib.cfg
index f4370c323c595cfa4aac18289ba7c08d86216d96..2fa602c2a57a8a829714b805166a573d1017b347 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning_jesd204b/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning_jesd204b/hdllib.cfg
@@ -2,27 +2,27 @@ hdl_lib_name = unb2c_test_pinning_jesd204b
 hdl_library_clause_name = unb2c_test_pinning_jesd204b_lib
 hdl_lib_uses_synth = common mm technology unb2c_board unb2c_test
 hdl_lib_uses_sim = 
-hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_technology = ip_arria10_e2sg
 hdl_lib_include_ip = 
                      # Comment all IP that is not used in this design
                      # 10GbE
-                     ip_arria10_e1sg_mac_10g
-                     ip_arria10_e1sg_pll_xgmii_mac_clocks
-                     ip_arria10_e1sg_transceiver_pll_10g
+                     ip_arria10_e2sg_mac_10g
+                     ip_arria10_e2sg_pll_xgmii_mac_clocks
+                     ip_arria10_e2sg_transceiver_pll_10g
                      
-                     ip_arria10_e1sg_phy_10gbase_r
-                     ip_arria10_e1sg_phy_10gbase_r_4
-                     ip_arria10_e1sg_phy_10gbase_r_12
-                     ip_arria10_e1sg_phy_10gbase_r_24
-                     ip_arria10_e1sg_phy_10gbase_r_48
+                     ip_arria10_e2sg_phy_10gbase_r
+                     ip_arria10_e2sg_phy_10gbase_r_4
+                     ip_arria10_e2sg_phy_10gbase_r_12
+                     ip_arria10_e2sg_phy_10gbase_r_24
+                     ip_arria10_e2sg_phy_10gbase_r_48
                      
-                     ip_arria10_e1sg_transceiver_reset_controller_1
-                     ip_arria10_e1sg_transceiver_reset_controller_4
-                     ip_arria10_e1sg_transceiver_reset_controller_12
-                     ip_arria10_e1sg_transceiver_reset_controller_24
-                     ip_arria10_e1sg_transceiver_reset_controller_48
+                     ip_arria10_e2sg_transceiver_reset_controller_1
+                     ip_arria10_e2sg_transceiver_reset_controller_4
+                     ip_arria10_e2sg_transceiver_reset_controller_12
+                     ip_arria10_e2sg_transceiver_reset_controller_24
+                     ip_arria10_e2sg_transceiver_reset_controller_48
 
-                     ip_arria10_e1sg_ddr4_8g_1600
+                     ip_arria10_e2sg_ddr4_8g_1600
 synth_files =
     unb2c_test_pinning_jesd204b.vhd
 
@@ -43,7 +43,8 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+#    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA_JESD.qsf
 
 quartus_sdc_pre_files =
     quartus/unb2c_test_pinning_jesd204b.sdc
@@ -52,7 +53,7 @@ quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
-    quartus/unb2c_test_pinning_jesd204b_pins.tcl
+#    quartus/unb2c_test_pinning_jesd204b_pins.tcl
 
 quartus_vhdl_files = 
 
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning_jesd204b/unb2c_test_pinning_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning_jesd204b/unb2c_test_pinning_jesd204b.vhd
index c3a5e32986f1fca1a67aca57ee0b21f9c4604b1b..efb4a7eda28b0d092d713c7e94cbdcbfca513576 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning_jesd204b/unb2c_test_pinning_jesd204b.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning_jesd204b/unb2c_test_pinning_jesd204b.vhd
@@ -72,7 +72,8 @@ ENTITY unb2c_test_pinning_jesd204b IS
     MB_II_REF_CLK : IN   STD_LOGIC;  -- Reference clock for MB_II
     
     -- back transceivers
-    BCK_RX       : IN    STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
+    BCK_RX       : IN    STD_LOGIC_VECTOR((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus)-1 downto 0);
+--    BCK_RX       : IN    STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
     --BCK_TX       : OUT   STD_LOGIC_VECTOR((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus)-1 downto 0);
  
     -- jesd204b syncronization signals
@@ -102,9 +103,6 @@ ENTITY unb2c_test_pinning_jesd204b IS
     QSFP_5_RX    : IN    STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
     QSFP_5_TX    : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
 
-    QSFP_SDA     : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.i2c_w-1 downto 0);
-    QSFP_SCL     : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.i2c_w-1 downto 0);
-
     -- SO-DIMM Memory Bank I
     MB_I_IN      : IN    t_tech_ddr4_phy_in;
     MB_I_IO      : INOUT t_tech_ddr4_phy_io;
@@ -122,12 +120,14 @@ END unb2c_test_pinning_jesd204b;
 
 ARCHITECTURE str OF unb2c_test_pinning_jesd204b IS
 
-    SIGNAL BCK_RX_INTERNAL  : STD_LOGIC_VECTOR((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus)-1 downto 0) := (others => '0');
+  SIGNAL BCK_RX_INTERNAL  : STD_LOGIC_VECTOR((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus)-1 downto 0) := (others => '0'); 
 
 BEGIN
 
+
+
   gen_bck_to_jesd204b : FOR i IN 0 TO (c_unb2c_board_tr_jesd204b.nof_bus * c_unb2c_board_tr_jesd204b.bus_w)-1 GENERATE
-    BCK_RX_INTERNAL(i) <= BCK_RX(0);
+    BCK_RX_INTERNAL(i) <= BCK_RX(36+i);
   END GENERATE;
 
   u_revision : ENTITY unb2c_test_lib.unb2c_test
@@ -205,9 +205,6 @@ BEGIN
     QSFP_5_RX    => QSFP_5_RX,
     QSFP_5_TX    => QSFP_5_TX,
 
-    QSFP_SDA     => QSFP_SDA,
-    QSFP_SCL     => QSFP_SCL,
-
     -- SO-DIMM Memory Bank I
     MB_I_IN      => MB_I_IN,
     MB_I_IO      => MB_I_IO,
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index 2a450d842d4d3083261f139efcd6a8a5ed485b53..c1d4ad2e0dd483e068fc1d4f3aea48b45a6e51d8 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -115,10 +115,6 @@ ENTITY unb2c_test IS
     QSFP_5_RX    : IN    STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
     QSFP_5_TX    : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
 
-    QSFP_SDA     : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.i2c_w-1 downto 0);
-    QSFP_SCL     : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.i2c_w-1 downto 0);
-    QSFP_RST     : INOUT STD_LOGIC;
-
     -- SO-DIMM Memory Bank I
     MB_I_IN      : IN    t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
     MB_I_IO      : INOUT t_tech_ddr4_phy_io;
@@ -1029,10 +1025,6 @@ BEGIN
       QSFP_RX    => i_QSFP_RX,
       QSFP_TX    => i_QSFP_TX,
 
-      --QSFP_SDA   => QSFP_SDA,
-      --QSFP_SCL   => QSFP_SCL,
-      --QSFP_RST   => QSFP_RST,
-
       QSFP_LED   => QSFP_LED
     );
 
@@ -1124,17 +1116,20 @@ BEGIN
       u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b 
       GENERIC MAP(
         g_sim                => g_sim,                
-        g_sim_level          => 1,          
-        g_nof_channels       => c_nof_jesd204b    
+        g_technology         => g_technology,
+        g_nof_streams        => c_nof_jesd204b    
       )
       PORT MAP(
         jesd204b_refclk      => BCK_REF_CLK,   
         jesd204b_sysref      => JESD204B_SYSREF,   
         jesd204b_sync_n_arr  => JESD204B_SYNC,   
-    
-        rx_src_out_arr       => jesd204b_rx_src_out_arr,          
-        jesd204b_frame_clk   => jesd204b_frame_clk,          
-    
+ 
+        -- Data to fabric
+        rx_sosi_arr          => jesd204b_rx_src_out_arr,        -- Parallel data out to fabric
+        rx_clk               => jesd204b_frame_clk,             -- Exported data clock (frame clock) to fabric
+        rx_rst               => open,                           -- Exported reset on rx_clk domain
+        rx_sysref            => open,                           -- Exported copy of sysref
+   
         -- MM
         mm_clk               => mm_clk,           
         mm_rst               => mm_rst,           
diff --git a/libraries/dsp/si/hdllib.cfg b/libraries/dsp/si/hdllib.cfg
index b9c5b293a1aec62f6d333dd08119ea202fc3ca15..1780c0edfe90edffed9a60da94d0dfc5109946fb 100755
--- a/libraries/dsp/si/hdllib.cfg
+++ b/libraries/dsp/si/hdllib.cfg
@@ -6,6 +6,7 @@ hdl_lib_technology =
 
 synth_files = 
     src/vhdl/si.vhd 
+    src/vhdl/si_arr.vhd 
  
 test_bench_files = 
     tb/vhdl/tb_si.vhd 
diff --git a/libraries/dsp/si/src/vhdl/si_arr.vhd b/libraries/dsp/si/src/vhdl/si_arr.vhd
new file mode 100755
index 0000000000000000000000000000000000000000..faa86d371483f52f1a93f3903abc1393465f46e1
--- /dev/null
+++ b/libraries/dsp/si/src/vhdl/si_arr.vhd
@@ -0,0 +1,97 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Array wrapper for Spectral inversion.
+-- Description:
+-- . Adds array support and Memory Mapped enable interface to si.vhd. 
+-- Remark:
+-- . See si.vhd for more detail.
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY si_arr IS
+  GENERIC (
+    g_nof_streams : NATURAL := 1;
+    g_pipeline    : NATURAL := 1;   -- 0 for wires, 1 for output pipeline
+    g_dat_w       : NATURAL := 18
+  );
+  PORT (
+    in_sosi_arr  : IN  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+    out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+    
+    reg_si_mosi  : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_si_miso  : OUT t_mem_miso;    
+
+    mm_rst       : IN  STD_LOGIC;
+    mm_clk       : IN  STD_LOGIC;
+    dp_clk       : IN  STD_LOGIC;
+    dp_rst       : IN  STD_LOGIC
+  );
+END si_arr;
+
+ARCHITECTURE str OF si_arr IS
+
+  CONSTANT c_si_mem_reg : t_c_mem := (c_mem_reg_rd_latency, 1, 1, 1, '0');
+
+  SIGNAL reg_si_en : STD_LOGIC_VECTOR(c_si_mem_reg.dat_w*c_si_mem_reg.nof_dat-1 DOWNTO 0);
+
+BEGIN
+
+  u_mms_common_reg : ENTITY common_lib.mms_common_reg
+  GENERIC MAP (
+    g_mm_reg       => c_si_mem_reg
+  )
+  PORT MAP (
+    mm_rst         => mm_rst,
+    mm_clk         => mm_clk,
+    st_rst         => dp_rst,
+    st_clk         => dp_clk,
+
+    reg_mosi       => reg_si_mosi,
+    reg_miso       => reg_si_miso,
+
+    in_reg         => reg_si_en,
+    out_reg        => reg_si_en
+  );
+
+  gen_nof_streams : FOR I in 0 TO g_nof_streams-1 GENERATE
+    u_si : ENTITY work.si
+    GENERIC MAP (
+      g_pipeline => g_pipeline,
+      g_dat_w    => g_dat_w
+    )
+    PORT MAP (
+      in_sosi   => in_sosi_arr(I), 
+      out_sosi  => out_sosi_arr(I), 
+      si_en     => reg_si_en(0), 
+      clk       => dp_clk,
+      rst       => dp_rst
+    );
+  END GENERATE;
+
+END str;
diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index 4efc3d6cbb312445443778922aad88cab0ec13e8..46c9db4f40ae8287c6fb472ea9d3c3b0e5112b05 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = tech_10gbase_r
 hdl_library_clause_name = tech_10gbase_r_lib
 hdl_lib_uses_synth = technology common tech_pll tech_transceiver
-hdl_lib_uses_ip = ip_arria10_phy_10gbase_r                    ip_arria10_e3sge3_phy_10gbase_r                             
+hdl_lib_uses_ip = ip_arria10_phy_10gbase_r  ip_arria10_e3sge3_phy_10gbase_r                             
                   ip_arria10_e1sg_phy_10gbase_r               ip_arria10_e2sg_phy_10gbase_r
                   ip_arria10_phy_10gbase_r_4                  ip_arria10_e3sge3_phy_10gbase_r_4                  ip_arria10_e1sg_phy_10gbase_r_4             ip_arria10_e2sg_phy_10gbase_r_4
                   ip_arria10_phy_10gbase_r_12                 ip_arria10_e3sge3_phy_10gbase_r_12                 ip_arria10_e1sg_phy_10gbase_r_12            ip_arria10_e2sg_phy_10gbase_r_12
@@ -53,18 +53,18 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e1sg_transceiver_reset_controller_4     ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180
     ip_arria10_e1sg_transceiver_reset_controller_12    ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180
     ip_arria10_e2sg_transceiver_reset_controller_24    ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180
-    ip_arria10_e2sg_phy_10gbase_r                      ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_194
-    ip_arria10_e2sg_phy_10gbase_r_3                    ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_194
-    ip_arria10_e2sg_phy_10gbase_r_4                    ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_194
-    ip_arria10_e2sg_phy_10gbase_r_12                   ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_194
-    ip_arria10_e2sg_phy_10gbase_r_24                   ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_194
-    ip_arria10_e2sg_phy_10gbase_r_48                   ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_194
-    ip_arria10_e2sg_transceiver_pll_10g                ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_194
-    ip_arria10_e2sg_transceiver_reset_controller_1     ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_194
-    ip_arria10_e2sg_transceiver_reset_controller_3     ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_194
-    ip_arria10_e2sg_transceiver_reset_controller_4     ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_194
-    ip_arria10_e2sg_transceiver_reset_controller_12    ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_194
-    ip_arria10_e2sg_transceiver_reset_controller_24    ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_194
+    ip_arria10_e2sg_phy_10gbase_r                      ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_194
+    ip_arria10_e2sg_phy_10gbase_r_3                    ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_194
+    ip_arria10_e2sg_phy_10gbase_r_4                    ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_194
+    ip_arria10_e2sg_phy_10gbase_r_12                   ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_194
+    ip_arria10_e2sg_phy_10gbase_r_24                   ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_194
+    ip_arria10_e2sg_phy_10gbase_r_48                   ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_194
+    ip_arria10_e2sg_transceiver_pll_10g                ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_194
+    ip_arria10_e2sg_transceiver_reset_controller_1     ip_arria10_e2sg_transceiver_reset_controller_1_altera_xcvr_reset_control_194
+    ip_arria10_e2sg_transceiver_reset_controller_3     ip_arria10_e2sg_transceiver_reset_controller_3_altera_xcvr_reset_control_194
+    ip_arria10_e2sg_transceiver_reset_controller_4     ip_arria10_e2sg_transceiver_reset_controller_4_altera_xcvr_reset_control_194
+    ip_arria10_e2sg_transceiver_reset_controller_12    ip_arria10_e2sg_transceiver_reset_controller_12_altera_xcvr_reset_control_194
+    ip_arria10_e2sg_transceiver_reset_controller_24    ip_arria10_e2sg_transceiver_reset_controller_24_altera_xcvr_reset_control_194
 
 synth_files =
     sim_10gbase_r.vhd
diff --git a/libraries/technology/flash/hdllib.cfg b/libraries/technology/flash/hdllib.cfg
index 815d88851c3e84e7370e503ef7424b3fbbb59327..8c7d702d6c8ab0d3f8861dc05499f24ca4c55c2e 100644
--- a/libraries/technology/flash/hdllib.cfg
+++ b/libraries/technology/flash/hdllib.cfg
@@ -20,8 +20,8 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update_altera_remote_update_151
     ip_arria10_e1sg_asmi_parallel   ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180
     ip_arria10_e1sg_remote_update   ip_arria10_e1sg_remote_update_altera_remote_update_180
-    ip_arria10_e2sg_asmi_parallel   ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_194
-    ip_arria10_e2sg_remote_update   ip_arria10_e1sg_remote_update_altera_remote_update_194
+    ip_arria10_e2sg_asmi_parallel   ip_arria10_e2sg_asmi_parallel_altera_asmi_parallel_194
+    ip_arria10_e2sg_remote_update   ip_arria10_e2sg_remote_update_altera_remote_update_194
 
     
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f2cbafc14d3dcb32f2749cc590357ec1409ebe50
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/compile_ip.tcl
@@ -0,0 +1,149 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mac_10g/sim"
+
+vmap alt_em10g32_194 ./work/
+
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/alt_em10g32.v"                                                                         -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/alt_em10g32unit.v"                                                                     -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_clk_rst.v"                                                             -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_clock_crosser.v"                                                       -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_crc32.v"                                                               -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_crc32_gf_mult32_kc.v"                                                  -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_creg_map.v"                                                            -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_creg_top.v"                                                            -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_frm_decoder.v"                                                         -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v"                                                -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_pipeline_base.v"                                                       -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_reset_synchronizer.v"                                                  -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rr_clock_crosser.v"                                                    -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rst_cnt.v"                                                             -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v"                                           -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_fctl_overflow.v"                                                    -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_fctl_preamble.v"                                                    -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_frm_control.v"                                                      -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_pfc_flow_control.v"                                                 -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_pfc_pause_conversion.v"                                             -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_pkt_backpressure_control.v"                                         -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b.v"                                                       -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b_top.v"                                                   -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_rs_gmii_mii.v"                                                      -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_rs_layer.v"                                                         -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii.v"                                                         -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_status_aligner.v"                                                   -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_top.v"                                                              -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_stat_mem.v"                                                            -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_stat_reg.v"                                                            -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_data_frm_gen.v"                                                     -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_srcaddr_inserter.v"                                                 -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_err_aligner.v"                                                      -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_flow_control.v"                                                     -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_frm_arbiter.v"                                                      -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_frm_muxer.v"                                                        -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_pause_beat_conversion.v"                                            -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_pause_frm_gen.v"                                                    -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_pause_req.v"                                                        -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_pfc_frm_gen.v"                                                      -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rr_buffer.v"                                                           -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b.v"                                                       -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b_top.v"                                                   -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_rs_layer.v"                                                         -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer.v"                                                   -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_sc_fifo.v"                                                             -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_top.v"                                                              -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder.v"                                                     -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder_dfa.v"                                                 -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder.v"                                                     -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder_dfa.v"                                                 -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v"                                              -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v"                                              -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v"                  -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v"                  -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v"                -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v"                -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v"                             -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/alt_em10g32_vldpkt_rddly.v"                      -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v"                           -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v"                           -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v"                              -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser.v"                   -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser_sync.v"              -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v"            -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v"         -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v"         -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_32_to_64_xgmii_conversion.v"  -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_64_to_32_xgmii_conversion.v"  -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_32_to_64_adapter.v"    -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_64_to_32_adapter.v"    -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_data_format_adapter.v" -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_altsyncram_bundle.v"                                                   -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_altsyncram.v"                                                          -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_lat_calc.v"                                             -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_hecc.v"                                                 -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_secc.v"                                                 -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo.v"                                                      -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_hecc.v"                                                 -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_secc.v"                                                 -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_ecc_dec_18_12.v"                                                       -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_ecc_dec_39_32.v"                                                       -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_ecc_enc_12_18.v"                                                       -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_ecc_enc_32_39.v"                                                       -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer_ultra.v"                                             -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii_ultra.v"                                                   -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_avst_to_gmii_if.v"                                                     -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_gmii_to_avst_if.v"                                                     -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_gmii_tsu.v"                                                            -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_gmii16b_tsu.v"                                                         -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_lpm_mult.v"                                                            -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_ptp_aligner.v"                                                      -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_ptp_detector.v"                                                     -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_rx_ptp_top.v"                                                          -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii_crc_inserter.v"                                                -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii16b_crc_inserter.v"                                             -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii_ptp_inserter.v"                                                -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter.v"                                             -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter_1g2p5g10g.v"                                   -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_ptp_processor.v"                                                    -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_ptp_top.v"                                                          -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_xgmii_crc_inserter.v"                                               -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v"                                               -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_xgmii_tsu.v"                                                           -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_crc328generator.v"                                                     -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_crc32ctl8.v"                                                           -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_crc32galois8.v"                                                        -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_gmii_crc_inserter.v"                                                   -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_gmii16b_crc_inserter.v"                                                -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/mentor/rtl/alt_em10g32_gmii16b_crc32.v"                                                       -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/alt_em10g32_avalon_dc_fifo.v"                                                                 -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/alt_em10g32_dcfifo_synchronizer_bundle.v"                                                     -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/alt_em10g32_std_synchronizer.v"                                                               -work alt_em10g32_194        
+  vlog  "$IP_DIR/../alt_em10g32_194/sim/altera_std_synchronizer_nocut.v"                                                              -work alt_em10g32_194                                                                                            
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..afa218082e1b446568c2fcd7d0cee26cd3e6cfb2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/hdllib.cfg
@@ -0,0 +1,20 @@
+hdl_lib_name = ip_arria10_e2sg_alt_em10g32_194
+hdl_library_clause_name = alt_em10g32_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+    # The generated testbench is listed here to create a simulation configuration for it. However
+    # the tb is commented because it is not useful, see generate_ip.sh.
+    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..bee3382d48564655bdf99aca1028225b977cde33
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/compile_ip.tcl
@@ -0,0 +1,38 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+
+vmap  alt_mem_if_jtag_master_194            ./work/
+
+  vcom         "$IP_DIR/../alt_mem_if_jtag_master_194/sim/ip_arria10_e2sg_ddr4_8g_1600_alt_mem_if_jtag_master_194_5ftfrmy.vhd" -work alt_mem_if_jtag_master_194           
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..0095249141b1a21eaa3d32b7fdcd4763889720d2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_alt_mem_if_jtag_master_194
+hdl_library_clause_name = alt_mem_if_jtag_master_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_jtag_dc_streaming_194 ip_arria10_e2sg_timing_adapter_194 ip_arria10_e2sg_altera_avalon_sc_fifo_194 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_194 ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_194 ip_arria10_e2sg_altera_avalon_packets_to_master_194 ip_arria10_e2sg_channel_adapter_194 ip_arria10_e2sg_altera_reset_controller_194
+
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ed7d97d055e7c6295054c1301ea2b158c0e71284
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_194/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_clkbuf_global/sim"
+
+vmap altclkctrl_194 ./work/
+  vcom  "$IP_DIR/../altclkctrl_194/sim/ip_arria10_e2sg_clkbuf_global_altclkctrl_194_uuznxiq.vhd" -work altclkctrl_194                                           
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..934e15176dacda9ab0bb8b77f69e2219cb55b46c
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_194/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altclkctrl_194
+hdl_library_clause_name = altclkctrl_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d543d321b43070389a27a75c38a93809a42ac166
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_194/compile_ip.tcl
@@ -0,0 +1,37 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+vlib ./work/         ;# Assume library work already exist                                                                                        
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_asmi_parallel/sim"
+
+vmap altera_asmi_parallel_194 ./work/
+
+
+  vcom  "$IP_DIR/../altera_asmi_parallel_194/sim/ip_arria10_e2sg_asmi_parallel_altera_asmi_parallel_194_2sjvniq.vhd" -work altera_asmi_parallel_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..5442578ccbf2517eb29c3f98ba0233618ab91385
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_194/hdllib.cfg
@@ -0,0 +1,15 @@
+hdl_lib_name = ip_arria10_e2sg_altera_asmi_parallel_194
+hdl_library_clause_name = altera_asmi_parallel_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_194/compile_ip.tcl
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a307e87a54414dc50124e9eb91753551fb898b36
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_194/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+
+vmap  altera_avalon_mm_bridge_194         ./work/                       
+
+  vlog      "$IP_DIR/../altera_avalon_mm_bridge_194/sim/altera_avalon_mm_bridge.v"  -work altera_avalon_mm_bridge_194                                                        
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..bb5bf29a495d77fcb5711f123ec2a9a82b1ca56e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_194/hdllib.cfg
@@ -0,0 +1,20 @@
+hdl_lib_name = ip_arria10_e2sg_altera_avalon_mm_bridge_194
+hdl_library_clause_name = altera_avalon_mm_bridge_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+    # The generated testbench is listed here to create a simulation configuration for it. However
+    # the tb is commented because it is not useful, see generate_ip.sh.
+    #$RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/mac_10g/generated_tb/generated/sim/ip_arria10_e2sg_mac_10g_tb.vhd
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..bb1ffeed0ede447587f7b137d360af84b16ff2d1
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_194/compile_ip.tcl
@@ -0,0 +1,46 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+vmap  altera_avalon_onchip_memory2_194    ./work/
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+  vcom         "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
+  vcom         "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+  vcom         "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+  vcom         "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
+                      
+
+                                                      
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..67c433f39b05824ae69e7fa9013211b1ded6908a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_avalon_onchip_memory2_194
+hdl_library_clause_name = altera_avalon_onchip_memory2_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..11f0931fdbddcf999e3dfc466c832ecb9208edc9
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_194/compile_ip.tcl
@@ -0,0 +1,37 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+                
+vmap  altera_avalon_packets_to_master_194   ./work/
+
+  vlog      "$IP_DIR/../altera_avalon_packets_to_master_194/sim/altera_avalon_packets_to_master.v" -work altera_avalon_packets_to_master_194  
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..eb49528555ca7102f8a3fa6001fc5c00e1cf3da7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_avalon_packets_to_master_194
+hdl_library_clause_name = altera_avalon_packets_to_master_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0bfd4ac5dfcc6ef48c342fad5b2f56c36e8c924d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_194/compile_ip.tcl
@@ -0,0 +1,40 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+
+vmap  altera_avalon_sc_fifo_194  ./work/
+  vlog      "$IP_DIR/../altera_avalon_sc_fifo_194/sim/altera_avalon_sc_fifo.v"  -work altera_avalon_sc_fifo_194            
+   
+                      
+
+                                                      
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..53ab04b9e2407658d1781246df84db84965b3617
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_avalon_sc_fifo_194
+hdl_library_clause_name = altera_avalon_sc_fifo_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d5c7116116424caf417ed59ea10197e8955e0df2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_194/compile_ip.tcl
@@ -0,0 +1,37 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+
+vmap  altera_avalon_st_bytes_to_packets_194  ./work/
+                                                      
+  vlog      "$IP_DIR/../altera_avalon_st_bytes_to_packets_194/sim/altera_avalon_st_bytes_to_packets.v"  -work altera_avalon_st_bytes_to_packets_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..739e6e61ea01e8110f5b1f658e4254c741fc4249
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_194
+hdl_library_clause_name = altera_avalon_st_bytes_to_packets_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3102573ba03f46e91391baa4753fa5e260f2ce59
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_194/compile_ip.tcl
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+
+set IP_DIR  "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+vmap  altera_avalon_st_packets_to_bytes_194 ./work/
+   
+  vlog  "$IP_DIR/../altera_avalon_st_packets_to_bytes_194/sim/altera_avalon_st_packets_to_bytes.v"  -work altera_avalon_st_packets_to_bytes_194
+                      
+
+                                                      
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..8a5524e48b7b74c83e4c75f5688b7fb1fbd55d9d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_194
+hdl_library_clause_name = altera_avalon_st_packets_to_bytes_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..23ab9cbfddc5882d11cede8530bf4a2930e4b202
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/compile_ip.tcl
@@ -0,0 +1,161 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist
+#
+vmap  altera_emif_194                     ./work/
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+  vlog      "$IP_DIR/../altera_emif_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_194_dzobyri.v"                                     -work altera_emif_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000sim"
+  vlog      "$IP_DIR/../altera_emif_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_194_lwknerq.v"                                     -work altera_emif_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+  vlog      "$IP_DIR/../altera_emif_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_194_ebfu2ha.v"                                     -work altera_emif_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+  vlog      "$IP_DIR/../altera_emif_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_194_nz3mdxa.v"                                     -work altera_emif_194
+
+vmap altera_emif_arch_nf_194 ./work/
+# ddr4_4g_1600
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_top.sv"                -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_io_aux.sv"             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y.sv"                    -work altera_emif_arch_nf_194
+
+# ddr4_4g_2000
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
+
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_top.sv"                -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_io_aux.sv"             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy.sv"                    -work altera_emif_arch_nf_194
+
+# ddr4_8g_1600
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_194_spx5pgi_top.sv"                -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_194_spx5pgi_io_aux.sv"             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_194_spx5pgi.sv"                    -work altera_emif_arch_nf_194
+
+# ddr4_8g_2400
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_top.sv"                -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_io_aux.sv"             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i.sv"                    -work altera_emif_arch_nf_194
+
+# common dependencies
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_bufs.sv"                                                        -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_se_i.sv"                                               -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_se_o.sv"                                               -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_df_i.sv"                                               -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_df_o.sv"                                               -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_cp_i.sv"                                               -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_bdir_df.sv"                                                 -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_bdir_se.sv"                                                 -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_unused.sv"                                                  -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_cal_counter.sv"                                                 -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_pll.sv"                                                         -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_pll_fast_sim.sv"                                                -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_pll_extra_clks.sv"                                              -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_oct.sv"                                                         -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_core_clks_rsts.sv"                                              -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hps_clks_rsts.sv"                                               -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_io_tiles_wrap.sv"                                               -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_io_tiles.sv"                                                    -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_io_tiles_abphy.sv"                                              -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_abphy_mux.sv"                                                   -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_avl_if.sv"                                                  -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_sideband_if.sv"                                             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_mmr_if.sv"                                                  -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_amm_data_if.sv"                                             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_ast_data_if.sv"                                             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_afi_if.sv"                                                      -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_seq_if.sv"                                                      -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_regs.sv"                                                        -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_oct.sv"                                                                      -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_oct_um_fsm.sv"                                                               -work altera_emif_arch_nf_194
+  vlog      "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_std_synchronizer_nocut.v"                                                    -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/mem_array_abphy.sv"                                                                 -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/twentynm_io_12_lane_abphy.sv"                                                       -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/twentynm_io_12_lane_encrypted_abphy.sv"                                             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv"                                       -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/io_12_lane_bcm__nf5es_abphy.sv"                                                     -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/io_12_lane__nf5es_abphy.sv"                                                         -work altera_emif_arch_nf_194
+
+vmap  altera_emif_cal_slave_nf_194        ./work/
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_cal_slave_nf_194_efslyyq.v"           -work altera_emif_cal_slave_nf_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
+  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_cal_slave_nf_194_efslyyq.v"           -work altera_emif_cal_slave_nf_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_194_efslyyq.v"           -work altera_emif_cal_slave_nf_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_cal_slave_nf_194_efslyyq.v"           -work altera_emif_cal_slave_nf_194
+
+vmap  altera_reset_controller_194         ./work/
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+  vlog      "$IP_DIR/../altera_reset_controller_194/sim/mentor/altera_reset_controller.v"                                               -work altera_reset_controller_194
+  vlog      "$IP_DIR/../altera_reset_controller_194/sim/mentor/altera_reset_synchronizer.v"                                             -work altera_reset_controller_194
+
+vmap  altera_mm_interconnect_194          ./work/
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_mm_interconnect_194_7km4trq.vhd"             -work altera_mm_interconnect_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_mm_interconnect_194_7km4trq.vhd"             -work altera_mm_interconnect_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_194_ibrpcbq.vhd"             -work altera_mm_interconnect_194
+  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_194_7km4trq.vhd"             -work altera_mm_interconnect_194
+  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_194_mtvmp4i.vhd"             -work altera_mm_interconnect_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_mm_interconnect_194_7km4trq.vhd"             -work altera_mm_interconnect_194
+
+vmap  altera_avalon_onchip_memory2_194    ./work/
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+  vcom         "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
+  vcom         "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+  vcom         "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+  vcom         "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
+
+
+vmap  altera_avalon_mm_bridge_194         ./work/
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+  vlog      "$IP_DIR/../altera_avalon_mm_bridge_194/sim/altera_avalon_mm_bridge.v"  -work altera_avalon_mm_bridge_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..7cd50e438d358e8ad0ccf72c4965391a5f9cc62b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_emif_194
+hdl_library_clause_name = altera_emif_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_194 ip_arria10_e2sg_altera_merlin_slave_translator_194
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ff633035c4f44b7c623a0dba9c8628de2c63cf17
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/compile_ip.tcl
@@ -0,0 +1,97 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap altera_emif_arch_nf_194 ./work/
+# ddr4_4g_1600
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_top.sv"                -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_io_aux.sv"             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y.sv"                    -work altera_emif_arch_nf_194
+
+# ddr4_4g_2000
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
+
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_top.sv"                -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_io_aux.sv"             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy.sv"                    -work altera_emif_arch_nf_194
+
+# ddr4_8g_1600
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_194_spx5pgi_top.sv"                -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_194_spx5pgi_io_aux.sv"             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_194_spx5pgi.sv"                    -work altera_emif_arch_nf_194
+
+# ddr4_8g_2400
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_top.sv"                -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_io_aux.sv"             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i.sv"                    -work altera_emif_arch_nf_194
+
+# common dependencies
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_bufs.sv"                                                        -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_se_i.sv"                                               -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_se_o.sv"                                               -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_df_i.sv"                                               -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_df_o.sv"                                               -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_udir_cp_i.sv"                                               -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_bdir_df.sv"                                                 -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_bdir_se.sv"                                                 -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_buf_unused.sv"                                                  -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_cal_counter.sv"                                                 -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_pll.sv"                                                         -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_pll_fast_sim.sv"                                                -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_pll_extra_clks.sv"                                              -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_oct.sv"                                                         -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_core_clks_rsts.sv"                                              -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hps_clks_rsts.sv"                                               -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_io_tiles_wrap.sv"                                               -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_io_tiles.sv"                                                    -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_io_tiles_abphy.sv"                                              -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_abphy_mux.sv"                                                   -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_avl_if.sv"                                                  -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_sideband_if.sv"                                             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_mmr_if.sv"                                                  -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_amm_data_if.sv"                                             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_hmc_ast_data_if.sv"                                             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_afi_if.sv"                                                      -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_seq_if.sv"                                                      -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_emif_arch_nf_regs.sv"                                                        -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_oct.sv"                                                                      -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_oct_um_fsm.sv"                                                               -work altera_emif_arch_nf_194
+  vlog      "$IP_DIR/../altera_emif_arch_nf_194/sim/altera_std_synchronizer_nocut.v"                                                    -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/mem_array_abphy.sv"                                                                 -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/twentynm_io_12_lane_abphy.sv"                                                       -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/twentynm_io_12_lane_encrypted_abphy.sv"                                             -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv"                                       -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/io_12_lane_bcm__nf5es_abphy.sv"                                                     -work altera_emif_arch_nf_194
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/io_12_lane__nf5es_abphy.sv"                                                         -work altera_emif_arch_nf_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..d491e596f2d91317933011e17c550df83f949f35
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/hdllib.cfg
@@ -0,0 +1,20 @@
+hdl_lib_name = ip_arria10_e2sg_altera_emif_arch_nf_194
+hdl_library_clause_name = altera_emif_arch_nf_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+    # The generated testbench is listed here to create a simulation configuration for it. However
+    # the tb is commented because it is not useful, see generate_ip.sh.
+    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9d9d4760dcca9c2d8f438388ed8cb987a04c9c81
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_194/compile_ip.tcl
@@ -0,0 +1,45 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+vmap  altera_emif_cal_slave_nf_194        ./work/
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_cal_slave_nf_194_efslyyq.v"           -work altera_emif_cal_slave_nf_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
+  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_cal_slave_nf_194_efslyyq.v"           -work altera_emif_cal_slave_nf_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_194_efslyyq.v"           -work altera_emif_cal_slave_nf_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_cal_slave_nf_194_efslyyq.v"           -work altera_emif_cal_slave_nf_194
+
+                                                      
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..907d0bce85fdef8c855154a50ddf0a42b19e5a52
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_emif_cal_slave_nf_194
+hdl_library_clause_name = altera_emif_cal_slave_nf_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..751a5e57d99a24d7d75a5f3845c13121b1eb4617
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_194/compile_ip.tcl
@@ -0,0 +1,40 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_eth_tse_194                     ./work/
+
+# tse_sgmii_gx
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+vcom         "$IP_DIR/../altera_eth_tse_194/sim/ip_arria10_e2sg_tse_sgmii_gx_altera_eth_tse_194_dm7dxyq.vhd"            -work altera_eth_tse_194     
+
+# tse_sgmii_lvds
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+vcom         "$IP_DIR/../altera_eth_tse_194/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_eth_tse_194_zsww75y.vhd"          -work altera_eth_tse_194                   
+            
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..22aa93e17fa3be2fbfae99469e580ca29ff137ec
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_194/hdllib.cfg
@@ -0,0 +1,27 @@
+hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_194
+hdl_library_clause_name = altera_eth_tse_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+ip_arria10_e2sg_altera_eth_tse_mac_194
+ip_arria10_e2sg_altera_eth_tse_avalon_arbiter_194
+ip_arria10_e2sg_altera_eth_tse_pcs_pma_nf_phyip_194
+ip_arria10_e2sg_altera_eth_tse_pcs_pma_nf_lvds_194
+ip_arria10_e2sg_altera_xcvr_native_a10_194
+ip_arria10_e2sg_altera_eth_tse_nf_phyip_terminator_194
+ip_arria10_e2sg_altera_eth_tse_nf_lvds_terminator_194
+ip_arria10_e2sg_altera_lvds_194
+ip_arria10_e2sg_altera_reset_controller_194
+
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d33aee121ed68d23ccb8a671a79c32287f4983f7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_194/compile_ip.tcl
@@ -0,0 +1,33 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+vmap  altera_eth_tse_avalon_arbiter_194      ./work/
+  vlog      "$IP_DIR/../altera_eth_tse_avalon_arbiter_194/sim/mentor/altera_eth_tse_avalon_arbiter.v"                                                   -work altera_eth_tse_avalon_arbiter_194  
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..eae52be1ef96d507e2a64d9741299954f3f9db66
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_194/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_avalon_arbiter_194
+hdl_library_clause_name = altera_eth_tse_avalon_arbiter_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..661bfc95dea84e1e803d44d2f7831060ad8151a4
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/compile_ip.tcl
@@ -0,0 +1,148 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+
+vmap  altera_eth_tse_mac_194                 ./work/
+
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/altera_xcvr_native_a10_functions_h.sv"                                     -work altera_common_sv_packages  
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_eth_tse_mac.v"                                                   -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_clk_cntl.v"                                                  -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_crc328checker.v"                                             -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_crc328generator.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_crc32ctl8.v"                                                 -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_crc32galois8.v"                                              -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_gmii_io.v"                                                   -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_lb_read_cntl.v"                                              -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_lb_wrt_cntl.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_hashing.v"                                                   -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_host_control.v"                                              -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_host_control_small.v"                                        -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mac_control.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_register_map.v"                                              -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_register_map_small.v"                                        -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_counter_cntl.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_shared_mac_control.v"                                        -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_shared_register_map.v"                                       -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_counter_cntl.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_lfsr_10.v"                                                   -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_loopback_ff.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_altshifttaps.v"                                              -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_fifoless_mac_rx.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mac_rx.v"                                                    -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_fifoless_mac_tx.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mac_tx.v"                                                    -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_magic_detection.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mdio.v"                                                      -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mdio_clk_gen.v"                                              -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mdio_cntl.v"                                                 -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_mdio.v"                                                  -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mii_rx_if.v"                                                 -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_mii_tx_if.v"                                                 -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_pipeline_base.v"                                             -work altera_eth_tse_mac_194                
+  vlog -sv  "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_pipeline_stage.sv"              -L altera_common_sv_packages -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_dpram_16x32.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_dpram_8x32.v"                                                -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_dpram_ecc_16x32.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_fifoless_retransmit_cntl.v"                                  -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_retransmit_cntl.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rgmii_in1.v"                                                 -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rgmii_in4.v"                                                 -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_nf_rgmii_module.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rgmii_module.v"                                              -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rgmii_out1.v"                                                -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rgmii_out4.v"                                                -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_ff.v"                                                     -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_min_ff.v"                                                 -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_ff_cntrl.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_ff_cntrl_32.v"                                            -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_ff_cntrl_32_shift16.v"                                    -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_ff_length.v"                                              -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_rx_stat_extract.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_timing_adapter32.v"                                          -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_timing_adapter8.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_timing_adapter_fifo32.v"                                     -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_timing_adapter_fifo8.v"                                      -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_1geth.v"                                                 -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_fifoless_1geth.v"                                        -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_w_fifo.v"                                                -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_w_fifo_10_100_1000.v"                                    -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_wo_fifo.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_wo_fifo_10_100_1000.v"                                   -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_top_gen_host.v"                                              -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_ff.v"                                                     -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_min_ff.v"                                                 -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_ff_cntrl.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_ff_cntrl_32.v"                                            -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_ff_cntrl_32_shift16.v"                                    -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_ff_length.v"                                              -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_ff_read_cntl.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_tx_stat_extract.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_eth_tse_std_synchronizer.v"                                      -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v"                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v"                                  -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_false_path_marker.v"                                         -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_reset_synchronizer.v"                                        -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_clock_crosser.v"                                             -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_a_fifo_13.v"                                                 -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_a_fifo_24.v"                                                 -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_a_fifo_34.v"                                                 -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_a_fifo_opt_1246.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_a_fifo_opt_14_44.v"                                          -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_a_fifo_opt_36_10.v"                                          -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_gray_cnt.v"                                                  -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_sdpm_altsyncram.v"                                           -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_altsyncram_dpm_fifo.v"                                       -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_bin_cnt.v"                                                   -work altera_eth_tse_mac_194                
+  vlog -sv  "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ph_calculator.sv"               -L altera_common_sv_packages -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_sdpm_gen.v"                                                  -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_dec_x10.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x10.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v"                                       -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_dec_x14.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x14.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v"                                       -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_dec_x2.v"                                                -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x2.v"                                                -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v"                                        -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_dec_x23.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x23.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v"                                       -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_dec_x36.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x36.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v"                                       -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_dec_x40.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x40.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v"                                       -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_dec_x30.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x30.v"                                               -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v"                                       -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/mentor/altera_tse_ecc_status_crosser.v"                                        -work altera_eth_tse_mac_194                
+  vlog      "$IP_DIR/../altera_eth_tse_mac_194/sim/altera_std_synchronizer_nocut.v"                                               -work altera_eth_tse_mac_194              
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..a1662486609c1a9a02c873b4dc7d6143e01ed281
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_mac_194
+hdl_library_clause_name = altera_eth_tse_mac_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_194/compile_ip.tcl
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..200fb828e38fe570dca1ef0e06a29b8a0a8a40d8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_194/compile_ip.tcl
@@ -0,0 +1,40 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+vmap  altera_eth_tse_nf_lvds_terminator_194 ./work/
+
+
+  vlog      "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_194/sim/mentor/altera_eth_tse_std_synchronizer.v"            -work altera_eth_tse_nf_lvds_terminator_194
+  vlog      "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_194/sim/mentor/altera_eth_tse_nf_lvds_terminator.v"          -work altera_eth_tse_nf_lvds_terminator_194
+  vlog      "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_194/sim/mentor/altera_tse_reset_synchronizer.v"              -work altera_eth_tse_nf_lvds_terminator_194
+  vlog      "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_194/sim/mentor/altera_tse_nf_lvds_channel_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_194
+  vlog      "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_194/sim/mentor/altera_tse_nf_lvds_common_reset_sequencer.v"  -work altera_eth_tse_nf_lvds_terminator_194
+  vlog      "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_194/sim/altera_std_synchronizer_nocut.v"                     -work altera_eth_tse_nf_lvds_terminator_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..730217235b5afab86da5b6f8f4d649d2904e14fe
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_194/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_nf_lvds_terminator_194
+hdl_library_clause_name = altera_eth_tse_nf_lvds_terminator_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..43a5ebafdade1fefec7ef836af585d25a2dbe55a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_194/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+
+vmap  altera_eth_tse_nf_phyip_terminator_194 ./work/
+
+  vlog      "$IP_DIR/../altera_eth_tse_nf_phyip_terminator_194/sim/mentor/altera_eth_tse_nf_phyip_terminator.v"                                         -work altera_eth_tse_nf_phyip_terminator_194                 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..3fcd13f653e7299c2dd3df4109113934afcf39b8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_194/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_nf_phyip_terminator_194
+hdl_library_clause_name = altera_eth_tse_nf_phyip_terminator_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..eb4c61cbbec425bb656e62d220eb884581796289
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/compile_ip.tcl
@@ -0,0 +1,114 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+    
+vmap  altera_eth_tse_pcs_pma_nf_lvds_194    ./work/
+
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_eth_tse_pcs_pma_nf_lvds.v"                -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_align_sync.v"                         -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_dec10b8b.v"                           -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_dec_func.v"                           -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_enc8b10b.v"                           -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_autoneg.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_carrier_sense.v"                      -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  #vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_clk_gen.v"                            -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_sgmii_clk_div.v"                      -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_sgmii_clk_enable.v"                   -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_rx_encapsulation.v"                   -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_tx_encapsulation.v"                   -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v"           -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_pcs_control.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_pcs_host_control.v"                   -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_mdio_reg.v"                           -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_mii_rx_if_pcs.v"                      -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_mii_tx_if_pcs.v"                      -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_rx_sync.v"                            -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_sgmii_clk_cntl.v"                     -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_colision_detect.v"                    -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_rx_converter.v"                       -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_rx_fifo_rd.v"                         -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_rx_converter.v"                   -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_sgmii.v"                          -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_sgmii_strx_gx.v"                  -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_tx_converter.v"                   -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_tx_converter.v"                       -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_1000_base_x.v"                    -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v"            -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_pcs.v"                            -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_pcs_strx_gx.v"                    -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_rx.v"                             -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_top_tx.v"                             -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_lvds_reset_sequencer.v"               -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_lvds_reverse_loopback.v"              -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_pma_lvds_rx_av.v"                     -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_pma_lvds_rx.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_pma_lvds_tx.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_eth_tse_std_synchronizer.v"               -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v"        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v"           -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_false_path_marker.v"                  -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_reset_synchronizer.v"                 -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_clock_crosser.v"                      -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_a_fifo_13.v"                          -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_a_fifo_24.v"                          -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_a_fifo_34.v"                          -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_a_fifo_opt_1246.v"                    -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_a_fifo_opt_14_44.v"                   -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_a_fifo_opt_36_10.v"                   -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_gray_cnt.v"                           -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_sdpm_altsyncram.v"                    -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_altsyncram_dpm_fifo.v"                -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_bin_cnt.v"                            -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog -sv  "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ph_calculator.sv"                     -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_sdpm_gen.v"                           -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_dec_x10.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x10.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v"                -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_dec_x14.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x14.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v"                -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_dec_x2.v"                         -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x2.v"                         -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v"                 -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_dec_x23.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x23.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v"                -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_dec_x36.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x36.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v"                -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_dec_x40.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x40.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v"                -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_dec_x30.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x30.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v"                -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/mentor/altera_tse_ecc_status_crosser.v"                 -work altera_eth_tse_pcs_pma_nf_lvds_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_194/sim/altera_std_synchronizer_nocut.v"                        -work altera_eth_tse_pcs_pma_nf_lvds_194 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..b9bd0d2607d999f4a29476e7c3a3abe58ab77bcd
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_pcs_pma_nf_lvds_194
+hdl_library_clause_name = altera_eth_tse_pcs_pma_nf_lvds_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..12c5615059aa11c797ebe8b3a1cb0781fa9e5e06
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/compile_ip.tcl
@@ -0,0 +1,116 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+
+              
+vmap  altera_eth_tse_pcs_pma_nf_phyip_194    ./work/
+
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/altera_xcvr_native_a10_functions_h.sv"                                                           -work altera_common_sv_packages
+
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_eth_tse_pcs_pma_nf_phyip.v"                                               -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_align_sync.v"                                                         -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_dec10b8b.v"                                                           -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_dec_func.v"                                                           -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_enc8b10b.v"                                                           -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_autoneg.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_carrier_sense.v"                                                      -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  #vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_clk_gen.v"                                                            -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_sgmii_clk_div.v"                                                      -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_sgmii_clk_enable.v"                                                   -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_rx_encapsulation.v"                                                   -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_tx_encapsulation.v"                                                   -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v"                                           -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_pcs_control.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_pcs_host_control.v"                                                   -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_mdio_reg.v"                                                           -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_mii_rx_if_pcs.v"                                                      -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_mii_tx_if_pcs.v"                                                      -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_rx_sync.v"                                                            -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_sgmii_clk_cntl.v"                                                     -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_colision_detect.v"                                                    -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_rx_converter.v"                                                       -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_rx_fifo_rd.v"                                                         -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_rx_converter.v"                                                   -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_sgmii.v"                                                          -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_sgmii_strx_gx.v"                                                  -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_tx_converter.v"                                                   -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_tx_converter.v"                                                       -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_1000_base_x.v"                                                    -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v"                                            -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_pcs.v"                                                            -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_pcs_strx_gx.v"                                                    -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_rx.v"                                                             -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_top_tx.v"                                                             -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog -sv  "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_reset_sequencer.sv"                      -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog -sv  "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_reset_ctrl_lego.sv"                      -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_xcvr_resync.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_gxb_aligned_rxsync.v"                                                 -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_eth_tse_std_synchronizer.v"                                               -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v"                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v"                                           -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_false_path_marker.v"                                                  -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_reset_synchronizer.v"                                                 -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_clock_crosser.v"                                                      -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_a_fifo_13.v"                                                          -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_a_fifo_24.v"                                                          -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_a_fifo_34.v"                                                          -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_a_fifo_opt_1246.v"                                                    -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_a_fifo_opt_14_44.v"                                                   -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_a_fifo_opt_36_10.v"                                                   -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_gray_cnt.v"                                                           -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_sdpm_altsyncram.v"                                                    -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_altsyncram_dpm_fifo.v"                                                -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_bin_cnt.v"                                                            -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog -sv  "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ph_calculator.sv"                        -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_sdpm_gen.v"                                                           -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_dec_x10.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x10.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v"                                                -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_dec_x14.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x14.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v"                                                -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_dec_x2.v"                                                         -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x2.v"                                                         -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v"                                                 -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_dec_x23.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x23.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v"                                                -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_dec_x36.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x36.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v"                                                -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_dec_x40.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x40.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v"                                                -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_dec_x30.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x30.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v"                                                -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/mentor/altera_tse_ecc_status_crosser.v"                                                 -work altera_eth_tse_pcs_pma_nf_phyip_194   
+  vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_194/sim/altera_std_synchronizer_nocut.v"                                                        -work altera_eth_tse_pcs_pma_nf_phyip_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..4de2cfd1bb8b25b4b610dd90773a13eaef4330eb
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_eth_tse_pcs_pma_nf_phyip_194
+hdl_library_clause_name = altera_eth_tse_pcs_pma_nf_phyip_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0ba739d595aa9c263a075c6c283fed92a3125aa6
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_194/compile_ip.tcl
@@ -0,0 +1,43 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_iopll_194           ./work/
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk25/sim"
+  vlog  "$IP_DIR/../altera_iopll_194/sim/ip_arria10_e2sg_pll_clk25_altera_iopll_194_fp6fpla.vo"  -work altera_iopll_194         
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk125/sim"
+  vlog  "$IP_DIR/../altera_iopll_194/sim/ip_arria10_e2sg_pll_clk125_altera_iopll_194_abkdtja.vo" -work altera_iopll_194          
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk200/sim"
+  vlog  "$IP_DIR/../altera_iopll_194/sim/ip_arria10_e2sg_pll_clk200_altera_iopll_194_qkytlfy.vo" -work altera_iopll_194          
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll/sim"
+  vlog  "$IP_DIR/../altera_iopll_194/sim/ip_arria10_e2sg_jesd204b_rx_core_pll_altera_iopll_194_4sgpama.vo" -work altera_iopll_194          
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..befbb799783e46dc4252a403813102216afdc213
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_194/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_iopll_194
+hdl_library_clause_name = altera_iopll_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..2d1c465c1f3f738dad7cd23289652318339f6591
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_194/compile_ip.tcl
@@ -0,0 +1,37 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+
+vmap  altera_ip_col_if_194 ./work/
+                                              
+  vlog  "$IP_DIR/../altera_ip_col_if_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_ip_col_if_194_jvd2zcq.v"  -work altera_ip_col_if_194                 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..3cf9a13ba8f132b589d86104febbe2bed74053b1
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_ip_col_if_194
+hdl_library_clause_name = altera_ip_col_if_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..508ba5f73ce7ecea2298af56a924517849c54778
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/compile_ip.tcl
@@ -0,0 +1,45 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+
+vmap  altera_jtag_dc_streaming_194          ./work/
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_avalon_st_jtag_interface.v"                                             -work altera_jtag_dc_streaming_194         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_jtag_dc_streaming.v"                                                    -work altera_jtag_dc_streaming_194         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_jtag_sld_node.v"                                                        -work altera_jtag_dc_streaming_194         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_jtag_streaming.v"                                                       -work altera_jtag_dc_streaming_194         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_avalon_st_clock_crosser.v"                                              -work altera_jtag_dc_streaming_194         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_std_synchronizer_nocut.v"                                               -work altera_jtag_dc_streaming_194         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_avalon_st_pipeline_base.v"                                              -work altera_jtag_dc_streaming_194         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_avalon_st_idle_remover.v"                                               -work altera_jtag_dc_streaming_194         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_avalon_st_idle_inserter.v"                                              -work altera_jtag_dc_streaming_194         
+  vlog -sv  "$IP_DIR/../altera_jtag_dc_streaming_194/sim/altera_avalon_st_pipeline_stage.sv"                                            -work altera_jtag_dc_streaming_194                 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..342af0f1dbc6f6be71d27c912babd0f2bc2dfb49
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_jtag_dc_streaming_194
+hdl_library_clause_name = altera_jtag_dc_streaming_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..281941337a14ea6877fbe7f966d324b70e8c76bd
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_194/compile_ip.tcl
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+vmap altera_lvds_194                 ./work/
+  vcom         "$IP_DIR/../altera_lvds_194/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_194_og2byry.vhd"                -work altera_lvds_194  
+  vcom         "$IP_DIR/../altera_lvds_194/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_194_zfbfxeq.vhd"                -work altera_lvds_194  
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..c57f79da674218d8f6f49cb6cdfcf0afb0518d7c
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_194/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_lvds_194
+hdl_library_clause_name = altera_lvds_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_lvds_core20_194
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5eab2a57c4e8f716d544392f736322c0ef19cdea
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_194/compile_ip.tcl
@@ -0,0 +1,38 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+vmap  altera_lvds_core20_194                ./work/
+
+  vlog -sv  "$IP_DIR/../altera_lvds_core20_194/sim/altera_lvds_core20.sv"                                       -work altera_lvds_core20_194               
+  vlog      "$IP_DIR/../altera_lvds_core20_194/sim/altera_lvds_core20_pll.v"                                    -work altera_lvds_core20_194               
+  vcom      "$IP_DIR/../altera_lvds_core20_194/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_194_5a5vzei.vhd"  -work altera_lvds_core20_194               
+  vlog -sv  "$IP_DIR/../altera_lvds_core20_194/sim/altera_lvds_core20.sv"                                       -work altera_lvds_core20_194               
+  vlog      "$IP_DIR/../altera_lvds_core20_194/sim/altera_lvds_core20_pll.v"                                    -work altera_lvds_core20_194               
+  vcom      "$IP_DIR/../altera_lvds_core20_194/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_194_kmpu4hy.vhd"  -work altera_lvds_core20_194  
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..27c3b198505b81601425015767e7eec0462f8fb4
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_194/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_lvds_core20_194
+hdl_library_clause_name = altera_lvds_core20_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3003c89fc6ce9d34ea743c9132b0e0d02913ce68
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_194/compile_ip.tcl
@@ -0,0 +1,36 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+ 
+vmap  altera_merlin_slave_translator_194  ./work/
+                                                      
+  vlog -sv  "$IP_DIR/../altera_merlin_slave_translator_194/sim/mentor/altera_merlin_slave_translator.sv"                                -work altera_merlin_slave_translator_194 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..b09e8c6e636860e3e4b245c4d5fae25bc505fdf8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_merlin_slave_translator_194
+hdl_library_clause_name = altera_merlin_slave_translator_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5e96123ae6b6d62d9098a8250f87d95093734a87
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/compile_ip.tcl
@@ -0,0 +1,45 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+                                                      
+vmap  altera_mm_interconnect_194          ./work/
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_mm_interconnect_194_7km4trq.vhd"             -work altera_mm_interconnect_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_mm_interconnect_194_7km4trq.vhd"             -work altera_mm_interconnect_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_194_ibrpcbq.vhd"             -work altera_mm_interconnect_194
+  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_194_7km4trq.vhd"             -work altera_mm_interconnect_194
+  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_194_mtvmp4i.vhd"             -work altera_mm_interconnect_194
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_mm_interconnect_194_7km4trq.vhd"             -work altera_mm_interconnect_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..2cfcd7b671ac5fdaa7d7df2a223d949a8fca49ec
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_mm_interconnect_194
+hdl_library_clause_name = altera_mm_interconnect_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_194 ip_arria10_e2sg_altera_merlin_slave_translator_194
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d39fb8820d7953fddc4c5144524da5ad82ee111d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_194/compile_ip.tcl
@@ -0,0 +1,37 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
+
+vmap  altera_remote_update_194      ./work/
+
+  vcom  "$IP_DIR/../altera_remote_update_194/sim/ip_arria10_e2sg_remote_update_altera_remote_update_194_oxfb6sq.vhd" -work altera_remote_update_194     
+                                                            
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..27f6df3ede21fc7dafff9544a561636fe433f551
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_194/hdllib.cfg
@@ -0,0 +1,15 @@
+hdl_lib_name = ip_arria10_e2sg_altera_remote_update_194
+hdl_library_clause_name = altera_remote_update_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_remote_update_core_194
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_194/compile_ip.tcl
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..408165ca1956cf41a9bad9e78faf9d3671b7d1c6
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_194/compile_ip.tcl
@@ -0,0 +1,40 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
+
+
+vmap  altera_remote_update_core_194 ./work/
+
+
+  vlog  "$IP_DIR/../altera_remote_update_core_194/sim/mentor/altera_remote_update_core.sv"  -work altera_remote_update_core_194
+  
+                                                            
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..b48ddb73fa464526c94b9783708a9a528cc7f523
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_194/hdllib.cfg
@@ -0,0 +1,12 @@
+hdl_lib_name = ip_arria10_e2sg_altera_remote_update_core_194
+hdl_library_clause_name = altera_remote_update_core_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_194/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5f1c942eaff54df6fd1e84b2cbc39650c5d34cea
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/compile_ip.tcl
@@ -0,0 +1,37 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+ 
+vmap  altera_reset_controller_194         ./work/
+
+  vlog      "$IP_DIR/../altera_reset_controller_194/sim/mentor/altera_reset_controller.v"                                               -work altera_reset_controller_194        
+  vlog      "$IP_DIR/../altera_reset_controller_194/sim/mentor/altera_reset_synchronizer.v"                                             -work altera_reset_controller_194 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..eca40b53b933c13f4e2586ef502194f8ded21734
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_reset_controller_194
+hdl_library_clause_name = altera_reset_controller_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5b680d82bd0beeb092f53844627794c6facd4135
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_194/compile_ip.tcl
@@ -0,0 +1,55 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/sim"
+
+vmap  altera_common_sv_packages           ./work/
+vmap  altera_xcvr_atx_pll_a10_194         ./work/
+
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/altera_xcvr_native_a10_functions_h.sv"                                                                   -work altera_common_sv_packages          
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/twentynm_xcvr_avmm.sv"                                                      -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/mentor/twentynm_xcvr_avmm.sv"                                               -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/alt_xcvr_resync.sv"                                                         -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/alt_xcvr_arbiter.sv"                                                        -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/mentor/alt_xcvr_resync.sv"                                                  -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/mentor/alt_xcvr_arbiter.sv"                                                 -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/a10_avmm_h.sv"                                                              -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/alt_xcvr_atx_pll_rcfg_arb.sv"                                               -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/a10_xcvr_atx_pll.sv"                                                        -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/alt_xcvr_pll_embedded_debug.sv"                                             -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/alt_xcvr_pll_avmm_csr.sv"                                                   -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/mentor/alt_xcvr_atx_pll_rcfg_arb.sv"                                        -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/mentor/a10_xcvr_atx_pll.sv"                                                 -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/mentor/alt_xcvr_pll_embedded_debug.sv"                                      -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/mentor/alt_xcvr_pll_avmm_csr.sv"                                            -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_194_fdgop6i.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_194/sim/alt_xcvr_atx_pll_rcfg_opt_logic_fdgop6i.sv"                                 -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_194        
+                                                                                               
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..795fc5093e64cafa6a2b829f45bc3b433142a2f8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_194/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_xcvr_atx_pll_a10_194
+hdl_library_clause_name = altera_xcvr_atx_pll_a10_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d265cec2938d1b654c5b7a78c8bc2eb15610f9cc
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_194/compile_ip.tcl
@@ -0,0 +1,50 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/sim"
+
+vmap  altera_xcvr_fpll_a10_194             ./work/
+
+#pll_xgmii_mac_clocks
+  vlog -sv  "$IP_DIR/../altera_xcvr_fpll_a10_194/sim/twentynm_xcvr_avmm.sv"                 -work altera_xcvr_fpll_a10_194            
+  vlog -sv  "$IP_DIR/../altera_xcvr_fpll_a10_194/sim/mentor/twentynm_xcvr_avmm.sv"          -work altera_xcvr_fpll_a10_194            
+  vlog -sv  "$IP_DIR/../altera_xcvr_fpll_a10_194/sim/alt_xcvr_resync.sv"                    -work altera_xcvr_fpll_a10_194            
+  vlog -sv  "$IP_DIR/../altera_xcvr_fpll_a10_194/sim/mentor/alt_xcvr_resync.sv"             -work altera_xcvr_fpll_a10_194            
+  vlog -sv  "$IP_DIR/../altera_xcvr_fpll_a10_194/sim/altera_xcvr_fpll_a10.sv"               -work altera_xcvr_fpll_a10_194            
+  vlog -sv  "$IP_DIR/../altera_xcvr_fpll_a10_194/sim/mentor/altera_xcvr_fpll_a10.sv"        -work altera_xcvr_fpll_a10_194            
+  vlog -sv  "$IP_DIR/../altera_xcvr_fpll_a10_194/sim/a10_avmm_h.sv"                         -work altera_xcvr_fpll_a10_194            
+  vlog -sv  "$IP_DIR/../altera_xcvr_fpll_a10_194/sim/alt_xcvr_native_avmm_nf.sv"            -work altera_xcvr_fpll_a10_194            
+  vlog -sv  "$IP_DIR/../altera_xcvr_fpll_a10_194/sim/alt_xcvr_pll_embedded_debug.sv"        -work altera_xcvr_fpll_a10_194            
+  vlog -sv  "$IP_DIR/../altera_xcvr_fpll_a10_194/sim/alt_xcvr_pll_avmm_csr.sv"              -work altera_xcvr_fpll_a10_194            
+  vlog -sv  "$IP_DIR/../altera_xcvr_fpll_a10_194/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_194            
+  vlog -sv  "$IP_DIR/../altera_xcvr_fpll_a10_194/sim/mentor/alt_xcvr_pll_avmm_csr.sv"       -work altera_xcvr_fpll_a10_194                            
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..0166aeb5c5eafdea6c2ffc93a80f3fe36d44d689
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_194/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_xcvr_fpll_a10_194
+hdl_library_clause_name = altera_xcvr_fpll_a10_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1c9e1d44e89ae43d9186326e784bd5182969eb4d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/compile_ip.tcl
@@ -0,0 +1,108 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist   
+
+vmap  altera_xcvr_native_a10_194       ./work/
+vmap  altera_common_sv_packages        ./work/
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/sim"
+
+# common dependencies
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/altera_xcvr_native_a10_functions_h.sv"                                                               -work altera_common_sv_packages       
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_resync.sv"                                                     -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_arbiter.sv"                                                    -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/mentor/alt_xcvr_resync.sv"                                              -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/mentor/alt_xcvr_arbiter.sv"                                             -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/twentynm_pcs.sv"                                                        -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/twentynm_pma.sv"                                                        -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/twentynm_xcvr_avmm.sv"                                                  -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/twentynm_xcvr_native.sv"                                                -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/mentor/twentynm_pcs.sv"                                                 -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/mentor/twentynm_pma.sv"                                                 -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/mentor/twentynm_xcvr_avmm.sv"                                           -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/mentor/twentynm_xcvr_native.sv"                                         -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/a10_avmm_h.sv"                                                          -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_pipe_retry.sv"                                          -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_avmm_csr.sv"                                            -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_prbs_accum.sv"                                          -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_odi_accel.sv"                                           -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_arb.sv"                                            -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/altera_xcvr_native_pcie_dfe_params_h.sv"                                -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/pcie_mgmt_commands_h.sv"                                                -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/pcie_mgmt_functions_h.sv"                                               -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/pcie_mgmt_program.sv"                                                   -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/pcie_mgmt_cpu.sv"                                                       -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/pcie_mgmt_master.sv"                                                    -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/altera_xcvr_native_pcie_dfe_ip.sv"                                      -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv"                 -L altera_common_sv_packages -work altera_xcvr_native_a10_194  
+
+# phy_10gbase_r_48
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_194_y6b7ffi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_y6b7ffi.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_194  
+
+# phy_10gbase_r_24
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/sim"
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_194_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_mhfwvwa.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_194  
+
+# phy_10gbase_r_12
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/sim"
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_194_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_194      
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_fs3onwi.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_194  
+
+# phy_10gbase_r_4
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/sim"
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_194_d2amdia.sv"  -L altera_common_sv_packages -work altera_xcvr_native_a10_194     
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_d2amdia.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_194  
+
+# phy_10gbase_r_3
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/sim"
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_194_skxmbpy.sv"  -L altera_common_sv_packages -work altera_xcvr_native_a10_194     
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_skxmbpy.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_194  
+
+# phy_10gbase_r
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/sim"
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_194_nbxifma.sv"    -L altera_common_sv_packages -work altera_xcvr_native_a10_194   
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_nbxifma.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_194 
+
+# tse_sgmii_gx
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_tse_sgmii_gx_altera_xcvr_native_a10_194_k23srea.sv"     -L altera_common_sv_packages -work altera_xcvr_native_a10_194            
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_k23srea.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_194  
+
+# jesd204b rx
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx/sim"
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_jesd204b_rx_altera_xcvr_native_a10_194_vcpx3ja.sv"      -L altera_common_sv_packages -work altera_xcvr_native_a10_194            
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_vcpx3ja.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_194  
+
+# jesd204b tx
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/ip_arria10_e2sg_jesd204b_tx_altera_xcvr_native_a10_194_q3qhp5a.sv"      -L altera_common_sv_packages -work altera_xcvr_native_a10_194            
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_194/sim/alt_xcvr_native_rcfg_opt_logic_q3qhp5a.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_194  
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..7fe974b390cc72a55325ed30a7e09db5b7d7af47
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_xcvr_native_a10_194
+hdl_library_clause_name = altera_xcvr_native_a10_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_194/compile_ip.tcl
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ec9d9441cfc80c67be4297e97b368d61094128a7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/compile_ip.tcl
@@ -0,0 +1,44 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/sim"
+
+vmap  altera_xcvr_reset_control_194                  ./work/
+
+  vlog -sv  "$IP_DIR/../altera_xcvr_reset_control_194/sim/altera_xcvr_functions.sv"            -work altera_xcvr_reset_control_194                 
+  vlog -sv  "$IP_DIR/../altera_xcvr_reset_control_194/sim/mentor/altera_xcvr_functions.sv"     -work altera_xcvr_reset_control_194                 
+  vlog -sv  "$IP_DIR/../altera_xcvr_reset_control_194/sim/alt_xcvr_resync.sv"                  -work altera_xcvr_reset_control_194                 
+  vlog -sv  "$IP_DIR/../altera_xcvr_reset_control_194/sim/mentor/alt_xcvr_resync.sv"           -work altera_xcvr_reset_control_194                 
+  vlog -sv  "$IP_DIR/../altera_xcvr_reset_control_194/sim/altera_xcvr_reset_control.sv"        -work altera_xcvr_reset_control_194                 
+  vlog -sv  "$IP_DIR/../altera_xcvr_reset_control_194/sim/alt_xcvr_reset_counter.sv"           -work altera_xcvr_reset_control_194                 
+  vlog -sv  "$IP_DIR/../altera_xcvr_reset_control_194/sim/mentor/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_194                 
+  vlog -sv  "$IP_DIR/../altera_xcvr_reset_control_194/sim/mentor/alt_xcvr_reset_counter.sv"    -work altera_xcvr_reset_control_194                 
+                
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..7998387912450c66991c09b29d170962e43fc206
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_xcvr_reset_control_194
+hdl_library_clause_name = altera_xcvr_reset_control_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_194/compile_ip.tcl
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..98920860f33eff3cef087eca53ebae5d1739254a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_194/compile_ip.tcl
@@ -0,0 +1,40 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+
+vmap  channel_adapter_194                   ./work/
+
+  vlog -sv  "$IP_DIR/../channel_adapter_194/sim/ip_arria10_e2sg_ddr4_8g_1600_channel_adapter_194_kn2anua.sv"    -work channel_adapter_194                  
+  vlog -sv  "$IP_DIR/../channel_adapter_194/sim/ip_arria10_e2sg_ddr4_8g_1600_channel_adapter_194_wjhhrui.sv"    -work channel_adapter_194              
+
+                                                      
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..c1c910d5b9f30d4e5e591aaa0a9354ad731614d2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_channel_adapter_194
+hdl_library_clause_name = channel_adapter_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/e2sg_altera_merlin_master_translator_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/e2sg_altera_merlin_master_translator_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7561dff1bee41cea33810fd6b2cce7a45707577b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/e2sg_altera_merlin_master_translator_194/compile_ip.tcl
@@ -0,0 +1,36 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+
+vmap  altera_merlin_master_translator_194 ./work/
+        
+  vlog -sv  "$IP_DIR/../altera_merlin_master_translator_194/sim/altera_merlin_master_translator.sv"   -work altera_merlin_master_translator_194
+                                                      
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/e2sg_altera_merlin_master_translator_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/e2sg_altera_merlin_master_translator_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..391076569b6df37b19e80d213a9d91ee4d59f43d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/e2sg_altera_merlin_master_translator_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_merlin_master_translator_194
+hdl_library_clause_name = altera_merlin_master_translator_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_194/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_194/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ef4fe65555322647414ec11617eca7461af56646
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_194/compile_ip.tcl
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+
+vmap  timing_adapter_194   ./work/
+                  
+  vlog -sv  "$IP_DIR/../timing_adapter_194/sim/ip_arria10_e2sg_ddr4_8g_1600_timing_adapter_194_ewif6gi.sv"  -work timing_adapter_194                   
+
+                                                      
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_194/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_194/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..0362ff7264cb074b1f33264a25fcbb036ce8fc1d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_194/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_timing_adapter_194
+hdl_library_clause_name = timing_adapter_194
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_194/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg
index 02390dc468895a831e6533fed8862a396dc3c80d..e99087d229b71a0c9c85caf84999d72b317cf7f9 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg
@@ -5,6 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_arria10_e2sg 
 
 synth_files =
+    ip_arria10_e2sg_jesd204b_component_pkg.vhd
     ip_arria10_e2sg_jesd204b.vhd
 
 test_bench_files =
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
index 057261fec54a73fb1038df1447d472be7803f9be..7fecf069be6dafa449682e60e63e0ddfc8a42335 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -24,31 +24,37 @@
 -- Purpose: Combine IP components needed to create a JESD204B interface
 --   Initially supports RX_ONLY for receiving data from an ADC
 -- Description 
---   
+--   Currently only 12 streams because of the 12 channel reset block
+--   The sync_n signals are gated together to form g_nof_sync_n outputs
 --  
 
-LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e2sg_jesd204b_rx, ip_arria10_e2sg_jesd204b_rx_reset_seq, ip_arria10_e2sg_jesd204b_rx_core_pll, ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12;
+--LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e2sg_jesd204b_rx, ip_arria10_e2sg_jesd204b_rx_reset_seq, ip_arria10_e2sg_jesd204b_rx_core_pll, ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12;
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e2sg_jesd204b_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
+USE ip_arria10_e2sg_jesd204b_lib.ip_arria10_e2sg_jesd204b_component_pkg.ALL;
 
 ENTITY ip_arria10_e2sg_jesd204b IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
-    g_nof_channels        : NATURAL := 1;
+    g_nof_streams         : NATURAL := 1;
+    g_nof_sync_n          : NATURAL := 1;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
   );
   PORT (
     -- JESD204B external signals
     jesd204b_refclk       : IN STD_LOGIC := '0';                             -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
     jesd204b_sysref       : IN STD_LOGIC := '0';                             -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk 
-    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);  -- output to control ADC initialization/syncronization phase
     
     -- Data to fabric
-    rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);    -- Parallel data out to fabric
-    jesd204b_frame_clk    : OUT  STD_LOGIC := '0';                           -- Regenerated data clock to fabric
+    rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    -- Parallel data out to fabric
+    rx_clk                : OUT  STD_LOGIC := '0';                           -- Exported data clock (frame clock) to fabric
+    rx_rst                : OUT  STD_LOGIC := '0';                           -- Exported reset on rx_clk domain
+    rx_sysref             : OUT  STD_LOGIC := '0';                           -- Exported copy of sysref
 
     -- MM Control
     mm_clk                : IN  STD_LOGIC;
@@ -58,105 +64,122 @@ ENTITY ip_arria10_e2sg_jesd204b IS
     jesd204b_miso         : OUT t_mem_miso; 
          
     -- Serial connections to transceiver pins
-    serial_tx_arr         : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);      -- Not used for ADC
-    serial_rx_arr         : IN  STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+    serial_tx_arr         : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);      -- Not used for ADC
+    serial_rx_arr         : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0)
   );
 END ip_arria10_e2sg_jesd204b;
 
 
 ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
 
+  -- JESD IP constants
+  CONSTANT c_jesd204b_mm_addr_w            : NATURAL :=8;
+  CONSTANT c_jesd204b_rx_data_w            : NATURAL :=32;
+  CONSTANT c_jesd204b_rx_framer_data_w     : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
+  CONSTANT c_jesd204b_rx_somf_w            : NATURAL :=c_jesd204b_rx_data_w/8; -- One somf bit per octet
+  CONSTANT c_jesd204b_rx_framer_somf_w     : NATURAL :=c_jesd204b_rx_somf_w/2; -- IP outputs two samples in parallel
+  CONSTANT c_nof_sync_n_per_group          : NATURAL :=sel_a_b(g_nof_streams / g_nof_sync_n = 0, 1, g_nof_streams / g_nof_sync_n);
+
   -- JESD204 control status registers
-  SIGNAL jesd204b_mosi_arr          : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
-  SIGNAL jesd204b_miso_arr          : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0); 
-  SIGNAL reset_seq_mosi_arr         : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
-  SIGNAL reset_seq_miso_arr         : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0); 
+  SIGNAL jesd204b_mosi_arr          : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL jesd204b_miso_arr          : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0); 
+  SIGNAL reset_seq_mosi_arr         : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+  SIGNAL reset_seq_miso_arr         : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst); 
 
   -- Clocks
   SIGNAL rxframe_clk                : STD_LOGIC; 
   SIGNAL rxlink_clk                 : STD_LOGIC; 
+  SIGNAL jesd204b_avs_clk           : STD_LOGIC;
 
   -- Reset and control signals
-  SIGNAL dev_lane_aligned           : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);  -- 1 bit, each interface channel has 1 lane
-  SIGNAL rx_analogreset_arr         : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);                
-  SIGNAL rx_cal_busy_arr            : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rx_digitalreset_arr        : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rx_islockedtodata_arr      : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL dev_lane_aligned_arr       : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rx_csr_lane_powerdown_arr  : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL xcvr_rst_ctrl_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rx_xcvr_ready_in_arr       : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL pll_reset_arr              : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL xcvr_rst_arr               : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rx_avs_rst_arr             : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rxlink_rst_arr             : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rxframe_rst_arr            : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rx_avs_rst_n_arr           : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rxlink_rst_n_arr           : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rxframe_rst_n_arr          : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL f2_div1_cnt_arr            : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
+  SIGNAL dev_lane_aligned           : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);  -- 1 bit, each interface channel has 1 lane
+  SIGNAL rx_analogreset_arr         : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);                
+  SIGNAL rx_cal_busy_arr            : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rx_digitalreset_arr        : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rx_islockedtodata_arr      : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL dev_lane_aligned_arr       : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rx_csr_lane_powerdown_arr  : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL xcvr_rst_ctrl_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rx_xcvr_ready_in_arr       : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL pll_reset_arr              : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL xcvr_rst_arr               : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '1');               
+  SIGNAL rx_avs_rst_arr             : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rxlink_rst_arr             : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rxframe_rst_arr            : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rx_avs_rst_n_arr           : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rxlink_rst_n_arr           : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rxframe_rst_n_arr          : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL f2_div1_cnt_arr            : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
   SIGNAL core_pll_locked            : STD_LOGIC;               
   SIGNAL core_pll_locked_reg        : STD_LOGIC;               
+  SIGNAL jesd204b_sysref_1          : STD_LOGIC;               
+  SIGNAL jesd204b_sysref_2          : STD_LOGIC;               
+  SIGNAL jesd204b_sysref_frameclk_1 : STD_LOGIC;               
+  SIGNAL jesd204b_sysref_frameclk_2 : STD_LOGIC;               
 
   -- Data path
-  SIGNAL jesd204b_rx_link_data_arr  : STD_LOGIC_VECTOR(32*g_nof_channels-1 DOWNTO 0);               
-  SIGNAL jesd204b_rx_link_valid_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
+  SIGNAL jesd204b_rx_link_data_arr  : STD_LOGIC_VECTOR(c_jesd204b_rx_data_w*g_nof_streams-1 DOWNTO 0);               
+  SIGNAL jesd204b_rx_link_valid_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL jesd204b_rx_somf_arr       : STD_LOGIC_VECTOR(c_jesd204b_rx_somf_w*g_nof_streams-1 DOWNTO 0);               
+
+  SIGNAL jesd204b_sync_n_internal_arr   : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);  -- output to control ADC initialization/syncronization phase
 
 
   -- Component declarations for the IP blocks
 
---    component ip_arria10_e2sg_jesd204b_rx is
---    port (
---      jesd204_0_alldev_lane_aligned_export        : in  std_logic                     := 'X';             -- export
---      csr_cf_export                     : out std_logic_vector(4 downto 0);                     -- export
---      csr_cs_export                     : out std_logic_vector(1 downto 0);                     -- export
---      csr_f_export                      : out std_logic_vector(7 downto 0);                     -- export
---      csr_hd_export                     : out std_logic;                                        -- export
---      csr_k_export                      : out std_logic_vector(4 downto 0);                     -- export
---      csr_l_export                      : out std_logic_vector(4 downto 0);                     -- export
---      csr_lane_powerdown_export         : out std_logic_vector(0 downto 0);                     -- export
---      csr_m_export                      : out std_logic_vector(7 downto 0);                     -- export
---      csr_n_export                      : out std_logic_vector(4 downto 0);                     -- export
---      csr_np_export                     : out std_logic_vector(4 downto 0);                     -- export
---      csr_rx_testmode_export            : out std_logic_vector(3 downto 0);                     -- export
---      csr_s_export                      : out std_logic_vector(4 downto 0);                     -- export
---      dev_lane_aligned_export           : out std_logic;                                        -- export
---      dev_sync_n_export                 : out std_logic;                                        -- export
---      jesd204_rx_avs_chipselect         : in  std_logic                     := 'X';             -- chipselect
---      jesd204_rx_avs_address            : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- address
---      jesd204_rx_avs_read               : in  std_logic                     := 'X';             -- read
---      jesd204_rx_avs_readdata           : out std_logic_vector(31 downto 0);                    -- readdata
---      jesd204_rx_avs_waitrequest        : out std_logic;                                        -- waitrequest
---      jesd204_rx_avs_write              : in  std_logic                     := 'X';             -- write
---      jesd204_rx_avs_writedata          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
---      jesd204_rx_avs_clk_clk            : in  std_logic                     := 'X';             -- clk
---      jesd204_rx_avs_rst_n_reset_n      : in  std_logic                     := 'X';             -- reset_n
---      jesd204_rx_dlb_data_export        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
---      jesd204_rx_dlb_data_valid_export  : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- export
---      jesd204_rx_dlb_disperr_export     : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- export
---      jesd204_rx_dlb_errdetect_export   : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- export
---      jesd204_rx_dlb_kchar_data_export  : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- export
---      jesd204_rx_frame_error_export     : in  std_logic                     := 'X';             -- export
---      jesd204_rx_int_irq                : out std_logic;                                        -- irq
---      jesd204_rx_link_data              : out std_logic_vector(31 downto 0);                    -- data
---      jesd204_rx_link_valid             : out std_logic;                                        -- valid
---      jesd204_rx_link_ready             : in  std_logic                     := 'X';             -- ready
---      pll_ref_clk_clk                   : in  std_logic                     := 'X';             -- clk
---      rx_analogreset_rx_analogreset     : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- rx_analogreset
---      rx_cal_busy_rx_cal_busy           : out std_logic_vector(0 downto 0);                     -- rx_cal_busy
---      rx_digitalreset_rx_digitalreset   : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- rx_digitalreset
---      rx_islockedtodata_rx_is_lockedtodata : out std_logic_vector(0 downto 0);                     -- rx_is_lockedtodata
---      rx_serial_data_rx_serial_data     : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- rx_serial_data
---      rxlink_clk_clk                    : in  std_logic                     := 'X';             -- clk
---      rxlink_rst_n_reset_n              : in  std_logic                     := 'X';             -- reset_n
---      rxphy_clk_export                  : out std_logic_vector(0 downto 0);                     -- export
---      sof_export                        : out std_logic_vector(3 downto 0);                     -- export
---      somf_export                       : out std_logic_vector(3 downto 0);                     -- export
---      sysref_export                     : in  std_logic                     := 'X'              -- export
---    );
---  end component ip_arria10_e2sg_jesd204b_rx;
-
-  component ip_arria10_e2sg_jesd204b_rx_core_pll_cmp is
+
+    component ip_arria10_e2sg_jesd204b_rx is
+    port (
+      alldev_lane_aligned        : in  std_logic                     := 'X';             -- export
+      csr_cf                     : out std_logic_vector(4 downto 0);                     -- export
+      csr_cs                     : out std_logic_vector(1 downto 0);                     -- export
+      csr_f                      : out std_logic_vector(7 downto 0);                     -- export
+      csr_hd                     : out std_logic;                                        -- export
+      csr_k                      : out std_logic_vector(4 downto 0);                     -- export
+      csr_l                      : out std_logic_vector(4 downto 0);                     -- export
+      csr_lane_powerdown         : out std_logic_vector(0 downto 0);                     -- export
+      csr_m                      : out std_logic_vector(7 downto 0);                     -- export
+      csr_n                      : out std_logic_vector(4 downto 0);                     -- export
+      csr_np                     : out std_logic_vector(4 downto 0);                     -- export
+      csr_rx_testmode            : out std_logic_vector(3 downto 0);                     -- export
+      csr_s                      : out std_logic_vector(4 downto 0);                     -- export
+      dev_lane_aligned           : out std_logic;                                        -- export
+      dev_sync_n                 : out std_logic;                                        -- export
+      jesd204_rx_avs_chipselect  : in  std_logic                     := 'X';             -- chipselect
+      jesd204_rx_avs_address     : in  std_logic_vector(c_jesd204b_mm_addr_w-1 downto 0)  := (others => 'X'); -- address
+      jesd204_rx_avs_read        : in  std_logic                     := 'X';             -- read
+      jesd204_rx_avs_readdata    : out std_logic_vector(31 downto 0);                    -- readdata
+      jesd204_rx_avs_waitrequest : out std_logic;                                        -- waitrequest
+      jesd204_rx_avs_write       : in  std_logic                     := 'X';             -- write
+      jesd204_rx_avs_writedata   : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+      jesd204_rx_avs_clk         : in  std_logic                     := 'X';             -- clk
+      jesd204_rx_avs_rst_n       : in  std_logic                     := 'X';             -- reset_n
+      jesd204_rx_dlb_data        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+      jesd204_rx_dlb_data_valid  : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- export
+      jesd204_rx_dlb_disperr     : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- export
+      jesd204_rx_dlb_errdetect   : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- export
+      jesd204_rx_dlb_kchar_data  : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- export
+      jesd204_rx_frame_error     : in  std_logic                     := 'X';             -- export
+      jesd204_rx_int             : out std_logic;                                        -- irq
+      jesd204_rx_link_data       : out std_logic_vector(c_jesd204b_rx_data_w-1 downto 0);                    -- data
+      jesd204_rx_link_valid      : out std_logic;                                        -- valid
+      jesd204_rx_link_ready      : in  std_logic                     := 'X';             -- ready
+      pll_ref_clk                : in  std_logic                     := 'X';             -- clk
+      rx_analogreset             : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- rx_analogreset
+      rx_cal_busy                : out std_logic_vector(0 downto 0);                     -- rx_cal_busy
+      rx_digitalreset            : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- rx_digitalreset
+      rx_islockedtodata          : out std_logic_vector(0 downto 0);                     -- rx_is_lockedtodata
+      rx_serial_data             : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- rx_serial_data
+      rxlink_clk                 : in  std_logic                     := 'X';             -- clk
+      rxlink_rst_n_reset_n              : in  std_logic                     := 'X';             -- reset_n
+      rxphy_clk                  : out std_logic_vector(0 downto 0);                     -- export
+      sof                        : out std_logic_vector(3 downto 0);                     -- export
+      somf                       : out std_logic_vector(c_jesd204b_rx_somf_w-1 downto 0);                     -- export
+      sysref                     : in  std_logic                     := 'X'              -- export
+    );
+  end component ip_arria10_e2sg_jesd204b_rx;
+
+  component ip_arria10_e2sg_jesd204b_rx_core_pll is
     port (
       locked   : out std_logic;        -- export
       outclk_0 : out std_logic;        -- clk
@@ -164,66 +187,9 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
       refclk   : in  std_logic := 'X'; -- clk
       rst      : in  std_logic := 'X'  -- reset
     );
-  end component ip_arria10_e2sg_jesd204b_rx_core_pll_cmp;
-
-  component ip_arria10_e2sg_jesd204b_rx_reset_seq_cmp is
-    generic (
-      NUM_OUTPUTS                   : integer := 3;
-      ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
-      ENABLE_ASSERTION_SEQUENCE     : integer := 0;
-      ENABLE_DEASSERTION_SEQUENCE   : integer := 0;
-      MIN_ASRT_TIME                 : integer := 0;
-      ASRT_DELAY0                   : integer := 0;
-      DSRT_DELAY0                   : integer := 0;
-      ASRT_REMAP0                   : integer := 0;
-      DSRT_REMAP0                   : integer := 0;
-      DSRT_QUALCNT_0                : integer := 0;
-      ASRT_DELAY1                   : integer := 0;
-      DSRT_DELAY1                   : integer := 0;
-      ASRT_REMAP1                   : integer := 1;
-      DSRT_REMAP1                   : integer := 1;
-      DSRT_QUALCNT_1                : integer := 0;
-      ASRT_DELAY2                   : integer := 0;
-      DSRT_DELAY2                   : integer := 0;
-      ASRT_REMAP2                   : integer := 2;
-      DSRT_REMAP2                   : integer := 2;
-      DSRT_QUALCNT_2                : integer := 0;
-      ASRT_DELAY3                   : integer := 0;
-      DSRT_DELAY3                   : integer := 0;
-      ASRT_REMAP3                   : integer := 3;
-      DSRT_REMAP3                   : integer := 3;
-      DSRT_QUALCNT_3                : integer := 0;
-      ASRT_DELAY4                   : integer := 0;
-      DSRT_DELAY4                   : integer := 0;
-      ASRT_REMAP4                   : integer := 4;
-      DSRT_REMAP4                   : integer := 4;
-      DSRT_QUALCNT_4                : integer := 0;
-      ASRT_DELAY5                   : integer := 0;
-      DSRT_DELAY5                   : integer := 0;
-      ASRT_REMAP5                   : integer := 5;
-      DSRT_REMAP5                   : integer := 5;
-      DSRT_QUALCNT_5                : integer := 0;
-      ASRT_DELAY6                   : integer := 0;
-      DSRT_DELAY6                   : integer := 0;
-      ASRT_REMAP6                   : integer := 6;
-      DSRT_REMAP6                   : integer := 6;
-      DSRT_QUALCNT_6                : integer := 0;
-      ASRT_DELAY7                   : integer := 0;
-      DSRT_DELAY7                   : integer := 0;
-      ASRT_REMAP7                   : integer := 7;
-      DSRT_REMAP7                   : integer := 7;
-      DSRT_QUALCNT_7                : integer := 0;
-      ASRT_DELAY8                   : integer := 0;
-      DSRT_DELAY8                   : integer := 0;
-      ASRT_REMAP8                   : integer := 8;
-      DSRT_REMAP8                   : integer := 8;
-      DSRT_QUALCNT_8                : integer := 0;
-      ASRT_DELAY9                   : integer := 0;
-      DSRT_DELAY9                   : integer := 0;
-      ASRT_REMAP9                   : integer := 9;
-      DSRT_REMAP9                   : integer := 9;
-      DSRT_QUALCNT_9                : integer := 0
-    );
+  end component ip_arria10_e2sg_jesd204b_rx_core_pll;
+
+  component ip_arria10_e2sg_jesd204b_rx_reset_seq is
     port (
       av_address       : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- address
       av_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
@@ -246,9 +212,9 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
       reset_out6       : out std_logic;                                        -- reset
       reset_out7       : out std_logic                                         -- reset
     );
-  end component ip_arria10_e2sg_jesd204b_rx_reset_seq_cmp;
+  end component ip_arria10_e2sg_jesd204b_rx_reset_seq;
 
-  component ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12_cmp is
+  component ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12 is
     port (
       clock              : in  std_logic                     := 'X';             -- clk
       reset              : in  std_logic                     := 'X';             -- reset
@@ -258,72 +224,35 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
       rx_is_lockedtodata : in  std_logic_vector(11 downto 0) := (others => 'X'); -- rx_is_lockedtodata
       rx_ready           : out std_logic_vector(11 downto 0)                     -- rx_ready
     );
-  end component ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12_cmp;
+  end component ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12;
 
 
 
 BEGIN
 
-  jesd204b_frame_clk <= rxframe_clk;
+  rx_clk <= rxframe_clk;
+  rx_rst <= not core_pll_locked;
+
+  -- The avs clock is driven by the rxlink_clk for simulation. This is a workaround for a bug 
+  -- in the Q18.0 IP where the jesd receiver fails to recognize the SYSREF pulse
+  gen_simclock : IF g_sim = TRUE GENERATE
+    jesd204b_avs_clk <= rxlink_clk;
+  END GENERATE;
+
+  -- For synthesis the avs clock is driven by the mm_clk as usual
+  gen_synthclock : IF g_sim = FALSE GENERATE
+    jesd204b_avs_clk <= mm_clk;
+  END GENERATE;
+
   
   gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
-    gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+    gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
   
       -----------------------------------------------------------------------------
       -- The JESD204 IP (rx only)
       -----------------------------------------------------------------------------
---      u_ip_arria10_e2sg_jesd204b_rx : ip_arria10_e2sg_jesd204b_rx
---      PORT MAP 
---      (
---        jesd204_0_alldev_lane_aligned_export        => dev_lane_aligned_arr(i),
---        csr_cf_export                     => OPEN,
---        csr_cs_export                     => OPEN,
---        csr_f_export                      => OPEN, 
---        csr_hd_export                     => OPEN,
---        csr_k_export                      => OPEN,
---        csr_l_export                      => OPEN, 
---        csr_lane_powerdown_export         => rx_csr_lane_powerdown_arr(i downto i), 
---        csr_m_export                      => OPEN, 
---        csr_n_export                      => OPEN, 
---        csr_np_export                     => OPEN, 
---        csr_rx_testmode_export            => OPEN, 
---        csr_s_export                      => OPEN, 
---        dev_lane_aligned_export           => dev_lane_aligned_arr(i),           
---        dev_sync_n_export                 => jesd204b_sync_n_arr(i),
---        jesd204_rx_avs_chipselect         => '0', --jesd204b_mosi_arr(i).chipselect,
---        jesd204_rx_avs_address            => jesd204b_mosi_arr(i).address(7 downto 0),
---        jesd204_rx_avs_read               => jesd204b_mosi_arr(i).rd,
---        jesd204_rx_avs_readdata           => jesd204b_miso_arr(i).rddata(31 downto 0),
---        jesd204_rx_avs_waitrequest        => jesd204b_miso_arr(i).waitrequest,
---        jesd204_rx_avs_write              => jesd204b_mosi_arr(i).wr,
---        jesd204_rx_avs_writedata          => jesd204b_mosi_arr(i).wrdata(31 downto 0),
---        jesd204_rx_avs_clk_clk            => mm_clk,
---        jesd204_rx_avs_rst_n_reset_n      => rx_avs_rst_n_arr(i), -- Todo: Check if this could use mm_rst,
---        jesd204_rx_dlb_data_export        => (others => '0'), -- debug/loopback testing
---        jesd204_rx_dlb_data_valid_export  => (others => '0'), -- debug/loopback testing
---        jesd204_rx_dlb_disperr_export     => (others => '0'), -- debug/loopback testing
---        jesd204_rx_dlb_errdetect_export   => (others => '0'), -- debug/loopback testing
---        jesd204_rx_dlb_kchar_data_export  => (others => '0'), -- debug/loopback testing
---        jesd204_rx_frame_error_export     => '0',             -- jesd204_rx_frame_error.export
---        jesd204_rx_int_irq                => OPEN,            -- Connected to status IO in example design 
---        jesd204_rx_link_data              => jesd204b_rx_link_data_arr(i*32+31 DOWNTO i*32),
---        jesd204_rx_link_valid             => jesd204b_rx_link_valid_arr(i),
---        jesd204_rx_link_ready             => '1',
---        pll_ref_clk_clk                   => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63) 
---        rx_analogreset_rx_analogreset     => rx_analogreset_arr(I DOWNTO I),
---        rx_cal_busy_rx_cal_busy           => rx_cal_busy_arr(I DOWNTO I),
---        rx_digitalreset_rx_digitalreset   => rx_digitalreset_arr(I DOWNTO I),
---        rx_islockedtodata_rx_is_lockedtodata          => rx_islockedtodata_arr(I DOWNTO I),
---        rx_serial_data_rx_serial_data     => serial_rx_arr(i downto i),
---        rxlink_clk_clk                    => rxlink_clk,             -- TODO: still not clear if this should be 100MHz or 200MHz (Intel JESD204B-UG p63)
---        rxlink_rst_n_reset_n              => rxlink_rst_n_arr(i),    -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
---        rxphy_clk_export                  => OPEN,                   -- Not used in Subclass 0 (Intel JESD204B-UG p63)
---        sof_export                        => OPEN,
---        somf_export                       => OPEN,
---        sysref_export                     => jesd204b_sysref
---      );
-
-    u_ip_arria10_e2sg_jesd204b_rx : ENTITY ip_arria10_e2sg_jesd204b_rx.ip_arria10_e2sg_jesd204b_rx
+
+    u_ip_arria10_e2sg_jesd204b_rx : ip_arria10_e2sg_jesd204b_rx
       PORT MAP 
       (
         alldev_lane_aligned        => dev_lane_aligned_arr(i),
@@ -340,15 +269,15 @@ BEGIN
         csr_rx_testmode            => OPEN, 
         csr_s                      => OPEN, 
         dev_lane_aligned           => dev_lane_aligned_arr(i),           
-        dev_sync_n                 => jesd204b_sync_n_arr(i),
-        jesd204_rx_avs_chipselect         => '0', --jesd204b_mosi_arr(i).chipselect,
-        jesd204_rx_avs_address            => jesd204b_mosi_arr(i).address(7 downto 0),
+        dev_sync_n                 => jesd204b_sync_n_internal_arr(i),
+        jesd204_rx_avs_chipselect         => '1', --jesd204b_mosi_arr(i).chipselect,
+        jesd204_rx_avs_address            => jesd204b_mosi_arr(i).address(c_jesd204b_mm_addr_w-1 downto 0),
         jesd204_rx_avs_read               => jesd204b_mosi_arr(i).rd,
         jesd204_rx_avs_readdata           => jesd204b_miso_arr(i).rddata(31 downto 0),
         jesd204_rx_avs_waitrequest        => jesd204b_miso_arr(i).waitrequest,
         jesd204_rx_avs_write              => jesd204b_mosi_arr(i).wr,
         jesd204_rx_avs_writedata          => jesd204b_mosi_arr(i).wrdata(31 downto 0),
-        jesd204_rx_avs_clk                => mm_clk,
+        jesd204_rx_avs_clk                => jesd204b_avs_clk, --mm_clk,
         jesd204_rx_avs_rst_n              => rx_avs_rst_n_arr(i), -- Todo: Check if this could use mm_rst,
         jesd204_rx_dlb_data               => (others => '0'), -- debug/loopback testing
         jesd204_rx_dlb_data_valid  => (others => '0'), -- debug/loopback testing
@@ -357,7 +286,7 @@ BEGIN
         jesd204_rx_dlb_kchar_data  => (others => '0'), -- debug/loopback testing
         jesd204_rx_frame_error     => '0',             -- jesd204_rx_frame_error.export
         jesd204_rx_int             => OPEN,            -- Connected to status IO in example design 
-        jesd204_rx_link_data              => jesd204b_rx_link_data_arr(i*32+31 DOWNTO i*32),
+        jesd204_rx_link_data              => jesd204b_rx_link_data_arr(i*c_jesd204b_rx_data_w+c_jesd204b_rx_data_w-1 DOWNTO i*c_jesd204b_rx_data_w),
         jesd204_rx_link_valid             => jesd204b_rx_link_valid_arr(i),
         jesd204_rx_link_ready             => '1',
         pll_ref_clk                => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63) 
@@ -370,14 +299,14 @@ BEGIN
         rxlink_rst_n_reset_n       => rxlink_rst_n_arr(i),    -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
         rxphy_clk                  => OPEN,                   -- Not used in Subclass 0 (Intel JESD204B-UG p63)
         sof                        => OPEN,
-        somf                       => OPEN,
-        sysref                     => jesd204b_sysref
+        somf                       => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_somf_w-1 downto c_jesd204b_rx_somf_w*i),
+        sysref                     => jesd204b_sysref_2
       );
 
       -----------------------------------------------------------------------------
       -- Reset sequencer for each channel
       -----------------------------------------------------------------------------
-      u_ip_arria10_e2sg_jesd204b_rx_reset_seq : ENTITY ip_arria10_e2sg_jesd204b_rx_reset_seq.ip_arria10_e2sg_jesd204b_rx_reset_seq
+      u_ip_arria10_e2sg_jesd204b_rx_reset_seq : ip_arria10_e2sg_jesd204b_rx_reset_seq
       PORT MAP (
         av_address                 => reset_seq_mosi_arr(i).address(7 downto 0), -- in  std_logic_vector(7 downto 0)  := (others => '0'); 
         av_readdata                => reset_seq_miso_arr(i).rddata(31 downto 0),
@@ -401,7 +330,8 @@ BEGIN
         reset_out7                 => rxframe_rst_arr(i)
       );
 
-      rx_xcvr_ready_in_arr(i) <= rx_csr_lane_powerdown_arr(i) OR xcvr_rst_ctrl_rx_ready_arr(i);
+      --rx_xcvr_ready_in_arr(i) <= rx_csr_lane_powerdown_arr(i) OR xcvr_rst_ctrl_rx_ready_arr(i);
+      rx_xcvr_ready_in_arr(i) <= '1' when  rx_csr_lane_powerdown_arr(i)='1' OR xcvr_rst_ctrl_rx_ready_arr(i)='1' else '0';
 
       -- Invert thr active-low resets
       rx_avs_rst_n_arr(i) <= not rx_avs_rst_arr(i);
@@ -409,6 +339,7 @@ BEGIN
       rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i);
      
 
+
       -----------------------------------------------------------------------------
       -- Minimal deframer (transport layer)
       -----------------------------------------------------------------------------
@@ -416,17 +347,21 @@ BEGIN
       BEGIN
         IF rising_edge(rxframe_clk) THEN
           IF rxframe_rst_n_arr(i) = '0' THEN
-            rx_src_out_arr(i).data(15 downto 0)  <= (OTHERS => '0');
+            rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w-1 downto 0)  <= (OTHERS => '0');
+            rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w-1 downto 0)  <= (OTHERS => '0');
             f2_div1_cnt_arr(i) <= '0';
           ELSE
             rx_src_out_arr(i).valid <= jesd204b_rx_link_valid_arr(i);
             IF jesd204b_rx_link_valid_arr(i) = '0' THEN
-              rx_src_out_arr(i).data(15 downto 0)  <= (OTHERS => '0');
+              rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w-1 downto 0)  <= (OTHERS => '0');
+              rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w-1 downto 0)  <= (OTHERS => '0');
             ELSE
               IF f2_div1_cnt_arr(i) = '1' THEN
-                rx_src_out_arr(i).data(15 downto 0)  <= jesd204b_rx_link_data_arr(32*i+15 downto 32*i);
+                rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w-1 downto 0)    <= jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w*i+c_jesd204b_rx_framer_data_w-1 downto c_jesd204b_rx_data_w*i);
+                rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w-1 downto 0)  <= jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_framer_somf_w-1 downto c_jesd204b_rx_somf_w*i);
               ELSE
-                rx_src_out_arr(i).data(15 downto 0)  <= jesd204b_rx_link_data_arr(32*i+31 downto 32*i+16);
+                rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w-1 downto 0)    <= jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w*i+c_jesd204b_rx_data_w-1 downto c_jesd204b_rx_data_w*i+c_jesd204b_rx_framer_data_w);
+                rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w-1 downto 0)  <= jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_somf_w-1 downto c_jesd204b_rx_somf_w*i+c_jesd204b_rx_framer_somf_w);
               END IF; 
               f2_div1_cnt_arr(i) <= not f2_div1_cnt_arr(i);
             END IF; 
@@ -435,9 +370,48 @@ BEGIN
       END PROCESS;
 
     END GENERATE;  
+
+    -----------------------------------------------------------------------------
+    -- Reclock sysref
+    -----------------------------------------------------------------------------
+    p_reclocksysref : PROCESS (rxlink_clk, core_pll_locked)
+    BEGIN
+      IF core_pll_locked = '0' THEN
+        jesd204b_sysref_1 <= '0';
+        jesd204b_sysref_2 <= '0';
+      ELSE
+        IF rising_edge(rxlink_clk) THEN
+          jesd204b_sysref_1 <= jesd204b_sysref;
+          jesd204b_sysref_2 <= jesd204b_sysref_1;
+        END IF;
+      END IF;
+    END PROCESS;
+
+    -----------------------------------------------------------------------------
+    -- Capture sysref on the frame clock for export
+    -----------------------------------------------------------------------------
+    p_rx_sysref : PROCESS (rxframe_clk, core_pll_locked)
+    BEGIN
+      IF core_pll_locked = '0' THEN
+        jesd204b_sysref_frameclk_1 <= '0';
+        jesd204b_sysref_frameclk_2 <= '0';
+        rx_sysref <= '0';
+      ELSE
+        IF rising_edge(rxframe_clk) THEN
+          jesd204b_sysref_frameclk_1 <= jesd204b_sysref;
+          jesd204b_sysref_frameclk_2 <= jesd204b_sysref_frameclk_1;
+          IF jesd204b_sysref_frameclk_1 = '1' and jesd204b_sysref_frameclk_2 = '0' THEN
+            rx_sysref <= '1';
+          ELSE
+            rx_sysref <= '0';
+          END IF;
+        END IF;
+      END IF;
+    END PROCESS;
+
   
     -- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66)
-    u_ip_arria10_e2sg_jesd204b_rx_corepll : ENTITY ip_arria10_e2sg_jesd204b_rx_core_pll.ip_arria10_e2sg_jesd204b_rx_core_pll
+    u_ip_arria10_e2sg_jesd204b_rx_corepll : ip_arria10_e2sg_jesd204b_rx_core_pll
     PORT MAP (
       locked                      => core_pll_locked,
       outclk_0                    => rxlink_clk,
@@ -458,10 +432,10 @@ BEGIN
     END PROCESS;
  
 
-    -- Transceiver reset controller. Use g_nof_channels out of 12 channels. Receive only
+    -- Transceiver reset controller. Use g_nof_streams out of 12 channels. Receive only
     -- Clock set to 100MHz (use mm_clk)
 
-    u_ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control : ENTITY ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12
+    u_ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control : ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12
     PORT MAP (
       clock                        => mm_clk,
       reset                        => xcvr_rst_arr(0),        -- From Reset Sequencer output1 as per example design
@@ -474,13 +448,21 @@ BEGIN
 
   END GENERATE;
 
+
+  -----------------------------------------------------------------------------
+  -- Group the SYNC_N outputs
+  -----------------------------------------------------------------------------
+  gen_group_sync_n : FOR i IN 0 TO g_nof_sync_n-1 GENERATE
+      jesd204b_sync_n_arr(i) <= vector_and(jesd204b_sync_n_internal_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
+  END GENERATE;
+
   -----------------------------------------------------------------------------
   -- MM bus mux
   -----------------------------------------------------------------------------
   u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
   GENERIC MAP (    
-    g_nof_mosi    => g_nof_channels,
-    g_mult_addr_w => 8 
+    g_nof_mosi    => g_nof_streams,
+    g_mult_addr_w => c_jesd204b_mm_addr_w 
   )
   PORT MAP (
     mosi     => jesd204b_mosi,
@@ -489,5 +471,8 @@ BEGIN
     miso_arr => jesd204b_miso_arr
   );  
 
+
   
 END str;
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
index d30d7f16bee770d2c03ddd9d4c7521aeb2a2a520..3c49f86f24e7259ccc8a1b584fa3a02cd2997d1d 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
@@ -3,7 +3,7 @@ hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_1_altera_
 hdl_lib_uses_synth = 
 hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_194
 hdl_lib_technology = ip_arria10_e2sg
-
+    
 synth_files =
     
 test_bench_files = 
diff --git a/libraries/technology/mac_10g/hdllib.cfg b/libraries/technology/mac_10g/hdllib.cfg
index c922483ad86242bafb51561600cc5021751d8df7..6d2d975753912695220c1609e501bf0e534e5797 100644
--- a/libraries/technology/mac_10g/hdllib.cfg
+++ b/libraries/technology/mac_10g/hdllib.cfg
@@ -9,7 +9,9 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_mac_10g        ip_arria10_mac_10g_alt_em10g32_150
     ip_arria10_e3sge3_mac_10g ip_arria10_e3sge3_mac_10g_alt_em10g32_151
     ip_arria10_e1sg_mac_10g   ip_arria10_e1sg_mac_10g_alt_em10g32_180
-    ip_arria10_e2sg_mac_10g   ip_arria10_e2sg_mac_10g_alt_em10g32_180
+    ip_arria10_e2sg_mac_10g   ip_arria10_e2sg_mac_10g_alt_em10g32_194
+
+
 
 synth_files =
     tech_mac_10g_component_pkg.vhd