From 151ad8d0f038aa5fece58752dd6864fa1104d33c Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Wed, 15 Nov 2017 14:48:11 +0000
Subject: [PATCH] -Added constants to fix multiple driver issue with some
combinations of generics. -Added comments to better explain the pipelining
options.
---
libraries/base/dp/src/vhdl/dp_counter.vhd | 40 ++++++++++++++---------
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git a/libraries/base/dp/src/vhdl/dp_counter.vhd b/libraries/base/dp/src/vhdl/dp_counter.vhd
index 78858f8422..648c6ac27a 100644
--- a/libraries/base/dp/src/vhdl/dp_counter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter.vhd
@@ -28,6 +28,9 @@
-- . dp_counter_func contains only functional logic (no pipelining).
-- . This wrapper adds pipelining for the source side outputs (g_pipeline_src_out)
-- and source side inputs (g_pipeline_src_in).
+-- Remarks:
+-- . Unfortunately there is no way to use g_nof_counters in another generic, hence
+-- the hardcoded range (9 DOWNTO 0) instead of g_nof_counters-1 DOWNTO 0.
LIBRARY IEEE,common_lib;
USE IEEE.std_logic_1164.ALL;
@@ -37,12 +40,12 @@ USE work.dp_stream_pkg.ALL;
ENTITY dp_counter IS
GENERIC (
- g_nof_counters : NATURAL;
- g_range_start : t_natural_arr(9 DOWNTO 0) := array_init(0, 10);
- g_range_stop : t_natural_arr(9 DOWNTO 0) := array_init(0, 10);
- g_range_step : t_natural_arr(9 DOWNTO 0) := array_init(0, 10);
- g_pipeline_src_out : NATURAL := 1;
- g_pipeline_src_in : NATURAL := 0 -- Will become 0 if g_pipeline_src_out=0
+ g_nof_counters : NATURAL; -- Limited to 10 due to below hardcoded ranges
+ g_range_start : t_natural_arr(9 DOWNTO 0) := array_init(0, 10); --g_nof_counters-1 DOWNTO 0 actually
+ g_range_stop : t_natural_arr(9 DOWNTO 0) := array_init(0, 10); --g_nof_counters-1 DOWNTO 0 actually
+ g_range_step : t_natural_arr(9 DOWNTO 0) := array_init(0, 10); --g_nof_counters-1 DOWNTO 0 actually
+ g_pipeline_src_out : NATURAL := 1; -- Pipeline source outputs (data,valid,sop,eop etc)
+ g_pipeline_src_in : NATURAL := 0 -- Pipeline source inputs (ready,xon). This will also pipeline src_out.
);
PORT (
clk : IN STD_LOGIC;
@@ -61,6 +64,9 @@ END dp_counter;
ARCHITECTURE wrap OF dp_counter IS
+ CONSTANT c_use_dp_pipeline : BOOLEAN := (g_pipeline_src_out>0 AND g_pipeline_src_in=0);
+ CONSTANT c_use_dp_pipeline_ready : BOOLEAN := (g_pipeline_src_in>0);
+
SIGNAL dp_counter_func_src_out_arr : t_dp_sosi_arr(g_nof_counters-1 DOWNTO 0);
BEGIN
@@ -85,9 +91,9 @@ BEGIN
);
------------------------------------------------------------------------------
- -- dp_pipeline if g_pipeline_src_out > 0
+ -- dp_pipeline
------------------------------------------------------------------------------
- gen_dp_pipeline : IF g_pipeline_src_out > 0 GENERATE
+ gen_dp_pipeline : IF c_use_dp_pipeline = TRUE GENERATE
u_dp_pipeline_snk_in : ENTITY work.dp_pipeline
GENERIC MAP (
g_pipeline => g_pipeline_src_out
@@ -120,15 +126,10 @@ BEGIN
END GENERATE;
END GENERATE;
- no_dp_pipeline : IF g_pipeline_src_out = 0 GENERATE
- src_out <= snk_in;
- snk_out <= src_in;
- END GENERATE;
-
------------------------------------------------------------------------------
- -- dp_pipeline_ready if g_pipeline_src_in > 0
+ -- dp_pipeline_ready
------------------------------------------------------------------------------
- gen_dp_pipeline_ready : IF g_pipeline_src_in > 0 GENERATE
+ gen_dp_pipeline_ready : IF c_use_dp_pipeline_ready = TRUE GENERATE
u_dp_pipeline_ready : ENTITY work.dp_pipeline_ready
GENERIC MAP (
g_in_latency => 1
@@ -161,4 +162,13 @@ BEGIN
END GENERATE;
END GENERATE;
+ ------------------------------------------------------------------------------
+ -- No pipelining
+ ------------------------------------------------------------------------------
+ no_dp_pipeline : IF c_use_dp_pipeline=FALSE AND c_use_dp_pipeline_ready=FALSE GENERATE
+ src_out <= snk_in;
+ snk_out <= src_in;
+ END GENERATE;
+
+
END wrap;
--
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