diff --git a/applications/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd b/applications/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b4fb015965b6aa6f8b4af7c679e07e4794165252 --- /dev/null +++ b/applications/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd @@ -0,0 +1,199 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2012 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +-- Purpose: Test bench for fn_bf +-- The DUT can be targeted at unb 0, fn 3 with the same Python scripts +-- that are used on hardware. + + +LIBRARY IEEE, common_lib, unb_common_lib, i2c_lib, bf_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_lib.common_pkg.ALL; +USE unb_common_lib.unb_common_pkg.ALL; +USE common_lib.tb_common_pkg.ALL; +USE bf_lib.bf_pkg.ALL; + +ENTITY tb_fn_bf IS +GENERIC( + -- TYPE t_c_bf IS RECORD + -- nof_signal_paths : POSITIVE; -- = 64 + -- nof_input_streams : POSITIVE; -- = 16 + -- nof_subbands : POSITIVE; -- = 24 + -- nof_weights : POSITIVE; -- = 256 + -- nof_bf_units : POSITIVE; -- = 4 + -- in_dat_w : POSITIVE; -- = 16 + -- in_weight_w : POSITIVE; -- = 16 + -- bst_gain_w : INTEGER; -- = 1 + -- bst_dat_w : POSITIVE; -- = 16 + -- out_gain_w : INTEGER; -- = -5 + -- out_dat_w : POSITIVE; -- = 8 + -- stat_data_w : POSITIVE; -- = 56 + -- stat_data_sz : POSITIVE; -- = 2 + -- END RECORD; + g_bf : t_c_bf := (64, 16, 24, 256, 4, 16, 16, 1, 16, -5, 8, 56, 2) +); +END tb_fn_bf; + +ARCHITECTURE tb OF tb_fn_bf IS + + CONSTANT c_sim : BOOLEAN := TRUE; + + CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0 + CONSTANT c_node_nr : NATURAL := 3; -- Front node 3 + CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb_nof_uniboard_w ) & TO_UVEC(c_node_nr, c_unb_nof_chip_w); + + CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; + CONSTANT c_fw_version : t_unb_fw_version := (1, 0); + + CONSTANT c_cable_delay : TIME := 12 ns; + CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard + CONSTANT c_clk_period : TIME := 1 ns; + CONSTANT c_pps_period : NATURAL := 1000; + + -- DUT + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL pps : STD_LOGIC := '0'; + SIGNAL pps_rst : STD_LOGIC := '0'; + + SIGNAL WDI : STD_LOGIC; + SIGNAL INTA : STD_LOGIC; + SIGNAL INTB : STD_LOGIC; + + SIGNAL eth_clk : STD_LOGIC := '0'; + SIGNAL eth_txp : STD_LOGIC; + SIGNAL eth_rxp : STD_LOGIC; + + SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb_aux.version_w-1 DOWNTO 0) := c_version; + SIGNAL ID : STD_LOGIC_VECTOR(c_unb_aux.id_w-1 DOWNTO 0) := c_id; + SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb_aux.testio_w-1 DOWNTO 0); + + SIGNAL sens_scl : STD_LOGIC; + SIGNAL sens_sda : STD_LOGIC; + + -- Model I2C sensor slaves as on the UniBoard + CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW + CONSTANT c_fpga_temp : INTEGER := 60; + CONSTANT c_eth_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0101001"; -- MAX1618 address MID LOW + CONSTANT c_eth_temp : INTEGER := 40; + CONSTANT c_hot_swap_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000100"; -- LTC4260 address L L L + CONSTANT c_hot_swap_R_sense : REAL := 0.01; -- = 10 mOhm on UniBoard + + CONSTANT c_uniboard_current : REAL := 5.0; -- = assume 5.0 A on UniBoard + CONSTANT c_uniboard_supply : REAL := 48.0; -- = assume 48.0 V on UniBoard + CONSTANT c_uniboard_adin : REAL := -1.0; -- = NC on UniBoard + +BEGIN + + ---------------------------------------------------------------------------- + -- System setup + ---------------------------------------------------------------------------- + clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz) + eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz) + + INTA <= 'H'; -- pull up + INTB <= 'H'; -- pull up + + sens_scl <= 'H'; -- pull up + sens_sda <= 'H'; -- pull up + + ------------------------------------------------------------------------------ + -- External PPS + ------------------------------------------------------------------------------ + proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps); + + ------------------------------------------------------------------------------ + -- 1GbE Loopback model + ------------------------------------------------------------------------------ + eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay; + + ------------------------------------------------------------------------------ + -- DUT + ------------------------------------------------------------------------------ + u_dut : ENTITY work.fn_bf + GENERIC MAP ( + g_sim => c_sim, + g_sim_unb_nr => c_unb_nr, + g_sim_node_nr => c_node_nr, + g_bf => g_bf + ) + PORT MAP ( + -- GENERAL + CLK => clk, + PPS => pps, + WDI => WDI, + INTA => INTA, + INTB => INTB, + + sens_sc => sens_scl, + sens_sd => sens_sda, + + -- Others + VERSION => VERSION, + ID => ID, + TESTIO => TESTIO, + + -- 1GbE Control Interface + ETH_clk => eth_clk, + ETH_SGIN => eth_rxp, + ETH_SGOUT => eth_txp + ); + + ------------------------------------------------------------------------------ + -- UniBoard sensors + ------------------------------------------------------------------------------ + -- I2C slaves that are available for each FPGA + u_fpga_temp : ENTITY i2c_lib.dev_max1618 + GENERIC MAP ( + g_address => c_fpga_temp_address + ) + PORT MAP ( + scl => sens_scl, + sda => sens_sda, + temp => c_fpga_temp + ); + + -- I2C slaves that are available only via FPGA back node 3 + u_eth_temp : ENTITY i2c_lib.dev_max1618 + GENERIC MAP ( + g_address => c_eth_temp_address + ) + PORT MAP ( + scl => sens_scl, + sda => sens_sda, + temp => c_eth_temp + ); + + u_power : ENTITY i2c_lib.dev_ltc4260 + GENERIC MAP ( + g_address => c_hot_swap_address, + g_R_sense => c_hot_swap_R_sense + ) + PORT MAP ( + scl => sens_scl, + sda => sens_sda, + ana_current_sense => c_uniboard_current, + ana_volt_source => c_uniboard_supply, + ana_volt_adin => c_uniboard_adin + ); + +END tb;