diff --git a/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd deleted file mode 100644 index fbb57a6c0ff7b8c3037c3adad36ed70083133620..0000000000000000000000000000000000000000 --- a/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd +++ /dev/null @@ -1,302 +0,0 @@ -------------------------------------------------------------------------------- --- --- Copyright 2020 --- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> --- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- -------------------------------------------------------------------------------- - -------------------------------------------------------------------------------- --- --- Author: J.W.E. Oudman --- Purpose: Create a histogram from the input data and present it to the MM bus --- Description: --- --- --- -------------------------------------------------------------------------------- - -LIBRARY IEEE, common_lib, mm_lib, dp_lib; -USE IEEE.std_logic_1164.ALL; -USE common_lib.common_pkg.ALL; -USE common_lib.tb_common_pkg.ALL; -USE common_lib.common_mem_pkg.ALL; -USE common_lib.tb_common_mem_pkg.ALL; -USE dp_lib.dp_stream_pkg.ALL; - -ENTITY tb_mms_st_histogram IS - GENERIC( - g_sync_length : NATURAL := 338; - g_nof_sync : NATURAL := 3; - g_data_w : NATURAL := 4; - g_nof_bins : NATURAL := 8; - g_nof_data : NATURAL := 338; - g_str : STRING := "freq.density"; - g_valid_gap : BOOLEAN := FALSE; - g_snk_in_data_sim_type : STRING := "counter" -- "counter" or "toggle" - ); -END tb_mms_st_histogram; - - -ARCHITECTURE tb OF tb_mms_st_histogram IS - - CONSTANT c_adr_w : NATURAL := ceil_log2(g_nof_bins); - - CONSTANT c_mm_init_time : NATURAL := 5; - CONSTANT c_dp_inti_time : NATURAL := 5; - - SIGNAL tb_end : STD_LOGIC := '0'; - SIGNAL first_sync : STD_LOGIC := '0'; - - ---------------------------------------------------------------------------- - -- Clocks and resets - ---------------------------------------------------------------------------- - CONSTANT c_mm_clk_period : TIME := 20 ns; - CONSTANT c_dp_clk_period : TIME := 5 ns; - - - SIGNAL mm_rst : STD_LOGIC := '1'; - SIGNAL mm_clk : STD_LOGIC := '1'; - - SIGNAL dp_rst : STD_LOGIC; - SIGNAL dp_clk : STD_LOGIC := '1'; - - - - - ---------------------------------------------------------------------------- - -- Streaming Input - ---------------------------------------------------------------------------- - - SIGNAL st_histogram_snk_in : t_dp_sosi; - - ---------------------------------------------------------------------------- - -- Memory Mapped Input - ---------------------------------------------------------------------------- - - SIGNAL st_histogram_ram_mosi : t_mem_mosi; - SIGNAL st_histogram_ram_miso : t_mem_miso; - - -BEGIN - - ---------------------------------------------------------------------------- - -- Clock and reset generation - ---------------------------------------------------------------------------- - mm_clk <= NOT mm_clk OR tb_end AFTER c_mm_clk_period/2; - mm_rst <= '1', '0' AFTER c_mm_clk_period*c_mm_init_time; - - dp_clk <= NOT dp_clk OR tb_end AFTER c_dp_clk_period/2; - dp_rst <= '1', '0' AFTER c_dp_clk_period*c_dp_inti_time; - - - - - ---------------------------------------------------------------------------- - -- Source: counter stimuli - ---------------------------------------------------------------------------- - - p_data : PROCESS(dp_rst, dp_clk, st_histogram_snk_in) - BEGIN - IF g_snk_in_data_sim_type = "counter" THEN - IF dp_rst='1' THEN - st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= (OTHERS=>'0'); - ELSIF rising_edge(dp_clk) AND st_histogram_snk_in.valid='1' THEN - st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= INCR_UVEC(st_histogram_snk_in.data(g_data_w-1 DOWNTO 0), 1); - END IF; - ELSIF g_snk_in_data_sim_type = "toggle" THEN - IF dp_rst='1' THEN - st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= (OTHERS=>'0'); - ELSIF rising_edge(dp_clk) AND st_histogram_snk_in.valid='1' THEN - IF st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) = TO_UVEC(0, g_data_w) THEN - st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= TO_UVEC(1, g_data_w); - ELSE - st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= TO_UVEC(0, g_data_w); - END IF; - END IF; - END IF; - END PROCESS; - - p_stimuli : PROCESS - BEGIN - IF g_valid_gap = FALSE THEN --- dp_rst <= '1'; - st_histogram_snk_in.sync <= '0'; - st_histogram_snk_in.valid <= '0'; - WAIT UNTIL rising_edge(dp_clk); --- FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP; --- dp_rst <= '0'; - FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP; - st_histogram_snk_in.valid <= '1'; - - - FOR I IN 0 TO g_nof_sync-1 LOOP - st_histogram_snk_in.sync <= '1'; - WAIT UNTIL rising_edge(dp_clk); - st_histogram_snk_in.sync <= '0'; - FOR I IN 0 TO g_sync_length-1 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP; - - END LOOP; - FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP; - tb_end <= '1'; - WAIT; - - ELSIF g_valid_gap = TRUE THEN --- dp_rst <= '1'; - st_histogram_snk_in.sync <= '0'; - st_histogram_snk_in.valid <= '0'; - WAIT UNTIL rising_edge(dp_clk); --- FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP; --- dp_rst <= '0'; - FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP; - st_histogram_snk_in.valid <= '1'; - - - FOR I IN 0 TO g_nof_sync-2 LOOP - st_histogram_snk_in.sync <= '1'; - WAIT UNTIL rising_edge(dp_clk); - st_histogram_snk_in.sync <= '0'; - FOR I IN 0 TO (g_sync_length/2)-1 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP; - st_histogram_snk_in.valid <= '0'; - WAIT UNTIL rising_edge(dp_clk); - --WAIT UNTIL rising_edge(dp_clk); - --WAIT UNTIL rising_edge(dp_clk); - st_histogram_snk_in.valid <= '1'; - FOR I IN 0 TO (g_sync_length/4)-1 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP; - st_histogram_snk_in.valid <= '0'; - WAIT UNTIL rising_edge(dp_clk); - --st_histogram_snk_in.valid <= '0'; - st_histogram_snk_in.sync <= '1'; - WAIT UNTIL rising_edge(dp_clk); - st_histogram_snk_in.valid <= '1'; - st_histogram_snk_in.sync <= '0'; - FOR I IN 0 TO (g_sync_length/4)-1 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP; - - END LOOP; - FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP; - tb_end <= '1'; - WAIT; - END IF; - END PROCESS; - - ---------------------------------------------------------------------------- - -- Source: read MM bus stimuli - ---------------------------------------------------------------------------- - --- p_mm_stimuli : PROCESS --(st_histogram_snk_in.sync) --- BEGIN --- IF mm_rst='1' THEN --- st_histogram_ram_mosi <= c_mem_mosi_rst; --.address(c_adr_w-1 DOWNTO 0) <= (OTHERS=>'0'); ----- ELSIF rising_edge(mm_clk) THEN --AND st_histogram_snk_in.valid='1' --- ELSE --- IF first_sync = '0' THEN --- WAIT UNTIL st_histogram_snk_in.sync = '1'; --- first_sync <= '1'; --- -- wait till one RAM block is written --- FOR I IN 0 TO (g_sync_length/4) LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP; --- -- wait for some more cycles --- FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP; ----- ELSIF rising_edge(mm_clk) THEN --- ELSE --- FOR I IN 0 TO g_nof_bins-1 --- -- --- st_histogram_ram_mosi.rd <= '1'; --- st_histogram_ram_mosi.address(c_adr_w-1 DOWNTO 0) <= INCR_UVEC(st_histogram_ram_mosi.address(c_adr_w-1 DOWNTO 0), 1); --- END IF; --- END IF; --- END PROCESS; - - p_mm_stimuli : PROCESS --(st_histogram_snk_in.sync) - BEGIN - --IF mm_rst='1' THEN - st_histogram_ram_mosi <= c_mem_mosi_rst; --.address(c_adr_w-1 DOWNTO 0) <= (OTHERS=>'0'); --- ELSIF rising_edge(mm_clk) THEN --AND st_histogram_snk_in.valid='1' - --ELSE - --IF first_sync = '0' THEN - WAIT UNTIL st_histogram_snk_in.sync = '1'; - --first_sync <= '1'; - -- wait till one RAM block is written - FOR I IN 0 TO (g_sync_length/4) LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP; - -- wait for some more cycles - FOR I IN 0 TO 2 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP; --- ELSIF rising_edge(mm_clk) THEN - --ELSE - FOR I IN 0 TO g_nof_bins-1 LOOP - proc_mem_mm_bus_rd(I, mm_clk, st_histogram_ram_mosi); - proc_common_wait_some_cycles(mm_clk, 11); - -- miso.rddata arrives - END LOOP; - -- - --st_histogram_ram_mosi.rd <= '1'; - --st_histogram_ram_mosi.address(c_adr_w-1 DOWNTO 0) <= INCR_UVEC(st_histogram_ram_mosi.address(c_adr_w-1 DOWNTO 0), 1); - --END IF; - --END IF; - END PROCESS; - --- -- Read data request to the MM bus --- -- Use proc_mem_mm_bus_rd_latency() to wait for the MM MISO rd_data signal --- -- to show the data after some read latency --- PROCEDURE proc_mem_mm_bus_rd(CONSTANT rd_addr : IN NATURAL; --- SIGNAL mm_clk : IN STD_LOGIC; --- SIGNAL mm_miso : IN t_mem_miso; --- SIGNAL mm_mosi : OUT t_mem_mosi) IS --- BEGIN --- mm_mosi.address <= TO_MEM_ADDRESS(rd_addr); --- proc_mm_access(mm_clk, mm_miso.waitrequest, mm_mosi.rd); --- END proc_mem_mm_bus_rd; - ----- Issues a rd or a wr MM access and wait for it to have finished --- PROCEDURE proc_mm_access(SIGNAL mm_clk : IN STD_LOGIC; --- SIGNAL mm_waitreq : IN STD_LOGIC; --- SIGNAL mm_access : OUT STD_LOGIC) IS --- BEGIN --- mm_access <= '1'; --- WAIT UNTIL rising_edge(mm_clk); --- WHILE mm_waitreq='1' LOOP --- WAIT UNTIL rising_edge(mm_clk); --- END LOOP; --- mm_access <= '0'; --- END proc_mm_access; - --- proc_mem_mm_bus_rd(0, mm_clk, mm_mosi); -- Read nof_early_syncs --- proc_common_wait_some_cycles(mm_clk, 1); --- mm_nof_early_syncs <= mm_miso.rddata(c_word_w-1 DOWNTO 0); - - ---------------------------------------------------------------------------- - -- DUT: Device Under Test - ---------------------------------------------------------------------------- - - u_mms_st_histogram : ENTITY work.mms_st_histogram - GENERIC MAP( - g_in_data_w => g_data_w, - g_nof_bins => g_nof_bins, - g_nof_data => g_nof_data, - g_str => g_str - ) - PORT MAP ( - dp_rst => dp_rst, - dp_clk => dp_clk, - mm_rst => mm_rst, - mm_clk => mm_clk, - - -- Streaming - snk_in => st_histogram_snk_in, - - -- Memory Mapped - ram_mosi => st_histogram_ram_mosi, - ram_miso => st_histogram_ram_miso --OPEN - ); - -END tb;