diff --git a/applications/compaan/designs/compaan_unb1_dp_offload/src/vhdl/compaan_unb1_dp_offload.vhd b/applications/compaan/designs/compaan_unb1_dp_offload/src/vhdl/compaan_unb1_dp_offload.vhd
index 473f276ad7453ed3dad0d12a6a4d0113da7fc21e..122e9d0097c847a61db253ff94b92295c32d501a 100644
--- a/applications/compaan/designs/compaan_unb1_dp_offload/src/vhdl/compaan_unb1_dp_offload.vhd
+++ b/applications/compaan/designs/compaan_unb1_dp_offload/src/vhdl/compaan_unb1_dp_offload.vhd
@@ -433,6 +433,7 @@ BEGIN
u_ctrl_unb1_board : ENTITY unb1_board_lib.ctrl_unb1_board
GENERIC MAP (
g_sim => g_sim,
+ g_sim_flash_model => FALSE,
g_design_name => c_design_name,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
index 76e1bced67d4b588418cdffe5b10e7b737fae927..3a0dcd21954fbd0972d536a9635d20341e0e0c3d 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
@@ -42,15 +42,16 @@ ENTITY ctrl_unb1_board IS
----------------------------------------------------------------------------
-- General
----------------------------------------------------------------------------
- g_technology : NATURAL := c_tech_stratixiv;
- g_sim : BOOLEAN := FALSE;
- g_design_name : STRING := "UNUSED";
- g_fw_version : t_unb1_board_fw_version := (0, 0); -- firmware version x.y
- g_stamp_date : NATURAL := 0;
- g_stamp_time : NATURAL := 0;
- g_stamp_svn : NATURAL := 0;
- g_design_note : STRING := "UNUSED";
- g_mm_clk_freq : NATURAL := c_unb1_board_mm_clk_freq_125M; -- default use same MM clock as for TSE clock
+ g_technology : NATURAL := c_tech_stratixiv;
+ g_sim : BOOLEAN := FALSE;
+ g_sim_flash_model : BOOLEAN := TRUE; -- only maximum one instance should have the flash model (see mms_epcs.vhd description)
+ g_design_name : STRING := "UNUSED";
+ g_fw_version : t_unb1_board_fw_version := (0, 0); -- firmware version x.y
+ g_stamp_date : NATURAL := 0;
+ g_stamp_time : NATURAL := 0;
+ g_stamp_svn : NATURAL := 0;
+ g_design_note : STRING := "UNUSED";
+ g_mm_clk_freq : NATURAL := c_unb1_board_mm_clk_freq_125M; -- default use same MM clock as for TSE clock
----------------------------------------------------------------------------
-- External CLK
@@ -513,6 +514,9 @@ BEGIN
-- EPCS
-----------------------------------------------------------------------------
u_mms_epcs: ENTITY epcs_lib.mms_epcs
+ GENERIC MAP (
+ g_sim_flash_model => g_sim_flash_model
+ )
PORT MAP (
mm_rst => i_mm_rst,
mm_clk => mm_clk,
diff --git a/libraries/io/epcs/src/vhdl/mms_epcs.vhd b/libraries/io/epcs/src/vhdl/mms_epcs.vhd
index 8d2ce47ef8463baddc4d2868a2d3d002f5da5bac..ac108c28fe4ee4516b743fc983839edf2121b6a8 100644
--- a/libraries/io/epcs/src/vhdl/mms_epcs.vhd
+++ b/libraries/io/epcs/src/vhdl/mms_epcs.vhd
@@ -19,13 +19,27 @@
--
-------------------------------------------------------------------------------
--- Note: To simulate this module, I've added an M25P128 simulation model (source: Numonyx)
--- to the generated ALTASMI_PARALLEL megafunction code, and hooked it up to the correct signals
--- internally.
--- Note 2: The simulation model requires real-life (long) powerup delays to be used. Refer to
--- /tb/vhdl/m25p128_model/lib/TimingData.vhd for the delays and references to the corresponding
--- table in the data sheet. These constants can be modified for faster simulation, but I've left them
--- as they were as simulating one page write and read is sufficient.
+-- Purpose: Provide read and write access to flash
+-- Description:
+-- . g_sim_flash_model
+-- When g_sim_flash_model=TRUE then the m25p128.vhd flash model is
+-- instantiated in ip_stratixiv_asmi_parallel forsimulation. It needs to be
+-- instantiated inside the IP, because the flash IO isnot available at
+-- the port IO, because sythesis automatically connects it to the proper
+-- pins.
+-- However the m25p128.vhd flash model uses shared variables. This
+-- probably causes the failure: "Signal 'blockboundary' has multiple
+-- drivers but is not a resolved signal". Therefore ensure that there is
+-- only one instance of mms_epcs that has g_sim_flash_model=TRUE.
+--
+-- Remarks:
+-- . To simulate this module, DS added an M25P128 simulation model (source: Numonyx)
+-- to the generated ALTASMI_PARALLEL megafunction code, and hooked it up to the correct signals
+-- internally.
+-- . The simulation model requires real-life (long) powerup delays to be used. Refer to
+-- /tb/vhdl/m25p128_model/lib/TimingData.vhd for the delays and references to the corresponding
+-- table in the data sheet. These constants can be modified for faster simulation, but I've left them
+-- as they were as simulating one page write and read is sufficient.
LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_flash_lib;
@@ -40,8 +54,8 @@ USE tech_flash_lib.tech_flash_component_pkg.ALL;
ENTITY mms_epcs IS
GENERIC (
- g_technology : NATURAL := c_tech_select_default;
- g_sim : BOOLEAN := FALSE
+ g_technology : NATURAL := c_tech_select_default;
+ g_sim_flash_model : BOOLEAN := FALSE
);
PORT (
mm_rst : IN STD_LOGIC;
@@ -211,7 +225,8 @@ BEGIN
u_asmi_parallel: ENTITY tech_flash_lib.tech_flash_asmi_parallel
GENERIC MAP (
- g_technology => g_technology
+ g_technology => g_technology,
+ g_sim_flash_model => g_sim_flash_model
)
PORT MAP (
addr => epcs_in_addr,
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index 6202680f61e95d5f37eba24f81740c6390560e92..35ed38ba5b4ed222d92aacb3393d6fe0155b3300 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -33,7 +33,8 @@ LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_141;
ENTITY tech_flash_asmi_parallel IS
GENERIC (
- g_technology : NATURAL := c_tech_select_default
+ g_technology : NATURAL := c_tech_select_default;
+ g_sim_flash_model : BOOLEAN := FALSE
);
PORT (
addr : IN STD_LOGIC_VECTOR (tech_flash_addr_w(g_technology)-1 DOWNTO 0);
@@ -64,6 +65,7 @@ BEGIN
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
u0 : ip_stratixiv_asmi_parallel
+ GENERIC MAP (g_sim_flash_model)
PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write);
END GENERATE;
diff --git a/libraries/technology/flash/tech_flash_component_pkg.vhd b/libraries/technology/flash/tech_flash_component_pkg.vhd
index 0ad3159ff65469680041e980a5099ff585570a91..243954ce2a9a32a03fe647ddf85236e405516dbd 100644
--- a/libraries/technology/flash/tech_flash_component_pkg.vhd
+++ b/libraries/technology/flash/tech_flash_component_pkg.vhd
@@ -32,6 +32,9 @@ PACKAGE tech_flash_component_pkg IS
-----------------------------------------------------------------------------
COMPONENT ip_stratixiv_asmi_parallel IS
+ GENERIC (
+ g_sim_flash_model : BOOLEAN := FALSE
+ );
PORT (
addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
clkin : IN STD_LOGIC ;
diff --git a/libraries/technology/ip_stratixiv/flash/ip_stratixiv_asmi_parallel.vhd b/libraries/technology/ip_stratixiv/flash/ip_stratixiv_asmi_parallel.vhd
index 1e3f83df1107c07c6b8bd6b3bb72ac52ddf9ccab..e91cad5402b94003f3093ff3d3af513413086975 100644
--- a/libraries/technology/ip_stratixiv/flash/ip_stratixiv_asmi_parallel.vhd
+++ b/libraries/technology/ip_stratixiv/flash/ip_stratixiv_asmi_parallel.vhd
@@ -45,6 +45,8 @@
LIBRARY stratixiv;
USE stratixiv.all;
+ --The m25p128.vhd flash model uses shared variables. This probably causes the failure Signal 'blockboundary' has multiple drivers but is not a resolved signal.
+ --Therefore ensure that there is only one instance of ip_stratixiv_asmi_parallel that has g_sim_flash_model=TRUE.
LIBRARY numonyx_m25p128_lib;
--synthesis_resources = a_graycounter 4 lpm_compare 2 lpm_counter 2 lut 29 mux21 1 reg 106 stratixiv_asmiblock 1
@@ -52,6 +54,9 @@
USE ieee.std_logic_1164.all;
ENTITY ip_stratixiv_asmi_parallel_altasmi_parallel_15a2 IS
+ GENERIC (
+ g_sim_flash_model : BOOLEAN := FALSE
+ );
PORT
(
addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
@@ -891,6 +896,7 @@
END COMPONENT;
BEGIN
+ gen_sim_flash_model : IF g_sim_flash_model=TRUE GENERATE
-- ASTRON, DS:
-- ==========
-- synthesis translate_off
@@ -909,6 +915,7 @@
Q => wire_stratixii_asmiblock2_data0out
);
-- synthesis translate_on
+ END GENERATE; --gen_sim_flash_model
wire_w552w(0) <= wire_w_lg_w_lg_w_lg_w_lg_do_write394w549w550w551w(0) AND end_operation;
wire_w359w(0) <= wire_w_lg_w_lg_w_lg_w_lg_do_read312w356w357w358w(0) AND end_read_byte;
@@ -2246,6 +2253,9 @@ LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ip_stratixiv_asmi_parallel IS
+ GENERIC (
+ g_sim_flash_model : BOOLEAN := FALSE
+ );
PORT
(
addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
@@ -2283,6 +2293,9 @@ ARCHITECTURE RTL OF ip_stratixiv_asmi_parallel IS
COMPONENT ip_stratixiv_asmi_parallel_altasmi_parallel_15a2
+ GENERIC (
+ g_sim_flash_model : BOOLEAN := FALSE
+ );
PORT (
illegal_write : OUT STD_LOGIC ;
read : IN STD_LOGIC ;
@@ -2309,6 +2322,9 @@ BEGIN
busy <= sub_wire4;
ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component : ip_stratixiv_asmi_parallel_altasmi_parallel_15a2
+ GENERIC MAP (
+ g_sim_flash_model => g_sim_flash_model
+ )
PORT MAP (
read => read,
shift_bytes => shift_bytes,