diff --git a/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd b/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
index eca9a6f5feb89e3ce158d8557206b9fa1728ceab..762c6642ddcf13db22ce69aded518d0a832b806c 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
@@ -46,10 +46,10 @@ ENTITY dp_fifo_monitor IS
     reg_mosi     : IN  t_mem_mosi;
     reg_miso     : OUT t_mem_miso;
     -- Status inputs
-    rd_usedw_32b : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-    wr_usedw_32b : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-    rd_emp       : IN  STD_LOGIC;
-    wr_full      : IN  STD_LOGIC;
+    rd_usedw_32b : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS=>'0');
+    wr_usedw_32b : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS=>'0');
+    rd_emp       : IN  STD_LOGIC := '0';
+    wr_full      : IN  STD_LOGIC := '0';
     -- Control output
     rd_fill_32b  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)
   );
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
index a502447b997ed780b8de1e2452f25f3340128a51..43b92ab50af2b46f9287d0e8db84a7663c48667a 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
@@ -48,10 +48,10 @@ ENTITY dp_fifo_monitor_arr IS
     reg_mosi         : IN  t_mem_mosi;
     reg_miso         : OUT t_mem_miso;
     -- Status inputs
-    rd_usedw_32b_arr : IN  t_slv_32_arr(g_nof_streams-1 DOWNTO 0);
-    wr_usedw_32b_arr : IN  t_slv_32_arr(g_nof_streams-1 DOWNTO 0); 
-    rd_emp_arr       : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
-    wr_full_arr      : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+    rd_usedw_32b_arr : IN  t_slv_32_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+    wr_usedw_32b_arr : IN  t_slv_32_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0')); 
+    rd_emp_arr       : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'0');
+    wr_full_arr      : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'0');
     -- Control output
     rd_fill_32b_arr  : OUT t_slv_32_arr(g_nof_streams-1 DOWNTO 0)
   );