diff --git a/libraries/base/dp/designs/unb1_dp_offload/quartus/sopc_unb1_dp_offload.sopc b/libraries/base/dp/designs/unb1_dp_offload/quartus/sopc_unb1_dp_offload.sopc
index 73aa8c0feb367c36cd333be91d51e48bc9e34d86..67b1ad38f7295b8b4517d5f936ccf50265bc8cf9 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/quartus/sopc_unb1_dp_offload.sopc
+++ b/libraries/base/dp/designs/unb1_dp_offload/quartus/sopc_unb1_dp_offload.sopc
@@ -22,7 +22,7 @@
{
datum _sortIndex
{
- value = "21";
+ value = "20";
type = "int";
}
}
@@ -100,7 +100,15 @@
type = "String";
}
}
- element pio_system_info.mem
+ element ram_diag_data_buffer.mem
+ {
+ datum baseAddress
+ {
+ value = "65536";
+ type = "long";
+ }
+ }
+ element reg_wdi.mem
{
datum _lockedAddress
{
@@ -109,64 +117,56 @@
}
datum baseAddress
{
- value = "0";
+ value = "12288";
type = "long";
}
}
- element reg_diag_bg.mem
+ element rom_system_info.mem
{
- datum baseAddress
+ datum _lockedAddress
{
- value = "12480";
- type = "long";
+ value = "1";
+ type = "boolean";
}
- }
- element reg_dp_offload_tx.mem
- {
datum baseAddress
{
- value = "12448";
+ value = "4096";
type = "long";
}
}
- element reg_bsn_monitor.mem
+ element ram_diag_bg.mem
{
datum baseAddress
{
- value = "256";
+ value = "16384";
type = "long";
}
}
- element reg_dp_offload_tx_hdr_ovr.mem
+ element reg_diag_data_buffer.mem
{
datum baseAddress
{
- value = "512";
+ value = "128";
type = "long";
}
}
- element ram_diag_bg.mem
+ element reg_dp_offload_rx_hdr_dat.mem
{
datum baseAddress
{
- value = "16384";
+ value = "13312";
type = "long";
}
}
- element reg_wdi.mem
+ element reg_bsn_monitor.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "12288";
+ value = "256";
type = "long";
}
}
- element rom_system_info.mem
+ element pio_system_info.mem
{
datum _lockedAddress
{
@@ -175,47 +175,39 @@
}
datum baseAddress
{
- value = "4096";
- type = "long";
- }
- }
- element reg_dp_offload_rx_hdr_dat.mem
- {
- datum baseAddress
- {
- value = "13312";
+ value = "0";
type = "long";
}
}
- element ram_diag_data_buffer.mem
+ element reg_dp_offload_tx.mem
{
datum baseAddress
{
- value = "65536";
+ value = "12448";
type = "long";
}
}
- element reg_unb_sens.mem
+ element reg_diag_bg.mem
{
datum baseAddress
{
- value = "12416";
+ value = "12480";
type = "long";
}
}
- element reg_diag_data_buffer.mem
+ element reg_dp_offload_tx_hdr_dat.mem
{
datum baseAddress
{
- value = "128";
+ value = "1024";
type = "long";
}
}
- element reg_dp_offload_tx_hdr_dat.mem
+ element reg_unb_sens.mem
{
datum baseAddress
{
- value = "1024";
+ value = "12416";
type = "long";
}
}
@@ -302,7 +294,7 @@
{
datum _sortIndex
{
- value = "20";
+ value = "19";
type = "int";
}
}
@@ -310,7 +302,7 @@
{
datum _sortIndex
{
- value = "18";
+ value = "17";
type = "int";
}
}
@@ -326,7 +318,7 @@
{
datum _sortIndex
{
- value = "19";
+ value = "18";
type = "int";
}
}
@@ -334,7 +326,7 @@
{
datum _sortIndex
{
- value = "17";
+ value = "16";
type = "int";
}
}
@@ -362,14 +354,6 @@
type = "int";
}
}
- element reg_dp_offload_tx_hdr_ovr
- {
- datum _sortIndex
- {
- value = "16";
- type = "int";
- }
- }
element reg_unb_sens
{
datum _sortIndex
@@ -410,6 +394,14 @@
type = "long";
}
}
+ element pio_debug_wave.s1
+ {
+ datum baseAddress
+ {
+ value = "12512";
+ type = "long";
+ }
+ }
element onchip_memory2_0.s1
{
datum _lockedAddress
@@ -423,14 +415,6 @@
type = "long";
}
}
- element pio_debug_wave.s1
- {
- datum baseAddress
- {
- value = "12512";
- type = "long";
- }
- }
element sopc_unb1_dp_offload
{
}
@@ -456,8 +440,8 @@
<parameter name="maxAdditionalLatency" value="0" />
<parameter name="projectName" value="unb1_dp_offload.qpf" />
<parameter name="sopcBorderPoints" value="true" />
- <parameter name="systemHash" value="-39580360459" />
- <parameter name="timeStamp" value="1424864115588" />
+ <parameter name="systemHash" value="-36996923733" />
+ <parameter name="timeStamp" value="1443001043877" />
<parameter name="useTestBenchNamingPattern" value="false" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="25000000" />
@@ -558,7 +542,7 @@
<parameter name="dcache_numTCDM" value="_0" />
<parameter name="dcache_lineSize" value="_32" />
<parameter name="dcache_bursts" value="false" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_bsn_monitor.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x400' end='0x800' /><slave name='avs_eth_0.mms_reg' start='0x800' end='0x840' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='altpll_0.pll_slave' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='reg_unb_sens.mem' start='0x3080' end='0x30A0' /><slave name='reg_dp_offload_tx.mem' start='0x30A0' end='0x30C0' /><slave name='reg_diag_bg.mem' start='0x30C0' end='0x30E0' /><slave name='pio_debug_wave.s1' start='0x30E0' end='0x30F0' /><slave name='pio_wdi.s1' start='0x30F0' end='0x3100' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_diag_bg.mem' start='0x4000' end='0x8000' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_bsn_monitor.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x400' end='0x800' /><slave name='avs_eth_0.mms_reg' start='0x800' end='0x840' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='altpll_0.pll_slave' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='reg_unb_sens.mem' start='0x3080' end='0x30A0' /><slave name='reg_dp_offload_tx.mem' start='0x30A0' end='0x30C0' /><slave name='reg_diag_bg.mem' start='0x30C0' end='0x30E0' /><slave name='pio_debug_wave.s1' start='0x30E0' end='0x30F0' /><slave name='pio_wdi.s1' start='0x30F0' end='0x3100' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_diag_bg.mem' start='0x4000' end='0x8000' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="dataAddrWidth" value="18" />
<parameter name="customInstSlavesSystemInfo" value="<info/>" />
<parameter name="cpuReset" value="false" />
@@ -873,15 +857,6 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module>
- <module
- kind="avs_common_mm"
- version="1.0"
- enabled="1"
- name="reg_dp_offload_tx_hdr_ovr">
- <parameter name="g_adr_w" value="7" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
<module
kind="avs_common_mm"
version="1.0"
@@ -1114,19 +1089,6 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3400" />
</connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_dp_offload_tx_hdr_ovr.system" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="reg_dp_offload_tx_hdr_ovr.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0200" />
- </connection>
<connection
kind="clock"
version="11.1"
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
index aeff89de0f148a11b949030823e7784c506fb420..a8e47f11248840b28820c365a3cb621fefba0e2d 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
@@ -108,9 +108,6 @@ ENTITY mmm_unb1_dp_offload IS
reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
reg_dp_offload_tx_hdr_dat_miso : IN t_mem_miso;
- reg_dp_offload_tx_hdr_ovr_mosi : OUT t_mem_mosi;
- reg_dp_offload_tx_hdr_ovr_miso : IN t_mem_miso;
-
reg_dp_offload_rx_hdr_dat_mosi : OUT t_mem_mosi;
reg_dp_offload_rx_hdr_dat_miso : IN t_mem_miso;
@@ -244,9 +241,6 @@ BEGIN
u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
- u_mm_file_reg_dp_offload_tx_hdr_ovr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_OVR")
- PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_ovr_mosi, reg_dp_offload_tx_hdr_ovr_miso );
-
u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
@@ -412,15 +406,6 @@ BEGIN
coe_write_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wr,
coe_writedata_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
- -- the_reg_dp_offload_tx_hdr_ovr
- coe_address_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.address(c_reg_dp_offload_tx_hdr_ovr_multi_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_dp_offload_tx_hdr_ovr => OPEN,
- coe_read_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_dp_offload_tx_hdr_ovr => OPEN,
- coe_write_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-- the_reg_dp_offload_rx_hdr_dat
coe_address_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
index 55818d73bd51badc972caf5bec1f5d1289a85f67..711a0b57a82f36414df7ff71a440cef1acf89dd9 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
@@ -78,20 +78,14 @@ END unb1_dp_offload;
ARCHITECTURE str OF unb1_dp_offload IS
CONSTANT c_design_name : STRING := "unb1_dp_offload";
-
- CONSTANT c_lpbk_data_w : NATURAL := 32; -- 128 c_tech_tse_data_w, c_xgmii_data_w
-
- -- Revision controlled constants
- CONSTANT c_use_1GbE : BOOLEAN := TRUE;
- CONSTANT c_nof_streams : NATURAL := 3;
-
+ CONSTANT c_nof_streams : NATURAL := 1;
CONSTANT c_data_w : NATURAL := c_tech_tse_data_w;
-- Block generator
CONSTANT c_bg_block_size : NATURAL := 900;
CONSTANT c_bg_gapsize : NATURAL := 100;
CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
- CONSTANT c_bg_ctrl : t_diag_block_gen := ('1', -- enable
+ CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable
'0', -- enable_sync
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
@@ -103,13 +97,13 @@ ARCHITECTURE str OF unb1_dp_offload IS
-- dp_offload_tx
CONSTANT c_nof_hdr_fields : NATURAL := 4+12+4+9; -- Total header bits = 512
CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(x"002286080000") ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(128) ),
( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
@@ -118,11 +112,11 @@ ARCHITECTURE str OF unb1_dp_offload IS
( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(4000) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(4000) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(108) ),
( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
@@ -132,23 +126,10 @@ ARCHITECTURE str OF unb1_dp_offload IS
( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
- CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111011111100"&"0001"&"101111111";
+ CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1101"&"111111111100"&"1111"&"001111111";
- CONSTANT c_use_jumbo_frames : BOOLEAN := TRUE;
- CONSTANT c_def_1GbE_block_size : NATURAL := 0; -- 0 first so we have time to set RX demux reg in dest. node
-
- CONSTANT c_max_frame_len : NATURAL := sel_a_b(c_use_jumbo_frames, 9018, 1518);
- CONSTANT c_max_frame_nof_words : NATURAL := (c_max_frame_len * c_byte_w ) / c_data_w;
- CONSTANT c_nof_header_words : NATURAL := field_slv_len(c_hdr_field_arr) / c_data_w;
- CONSTANT c_nof_header_bytes : NATURAL := field_slv_len(c_hdr_field_arr) / c_byte_w;
- CONSTANT c_nof_crc_words : NATURAL := 1;
- CONSTANT c_max_udp_payload_len : NATURAL := c_max_frame_len-c_nof_header_bytes-c_network_eth_crc_len;
- CONSTANT c_max_udp_payload_nof_words : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w;
- CONSTANT c_max_nof_words_per_block : NATURAL := c_bg_block_size;
- CONSTANT c_min_nof_words_per_block : NATURAL := 1;
- CONSTANT c_def_nof_words_per_block : NATURAL := sel_a_b(c_use_1GbE, c_def_1GbE_block_size, c_bg_block_size);
- CONSTANT c_max_nof_blocks_per_packet : NATURAL := c_max_udp_payload_nof_words/c_min_nof_words_per_block;
- CONSTANT c_def_nof_blocks_per_packet : NATURAL := 1;
+ CONSTANT c_nof_words_per_block : NATURAL := 11;
+ CONSTANT c_nof_blocks_per_packet : NATURAL := 2;
SIGNAL hdr_fields_in_arr : t_slv_1024_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_streams-1 DOWNTO 0);
@@ -194,8 +175,6 @@ ARCHITECTURE str OF unb1_dp_offload IS
SIGNAL reg_dp_offload_tx_miso : t_mem_miso;
SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
- SIGNAL reg_dp_offload_tx_hdr_ovr_mosi : t_mem_mosi;
- SIGNAL reg_dp_offload_tx_hdr_ovr_miso : t_mem_miso;
SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
@@ -209,6 +188,9 @@ ARCHITECTURE str OF unb1_dp_offload IS
SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL block_gen_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+ SIGNAL dp_offload_tx_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+
SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
@@ -221,11 +203,8 @@ ARCHITECTURE str OF unb1_dp_offload IS
SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
- -- Interface: 1GbE UDP streaming ports
- SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_fifo_fill_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_fifo_fill_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
BEGIN
@@ -256,6 +235,31 @@ BEGIN
ram_bg_data_miso => ram_diag_bg_miso
);
+ ---------------------------------------------------------------------------------------
+ -- Use a FIFO when the source has no flow control
+ -- . unless source is 100% valid, read note in dp_offload_tx
+ ---------------------------------------------------------------------------------------
+ gen_dp_fifo_sc : FOR i IN 0 TO c_nof_streams-1 GENERATE
+ u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
+ GENERIC MAP (
+ g_data_w => c_data_w,
+ g_use_bsn => TRUE,
+ g_bsn_w => 64,
+ g_use_sync => TRUE,
+ g_fifo_size => 100
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => block_gen_src_out_arr(i),
+ snk_out => block_gen_src_in_arr(i),
+
+ src_out => dp_offload_tx_snk_in_arr(i),
+ src_in => dp_offload_tx_snk_out_arr(i)
+ );
+ END GENERATE;
+
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
@@ -264,13 +268,11 @@ BEGIN
g_nof_streams => c_nof_streams,
g_data_w => c_data_w,
g_use_complex => FALSE,
- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_def_nof_words_per_block => c_def_nof_words_per_block,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet,
- g_def_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_nof_words_per_block => c_nof_words_per_block,
+ g_nof_blocks_per_packet => c_nof_blocks_per_packet,
g_hdr_field_arr => c_hdr_field_arr,
g_hdr_field_sel => c_hdr_field_ovr_init,
- g_use_post_split_fifo => TRUE -- BG does NOT have ready flow control and out header takes more cycles than the inter-block gap.
+ g_use_post_split_fifo => TRUE
)
PORT MAP (
mm_rst => mm_rst,
@@ -279,14 +281,11 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
- reg_mosi => reg_dp_offload_tx_mosi,
- reg_miso => reg_dp_offload_tx_miso,
-
reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
- snk_in_arr => block_gen_src_out_arr,
- snk_out_arr => block_gen_src_in_arr,
+ snk_in_arr => dp_offload_tx_snk_in_arr,
+ snk_out_arr => dp_offload_tx_snk_out_arr,
src_out_arr => dp_offload_tx_src_out_arr,
src_in_arr => dp_offload_tx_src_in_arr,
@@ -295,38 +294,13 @@ BEGIN
);
gen_hdr_in_fields : FOR i IN 0 TO c_nof_streams-1 GENERATE
- -- dst = src
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_dst_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_dst_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr")) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_dst_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_dst_addr")) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
- -- dst port goes through 4000,4001,4002
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_src_port") DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= TO_UVEC(4000+i, 16);
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port") DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= TO_UVEC(4000+i, 16);
-
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_sync" ) DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )) <= slv(block_gen_src_out_arr(i).sync);
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )) <= block_gen_src_out_arr(i).bsn(59 DOWNTO 0);
- END GENERATE;
-
- -----------------------------------------------------------------------------
- -- Interface : Loopback
- -----------------------------------------------------------------------------
- gen_loopback : IF c_use_1GbE=FALSE GENERATE
- dp_offload_rx_snk_in_arr <= dp_offload_tx_src_out_arr;
- dp_offload_tx_src_in_arr <= (OTHERS=>c_dp_siso_rdy);
- END GENERATE;
-
- -----------------------------------------------------------------------------
- -- Interface : 1GbE
- -----------------------------------------------------------------------------
- gen_wires_1GbE : IF c_use_1GbE=TRUE GENERATE
- eth1g_udp_tx_sosi_arr <= dp_offload_tx_src_out_arr;
- dp_offload_tx_src_in_arr <= eth1g_udp_tx_siso_arr;
-
- dp_offload_rx_snk_in_arr <= eth1g_udp_rx_sosi_arr;
- eth1g_udp_rx_siso_arr <= dp_offload_rx_snk_out_arr;
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_sync" ) DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )) <= slv(dp_offload_tx_snk_in_arr(i).sync);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )) <= dp_offload_tx_snk_in_arr(i).bsn(59 DOWNTO 0);
END GENERATE;
-----------------------------------------------------------------------------
@@ -337,8 +311,8 @@ BEGIN
g_nof_streams => c_nof_streams,
g_data_w => c_data_w,
g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => c_use_1GbE,
- g_crc_nof_words => c_nof_crc_words
+ g_remove_crc => TRUE,
+ g_crc_nof_words => 1
)
PORT MAP (
mm_rst => mm_rst,
@@ -381,7 +355,7 @@ BEGIN
GENERIC MAP (
g_nof_streams => c_nof_streams,
g_cross_clock_domain => TRUE,
- g_sync_timeout => c_bg_blocks_per_sync*(c_bg_block_size+c_bg_gapsize),
+ g_sync_timeout => 2*c_bg_blocks_per_sync*(c_bg_block_size+c_bg_gapsize),
g_cnt_sop_w => ceil_log2(c_bg_blocks_per_sync+1),
g_cnt_valid_w => ceil_log2(c_bg_blocks_per_sync*c_bg_block_size+1),
g_log_first_bsn => TRUE
@@ -433,7 +407,7 @@ BEGIN
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn,
g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_udp_offload => c_use_1GbE,
+ g_udp_offload => TRUE,
g_udp_offload_nof_streams => c_nof_streams,
g_dp_clk_use_pll => FALSE
)
@@ -472,10 +446,10 @@ BEGIN
eth1g_ram_miso => eth1g_ram_miso,
-- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+ udp_tx_sosi_arr => dp_offload_tx_src_out_arr,
+ udp_tx_siso_arr => dp_offload_tx_src_in_arr,
+ udp_rx_sosi_arr => dp_offload_rx_snk_in_arr,
+ udp_rx_siso_arr => dp_offload_rx_snk_out_arr,
-- system_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
@@ -565,9 +539,6 @@ BEGIN
reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
- reg_dp_offload_tx_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
- reg_dp_offload_tx_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
-
reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
diff --git a/libraries/base/dp/designs/unb1_dp_offload/tb/python/tc_unb1_dp_offload.py b/libraries/base/dp/designs/unb1_dp_offload/tb/python/tc_unb1_dp_offload.py
index 13bc01f671f2a27d3179f98f680e62e6389cb84b..de716f529409264c61252b601161cf93a78dbb24 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/tb/python/tc_unb1_dp_offload.py
+++ b/libraries/base/dp/designs/unb1_dp_offload/tb/python/tc_unb1_dp_offload.py
@@ -25,9 +25,9 @@
# Description:
# . Usage:
# . Sim: Target only one node *after 2us*:
-# $ python tc_unb_dp_offload.py --unb 0 --fn 0 -r 0:2 --sim
+# $ python tc_unb_dp_offload.py --unb 0 --fn 0 -r 0 --sim
# . Synth: Target any TWO nodes:
-# $ python tc_unb_dp_offload.py --unb 0 --fn 0,1 -r 0:2
+# $ python tc_unb_dp_offload.py --unb 0 --fn 0,1 -r 0
from common import *
@@ -53,10 +53,11 @@ tc = test_case.Testcase('TB - ', '')
io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
BASE_MAC = 0x2286080000
-NOF_STREAMS = 3
-NOF_BLOCKS_PER_SYNC = 1
-NOF_WORDS_PER_BLOCK_TEST_RANGE = [11, 6, 2, 1]
-NOF_BLOCKS_PER_PACKET_TEST_RANGE = [ 1, 2, 7, 13]
+NOF_STREAMS = 1
+NOF_BLOCKS_PER_SYNC = 5
+NOF_WORDS_PER_BLOCK = 11
+NOF_BLOCKS_PER_PACKET = 2
+BLOCK_LEN = NOF_WORDS_PER_BLOCK * NOF_BLOCKS_PER_PACKET
tc.set_result('PASSED')
tc.append_log(3, '>>>')
@@ -64,9 +65,9 @@ tc.append_log(1, '>>> Title : Test case for design unb_dp_offload. Targets: %s'
tc.append_log(3, '>>>')
tc.append_log(3, '')
+bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, nofChannels=NOF_STREAMS, ramSizePerChannel=1024)
dpotx = pi_dp_offload_tx.PiDpOffloadTx(tc, io, nof_inst=NOF_STREAMS)
dpotx_hdr_dat = pi_dp_offload_tx_hdr_dat_unb_dp_offload.PiDpOffloadTxHdrDatUnbDpOffload(tc, io, nof_inst=NOF_STREAMS)
-dpotx_hdr_ovr = pi_dp_offload_tx_hdr_ovr_unb_dp_offload.PiDpOffloadTxHdrOvrUnbDpOffload(tc, io, nof_inst=NOF_STREAMS)
info = pi_system_info.PiSystemInfo(tc, io)
mon = pi2_bsn_monitor.PiBsnMonitor(tc, io, nof_inst=NOF_STREAMS)
@@ -99,40 +100,24 @@ if tc.sim==False:
eth_dst_mac[0] = tc.nodeNrs[0]%8
dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('eth_dst_mac', eth_dst_mac.data)], regmap=dpotx_hdr_dat.regmap)
- # Now override the eth_dst_mac field so it is no longer read from the data path but from the MM register we've just written to.
- dpotx_hdr_ovr.write(inst_nrs=tc.gpNumbers, registers=[('eth_dst_mac', 1)], regmap=dpotx_hdr_ovr.regmap)
+bg.write_enable()
-for rep in range(tc.repeat):
+# Declare our reference values
+ref = { 'xon_stable' : 1,
+ 'ready_stable' : 1,
+ 'sync_timeout' : 0,
+# 'bsn_at_sync' : 0 ,# increments every second on HW
+ 'nof_sop' : NOF_BLOCKS_PER_SYNC,
+ 'nof_valid' : NOF_BLOCKS_PER_SYNC*BLOCK_LEN,
+ 'nof_err' : 0,
+ 'block_len' : BLOCK_LEN}
+# 'nof_sync' : 0 } # increments every second on HW
- for i in range(len(NOF_WORDS_PER_BLOCK_TEST_RANGE)):
+# Wiat for one sync interval so out BSN monitor values are valid
+do_until_eq( method=mon.read, val=NOF_BLOCKS_PER_SYNC, ms_retry=1000, s_timeout=20, inst_nrs=tc.gpNumbers, registers=['nof_sop'], regmap=mon.regmap, flatten_result=True)
- # Write the dp_offload_tx settings
- registers = [('nof_words_per_block', NOF_WORDS_PER_BLOCK_TEST_RANGE[i]), ('nof_blocks_per_packet', NOF_BLOCKS_PER_PACKET_TEST_RANGE[i])]
- dpotx.write(inst_nrs=tc.gpNumbers, registers=registers, regmap=dpotx.regmap)
-
- # Calculate our reference block size
- block_len = NOF_WORDS_PER_BLOCK_TEST_RANGE[i] * NOF_BLOCKS_PER_PACKET_TEST_RANGE[i]
-
- # Declare our reference values
- ref = { 'xon_stable' : 1,
- 'ready_stable' : 1,
- 'sync_timeout' : 0,
- # 'bsn_at_sync' : 0 ,# increments every second on HW
- 'nof_sop' : NOF_BLOCKS_PER_SYNC,
- 'nof_valid' : NOF_BLOCKS_PER_SYNC*block_len,
- 'nof_err' : 0,
- 'block_len' : block_len}
- # 'nof_sync' : 0 } # increments every second on HW
-
- # Keep reading the block_len at the RX side until it matches our settings at the TX side
- do_until_retry_interval = sel_a_b(tc.sim, 2000, 1)
- do_until_timeout_interval = sel_a_b(tc.sim, 300, 1)
- do_until_block_len = do_until_eq( method=mon.read, val=block_len, ms_retry=do_until_retry_interval, s_timeout=do_until_timeout_interval, inst_nrs=tc.gpNumbers, registers=['block_len'], regmap=mon.regmap, flatten_result=True)
-
- # Read BSN moitors and compare to reference
- pi_common.ref_compare(tc, mon.read(inst_nrs=tc.gpNumbers, regmap=mon.regmap), ref)
-
- time.sleep(tc.time)
+# Read BSN moitors and compare to reference
+pi_common.ref_compare(tc, mon.read(inst_nrs=tc.gpNumbers, regmap=mon.regmap), ref)
###############################################################################
# end