diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1361c5cb2a170f68378bed539835710e5ac66e0c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
@@ -0,0 +1,155 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on Megawizard-generated file msim_setup.tcl.
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+
+# Assume library work already exists
+
+# Compile the design files in correct order and map them all to library work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_mm_st_converter.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_addr_cmd.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_addr_cmd_wrap.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_ddr2_odt_gen.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_ddr3_odt_gen.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_lpddr2_addr_cmd.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_odt_gen.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_rdwr_data_tmg.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_arbiter.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_burst_gen.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_cmd_gen.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_csr.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_buffer.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_buffer_manager.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_burst_tracking.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_dataid_manager.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_fifo.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_list.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_rdata_path.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_wdata_path.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_ecc_decoder.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_ecc_decoder_32_syn.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_ecc_decoder_64_syn.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_ecc_encoder.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_ecc_encoder_32_syn.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_ecc_encoder_64_syn.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_axi_st_converter.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_input_if.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_rank_timer.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_sideband.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_tbp.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_timing_param.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_controller.v" -work work
+vlog +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_ddrx_controller_st_top.v" -work work
+vlog -sv +incdir+$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/alt_mem_if_nextgen_ddr3_controller_core.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altera_mem_if_dll_stratixiv.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altera_mem_if_oct_stratixiv.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_c0.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_s0.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_ram.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altera_avalon_sc_fifo.v" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altera_merlin_master_translator.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench.v" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/sequencer_scc_sv_wrapper.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_inst_ROM_no_ifdef_params.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altera_reset_synchronizer.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_write_decoder.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_bitcheck.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_read_datapath.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altera_reset_controller.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_ddr3.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_di_buffer_wrap.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_jumplogic.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_ac_ROM_reg.v" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/sequencer_data_mgr.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/sequencer_scc_siii_wrapper.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_s0_addr_router.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altera_merlin_master_agent.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_s0_cmd_xbar_demux.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_data_decoder.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/sequencer_scc_siii_phase_decode.v" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_s0_cmd_xbar_mux_003.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_s0_cmd_xbar_demux_001.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_pattern_fifo.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_dm_decoder.v" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altera_merlin_slave_agent.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/sequencer_phy_mgr.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/sequencer_scc_sv_phase_decode.v" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_s0_id_router.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altera_merlin_slave_translator.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_inst_ROM_reg.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/sequencer_scc_reg_file.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_lfsr12.v" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_s0_rsp_xbar_demux_003.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_ac_ROM_no_ifdef_params.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_lfsr72.v" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_s0_rsp_xbar_mux.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_datamux.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_data_broadcast.v" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/sequencer_scc_mgr.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_ram_csr.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_lfsr36.v" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_generic.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_s0_addr_router_001.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_core.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altera_merlin_burst_uncompressor.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altera_merlin_arbitrator.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/sequencer_scc_acv_wrapper.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/sequencer_scc_acv_phase_decode.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/rw_manager_di_buffer.v" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altera_mem_if_sequencer_mem_no_ifdef_params.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_s0_id_router_003.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/sequencer_reg_file.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_s0_irq_mapper.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/afi_mux_ddr3_ddrx.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_clock_pair_generator.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_read_valid_selector.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_addr_cmd_datapath.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_reset.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_acv_ldc.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_addr_cmd_pads.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_addr_cmd_ldc_pads.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_addr_cmd_ldc_pad.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/addr_cmd_non_ldc_pad.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_memphy.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_reset_sync.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_new_io_pads.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_fr_cycle_shifter.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_read_datapath.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_write_datapath.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_hr_to_fr.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_simple_ddio_out.v" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_sequencer_mux_bridge.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_phy_csr.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_iss_probe.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_flop_mem.v" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_p0_altdqdqs.v" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altdq_dqs2_ddio_3reg_stratixiv.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altdq_dqs2_abstract.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/altdq_dqs2_cal_delays.sv" -work work
+vlog -sv "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_pll0.sv" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_0002.v" -work work
+vlog "$IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v"
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a65e8718ff1088e954f9f45ce6c962b2f4dae7fd
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
@@ -0,0 +1,32 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on Megawizard-generated file msim_setup.tcl.
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+
+# Copy ROM/RAM files to simulation directory
+if {[file isdirectory $IP_DIR]} {
+ file copy -force $IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_s0_sequencer_mem.hex ./
+ file copy -force $IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_s0_AC_ROM.hex ./
+ file copy -force $IP_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_s0_inst_ROM.hex ./
+}
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generate_ip.sh b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..d33ae63c3d7744c252049608d8d8dd40ef9089ca
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generate_ip.sh
@@ -0,0 +1,50 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate ddr3 uniphy IP with MegaWizard
+# Description:
+# Generate the IP in a separate generated/ subdirectory. Therefore first copy the MegaWizard variation file in the 'generated' output dir, because:
+# 1) setting the output dir is not an option in the MegaWizard
+# 2) The MegaWizard overwrites the variation file sometimes - we don't want that as it could be hand-modified with e.g. added generics
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+# Remarks:
+# . This dedicated script is derived from the generic script $UNB/Firmware/software/build/unb_mgw
+#
+
+# Tool settings for selected target "unb1" with stratixiv
+. ${RADIOHDL}/tools/quartus/set_quartus unb1
+
+# Generate IP
+if ! [ -d "generated" ]; then
+ mkdir generated
+fi
+cd generated
+cp ../ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v .
+
+qmegawiz -silent -f:$UNB/Firmware/software/build/unb_mgw_params.txt ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+
+#rm ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..5fceb77404d44528e0d033ee68026ce53954001e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+hdl_library_clause_name = ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_lib
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
+
+synth_files =
+
+test_bench_files =
+
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
+ altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
+
+quartus_qip_files =
+ generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.qip
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
new file mode 100644
index 0000000000000000000000000000000000000000..6390cb70fff1f3e0632db12695d4fb50e02bba8d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
@@ -0,0 +1,390 @@
+// megafunction wizard: %DDR3 SDRAM Controller with UniPHY v11.1%
+// GENERATION: XML
+// ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+
+// Generated using ACDS version 11.1sp2 259 at 2015.04.22.11:47:15
+
+`timescale 1 ps / 1 ps
+module ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave (
+ input wire pll_ref_clk, // pll_ref_clk.clk
+ input wire global_reset_n, // global_reset.reset_n
+ input wire soft_reset_n, // soft_reset.reset_n
+ input wire afi_clk, // afi_clk_in.clk
+ input wire afi_half_clk, // afi_half_clk_in.clk
+ input wire afi_reset_n, // afi_reset_in.reset_n
+ output wire [15:0] mem_a, // memory.mem_a
+ output wire [2:0] mem_ba, // .mem_ba
+ output wire [1:0] mem_ck, // .mem_ck
+ output wire [1:0] mem_ck_n, // .mem_ck_n
+ output wire mem_cke, // .mem_cke
+ output wire mem_cs_n, // .mem_cs_n
+ output wire [7:0] mem_dm, // .mem_dm
+ output wire mem_ras_n, // .mem_ras_n
+ output wire mem_cas_n, // .mem_cas_n
+ output wire mem_we_n, // .mem_we_n
+ output wire mem_reset_n, // .mem_reset_n
+ inout wire [63:0] mem_dq, // .mem_dq
+ inout wire [7:0] mem_dqs, // .mem_dqs
+ inout wire [7:0] mem_dqs_n, // .mem_dqs_n
+ output wire mem_odt, // .mem_odt
+ output wire avl_ready, // avl.waitrequest_n
+ input wire avl_burstbegin, // .beginbursttransfer
+ input wire [26:0] avl_addr, // .address
+ output wire avl_rdata_valid, // .readdatavalid
+ output wire [255:0] avl_rdata, // .readdata
+ input wire [255:0] avl_wdata, // .writedata
+ input wire [31:0] avl_be, // .byteenable
+ input wire avl_read_req, // .read
+ input wire avl_write_req, // .write
+ input wire [6:0] avl_size, // .burstcount
+ output wire local_init_done, // status.local_init_done
+ output wire local_cal_success, // .local_cal_success
+ output wire local_cal_fail, // .local_cal_fail
+ input wire [13:0] seriesterminationcontrol, // oct_sharing.seriesterminationcontrol
+ input wire [13:0] parallelterminationcontrol, // .parallelterminationcontrol
+ input wire pll_mem_clk, // pll_sharing.pll_mem_clk
+ input wire pll_write_clk, // .pll_write_clk
+ input wire pll_write_clk_pre_phy_clk, // .pll_write_clk_pre_phy_clk
+ input wire pll_addr_cmd_clk, // .pll_addr_cmd_clk
+ input wire pll_locked, // .pll_locked
+ input wire pll_avl_clk, // .pll_avl_clk
+ input wire pll_config_clk, // .pll_config_clk
+ input wire [5:0] dll_delayctrl // dll_sharing.dll_delayctrl
+ );
+
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_0002 ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_inst (
+ .pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
+ .global_reset_n (global_reset_n), // global_reset.reset_n
+ .soft_reset_n (soft_reset_n), // soft_reset.reset_n
+ .afi_clk (afi_clk), // afi_clk_in.clk
+ .afi_half_clk (afi_half_clk), // afi_half_clk_in.clk
+ .afi_reset_n (afi_reset_n), // afi_reset_in.reset_n
+ .mem_a (mem_a), // memory.mem_a
+ .mem_ba (mem_ba), // .mem_ba
+ .mem_ck (mem_ck), // .mem_ck
+ .mem_ck_n (mem_ck_n), // .mem_ck_n
+ .mem_cke (mem_cke), // .mem_cke
+ .mem_cs_n (mem_cs_n), // .mem_cs_n
+ .mem_dm (mem_dm), // .mem_dm
+ .mem_ras_n (mem_ras_n), // .mem_ras_n
+ .mem_cas_n (mem_cas_n), // .mem_cas_n
+ .mem_we_n (mem_we_n), // .mem_we_n
+ .mem_reset_n (mem_reset_n), // .mem_reset_n
+ .mem_dq (mem_dq), // .mem_dq
+ .mem_dqs (mem_dqs), // .mem_dqs
+ .mem_dqs_n (mem_dqs_n), // .mem_dqs_n
+ .mem_odt (mem_odt), // .mem_odt
+ .avl_ready (avl_ready), // avl.waitrequest_n
+ .avl_burstbegin (avl_burstbegin), // .beginbursttransfer
+ .avl_addr (avl_addr), // .address
+ .avl_rdata_valid (avl_rdata_valid), // .readdatavalid
+ .avl_rdata (avl_rdata), // .readdata
+ .avl_wdata (avl_wdata), // .writedata
+ .avl_be (avl_be), // .byteenable
+ .avl_read_req (avl_read_req), // .read
+ .avl_write_req (avl_write_req), // .write
+ .avl_size (avl_size), // .burstcount
+ .local_init_done (local_init_done), // status.local_init_done
+ .local_cal_success (local_cal_success), // .local_cal_success
+ .local_cal_fail (local_cal_fail), // .local_cal_fail
+ .seriesterminationcontrol (seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
+ .parallelterminationcontrol (parallelterminationcontrol), // .parallelterminationcontrol
+ .pll_mem_clk (pll_mem_clk), // pll_sharing.pll_mem_clk
+ .pll_write_clk (pll_write_clk), // .pll_write_clk
+ .pll_write_clk_pre_phy_clk (pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
+ .pll_addr_cmd_clk (pll_addr_cmd_clk), // .pll_addr_cmd_clk
+ .pll_locked (pll_locked), // .pll_locked
+ .pll_avl_clk (pll_avl_clk), // .pll_avl_clk
+ .pll_config_clk (pll_config_clk), // .pll_config_clk
+ .dll_delayctrl (dll_delayctrl) // dll_sharing.dll_delayctrl
+ );
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+// Generated by Altera MegaWizard Launcher Utility version 1.0
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+// Copyright (C) 1991-2015 Altera Corporation
+// Any megafunction design, and related net list (encrypted or decrypted),
+// support information, device programming or simulation file, and any other
+// associated documentation or information provided by Altera or a partner
+// under Altera's Megafunction Partnership Program may be used only to
+// program PLD devices (but not masked PLD devices) from Altera. Any other
+// use of such megafunction design, net list, support information, device
+// programming or simulation file, or any other related documentation or
+// information is prohibited for any other purpose, including, but not
+// limited to modification, reverse engineering, de-compiling, or use with
+// any other silicon devices, unless such use is explicitly licensed under
+// a separate agreement with Altera or a megafunction partner. Title to
+// the intellectual property, including patents, copyrights, trademarks,
+// trade secrets, or maskworks, embodied in any such megafunction design,
+// net list, support information, device programming or simulation file, or
+// any other related documentation or information provided by Altera or a
+// megafunction partner, remains with Altera, the megafunction partner, or
+// their respective licensors. No other licenses, including any licenses
+// needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_mem_if_ddr3_emif" version="11.1" >
+// Retrieval info: <generic name="MEM_VENDOR" value="Micron" />
+// Retrieval info: <generic name="MEM_FORMAT" value="UNBUFFERED" />
+// Retrieval info: <generic name="AC_PARITY" value="false" />
+// Retrieval info: <generic name="RDIMM_CONFIG" value="0" />
+// Retrieval info: <generic name="DISCRETE_FLY_BY" value="true" />
+// Retrieval info: <generic name="DEVICE_DEPTH" value="1" />
+// Retrieval info: <generic name="MEM_MIRROR_ADDRESSING" value="0" />
+// Retrieval info: <generic name="MEM_CLK_FREQ_MAX" value="800.0" />
+// Retrieval info: <generic name="MEM_ROW_ADDR_WIDTH" value="16" />
+// Retrieval info: <generic name="MEM_COL_ADDR_WIDTH" value="10" />
+// Retrieval info: <generic name="MEM_DQ_WIDTH" value="64" />
+// Retrieval info: <generic name="MEM_DQ_PER_DQS" value="8" />
+// Retrieval info: <generic name="MEM_BANKADDR_WIDTH" value="3" />
+// Retrieval info: <generic name="MEM_IF_DM_PINS_EN" value="true" />
+// Retrieval info: <generic name="MEM_IF_DQSN_EN" value="true" />
+// Retrieval info: <generic name="MEM_NUMBER_OF_DIMMS" value="1" />
+// Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+// Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+// Retrieval info: <generic name="MEM_CK_WIDTH" value="2" />
+// Retrieval info: <generic name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+// Retrieval info: <generic name="NEXTGEN" value="true" />
+// Retrieval info: <generic name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+// Retrieval info: <generic name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+// Retrieval info: <generic name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+// Retrieval info: <generic name="MEM_VERBOSE" value="true" />
+// Retrieval info: <generic name="MEM_BL" value="OTF" />
+// Retrieval info: <generic name="MEM_BT" value="Sequential" />
+// Retrieval info: <generic name="MEM_ASR" value="Manual" />
+// Retrieval info: <generic name="MEM_SRT" value="Normal" />
+// Retrieval info: <generic name="MEM_PD" value="DLL off" />
+// Retrieval info: <generic name="MEM_DRV_STR" value="RZQ/7" />
+// Retrieval info: <generic name="MEM_DLL_EN" value="true" />
+// Retrieval info: <generic name="MEM_RTT_NOM" value="RZQ/4" />
+// Retrieval info: <generic name="MEM_RTT_WR" value="RZQ/4" />
+// Retrieval info: <generic name="MEM_WTCL" value="5" />
+// Retrieval info: <generic name="MEM_ATCL" value="Disabled" />
+// Retrieval info: <generic name="MEM_TCL" value="6" />
+// Retrieval info: <generic name="MEM_AUTO_LEVELING_MODE" value="true" />
+// Retrieval info: <generic name="MEM_USER_LEVELING_MODE" value="Leveling" />
+// Retrieval info: <generic name="MEM_INIT_EN" value="false" />
+// Retrieval info: <generic name="MEM_INIT_FILE" value="" />
+// Retrieval info: <generic name="DAT_DATA_WIDTH" value="32" />
+// Retrieval info: <generic name="TIMING_TIS" value="215" />
+// Retrieval info: <generic name="TIMING_TIH" value="285" />
+// Retrieval info: <generic name="TIMING_TDS" value="90" />
+// Retrieval info: <generic name="TIMING_TDH" value="160" />
+// Retrieval info: <generic name="TIMING_TDQSQ" value="200" />
+// Retrieval info: <generic name="TIMING_TQH" value="0.38" />
+// Retrieval info: <generic name="TIMING_TDQSCK" value="400" />
+// Retrieval info: <generic name="TIMING_TDQSS" value="0.25" />
+// Retrieval info: <generic name="TIMING_TQSH" value="0.38" />
+// Retrieval info: <generic name="TIMING_TDSH" value="0.2" />
+// Retrieval info: <generic name="TIMING_TDSS" value="0.2" />
+// Retrieval info: <generic name="MEM_TINIT_US" value="640" />
+// Retrieval info: <generic name="MEM_TMRD_CK" value="4" />
+// Retrieval info: <generic name="MEM_TRAS_NS" value="37.5" />
+// Retrieval info: <generic name="MEM_TRCD_NS" value="15.0" />
+// Retrieval info: <generic name="MEM_TRP_NS" value="15.0" />
+// Retrieval info: <generic name="MEM_TREFI_US" value="7.8" />
+// Retrieval info: <generic name="MEM_TRFC_NS" value="350.0" />
+// Retrieval info: <generic name="CFG_TCCD_NS" value="2.5" />
+// Retrieval info: <generic name="MEM_TWR_NS" value="15.0" />
+// Retrieval info: <generic name="MEM_TWTR" value="4" />
+// Retrieval info: <generic name="MEM_TFAW_NS" value="40.0" />
+// Retrieval info: <generic name="MEM_TRRD_NS" value="10.0" />
+// Retrieval info: <generic name="MEM_TRTP_NS" value="10.0" />
+// Retrieval info: <generic name="POWER_OF_TWO_BUS" value="false" />
+// Retrieval info: <generic name="SOPC_COMPAT_RESET" value="false" />
+// Retrieval info: <generic name="AVL_MAX_SIZE" value="64" />
+// Retrieval info: <generic name="BYTE_ENABLE" value="true" />
+// Retrieval info: <generic name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
+// Retrieval info: <generic name="CTL_DEEP_POWERDN_EN" value="false" />
+// Retrieval info: <generic name="CTL_SELF_REFRESH_EN" value="false" />
+// Retrieval info: <generic name="AUTO_POWERDN_EN" value="false" />
+// Retrieval info: <generic name="MEM_AUTO_PD_CYCLES" value="0" />
+// Retrieval info: <generic name="CTL_USR_REFRESH_EN" value="false" />
+// Retrieval info: <generic name="CTL_AUTOPCH_EN" value="false" />
+// Retrieval info: <generic name="ADDR_ORDER" value="1" />
+// Retrieval info: <generic name="CTL_LOOK_AHEAD_DEPTH" value="4" />
+// Retrieval info: <generic name="CONTROLLER_LATENCY" value="5" />
+// Retrieval info: <generic name="CFG_REORDER_DATA" value="false" />
+// Retrieval info: <generic name="CFG_STARVE_LIMIT" value="10" />
+// Retrieval info: <generic name="CTL_CSR_ENABLED" value="false" />
+// Retrieval info: <generic name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
+// Retrieval info: <generic name="CTL_ECC_ENABLED" value="false" />
+// Retrieval info: <generic name="CTL_HRB_ENABLED" value="false" />
+// Retrieval info: <generic name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
+// Retrieval info: <generic name="MULTICAST_EN" value="false" />
+// Retrieval info: <generic name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
+// Retrieval info: <generic name="CTL_DYNAMIC_BANK_NUM" value="4" />
+// Retrieval info: <generic name="DEBUG_MODE" value="false" />
+// Retrieval info: <generic name="ENABLE_BURST_MERGE" value="false" />
+// Retrieval info: <generic name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
+// Retrieval info: <generic name="CTL_ENABLE_BURST_TERMINATE" value="false" />
+// Retrieval info: <generic name="LOCAL_ID_WIDTH" value="8" />
+// Retrieval info: <generic name="WRBUFFER_ADDR_WIDTH" value="6" />
+// Retrieval info: <generic name="USE_MM_ADAPTOR" value="true" />
+// Retrieval info: <generic name="USE_AXI_ADAPTOR" value="false" />
+// Retrieval info: <generic name="HCX_COMPAT_MODE" value="false" />
+// Retrieval info: <generic name="CTL_CMD_QUEUE_DEPTH" value="8" />
+// Retrieval info: <generic name="CTL_CSR_READ_ONLY" value="1" />
+// Retrieval info: <generic name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
+// Retrieval info: <generic name="NUM_OF_PORTS" value="1" />
+// Retrieval info: <generic name="ENABLE_BONDING" value="false" />
+// Retrieval info: <generic name="ENABLE_USER_ECC" value="false" />
+// Retrieval info: <generic name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
+// Retrieval info: <generic name="PRIORITY_PORT" value="0,0,0,0,0,0" />
+// Retrieval info: <generic name="WEIGHT_PORT" value="0,0,0,0,0,0" />
+// Retrieval info: <generic name="CPORT_TYPE_PORT" value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
+// Retrieval info: <generic name="ENABLE_EMIT_BFM_MASTER" value="false" />
+// Retrieval info: <generic name="REF_CLK_FREQ" value="200.0" />
+// Retrieval info: <generic name="REF_CLK_FREQ_PARAM_VALID" value="false" />
+// Retrieval info: <generic name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
+// Retrieval info: <generic name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
+// Retrieval info: <generic name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
+// Retrieval info: <generic name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_DR_CLK_MULT_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_DR_CLK_DIV_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
+// Retrieval info: <generic name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_MEM_CLK_MULT_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_MEM_CLK_DIV_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
+// Retrieval info: <generic name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_AFI_CLK_MULT_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_AFI_CLK_DIV_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
+// Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
+// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
+// Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
+// Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
+// Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
+// Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
+// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
+// Retrieval info: <generic name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+// Retrieval info: <generic name="PLL_HR_CLK_MULT_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_HR_CLK_DIV_PARAM" value="0" />
+// Retrieval info: <generic name="PLL_CLK_PARAM_VALID" value="false" />
+// Retrieval info: <generic name="ENABLE_EXTRA_REPORTING" value="false" />
+// Retrieval info: <generic name="NUM_EXTRA_REPORT_PATH" value="10" />
+// Retrieval info: <generic name="ENABLE_ISS_PROBES" value="false" />
+// Retrieval info: <generic name="CALIB_REG_WIDTH" value="8" />
+// Retrieval info: <generic name="USE_SEQUENCER_BFM" value="false" />
+// Retrieval info: <generic name="HHP_HPS" value="false" />
+// Retrieval info: <generic name="HHP_REMAP_ADDR" value="true" />
+// Retrieval info: <generic name="USE_SEQUENCER_APB_BRIDGE" value="false" />
+// Retrieval info: <generic name="DEFAULT_FAST_SIM_MODEL" value="true" />
+// Retrieval info: <generic name="PLL_SHARING_MODE" value="Slave" />
+// Retrieval info: <generic name="DLL_SHARING_MODE" value="Slave" />
+// Retrieval info: <generic name="OCT_SHARING_MODE" value="Slave" />
+// Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
+// Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
+// Retrieval info: <generic name="USE_FAKE_PHY" value="false" />
+// Retrieval info: <generic name="PHY_ONLY" value="false" />
+// Retrieval info: <generic name="EXTRA_SETTINGS" value="" />
+// Retrieval info: <generic name="MEM_DEVICE" value="MISSING_MODEL" />
+// Retrieval info: <generic name="FORCE_SYNTHESIS_LANGUAGE" value="" />
+// Retrieval info: <generic name="SEQUENCER_TYPE" value="NIOS" />
+// Retrieval info: <generic name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
+// Retrieval info: <generic name="SEQ_MODE" value="0" />
+// Retrieval info: <generic name="ADVANCED_CK_PHASES" value="false" />
+// Retrieval info: <generic name="COMMAND_PHASE" value="0.0" />
+// Retrieval info: <generic name="MEM_CK_PHASE" value="0.0" />
+// Retrieval info: <generic name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
+// Retrieval info: <generic name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
+// Retrieval info: <generic name="MEM_VOLTAGE" value="1.5V DDR3" />
+// Retrieval info: <generic name="PLL_LOCATION" value="Top_Bottom" />
+// Retrieval info: <generic name="SKIP_MEM_INIT" value="true" />
+// Retrieval info: <generic name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
+// Retrieval info: <generic name="DQ_INPUT_REG_USE_CLKN" value="false" />
+// Retrieval info: <generic name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
+// Retrieval info: <generic name="AFI_DEBUG_INFO_WIDTH" value="32" />
+// Retrieval info: <generic name="CALIBRATION_MODE" value="Quick" />
+// Retrieval info: <generic name="NIOS_ROM_DATA_WIDTH" value="32" />
+// Retrieval info: <generic name="READ_FIFO_SIZE" value="8" />
+// Retrieval info: <generic name="PHY_CSR_ENABLED" value="false" />
+// Retrieval info: <generic name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
+// Retrieval info: <generic name="USER_DEBUG_LEVEL" value="0" />
+// Retrieval info: <generic name="TIMING_BOARD_DERATE_METHOD" value="SLEW_RATE" />
+// Retrieval info: <generic name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
+// Retrieval info: <generic name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
+// Retrieval info: <generic name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
+// Retrieval info: <generic name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
+// Retrieval info: <generic name="TIMING_BOARD_TIS" value="0.0" />
+// Retrieval info: <generic name="TIMING_BOARD_TIH" value="0.0" />
+// Retrieval info: <generic name="TIMING_BOARD_TDS" value="0.0" />
+// Retrieval info: <generic name="TIMING_BOARD_TDH" value="0.0" />
+// Retrieval info: <generic name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
+// Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
+// Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
+// Retrieval info: <generic name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
+// Retrieval info: <generic name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
+// Retrieval info: <generic name="PACKAGE_DESKEW" value="false" />
+// Retrieval info: <generic name="TIMING_BOARD_MAX_CK_DELAY" value="0.2" />
+// Retrieval info: <generic name="TIMING_BOARD_MAX_DQS_DELAY" value="0.3" />
+// Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
+// Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
+// Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
+// Retrieval info: <generic name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
+// Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
+// Retrieval info: <generic name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
+// Retrieval info: <generic name="TIMING_BOARD_AC_SKEW" value="0.02" />
+// Retrieval info: <generic name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
+// Retrieval info: <generic name="RATE" value="Half" />
+// Retrieval info: <generic name="MEM_CLK_FREQ" value="400.0" />
+// Retrieval info: <generic name="FORCE_DQS_TRACKING" value="AUTO" />
+// Retrieval info: <generic name="SYS_INFO_DEVICE_FAMILY" value="Stratix IV" />
+// Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
+// Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
+// Retrieval info: <generic name="DEVICE_FAMILY_PARAM" value="" />
+// Retrieval info: <generic name="DISABLE_CHILD_MESSAGING" value="false" />
+// Retrieval info: <generic name="SPEED_GRADE" value="2" />
+// Retrieval info: <generic name="HARD_EMIF" value="false" />
+// Retrieval info: <generic name="ADD_EFFICIENCY_MONITOR" value="false" />
+// Retrieval info: <generic name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
+// Retrieval info: <generic name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
+// Retrieval info: </instance>
+// IPFS_FILES : NONE