diff --git a/applications/arts/designs/arts_unb1_sc4/quartus/qsys_mm_master.qsys b/applications/arts/designs/arts_unb1_sc4/quartus/qsys_mm_master.qsys
index 6bc050a654d3c9a9f310c11eb583d77672b7d140..033709b7bea3d04dc85daa5c2bfd1f7118bb3e40 100644
--- a/applications/arts/designs/arts_unb1_sc4/quartus/qsys_mm_master.qsys
+++ b/applications/arts/designs/arts_unb1_sc4/quartus/qsys_mm_master.qsys
@@ -85,67 +85,67 @@
type = "boolean";
}
}
- element reg_dp_offload_tx_iab_i_hdr_dat.mem
+ element reg_dp_xonoff_tab_iquv.mem
{
datum baseAddress
{
- value = "1024";
+ value = "1528";
type = "long";
}
}
- element reg_dp_offload_tx_tab_iquv_hdr_dat.mem
+ element reg_diag_data_buffer_meshin.mem
{
datum baseAddress
{
- value = "512";
+ value = "548864";
type = "long";
}
}
- element reg_dp_gain_v.mem
+ element reg_tab_dest_ip.mem
{
datum baseAddress
{
- value = "1576";
+ value = "3328";
type = "long";
}
}
- element ram_bf_unit_x_st_sst.mem
+ element reg_dp_xonoff_tab_i.mem
{
datum baseAddress
{
- value = "1632";
+ value = "1536";
type = "long";
}
}
- element reg_dp_bsn_align_mesh.mem
+ element reg_tr_10GbE.mem
{
datum baseAddress
{
- value = "1440";
+ value = "262144";
type = "long";
}
}
- element reg_bsn_monitor_mesh.mem
+ element reg_dp_offload_tx_tab_i_hdr_dat.mem
{
datum baseAddress
{
- value = "2560";
+ value = "589824";
type = "long";
}
}
- element reg_remu.mem
+ element reg_tab_dest_mac.mem
{
datum baseAddress
{
- value = "1312";
+ value = "3392";
type = "long";
}
}
- element reg_bf_unit_x_st_sst.mem
+ element reg_mmdp_data.mem
{
datum baseAddress
{
- value = "1024";
+ value = "1808";
type = "long";
}
}
@@ -157,32 +157,32 @@
type = "long";
}
}
- element reg_dp_xonoff_tab_i.mem
+ element rom_unb_system_info.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "1536";
+ value = "4096";
type = "long";
}
}
- element ram_arts_tab_beamformer.mem
+ element reg_diag_data_buffer_input.mem
{
datum baseAddress
{
- value = "786432";
+ value = "73728";
type = "long";
}
}
- element rom_unb_system_info.mem
+ element ram_bf_unit_x_st_sst.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "4096";
+ value = "1632";
type = "long";
}
}
@@ -194,19 +194,19 @@
type = "long";
}
}
- element reg_epcs.mem
+ element reg_dp_gain_v.mem
{
datum baseAddress
{
- value = "1280";
+ value = "1576";
type = "long";
}
}
- element reg_dp_gain_q.mem
+ element reg_epcs.mem
{
datum baseAddress
{
- value = "1560";
+ value = "1280";
type = "long";
}
}
@@ -218,272 +218,272 @@
type = "long";
}
}
- element reg_dp_offload_tx_tab_i_hdr_dat.mem
+ element reg_bf_unit_x_st_sst.mem
{
datum baseAddress
{
- value = "589824";
+ value = "1024";
type = "long";
}
}
- element ram_diag_data_buffer_wpfbin.mem
+ element ram_diag_data_buffer_wpfbout.mem
{
datum baseAddress
{
- value = "524288";
+ value = "573440";
type = "long";
}
}
- element ram_bf_unit_x_ss_ss_wide.mem
+ element reg_remu.mem
{
datum baseAddress
{
- value = "1344";
+ value = "1312";
type = "long";
}
}
- element reg_mmdp_data.mem
+ element reg_dp_bsn_align_mesh.mem
{
datum baseAddress
{
- value = "1808";
+ value = "1440";
type = "long";
}
}
- element ram_bf_unit_x_bf_weights.mem
+ element reg_unb_sens.mem
{
datum baseAddress
{
- value = "128";
+ value = "224";
type = "long";
}
}
- element reg_mdio_1.mem
+ element pio_system_info.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "1376";
+ value = "0";
type = "long";
}
}
- element reg_wdi.mem
+ element reg_dp_offload_rx_hdr_dat.mem
{
datum baseAddress
{
- value = "1520";
+ value = "512";
type = "long";
}
}
- element ram_diag_data_buffer_input.mem
+ element reg_dpmm_data.mem
{
datum baseAddress
{
- value = "540672";
+ value = "1792";
type = "long";
}
}
- element reg_dp_xonoff_output.mem
+ element reg_bsn_monitor_mesh.mem
{
datum baseAddress
{
- value = "1752";
+ value = "2560";
type = "long";
}
}
- element reg_diag_data_buffer_wpfbout.mem
+ element reg_dp_gain_i.mem
{
datum baseAddress
{
- value = "3072";
+ value = "1552";
type = "long";
}
}
- element reg_diag_data_buffer_wpfbin.mem
+ element reg_dp_bsn_align_input.mem
{
datum baseAddress
{
- value = "3584";
+ value = "1488";
type = "long";
}
}
- element reg_mdio_0.mem
+ element reg_dp_gain_u.mem
{
datum baseAddress
{
- value = "1408";
+ value = "1568";
type = "long";
}
}
- element reg_tr_10GbE.mem
+ element reg_mdio_2.mem
{
datum baseAddress
{
- value = "262144";
+ value = "1344";
type = "long";
}
}
- element pio_system_info.mem
+ element reg_wdi.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "0";
+ value = "1520";
type = "long";
}
}
- element pio_pps.mem
+ element ram_diag_data_buffer_wpfbin.mem
{
datum baseAddress
{
- value = "1512";
+ value = "524288";
type = "long";
}
}
- element reg_dp_xonoff_tab_iquv.mem
+ element ram_arts_tab_beamformer.mem
{
datum baseAddress
{
- value = "1528";
+ value = "786432";
type = "long";
}
}
- element reg_dp_offload_rx_hdr_dat.mem
+ element reg_mdio_1.mem
{
datum baseAddress
{
- value = "512";
+ value = "1376";
type = "long";
}
}
- element reg_dp_gain_u.mem
+ element ram_diag_data_buffer_meshin.mem
{
datum baseAddress
{
- value = "1568";
+ value = "557056";
type = "long";
}
}
- element reg_dp_gain_i.mem
+ element reg_dp_xonoff_output.mem
{
datum baseAddress
{
- value = "1552";
+ value = "1752";
type = "long";
}
}
- element reg_diag_data_buffer_input.mem
+ element reg_bsn_monitor_input.mem
{
datum baseAddress
{
- value = "73728";
+ value = "2048";
type = "long";
}
}
- element ram_diag_data_buffer_meshin.mem
+ element reg_tr_xaui.mem
{
datum baseAddress
{
- value = "557056";
+ value = "8192";
type = "long";
}
}
- element reg_dpmm_data.mem
+ element ram_bf_unit_x_bf_weights.mem
{
datum baseAddress
{
- value = "1792";
+ value = "128";
type = "long";
}
}
- element reg_force_data_input.mem
+ element ram_bf_unit_x_ss_ss_wide.mem
{
datum baseAddress
{
- value = "1920";
+ value = "1344";
type = "long";
}
}
- element reg_tr_xaui.mem
+ element reg_force_data_input.mem
{
datum baseAddress
{
- value = "8192";
+ value = "1920";
type = "long";
}
}
- element reg_dp_bsn_align_input.mem
+ element reg_dp_offload_tx_iab_i_hdr_dat.mem
{
datum baseAddress
{
- value = "1488";
+ value = "1024";
type = "long";
}
}
- element reg_bsn_monitor_input.mem
+ element reg_dp_offload_tx_tab_iquv_hdr_dat.mem
{
datum baseAddress
{
- value = "2048";
+ value = "512";
type = "long";
}
}
- element ram_diag_data_buffer_wpfbout.mem
+ element reg_diag_data_buffer_wpfbin.mem
{
datum baseAddress
{
- value = "573440";
+ value = "3584";
type = "long";
}
}
- element reg_dp_xonoff_iab_i.mem
+ element ram_diag_data_buffer_input.mem
{
datum baseAddress
{
- value = "1544";
+ value = "540672";
type = "long";
}
}
- element reg_mdio_2.mem
+ element reg_diag_data_buffer_wpfbout.mem
{
datum baseAddress
{
- value = "1344";
+ value = "3072";
type = "long";
}
}
- element reg_tab_dest_mac.mem
+ element pio_pps.mem
{
datum baseAddress
{
- value = "3392";
+ value = "1512";
type = "long";
}
}
- element reg_diag_data_buffer_meshin.mem
+ element reg_dp_gain_q.mem
{
datum baseAddress
{
- value = "548864";
+ value = "1560";
type = "long";
}
}
- element reg_unb_sens.mem
+ element reg_dp_xonoff_iab_i.mem
{
datum baseAddress
{
- value = "224";
+ value = "1544";
type = "long";
}
}
- element reg_tab_dest_ip.mem
+ element reg_mdio_0.mem
{
datum baseAddress
{
- value = "3328";
+ value = "1408";
type = "long";
}
}
@@ -1172,19 +1172,19 @@
type = "boolean";
}
}
- element pio_wdi.s1
+ element timer_0.s1
{
datum baseAddress
{
- value = "1472";
+ value = "192";
type = "long";
}
}
- element timer_0.s1
+ element pio_wdi.s1
{
datum baseAddress
{
- value = "192";
+ value = "1472";
type = "long";
}
}
@@ -1229,7 +1229,7 @@
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
- <parameter name="timeStamp" value="1539156758419" />
+ <parameter name="timeStamp" value="1556107927929" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
@@ -1555,39 +1555,25 @@
dir="end" />
<interface
name="reg_dp_offload_tx_hdr_dat_reset"
- internal="reg_dp_offload_tx_hdr_dat.reset"
- type="conduit"
- dir="end" />
+ internal="reg_dp_offload_tx_hdr_dat.reset" />
<interface
name="reg_dp_offload_tx_hdr_dat_clk"
- internal="reg_dp_offload_tx_hdr_dat.clk"
- type="conduit"
- dir="end" />
+ internal="reg_dp_offload_tx_hdr_dat.clk" />
<interface
name="reg_dp_offload_tx_hdr_dat_address"
- internal="reg_dp_offload_tx_hdr_dat.address"
- type="conduit"
- dir="end" />
+ internal="reg_dp_offload_tx_hdr_dat.address" />
<interface
name="reg_dp_offload_tx_hdr_dat_write"
- internal="reg_dp_offload_tx_hdr_dat.write"
- type="conduit"
- dir="end" />
+ internal="reg_dp_offload_tx_hdr_dat.write" />
<interface
name="reg_dp_offload_tx_hdr_dat_writedata"
- internal="reg_dp_offload_tx_hdr_dat.writedata"
- type="conduit"
- dir="end" />
+ internal="reg_dp_offload_tx_hdr_dat.writedata" />
<interface
name="reg_dp_offload_tx_hdr_dat_read"
- internal="reg_dp_offload_tx_hdr_dat.read"
- type="conduit"
- dir="end" />
+ internal="reg_dp_offload_tx_hdr_dat.read" />
<interface
name="reg_dp_offload_tx_hdr_dat_readdata"
- internal="reg_dp_offload_tx_hdr_dat.readdata"
- type="conduit"
- dir="end" />
+ internal="reg_dp_offload_tx_hdr_dat.readdata" />
<interface
name="reg_tr_10gbe_reset"
internal="reg_tr_10GbE.reset"
@@ -1985,39 +1971,25 @@
dir="end" />
<interface
name="reg_dp_offload_tx_iab_i_hdr_dat_reset"
- internal="reg_dp_offload_tx_iab_i_hdr_dat.reset"
- type="conduit"
- dir="end" />
+ internal="reg_dp_offload_tx_iab_i_hdr_dat.reset" />
<interface
name="reg_dp_offload_tx_iab_i_hdr_dat_clk"
- internal="reg_dp_offload_tx_iab_i_hdr_dat.clk"
- type="conduit"
- dir="end" />
+ internal="reg_dp_offload_tx_iab_i_hdr_dat.clk" />
<interface
name="reg_dp_offload_tx_iab_i_hdr_dat_address"
- internal="reg_dp_offload_tx_iab_i_hdr_dat.address"
- type="conduit"
- dir="end" />
+ internal="reg_dp_offload_tx_iab_i_hdr_dat.address" />
<interface
name="reg_dp_offload_tx_iab_i_hdr_dat_write"
- internal="reg_dp_offload_tx_iab_i_hdr_dat.write"
- type="conduit"
- dir="end" />
+ internal="reg_dp_offload_tx_iab_i_hdr_dat.write" />
<interface
name="reg_dp_offload_tx_iab_i_hdr_dat_writedata"
- internal="reg_dp_offload_tx_iab_i_hdr_dat.writedata"
- type="conduit"
- dir="end" />
+ internal="reg_dp_offload_tx_iab_i_hdr_dat.writedata" />
<interface
name="reg_dp_offload_tx_iab_i_hdr_dat_read"
- internal="reg_dp_offload_tx_iab_i_hdr_dat.read"
- type="conduit"
- dir="end" />
+ internal="reg_dp_offload_tx_iab_i_hdr_dat.read" />
<interface
name="reg_dp_offload_tx_iab_i_hdr_dat_readdata"
- internal="reg_dp_offload_tx_iab_i_hdr_dat.readdata"
- type="conduit"
- dir="end" />
+ internal="reg_dp_offload_tx_iab_i_hdr_dat.readdata" />
<interface
name="reg_dp_gain_i_reset"
internal="reg_dp_gain_i.reset"
@@ -2158,41 +2130,19 @@
internal="reg_dp_gain_v.readdata"
type="conduit"
dir="end" />
- <interface
- name="reg_dp_xonoff_iab_i_reset"
- internal="reg_dp_xonoff_iab_i.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_xonoff_iab_i_clk"
- internal="reg_dp_xonoff_iab_i.clk"
- type="conduit"
- dir="end" />
+ <interface name="reg_dp_xonoff_iab_i_reset" internal="reg_dp_xonoff_iab_i.reset" />
+ <interface name="reg_dp_xonoff_iab_i_clk" internal="reg_dp_xonoff_iab_i.clk" />
<interface
name="reg_dp_xonoff_iab_i_address"
- internal="reg_dp_xonoff_iab_i.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_xonoff_iab_i_write"
- internal="reg_dp_xonoff_iab_i.write"
- type="conduit"
- dir="end" />
+ internal="reg_dp_xonoff_iab_i.address" />
+ <interface name="reg_dp_xonoff_iab_i_write" internal="reg_dp_xonoff_iab_i.write" />
<interface
name="reg_dp_xonoff_iab_i_writedata"
- internal="reg_dp_xonoff_iab_i.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_xonoff_iab_i_read"
- internal="reg_dp_xonoff_iab_i.read"
- type="conduit"
- dir="end" />
+ internal="reg_dp_xonoff_iab_i.writedata" />
+ <interface name="reg_dp_xonoff_iab_i_read" internal="reg_dp_xonoff_iab_i.read" />
<interface
name="reg_dp_xonoff_iab_i_readdata"
- internal="reg_dp_xonoff_iab_i.readdata"
- type="conduit"
- dir="end" />
+ internal="reg_dp_xonoff_iab_i.readdata" />
<interface
name="reg_bsn_monitor_input_clk"
internal="reg_bsn_monitor_input.clk"
@@ -2981,7 +2931,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x6000' end='0x6800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_tab_iquv_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_dp_offload_tx_iab_i_hdr_dat.mem' start='0x400' end='0x500' /><slave name='reg_epcs.mem' start='0x500' end='0x520' /><slave name='reg_remu.mem' start='0x520' end='0x540' /><slave name='reg_mdio_2.mem' start='0x540' end='0x560' /><slave name='reg_mdio_1.mem' start='0x560' end='0x580' /><slave name='reg_mdio_0.mem' start='0x580' end='0x5A0' /><slave name='reg_dp_bsn_align_mesh.mem' start='0x5A0' end='0x5C0' /><slave name='pio_wdi.s1' start='0x5C0' end='0x5D0' /><slave name='reg_dp_bsn_align_input.mem' start='0x5D0' end='0x5E0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x5E0' end='0x5E8' /><slave name='pio_pps.mem' start='0x5E8' end='0x5F0' /><slave name='reg_wdi.mem' start='0x5F0' end='0x5F8' /><slave name='reg_dp_xonoff_tab_iquv.mem' start='0x5F8' end='0x600' /><slave name='reg_dp_xonoff_tab_i.mem' start='0x600' end='0x608' /><slave name='reg_dp_xonoff_iab_i.mem' start='0x608' end='0x610' /><slave name='reg_dp_gain_i.mem' start='0x610' end='0x618' /><slave name='reg_dp_gain_q.mem' start='0x618' end='0x620' /><slave name='reg_dp_gain_u.mem' start='0x620' end='0x628' /><slave name='reg_dp_gain_v.mem' start='0x628' end='0x630' /><slave name='reg_dpmm_data.mem' start='0x700' end='0x708' /><slave name='reg_dpmm_ctrl.mem' start='0x708' end='0x710' /><slave name='reg_mmdp_data.mem' start='0x710' end='0x718' /><slave name='reg_mmdp_ctrl.mem' start='0x718' end='0x720' /><slave name='reg_force_data_input.mem' start='0x780' end='0x800' /><slave name='reg_bsn_monitor_input.mem' start='0x800' end='0xA00' /><slave name='reg_bsn_monitor_mesh.mem' start='0xA00' end='0xC00' /><slave name='reg_diag_data_buffer_wpfbout.mem' start='0xC00' end='0xC80' /><slave name='reg_tab_dest_ip.mem' start='0xD00' end='0xD20' /><slave name='reg_tab_dest_mac.mem' start='0xD40' end='0xD80' /><slave name='reg_diag_data_buffer_wpfbin.mem' start='0xE00' end='0x1000' /><slave name='rom_unb_system_info.mem' start='0x1000' end='0x2000' /><slave name='reg_tr_xaui.mem' start='0x2000' end='0x4000' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' /><slave name='avs_eth_0.mms_ram' start='0x5000' end='0x6000' /><slave name='cpu_0.jtag_debug_module' start='0x6000' end='0x6800' /><slave name='reg_diag_data_buffer_input.mem' start='0x12000' end='0x12100' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_diag_data_buffer_wpfbin.mem' start='0x80000' end='0x84000' /><slave name='ram_diag_data_buffer_input.mem' start='0x84000' end='0x86000' /><slave name='reg_diag_data_buffer_meshin.mem' start='0x86000' end='0x86100' /><slave name='ram_diag_data_buffer_meshin.mem' start='0x88000' end='0x8C000' /><slave name='ram_diag_data_buffer_wpfbout.mem' start='0x8C000' end='0x90000' /><slave name='reg_dp_offload_tx_tab_i_hdr_dat.mem' start='0x90000' end='0x90800' /><slave name='ram_arts_tab_beamformer.mem' start='0xC0000' end='0xC0800' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_dp_offload_tx_tab_iquv_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_epcs.mem' start='0x500' end='0x520' /><slave name='reg_remu.mem' start='0x520' end='0x540' /><slave name='reg_mdio_2.mem' start='0x540' end='0x560' /><slave name='reg_mdio_1.mem' start='0x560' end='0x580' /><slave name='reg_mdio_0.mem' start='0x580' end='0x5A0' /><slave name='reg_dp_bsn_align_mesh.mem' start='0x5A0' end='0x5C0' /><slave name='pio_wdi.s1' start='0x5C0' end='0x5D0' /><slave name='reg_dp_bsn_align_input.mem' start='0x5D0' end='0x5E0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x5E0' end='0x5E8' /><slave name='pio_pps.mem' start='0x5E8' end='0x5F0' /><slave name='reg_wdi.mem' start='0x5F0' end='0x5F8' /><slave name='reg_dp_xonoff_tab_iquv.mem' start='0x5F8' end='0x600' /><slave name='reg_dp_xonoff_tab_i.mem' start='0x600' end='0x608' /><slave name='reg_dp_gain_i.mem' start='0x610' end='0x618' /><slave name='reg_dp_gain_q.mem' start='0x618' end='0x620' /><slave name='reg_dp_gain_u.mem' start='0x620' end='0x628' /><slave name='reg_dp_gain_v.mem' start='0x628' end='0x630' /><slave name='reg_dpmm_data.mem' start='0x700' end='0x708' /><slave name='reg_dpmm_ctrl.mem' start='0x708' end='0x710' /><slave name='reg_mmdp_data.mem' start='0x710' end='0x718' /><slave name='reg_mmdp_ctrl.mem' start='0x718' end='0x720' /><slave name='reg_force_data_input.mem' start='0x780' end='0x800' /><slave name='reg_bsn_monitor_input.mem' start='0x800' end='0xA00' /><slave name='reg_bsn_monitor_mesh.mem' start='0xA00' end='0xC00' /><slave name='reg_diag_data_buffer_wpfbout.mem' start='0xC00' end='0xC80' /><slave name='reg_tab_dest_ip.mem' start='0xD00' end='0xD20' /><slave name='reg_tab_dest_mac.mem' start='0xD40' end='0xD80' /><slave name='reg_diag_data_buffer_wpfbin.mem' start='0xE00' end='0x1000' /><slave name='rom_unb_system_info.mem' start='0x1000' end='0x2000' /><slave name='reg_tr_xaui.mem' start='0x2000' end='0x4000' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' /><slave name='avs_eth_0.mms_ram' start='0x5000' end='0x6000' /><slave name='cpu_0.jtag_debug_module' start='0x6000' end='0x6800' /><slave name='reg_diag_data_buffer_input.mem' start='0x12000' end='0x12100' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_diag_data_buffer_wpfbin.mem' start='0x80000' end='0x84000' /><slave name='ram_diag_data_buffer_input.mem' start='0x84000' end='0x86000' /><slave name='reg_diag_data_buffer_meshin.mem' start='0x86000' end='0x86100' /><slave name='ram_diag_data_buffer_meshin.mem' start='0x88000' end='0x8C000' /><slave name='ram_diag_data_buffer_wpfbout.mem' start='0x8C000' end='0x90000' /><slave name='reg_dp_offload_tx_tab_i_hdr_dat.mem' start='0x90000' end='0x90800' /><slave name='ram_arts_tab_beamformer.mem' start='0xC0000' end='0xC0800' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="25000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" />
@@ -3047,7 +2997,7 @@ q]]></parameter>
<module
kind="avs_common_mm"
version="1.0"
- enabled="1"
+ enabled="0"
name="reg_dp_offload_tx_hdr_dat">
<parameter name="g_adr_w" value="6" />
<parameter name="g_dat_w" value="32" />
@@ -3197,7 +3147,7 @@ q]]></parameter>
<module
kind="avs_common_mm"
version="1.0"
- enabled="1"
+ enabled="0"
name="reg_dp_offload_tx_iab_i_hdr_dat">
<parameter name="g_adr_w" value="6" />
<parameter name="g_dat_w" value="32" />
@@ -3226,7 +3176,7 @@ q]]></parameter>
<module
kind="avs_common_mm"
version="1.0"
- enabled="1"
+ enabled="0"
name="reg_dp_xonoff_iab_i">
<parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4.vhd
index 9d22d473a1d3cf24aad1ac0df984cb259f427d33..04eeb48678a6bc7db00ece6dbfd3f958f9f9e5d3 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4.vhd
@@ -793,11 +793,11 @@ BEGIN
reg_dp_offload_tx_tab_i_hdr_dat_mosi => reg_dp_offload_tx_tab_i_hdr_dat_mosi,
reg_dp_offload_tx_tab_i_hdr_dat_miso => reg_dp_offload_tx_tab_i_hdr_dat_miso,
- reg_dp_offload_tx_iab_i_hdr_dat_mosi => reg_dp_offload_tx_iab_i_hdr_dat_mosi,
- reg_dp_offload_tx_iab_i_hdr_dat_miso => reg_dp_offload_tx_iab_i_hdr_dat_miso,
+-- reg_dp_offload_tx_iab_i_hdr_dat_mosi => reg_dp_offload_tx_iab_i_hdr_dat_mosi,
+-- reg_dp_offload_tx_iab_i_hdr_dat_miso => reg_dp_offload_tx_iab_i_hdr_dat_miso,
- reg_dp_xonoff_iab_i_mosi => reg_dp_xonoff_iab_i_mosi,
- reg_dp_xonoff_iab_i_miso => reg_dp_xonoff_iab_i_miso,
+-- reg_dp_xonoff_iab_i_mosi => reg_dp_xonoff_iab_i_mosi,
+-- reg_dp_xonoff_iab_i_miso => reg_dp_xonoff_iab_i_miso,
reg_tab_dest_ip_mosi => reg_tab_dest_ip_mosi,
reg_tab_dest_ip_miso => reg_tab_dest_ip_miso,
reg_tab_dest_mac_mosi => reg_tab_dest_mac_mosi,
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_mm_master.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_mm_master.vhd
index 701b09fb26900db5760e938134f1379398d7ef0c..ab6ac6a686c3d21721ef02656a70f66044ed86d5 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_mm_master.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_mm_master.vhd
@@ -99,12 +99,12 @@ ENTITY arts_unb1_sc4_mm_master IS
reg_dp_offload_tx_tab_iquv_hdr_dat_miso : IN t_mem_miso := c_mem_miso_rst;
reg_dp_xonoff_tab_i_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_dp_xonoff_tab_i_miso : IN t_mem_miso := c_mem_miso_rst;
- reg_dp_xonoff_iab_i_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
- reg_dp_xonoff_iab_i_miso : IN t_mem_miso := c_mem_miso_rst;
+-- reg_dp_xonoff_iab_i_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
+-- reg_dp_xonoff_iab_i_miso : IN t_mem_miso := c_mem_miso_rst;
reg_dp_offload_tx_tab_i_hdr_dat_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_dp_offload_tx_tab_i_hdr_dat_miso : IN t_mem_miso := c_mem_miso_rst;
- reg_dp_offload_tx_iab_i_hdr_dat_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
- reg_dp_offload_tx_iab_i_hdr_dat_miso : IN t_mem_miso := c_mem_miso_rst;
+-- reg_dp_offload_tx_iab_i_hdr_dat_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
+-- reg_dp_offload_tx_iab_i_hdr_dat_miso : IN t_mem_miso := c_mem_miso_rst;
reg_tab_dest_ip_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_tab_dest_ip_miso : IN t_mem_miso := c_mem_miso_rst;
reg_tab_dest_mac_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
@@ -354,13 +354,13 @@ ARCHITECTURE str OF arts_unb1_sc4_mm_master IS
reg_dp_xonoff_tab_i_write_export : OUT STD_LOGIC;
reg_dp_xonoff_tab_i_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- reg_dp_xonoff_iab_i_address_export : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0);
+-- reg_dp_xonoff_iab_i_address_export : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0);
-- reg_dp_xonoff_iab_i_clk_export : OUT STD_LOGIC;
- reg_dp_xonoff_iab_i_read_export : OUT STD_LOGIC;
- reg_dp_xonoff_iab_i_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+-- reg_dp_xonoff_iab_i_read_export : OUT STD_LOGIC;
+-- reg_dp_xonoff_iab_i_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-- reg_dp_xonoff_iab_i_reset_export : OUT STD_LOGIC;
- reg_dp_xonoff_iab_i_write_export : OUT STD_LOGIC;
- reg_dp_xonoff_iab_i_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+-- reg_dp_xonoff_iab_i_write_export : OUT STD_LOGIC;
+-- reg_dp_xonoff_iab_i_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
reg_dp_offload_tx_tab_iquv_hdr_dat_address_export : OUT STD_LOGIC_VECTOR(6-1 DOWNTO 0);
-- reg_dp_offload_tx_tab_iquv_hdr_dat_clk_export : OUT STD_LOGIC;
@@ -378,13 +378,13 @@ ARCHITECTURE str OF arts_unb1_sc4_mm_master IS
reg_dp_offload_tx_tab_i_hdr_dat_write_export : OUT STD_LOGIC;
reg_dp_offload_tx_tab_i_hdr_dat_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- reg_dp_offload_tx_iab_i_hdr_dat_address_export : OUT STD_LOGIC_VECTOR(6-1 DOWNTO 0);
+-- reg_dp_offload_tx_iab_i_hdr_dat_address_export : OUT STD_LOGIC_VECTOR(6-1 DOWNTO 0);
-- reg_dp_offload_tx_iab_i_hdr_dat_clk_export : OUT STD_LOGIC;
- reg_dp_offload_tx_iab_i_hdr_dat_read_export : OUT STD_LOGIC;
- reg_dp_offload_tx_iab_i_hdr_dat_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+-- reg_dp_offload_tx_iab_i_hdr_dat_read_export : OUT STD_LOGIC;
+-- reg_dp_offload_tx_iab_i_hdr_dat_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-- reg_dp_offload_tx_iab_i_hdr_dat_reset_export : OUT STD_LOGIC;
- reg_dp_offload_tx_iab_i_hdr_dat_write_export : OUT STD_LOGIC;
- reg_dp_offload_tx_iab_i_hdr_dat_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+-- reg_dp_offload_tx_iab_i_hdr_dat_write_export : OUT STD_LOGIC;
+-- reg_dp_offload_tx_iab_i_hdr_dat_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
reg_tab_dest_ip_address_export : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
reg_tab_dest_ip_read_export : OUT STD_LOGIC;
@@ -505,9 +505,9 @@ BEGIN
reg_dp_xonoff_tab_iquv_mosi <= c_mem_mosi_rst;
reg_dp_offload_tx_tab_iquv_hdr_dat_mosi <= c_mem_mosi_rst;
reg_dp_xonoff_tab_i_mosi <= c_mem_mosi_rst;
- reg_dp_xonoff_iab_i_mosi <= c_mem_mosi_rst;
+-- reg_dp_xonoff_iab_i_mosi <= c_mem_mosi_rst;
reg_dp_offload_tx_tab_i_hdr_dat_mosi <= c_mem_mosi_rst;
- reg_dp_offload_tx_iab_i_hdr_dat_mosi <= c_mem_mosi_rst;
+-- reg_dp_offload_tx_iab_i_hdr_dat_mosi <= c_mem_mosi_rst;
reg_dp_bsn_align_input_mosi <= c_mem_mosi_rst;
reg_dp_bsn_align_mesh_mosi <= c_mem_mosi_rst;
reg_dp_bsn_monitor_input_mosi <= c_mem_mosi_rst;
@@ -743,13 +743,13 @@ BEGIN
reg_dp_xonoff_tab_i_write_export => reg_dp_xonoff_tab_i_mosi.wr,
reg_dp_xonoff_tab_i_writedata_export => reg_dp_xonoff_tab_i_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_xonoff_iab_i_address_export => reg_dp_xonoff_iab_i_mosi.address(1-1 DOWNTO 0),
+-- reg_dp_xonoff_iab_i_address_export => reg_dp_xonoff_iab_i_mosi.address(1-1 DOWNTO 0),
-- reg_dp_xonoff_iab_i_clk_export => OPEN,
- reg_dp_xonoff_iab_i_read_export => reg_dp_xonoff_iab_i_mosi.rd,
- reg_dp_xonoff_iab_i_readdata_export => reg_dp_xonoff_iab_i_miso.rddata(c_word_w-1 DOWNTO 0),
+-- reg_dp_xonoff_iab_i_read_export => reg_dp_xonoff_iab_i_mosi.rd,
+-- reg_dp_xonoff_iab_i_readdata_export => reg_dp_xonoff_iab_i_miso.rddata(c_word_w-1 DOWNTO 0),
-- reg_dp_xonoff_iab_i_reset_export => OPEN,
- reg_dp_xonoff_iab_i_write_export => reg_dp_xonoff_iab_i_mosi.wr,
- reg_dp_xonoff_iab_i_writedata_export => reg_dp_xonoff_iab_i_mosi.wrdata(c_word_w-1 DOWNTO 0),
+-- reg_dp_xonoff_iab_i_write_export => reg_dp_xonoff_iab_i_mosi.wr,
+-- reg_dp_xonoff_iab_i_writedata_export => reg_dp_xonoff_iab_i_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_tab_i_hdr_dat_address_export => reg_dp_offload_tx_tab_i_hdr_dat_mosi.address(9-1 DOWNTO 0),
-- reg_dp_offload_tx_tab_i_hdr_dat_clk_export => OPEN,
@@ -759,13 +759,13 @@ BEGIN
reg_dp_offload_tx_tab_i_hdr_dat_write_export => reg_dp_offload_tx_tab_i_hdr_dat_mosi.wr,
reg_dp_offload_tx_tab_i_hdr_dat_writedata_export => reg_dp_offload_tx_tab_i_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_offload_tx_iab_i_hdr_dat_address_export => reg_dp_offload_tx_iab_i_hdr_dat_mosi.address(6-1 DOWNTO 0),
+-- reg_dp_offload_tx_iab_i_hdr_dat_address_export => reg_dp_offload_tx_iab_i_hdr_dat_mosi.address(6-1 DOWNTO 0),
-- reg_dp_offload_tx_iab_i_hdr_dat_clk_export => OPEN,
- reg_dp_offload_tx_iab_i_hdr_dat_read_export => reg_dp_offload_tx_iab_i_hdr_dat_mosi.rd,
- reg_dp_offload_tx_iab_i_hdr_dat_readdata_export => reg_dp_offload_tx_iab_i_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+-- reg_dp_offload_tx_iab_i_hdr_dat_read_export => reg_dp_offload_tx_iab_i_hdr_dat_mosi.rd,
+-- reg_dp_offload_tx_iab_i_hdr_dat_readdata_export => reg_dp_offload_tx_iab_i_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
-- reg_dp_offload_tx_iab_i_hdr_dat_reset_export => OPEN,
- reg_dp_offload_tx_iab_i_hdr_dat_write_export => reg_dp_offload_tx_iab_i_hdr_dat_mosi.wr,
- reg_dp_offload_tx_iab_i_hdr_dat_writedata_export => reg_dp_offload_tx_iab_i_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+-- reg_dp_offload_tx_iab_i_hdr_dat_write_export => reg_dp_offload_tx_iab_i_hdr_dat_mosi.wr,
+-- reg_dp_offload_tx_iab_i_hdr_dat_writedata_export => reg_dp_offload_tx_iab_i_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_tab_dest_ip_address_export => reg_tab_dest_ip_mosi.address(2 DOWNTO 0),
reg_tab_dest_ip_read_export => reg_tab_dest_ip_mosi.rd,