diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 8f5fd8404d6f5a9e6a8c3a0092052d9b65d225f6..4542a38328c017533c966250a6b03384f588d23c 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -35,7 +35,7 @@ USE mm_lib.mm_file_unb_pkg.ALL;
 USE eth_lib.eth_pkg.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE tech_tse_lib.tech_tse_pkg.ALL;
---USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
 USE work.qsys_unb1_test_pkg.ALL;
 
 
@@ -317,7 +317,7 @@ BEGIN
       eth1g_tse_mosi.rd <= '0';
       WAIT FOR 400 ns;
       WAIT UNTIL rising_edge(i_mm_clk);
-      --proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
+      proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
 
       -- Enable RX
       proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, i_mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi);  -- control rx en