diff --git a/applications/apertif/designs/apertif_unb1_correlator/quartus/qsys_apertif_unb1_correlator.qsys b/applications/apertif/designs/apertif_unb1_correlator/quartus/qsys_apertif_unb1_correlator.qsys
index f92ff09d5178d57127c880ed242568feda93088e..b26c972c0fc5d945a0d03673322220943546a4b8 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/quartus/qsys_apertif_unb1_correlator.qsys
+++ b/applications/apertif/designs/apertif_unb1_correlator/quartus/qsys_apertif_unb1_correlator.qsys
@@ -12,19 +12,11 @@
element $${FILENAME}
{
}
- element altpll_0
- {
- datum _sortIndex
- {
- value = "20";
- type = "int";
- }
- }
element jtag_uart_0.avalon_jtag_slave
{
datum baseAddress
{
- value = "1712";
+ value = "12296";
type = "long";
}
}
@@ -41,43 +33,11 @@
type = "boolean";
}
}
- element altpll_0.c0
- {
- datum _clockDomain
- {
- value = "mm_clk";
- type = "String";
- }
- }
- element altpll_0.c1
- {
- datum _clockDomain
- {
- value = "epcs_clk";
- type = "String";
- }
- }
- element altpll_0.c2
- {
- datum _clockDomain
- {
- value = "tse_clk";
- type = "String";
- }
- }
element clk_input
{
datum _sortIndex
{
- value = "24";
- type = "int";
- }
- }
- element cpu_0
- {
- datum _sortIndex
- {
- value = "2";
+ value = "22";
type = "int";
}
datum sopceditor_expanded
@@ -86,32 +46,24 @@
type = "boolean";
}
}
- element export_mm
+ element cpu_0
{
datum _sortIndex
{
- value = "3";
+ value = "2";
type = "int";
}
datum sopceditor_expanded
{
- value = "1";
+ value = "0";
type = "boolean";
}
}
- element altpll_0.inclk_interface
- {
- datum _tags
- {
- value = "";
- type = "String";
- }
- }
element cpu_0.jtag_debug_module
{
datum baseAddress
{
- value = "28672";
+ value = "32768";
type = "long";
}
}
@@ -119,7 +71,7 @@
{
datum _sortIndex
{
- value = "6";
+ value = "5";
type = "int";
}
datum megawizard_uipreferences
@@ -129,7 +81,7 @@
}
datum sopceditor_expanded
{
- value = "1";
+ value = "0";
type = "boolean";
}
}
@@ -137,52 +89,52 @@
{
datum baseAddress
{
- value = "1600";
+ value = "12448";
type = "long";
}
}
- element reg_diag_bg.mem
+ element reg_diag_data_buf_mesh.mem
{
datum baseAddress
{
- value = "1632";
+ value = "12576";
type = "long";
}
}
- element reg_wdi.mem
+ element reg_mdio_1.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "12288";
+ value = "12352";
type = "long";
}
}
- element reg_bsn_monitor.mem
+ element reg_diag_bg_mesh.mem
{
datum baseAddress
{
- value = "1024";
+ value = "12512";
type = "long";
}
}
- element ram_diag_data_buf.mem
+ element pio_pps.mem
{
datum baseAddress
{
- value = "524288";
+ value = "12568";
type = "long";
}
}
- element reg_mdio_0.mem
+ element rom_system_info.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "1568";
+ value = "4096";
type = "long";
}
}
@@ -194,11 +146,27 @@
type = "long";
}
}
- element reg_diag_data_buf.mem
+ element ram_diag_data_buf_input.mem
+ {
+ datum baseAddress
+ {
+ value = "524288";
+ type = "long";
+ }
+ }
+ element reg_diag_bg_input.mem
+ {
+ datum baseAddress
+ {
+ value = "12480";
+ type = "long";
+ }
+ }
+ element reg_tr_nonbonded.mem
{
datum baseAddress
{
- value = "1720";
+ value = "192";
type = "long";
}
}
@@ -215,11 +183,32 @@
type = "long";
}
}
- element reg_tr_xaui.mem
+ element reg_diag_data_buf_input.mem
{
datum baseAddress
{
- value = "16384";
+ value = "12560";
+ type = "long";
+ }
+ }
+ element pio_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "0";
+ type = "long";
+ }
+ }
+ element ram_diag_bg_mesh.mem
+ {
+ datum baseAddress
+ {
+ value = "28672";
type = "long";
}
}
@@ -227,40 +216,51 @@
{
datum baseAddress
{
- value = "1536";
+ value = "12384";
type = "long";
}
}
- element reg_mdio_1.mem
+ element reg_mdio_0.mem
{
datum baseAddress
{
- value = "224";
+ value = "12416";
type = "long";
}
}
- element pio_system_info.mem
+ element ram_diag_data_buf_mesh.mem
{
- datum _lockedAddress
+ datum baseAddress
{
- value = "1";
- type = "boolean";
+ value = "1536";
+ type = "long";
}
+ }
+ element reg_tr_xaui.mem
+ {
datum baseAddress
{
- value = "0";
+ value = "16384";
type = "long";
}
}
- element pio_pps.mem
+ element ram_fil_coefs.mem
{
datum baseAddress
{
- value = "1728";
+ value = "14336";
type = "long";
}
}
- element rom_system_info.mem
+ element reg_dp_offload_rx_hdr_dat.mem
+ {
+ datum baseAddress
+ {
+ value = "512";
+ type = "long";
+ }
+ }
+ element reg_wdi.mem
{
datum _lockedAddress
{
@@ -269,23 +269,23 @@
}
datum baseAddress
{
- value = "4096";
+ value = "12288";
type = "long";
}
}
- element reg_dp_offload_rx_hdr_dat.mem
+ element reg_diagnostics.mem
{
datum baseAddress
{
- value = "512";
+ value = "1792";
type = "long";
}
}
- element ram_fil_coefs.mem
+ element reg_bsn_monitor.mem
{
datum baseAddress
{
- value = "14336";
+ value = "1024";
type = "long";
}
}
@@ -317,7 +317,7 @@
{
datum _sortIndex
{
- value = "5";
+ value = "4";
type = "int";
}
datum megawizard_uipreferences
@@ -335,7 +335,7 @@
{
datum _sortIndex
{
- value = "4";
+ value = "3";
type = "int";
}
datum sopceditor_expanded
@@ -348,7 +348,7 @@
{
datum _sortIndex
{
- value = "17";
+ value = "16";
type = "int";
}
datum sopceditor_expanded
@@ -374,7 +374,7 @@
{
datum _sortIndex
{
- value = "7";
+ value = "6";
type = "int";
}
datum megawizard_uipreferences
@@ -388,32 +388,37 @@
type = "boolean";
}
}
- element altpll_0.pll_slave
+ element ram_diag_bg_mesh
{
- datum baseAddress
+ datum _sortIndex
{
- value = "1696";
- type = "long";
+ value = "28";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
}
}
- element ram_diag_data_buf
+ element ram_diag_data_buf_input
{
datum _sortIndex
{
- value = "9";
+ value = "8";
type = "int";
}
datum sopceditor_expanded
{
- value = "1";
+ value = "0";
type = "boolean";
}
}
- element ram_fil_coefs
+ element ram_diag_data_buf_mesh
{
datum _sortIndex
{
- value = "11";
+ value = "26";
type = "int";
}
datum sopceditor_expanded
@@ -422,6 +427,19 @@
type = "boolean";
}
}
+ element ram_fil_coefs
+ {
+ datum _sortIndex
+ {
+ value = "10";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
element avs_eth_0.ram_write
{
datum _tags
@@ -430,7 +448,7 @@
type = "String";
}
}
- element reg_bsn_monitor.read
+ element reg_diag_data_buf_input.read
{
datum _tags
{
@@ -438,7 +456,7 @@
type = "String";
}
}
- element reg_diag_data_buf.read
+ element reg_bsn_monitor.read
{
datum _tags
{
@@ -450,36 +468,33 @@
{
datum _sortIndex
{
- value = "23";
+ value = "21";
type = "int";
}
- }
- element reg_diag_bg
- {
- datum _sortIndex
+ datum sopceditor_expanded
{
- value = "26";
- type = "int";
+ value = "0";
+ type = "boolean";
}
}
- element reg_diag_data_buf
+ element reg_diag_bg_input
{
datum _sortIndex
{
- value = "10";
+ value = "24";
type = "int";
}
datum sopceditor_expanded
{
- value = "1";
+ value = "0";
type = "boolean";
}
}
- element reg_dp_offload_rx_hdr_dat
+ element reg_diag_bg_mesh
{
datum _sortIndex
{
- value = "15";
+ value = "27";
type = "int";
}
datum sopceditor_expanded
@@ -488,19 +503,24 @@
type = "boolean";
}
}
- element reg_dp_offload_tx_hdr_dat
+ element reg_diag_data_buf_input
{
datum _sortIndex
{
- value = "25";
+ value = "9";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
}
- element reg_mdio_0
+ element reg_diag_data_buf_mesh
{
datum _sortIndex
{
- value = "12";
+ value = "25";
type = "int";
}
datum sopceditor_expanded
@@ -509,11 +529,11 @@
type = "boolean";
}
}
- element reg_mdio_1
+ element reg_diagnostics
{
datum _sortIndex
{
- value = "13";
+ value = "29";
type = "int";
}
datum sopceditor_expanded
@@ -522,7 +542,7 @@
type = "boolean";
}
}
- element reg_mdio_2
+ element reg_dp_offload_rx_hdr_dat
{
datum _sortIndex
{
@@ -535,40 +555,50 @@
type = "boolean";
}
}
- element reg_tr_10GbE
+ element reg_dp_offload_tx_hdr_dat
{
datum _sortIndex
{
- value = "21";
+ value = "23";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
}
- element reg_tr_xaui
+ element reg_mdio_0
{
datum _sortIndex
{
- value = "22";
+ value = "11";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
}
- element reg_unb_sens
+ element reg_mdio_1
{
datum _sortIndex
{
- value = "16";
+ value = "12";
type = "int";
}
datum sopceditor_expanded
{
- value = "0";
+ value = "1";
type = "boolean";
}
}
- element reg_wdi
+ element reg_mdio_2
{
datum _sortIndex
{
- value = "18";
+ value = "13";
type = "int";
}
datum sopceditor_expanded
@@ -577,7 +607,7 @@
type = "boolean";
}
}
- element rom_system_info
+ element reg_tr_10GbE
{
datum _sortIndex
{
@@ -590,23 +620,80 @@
type = "boolean";
}
}
- element pio_wdi.s1
+ element reg_tr_nonbonded
{
- datum baseAddress
+ datum _sortIndex
{
- value = "1680";
- type = "long";
+ value = "30";
+ type = "int";
}
- }
- element timer_0.s1
- {
- datum baseAddress
+ datum sopceditor_expanded
{
- value = "192";
- type = "long";
+ value = "0";
+ type = "boolean";
}
}
- element onchip_memory2_0.s1
+ element reg_tr_xaui
+ {
+ datum _sortIndex
+ {
+ value = "20";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_unb_sens
+ {
+ datum _sortIndex
+ {
+ value = "15";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_wdi
+ {
+ datum _sortIndex
+ {
+ value = "17";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element rom_system_info
+ {
+ datum _sortIndex
+ {
+ value = "18";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element timer_0.s1
+ {
+ datum baseAddress
+ {
+ value = "12320";
+ type = "long";
+ }
+ }
+ element onchip_memory2_0.s1
{
datum _lockedAddress
{
@@ -623,7 +710,15 @@
{
datum baseAddress
{
- value = "1664";
+ value = "12304";
+ type = "long";
+ }
+ }
+ element pio_wdi.s1
+ {
+ datum baseAddress
+ {
+ value = "12544";
type = "long";
}
}
@@ -639,7 +734,7 @@
{
datum _sortIndex
{
- value = "8";
+ value = "7";
type = "int";
}
datum sopceditor_expanded
@@ -648,7 +743,7 @@
type = "boolean";
}
}
- element reg_diag_data_buf.write
+ element reg_diag_data_buf_input.write
{
datum _tags
{
@@ -676,15 +771,12 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VHDL" />
<parameter name="maxAdditionalLatency" value="0" />
- <parameter name="projectName">apertif_unb1_correlator.qpf</parameter>
+ <parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
- <parameter name="timeStamp" value="1429252295516" />
+ <parameter name="timeStamp" value="1439282587140" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
- <interface name="mm_clk" internal="export_mm.out_clk" type="clock" dir="start">
- <port name="mm_clk" internal="out_clk" />
- </interface>
<interface
name="pio_debug_wave_external_connection"
internal="pio_debug_wave.external_connection"
@@ -700,73 +792,73 @@
<port name="out_port_from_the_pio_wdi" internal="out_port" />
</interface>
<interface
- name="ram_diag_data_buf_readdata"
- internal="ram_diag_data_buf.readdata"
+ name="ram_diag_data_buf_input_readdata"
+ internal="ram_diag_data_buf_input.readdata"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buf_read"
- internal="ram_diag_data_buf.read"
+ name="ram_diag_data_buf_input_read"
+ internal="ram_diag_data_buf_input.read"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buf_writedata"
- internal="ram_diag_data_buf.writedata"
+ name="ram_diag_data_buf_input_writedata"
+ internal="ram_diag_data_buf_input.writedata"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buf_write"
- internal="ram_diag_data_buf.write"
+ name="ram_diag_data_buf_input_write"
+ internal="ram_diag_data_buf_input.write"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buf_address"
- internal="ram_diag_data_buf.address"
+ name="ram_diag_data_buf_input_address"
+ internal="ram_diag_data_buf_input.address"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buf_clk"
- internal="ram_diag_data_buf.clk"
+ name="ram_diag_data_buf_input_clk"
+ internal="ram_diag_data_buf_input.clk"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buf_reset"
- internal="ram_diag_data_buf.reset"
+ name="ram_diag_data_buf_input_reset"
+ internal="ram_diag_data_buf_input.reset"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buf_readdata"
- internal="reg_diag_data_buf.readdata"
+ name="reg_diag_data_buf_input_readdata"
+ internal="reg_diag_data_buf_input.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buf_read"
- internal="reg_diag_data_buf.read"
+ name="reg_diag_data_buf_input_read"
+ internal="reg_diag_data_buf_input.read"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buf_writedata"
- internal="reg_diag_data_buf.writedata"
+ name="reg_diag_data_buf_input_writedata"
+ internal="reg_diag_data_buf_input.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buf_write"
- internal="reg_diag_data_buf.write"
+ name="reg_diag_data_buf_input_write"
+ internal="reg_diag_data_buf_input.write"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buf_address"
- internal="reg_diag_data_buf.address"
+ name="reg_diag_data_buf_input_address"
+ internal="reg_diag_data_buf_input.address"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buf_clk"
- internal="reg_diag_data_buf.clk"
+ name="reg_diag_data_buf_input_clk"
+ internal="reg_diag_data_buf_input.clk"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buf_reset"
- internal="reg_diag_data_buf.reset"
+ name="reg_diag_data_buf_input_reset"
+ internal="reg_diag_data_buf_input.reset"
type="conduit"
dir="end" />
<interface
@@ -1190,24 +1282,6 @@
internal="rom_system_info.readdata"
type="conduit"
dir="end" />
- <interface name="epcs" internal="altpll_0.c1" type="clock" dir="start" />
- <interface name="tse" internal="altpll_0.c2" type="clock" dir="start" />
- <interface name="altpll_0_c3" internal="altpll_0.c3" type="clock" dir="start" />
- <interface
- name="altpll_0_areset"
- internal="altpll_0.areset_conduit"
- type="conduit"
- dir="end" />
- <interface
- name="altpll_0_locked"
- internal="altpll_0.locked_conduit"
- type="conduit"
- dir="end" />
- <interface
- name="altpll_0_phasedone"
- internal="altpll_0.phasedone_conduit"
- type="conduit"
- dir="end" />
<interface
name="reg_tr_10gbe_reset"
internal="reg_tr_10GbE.reset"
@@ -1365,38 +1439,248 @@
type="conduit"
dir="end" />
<interface
- name="reg_diag_bg_reset"
- internal="reg_diag_bg.reset"
+ name="reg_diag_bg_input_reset"
+ internal="reg_diag_bg_input.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_input_clk"
+ internal="reg_diag_bg_input.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_input_address"
+ internal="reg_diag_bg_input.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_input_write"
+ internal="reg_diag_bg_input.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_input_writedata"
+ internal="reg_diag_bg_input.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_input_read"
+ internal="reg_diag_bg_input.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_input_readdata"
+ internal="reg_diag_bg_input.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buf_mesh_reset"
+ internal="reg_diag_data_buf_mesh.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buf_mesh_clk"
+ internal="reg_diag_data_buf_mesh.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buf_mesh_address"
+ internal="reg_diag_data_buf_mesh.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buf_mesh_write"
+ internal="reg_diag_data_buf_mesh.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buf_mesh_writedata"
+ internal="reg_diag_data_buf_mesh.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buf_mesh_read"
+ internal="reg_diag_data_buf_mesh.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buf_mesh_readdata"
+ internal="reg_diag_data_buf_mesh.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buf_mesh_reset"
+ internal="ram_diag_data_buf_mesh.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buf_mesh_clk"
+ internal="ram_diag_data_buf_mesh.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buf_mesh_address"
+ internal="ram_diag_data_buf_mesh.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buf_mesh_write"
+ internal="ram_diag_data_buf_mesh.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buf_mesh_writedata"
+ internal="ram_diag_data_buf_mesh.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buf_mesh_read"
+ internal="ram_diag_data_buf_mesh.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buf_mesh_readdata"
+ internal="ram_diag_data_buf_mesh.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_mesh_reset"
+ internal="reg_diag_bg_mesh.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_mesh_clk"
+ internal="reg_diag_bg_mesh.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_mesh_address"
+ internal="reg_diag_bg_mesh.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_mesh_write"
+ internal="reg_diag_bg_mesh.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_mesh_writedata"
+ internal="reg_diag_bg_mesh.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_mesh_read"
+ internal="reg_diag_bg_mesh.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_mesh_readdata"
+ internal="reg_diag_bg_mesh.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_mesh_reset"
+ internal="ram_diag_bg_mesh.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_mesh_clk"
+ internal="ram_diag_bg_mesh.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_mesh_address"
+ internal="ram_diag_bg_mesh.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_mesh_write"
+ internal="ram_diag_bg_mesh.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_mesh_writedata"
+ internal="ram_diag_bg_mesh.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_mesh_read"
+ internal="ram_diag_bg_mesh.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_mesh_readdata"
+ internal="ram_diag_bg_mesh.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diagnostics_reset"
+ internal="reg_diagnostics.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diagnostics_clk"
+ internal="reg_diagnostics.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diagnostics_address"
+ internal="reg_diagnostics.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diagnostics_write"
+ internal="reg_diagnostics.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diagnostics_writedata"
+ internal="reg_diagnostics.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diagnostics_read"
+ internal="reg_diagnostics.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diagnostics_readdata"
+ internal="reg_diagnostics.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_nonbonded_reset"
+ internal="reg_tr_nonbonded.reset"
type="conduit"
dir="end" />
<interface
- name="reg_diag_bg_clk"
- internal="reg_diag_bg.clk"
+ name="reg_tr_nonbonded_clk"
+ internal="reg_tr_nonbonded.clk"
type="conduit"
dir="end" />
<interface
- name="reg_diag_bg_address"
- internal="reg_diag_bg.address"
+ name="reg_tr_nonbonded_address"
+ internal="reg_tr_nonbonded.address"
type="conduit"
dir="end" />
<interface
- name="reg_diag_bg_write"
- internal="reg_diag_bg.write"
+ name="reg_tr_nonbonded_write"
+ internal="reg_tr_nonbonded.write"
type="conduit"
dir="end" />
<interface
- name="reg_diag_bg_writedata"
- internal="reg_diag_bg.writedata"
+ name="reg_tr_nonbonded_writedata"
+ internal="reg_tr_nonbonded.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_diag_bg_read"
- internal="reg_diag_bg.read"
+ name="reg_tr_nonbonded_read"
+ internal="reg_tr_nonbonded.read"
type="conduit"
dir="end" />
<interface
- name="reg_diag_bg_readdata"
- internal="reg_diag_bg.readdata"
+ name="reg_tr_nonbonded_readdata"
+ internal="reg_tr_nonbonded.readdata"
type="conduit"
dir="end" />
<module
@@ -1405,7 +1689,7 @@
enabled="1"
name="onchip_memory2_0">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
- <parameter name="autoInitializationFileName">qsys_apertif_unb1_correlator_onchip_memory2_0</parameter>
+ <parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
<parameter name="blockType" value="M144K" />
<parameter name="dataWidth" value="32" />
<parameter name="deviceFamily" value="Stratix IV" />
@@ -1450,7 +1734,7 @@ q]]></parameter>
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
- <parameter name="clockRate" value="50000000" />
+ <parameter name="clockRate" value="25000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
@@ -1464,7 +1748,7 @@ q]]></parameter>
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
- <parameter name="clockRate" value="50000000" />
+ <parameter name="clockRate" value="25000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
@@ -1482,7 +1766,7 @@ q]]></parameter>
<parameter name="periodUnits" value="MSEC" />
<parameter name="resetOutput" value="false" />
<parameter name="snapshot" value="false" />
- <parameter name="systemFrequency" value="50000000" />
+ <parameter name="systemFrequency" value="25000000" />
<parameter name="timeoutPulseOutput" value="false" />
<parameter name="timerPreset">SIMPLE_PERIODIC_INTERRUPT</parameter>
</module>
@@ -1574,9 +1858,9 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
- <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x7000' end='0x7800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_mdio_1.mem' start='0xE0' end='0x100' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x200' end='0x400' /><slave name='reg_bsn_monitor.mem' start='0x400' end='0x600' /><slave name='reg_mdio_2.mem' start='0x600' end='0x620' /><slave name='reg_mdio_0.mem' start='0x620' end='0x640' /><slave name='reg_unb_sens.mem' start='0x640' end='0x660' /><slave name='reg_diag_bg.mem' start='0x660' end='0x680' /><slave name='pio_debug_wave.s1' start='0x680' end='0x690' /><slave name='pio_wdi.s1' start='0x690' end='0x6A0' /><slave name='altpll_0.pll_slave' start='0x6A0' end='0x6B0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x6B0' end='0x6B8' /><slave name='reg_diag_data_buf.mem' start='0x6B8' end='0x6C0' /><slave name='pio_pps.mem' start='0x6C0' end='0x6C8' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='ram_fil_coefs.mem' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='cpu_0.jtag_debug_module' start='0x7000' end='0x7800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_diag_data_buf.mem' start='0x80000' end='0x100000' /></address-map>]]></parameter>
- <parameter name="clockFrequency" value="50000000" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x8000' end='0x8800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='reg_tr_nonbonded.mem' start='0xC0' end='0x100' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x200' end='0x400' /><slave name='reg_bsn_monitor.mem' start='0x400' end='0x600' /><slave name='ram_diag_data_buf_mesh.mem' start='0x600' end='0x700' /><slave name='reg_diagnostics.mem' start='0x700' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_debug_wave.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='reg_mdio_1.mem' start='0x3040' end='0x3060' /><slave name='reg_mdio_2.mem' start='0x3060' end='0x3080' /><slave name='reg_mdio_0.mem' start='0x3080' end='0x30A0' /><slave name='reg_unb_sens.mem' start='0x30A0' end='0x30C0' /><slave name='reg_diag_bg_input.mem' start='0x30C0' end='0x30E0' /><slave name='reg_diag_bg_mesh.mem' start='0x30E0' end='0x3100' /><slave name='pio_wdi.s1' start='0x3100' end='0x3110' /><slave name='reg_diag_data_buf_input.mem' start='0x3110' end='0x3118' /><slave name='pio_pps.mem' start='0x3118' end='0x3120' /><slave name='reg_diag_data_buf_mesh.mem' start='0x3120' end='0x3128' /><slave name='ram_fil_coefs.mem' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='ram_diag_bg_mesh.mem' start='0x7000' end='0x8000' /><slave name='cpu_0.jtag_debug_module' start='0x8000' end='0x8800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_diag_data_buf_input.mem' start='0x80000' end='0x100000' /></address-map>]]></parameter>
+ <parameter name="clockFrequency" value="25000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" />
<parameter name="customInstSlavesSystemInfo" value="<info/>" />
@@ -1590,52 +1874,43 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
</module>
- <module
- kind="altera_clock_bridge"
- version="11.1"
- enabled="1"
- name="export_mm">
- <parameter name="DERIVED_CLOCK_RATE" value="50000000" />
- <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
- <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
<module
kind="avs_common_mm"
version="1.0"
enabled="1"
- name="ram_diag_data_buf">
+ name="ram_diag_data_buf_input">
<parameter name="g_adr_w" value="17" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module
kind="avs_common_mm"
version="1.0"
enabled="1"
- name="reg_diag_data_buf">
+ name="reg_diag_data_buf_input">
<parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="ram_fil_coefs">
<parameter name="g_adr_w" value="9" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_0">
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_1">
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_2">
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module
kind="avs_common_mm"
@@ -1644,202 +1919,35 @@ q]]></parameter>
name="reg_dp_offload_rx_hdr_dat">
<parameter name="g_adr_w" value="7" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module kind="avs2_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
- <parameter name="AUTO_MM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_MM_CLOCK_RATE" value="25000000" />
</module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="pio_system_info">
<parameter name="g_adr_w" value="5" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="pio_pps">
<parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
<parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info">
<parameter name="g_adr_w" value="10" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module kind="altpll" version="11.1" enabled="1" name="altpll_0">
- <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
- <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
- <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix IV" />
- <parameter name="WIDTH_CLOCK" value="10" />
- <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
- <parameter name="PRIMARY_CLOCK" value="" />
- <parameter name="INCLK0_INPUT_FREQUENCY" value="40000" />
- <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
- <parameter name="OPERATION_MODE" value="NORMAL" />
- <parameter name="PLL_TYPE" value="AUTO" />
- <parameter name="QUALIFY_CONF_DONE" value="" />
- <parameter name="COMPENSATE_CLOCK" value="CLK0" />
- <parameter name="SCAN_CHAIN" value="" />
- <parameter name="GATE_LOCK_SIGNAL" value="" />
- <parameter name="GATE_LOCK_COUNTER" value="" />
- <parameter name="LOCK_HIGH" value="" />
- <parameter name="LOCK_LOW" value="" />
- <parameter name="VALID_LOCK_MULTIPLIER" value="" />
- <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
- <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
- <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
- <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
- <parameter name="SKIP_VCO" value="" />
- <parameter name="SWITCH_OVER_COUNTER" value="" />
- <parameter name="SWITCH_OVER_TYPE" value="" />
- <parameter name="FEEDBACK_SOURCE" value="" />
- <parameter name="BANDWIDTH" value="" />
- <parameter name="BANDWIDTH_TYPE" value="AUTO" />
- <parameter name="SPREAD_FREQUENCY" value="" />
- <parameter name="DOWN_SPREAD" value="" />
- <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
- <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
- <parameter name="CLK0_MULTIPLY_BY" value="2" />
- <parameter name="CLK1_MULTIPLY_BY" value="4" />
- <parameter name="CLK2_MULTIPLY_BY" value="5" />
- <parameter name="CLK3_MULTIPLY_BY" value="8" />
- <parameter name="CLK4_MULTIPLY_BY" value="" />
- <parameter name="CLK5_MULTIPLY_BY" value="" />
- <parameter name="CLK6_MULTIPLY_BY" value="" />
- <parameter name="CLK7_MULTIPLY_BY" value="" />
- <parameter name="CLK8_MULTIPLY_BY" value="" />
- <parameter name="CLK9_MULTIPLY_BY" value="" />
- <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
- <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
- <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
- <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
- <parameter name="CLK0_DIVIDE_BY" value="1" />
- <parameter name="CLK1_DIVIDE_BY" value="5" />
- <parameter name="CLK2_DIVIDE_BY" value="1" />
- <parameter name="CLK3_DIVIDE_BY" value="5" />
- <parameter name="CLK4_DIVIDE_BY" value="" />
- <parameter name="CLK5_DIVIDE_BY" value="" />
- <parameter name="CLK6_DIVIDE_BY" value="" />
- <parameter name="CLK7_DIVIDE_BY" value="" />
- <parameter name="CLK8_DIVIDE_BY" value="" />
- <parameter name="CLK9_DIVIDE_BY" value="" />
- <parameter name="EXTCLK0_DIVIDE_BY" value="" />
- <parameter name="EXTCLK1_DIVIDE_BY" value="" />
- <parameter name="EXTCLK2_DIVIDE_BY" value="" />
- <parameter name="EXTCLK3_DIVIDE_BY" value="" />
- <parameter name="CLK0_PHASE_SHIFT" value="0" />
- <parameter name="CLK1_PHASE_SHIFT" value="0" />
- <parameter name="CLK2_PHASE_SHIFT" value="0" />
- <parameter name="CLK3_PHASE_SHIFT" value="0" />
- <parameter name="CLK4_PHASE_SHIFT" value="" />
- <parameter name="CLK5_PHASE_SHIFT" value="" />
- <parameter name="CLK6_PHASE_SHIFT" value="" />
- <parameter name="CLK7_PHASE_SHIFT" value="" />
- <parameter name="CLK8_PHASE_SHIFT" value="" />
- <parameter name="CLK9_PHASE_SHIFT" value="" />
- <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
- <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
- <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
- <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
- <parameter name="CLK0_DUTY_CYCLE" value="50" />
- <parameter name="CLK1_DUTY_CYCLE" value="50" />
- <parameter name="CLK2_DUTY_CYCLE" value="50" />
- <parameter name="CLK3_DUTY_CYCLE" value="50" />
- <parameter name="CLK4_DUTY_CYCLE" value="" />
- <parameter name="CLK5_DUTY_CYCLE" value="" />
- <parameter name="CLK6_DUTY_CYCLE" value="" />
- <parameter name="CLK7_DUTY_CYCLE" value="" />
- <parameter name="CLK8_DUTY_CYCLE" value="" />
- <parameter name="CLK9_DUTY_CYCLE" value="" />
- <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
- <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
- <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
- <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
- <parameter name="PORT_clkena0" value="PORT_UNUSED" />
- <parameter name="PORT_clkena1" value="PORT_UNUSED" />
- <parameter name="PORT_clkena2" value="PORT_UNUSED" />
- <parameter name="PORT_clkena3" value="PORT_UNUSED" />
- <parameter name="PORT_clkena4" value="PORT_UNUSED" />
- <parameter name="PORT_clkena5" value="PORT_UNUSED" />
- <parameter name="PORT_extclkena0" value="" />
- <parameter name="PORT_extclkena1" value="" />
- <parameter name="PORT_extclkena2" value="" />
- <parameter name="PORT_extclkena3" value="" />
- <parameter name="PORT_extclk0" value="" />
- <parameter name="PORT_extclk1" value="" />
- <parameter name="PORT_extclk2" value="" />
- <parameter name="PORT_extclk3" value="" />
- <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
- <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
- <parameter name="PORT_clk0" value="PORT_USED" />
- <parameter name="PORT_clk1" value="PORT_USED" />
- <parameter name="PORT_clk2" value="PORT_USED" />
- <parameter name="PORT_clk3" value="PORT_USED" />
- <parameter name="PORT_clk4" value="PORT_UNUSED" />
- <parameter name="PORT_clk5" value="PORT_UNUSED" />
- <parameter name="PORT_clk6" value="PORT_UNUSED" />
- <parameter name="PORT_clk7" value="PORT_UNUSED" />
- <parameter name="PORT_clk8" value="PORT_UNUSED" />
- <parameter name="PORT_clk9" value="PORT_UNUSED" />
- <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
- <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
- <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
- <parameter name="PORT_SCLKOUT1" value="" />
- <parameter name="PORT_SCLKOUT0" value="" />
- <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
- <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
- <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
- <parameter name="PORT_INCLK0" value="PORT_USED" />
- <parameter name="PORT_FBIN" value="PORT_UNUSED" />
- <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
- <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
- <parameter name="PORT_ARESET" value="PORT_UNUSED" />
- <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
- <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
- <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
- <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
- <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
- <parameter name="PORT_ENABLE0" value="" />
- <parameter name="PORT_ENABLE1" value="" />
- <parameter name="PORT_LOCKED" value="PORT_USED" />
- <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
- <parameter name="PORT_FBOUT" value="PORT_UNUSED" />
- <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
- <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
- <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
- <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
- <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
- <parameter name="PORT_VCOOVERRANGE" value="" />
- <parameter name="PORT_VCOUNDERRANGE" value="" />
- <parameter name="DPA_MULTIPLY_BY" value="" />
- <parameter name="DPA_DIVIDE_BY" value="" />
- <parameter name="DPA_DIVIDER" value="" />
- <parameter name="VCO_MULTIPLY_BY" value="" />
- <parameter name="VCO_DIVIDE_BY" value="" />
- <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
- <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
- <parameter name="VCO_FREQUENCY_CONTROL" value="" />
- <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
- <parameter name="USING_FBMIMICBIDIR_PORT" value="OFF" />
- <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
- <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
- <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 1 CT#PORT_clk9 PORT_UNUSED CT#PORT_clk8 PORT_UNUSED CT#PORT_clk7 PORT_UNUSED CT#PORT_clk6 PORT_UNUSED CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 5 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 10 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 4 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 40000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_FBOUT PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 5 CT#INTENDED_DEVICE_FAMILY {Stratix IV} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 5 CT#CLK3_MULTIPLY_BY 8 CT#USING_FBMIMICBIDIR_PORT OFF CT#PORT_LOCKED PORT_USED</parameter>
- <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 25.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ3 40.00000000 PT#OUTPUT_FREQ2 125.00000000 PT#OUTPUT_FREQ1 20.00000000 PT#OUTPUT_FREQ0 50.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE3 40.000000 PT#EFF_OUTPUT_FREQ_VALUE2 125.000000 PT#EFF_OUTPUT_FREQ_VALUE1 20.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Stratix IV} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1425379691517626.mif PT#ACTIVECLK_CHECK 0</parameter>
- <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
- <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
- <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
- <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
- <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
- <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="25000000" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Stratix IV" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module
kind="avs_common_mm_readlatency0"
@@ -1848,7 +1956,7 @@ q]]></parameter>
name="reg_tr_10GbE">
<parameter name="g_adr_w" value="15" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module
kind="avs_common_mm_readlatency0"
@@ -1857,12 +1965,12 @@ q]]></parameter>
name="reg_tr_xaui">
<parameter name="g_adr_w" value="11" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="reg_bsn_monitor">
<parameter name="g_adr_w" value="7" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module kind="clock_source" version="11.1" enabled="1" name="clk_input">
<parameter name="clockFrequency" value="25000000" />
@@ -1877,12 +1985,66 @@ q]]></parameter>
name="reg_dp_offload_tx_hdr_dat">
<parameter name="g_adr_w" value="6" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_bg_input">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_data_buf_mesh">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="ram_diag_data_buf_mesh">
+ <parameter name="g_adr_w" value="6" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_diag_bg">
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_bg_mesh">
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="ram_diag_bg_mesh">
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_diagnostics">
+ <parameter name="g_adr_w" value="6" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_tr_nonbonded">
+ <parameter name="g_adr_w" value="4" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<connection
kind="avalon"
@@ -1890,7 +2052,7 @@ q]]></parameter>
start="cpu_0.instruction_master"
end="cpu_0.jtag_debug_module">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x7000" />
+ <parameter name="baseAddress" value="0x8000" />
</connection>
<connection
kind="avalon"
@@ -1898,7 +2060,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="cpu_0.jtag_debug_module">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x7000" />
+ <parameter name="baseAddress" value="0x8000" />
</connection>
<connection
kind="avalon"
@@ -1922,7 +2084,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x06b0" />
+ <parameter name="baseAddress" value="0x3008" />
</connection>
<connection
kind="interrupt"
@@ -1937,7 +2099,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_debug_wave.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0680" />
+ <parameter name="baseAddress" value="0x3010" />
</connection>
<connection
kind="avalon"
@@ -1945,7 +2107,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_wdi.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0690" />
+ <parameter name="baseAddress" value="0x3100" />
</connection>
<connection
kind="avalon"
@@ -1953,7 +2115,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00c0" />
+ <parameter name="baseAddress" value="0x3020" />
</connection>
<connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
<parameter name="irqNumber" value="1" />
@@ -1992,17 +2154,17 @@ q]]></parameter>
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="ram_diag_data_buf.system_reset" />
+ end="ram_diag_data_buf_input.system_reset" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="reg_diag_data_buf.system_reset" />
+ end="reg_diag_data_buf_input.system_reset" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="ram_diag_data_buf.mem">
+ end="ram_diag_data_buf_input.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00080000" />
</connection>
@@ -2010,9 +2172,9 @@ q]]></parameter>
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="reg_diag_data_buf.mem">
+ end="reg_diag_data_buf_input.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x06b8" />
+ <parameter name="baseAddress" value="0x3110" />
</connection>
<connection
kind="reset"
@@ -2038,7 +2200,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mdio_1.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00e0" />
+ <parameter name="baseAddress" value="0x3040" />
</connection>
<connection
kind="reset"
@@ -2056,7 +2218,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mdio_2.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0600" />
+ <parameter name="baseAddress" value="0x3060" />
</connection>
<connection
kind="reset"
@@ -2077,7 +2239,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mdio_0.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0620" />
+ <parameter name="baseAddress" value="0x3080" />
</connection>
<connection
kind="avalon"
@@ -2114,7 +2276,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_unb_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0640" />
+ <parameter name="baseAddress" value="0x30a0" />
</connection>
<connection
kind="reset"
@@ -2140,7 +2302,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x06c0" />
+ <parameter name="baseAddress" value="0x3118" />
</connection>
<connection
kind="reset"
@@ -2175,19 +2337,6 @@ q]]></parameter>
end="avs_eth_0.interrupt">
<parameter name="irqNumber" value="2" />
</connection>
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="altpll_0.pll_slave">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x06a0" />
- </connection>
- <connection
- kind="reset"
- version="11.1"
- start="cpu_0.jtag_debug_module_reset"
- end="altpll_0.inclk_interface_reset" />
<connection
kind="reset"
version="11.1"
@@ -2227,98 +2376,6 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0400" />
</connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="rom_system_info.system" />
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_wdi.system" />
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_pps.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_unb_sens.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_dp_offload_rx_hdr_dat.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_mdio_2.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_mdio_1.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_mdio_0.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="ram_fil_coefs.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_diag_data_buf.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="ram_diag_data_buf.system" />
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="timer_0.clk" />
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_wdi.clk" />
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="jtag_uart_0.clk" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="onchip_memory2_0.clk1" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="pio_debug_wave.clk" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="pio_system_info.system" />
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="cpu_0.clk" />
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_tr_10GbE.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_tr_xaui.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_bsn_monitor.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="export_mm.in_clk" />
- <connection
- kind="clock"
- version="11.1"
- start="clk_input.clk"
- end="altpll_0.inclk_interface" />
<connection
kind="reset"
version="11.1"
@@ -2328,7 +2385,7 @@ q]]></parameter>
kind="reset"
version="11.1"
start="clk_input.clk_reset"
- end="reg_diag_data_buf.system_reset" />
+ end="reg_diag_data_buf_input.system_reset" />
<connection
kind="reset"
version="11.1"
@@ -2379,11 +2436,6 @@ q]]></parameter>
version="11.1"
start="clk_input.clk_reset"
end="reg_tr_10GbE.system_reset" />
- <connection
- kind="reset"
- version="11.1"
- start="clk_input.clk_reset"
- end="altpll_0.inclk_interface_reset" />
<connection
kind="reset"
version="11.1"
@@ -2398,7 +2450,7 @@ q]]></parameter>
kind="reset"
version="11.1"
start="clk_input.clk_reset"
- end="ram_diag_data_buf.system_reset" />
+ end="ram_diag_data_buf_input.system_reset" />
<connection
kind="reset"
version="11.1"
@@ -2439,11 +2491,6 @@ q]]></parameter>
version="11.1"
start="clk_input.clk_reset"
end="avs_eth_0.mm_reset" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_dp_offload_tx_hdr_dat.system" />
<connection
kind="reset"
version="11.1"
@@ -2466,18 +2513,225 @@ q]]></parameter>
kind="reset"
version="11.1"
start="clk_input.clk_reset"
- end="reg_diag_bg.system_reset" />
+ end="reg_diag_bg_input.system_reset" />
<connection
- kind="clock"
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_bg_input.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x30c0" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_diag_data_buf_mesh.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_data_buf_mesh.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3120" />
+ </connection>
+ <connection
+ kind="reset"
version="11.1"
- start="altpll_0.c0"
- end="reg_diag_bg.system" />
+ start="clk_input.clk_reset"
+ end="ram_diag_data_buf_mesh.system_reset" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="reg_diag_bg.mem">
+ end="ram_diag_data_buf_mesh.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0660" />
+ <parameter name="baseAddress" value="0x0600" />
</connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_diag_bg_mesh.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_bg_mesh.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x30e0" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="ram_diag_bg_mesh.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_diag_bg_mesh.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x7000" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_diagnostics.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diagnostics.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0700" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_tr_nonbonded.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_tr_nonbonded.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00c0" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_tr_nonbonded.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_diagnostics.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="ram_diag_bg_mesh.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_diag_bg_mesh.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="ram_diag_data_buf_mesh.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_diag_data_buf_mesh.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_diag_bg_input.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_dp_offload_tx_hdr_dat.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_diag_data_buf_input.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="ram_fil_coefs.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_bsn_monitor.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_mdio_2.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_tr_xaui.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_tr_10GbE.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="rom_system_info.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_wdi.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="pio_pps.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_unb_sens.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_dp_offload_rx_hdr_dat.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_mdio_1.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_mdio_0.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="ram_diag_data_buf_input.system" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="timer_0.clk" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="pio_wdi.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="jtag_uart_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="onchip_memory2_0.clk1" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="pio_debug_wave.clk" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="cpu_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="pio_system_info.system" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="avs_eth_0.mm" />
</system>